A system board

Abstract

This utility model discloses a system board, including a circuit board and a main control chip, a memory module, a power supply module, a communication module, and a clock module respectively disposed on the circuit board. The communication module includes a multi-channel Ethernet module, with half of the Ethernet modules disposed on the processing system (PS) side of the main control chip and the other half disposed on the programmable logic (PL) side of the main control chip, and both are communicatively connected to the main control chip. The power supply module is electrically connected to the main control chip, the multi-channel Ethernet module, the memory module, and the clock module respectively. The clock module is communicatively connected to the main control chip. This system board, with the main control chip as its core, includes multiple modules, supports multi-channel Ethernet module data transmission, supports storing the main control chip's runtime files and boot image files, supports outputting the basic clock required by the main control chip, and supports providing the reference clock required for communication by the main control chip. It can basically meet the testing work of 4D millimeter-wave radar soft IP and is suitable for the needs of FPGA engineers.

Description

Technical Field

[0001] This utility model relates to the field of automobile manufacturing technology, and in particular to a system board. Background Technology

[0002] To meet the practical deployment needs of millimeter-wave radar manufacturers and automakers for 4D millimeter-wave imaging radar, the soft IP data processing system product includes functions such as upstream and downstream data transmission on the FPGA platform and soft IP-based point cloud data processing, enabling clustering, tracking, and point cloud feature extraction of initial point cloud data. Therefore, it can be quickly integrated into hardware deployment platforms with programmable devices such as FPGAs, cRIOs, and MPSoCs, becoming a crucial component. Xilinx has designed a powerful development board based on the Zynq UltraScale+RFSoC heterogeneous chip.

[0003] Although Xilinx has powerful development boards, some of their functions may be redundant or insufficient, and they are expensive. It is not feasible for every FPGA engineer to have a development board when performing data processing. Therefore, it is necessary to design a hardware platform that meets the needs of FPGA engineers to satisfy the testing work of 4D millimeter-wave radar soft IP. Utility Model Content

[0004] In view of this, the present invention provides a system board that can meet the needs of FPGA engineers.

[0005] To achieve the above objectives, this utility model provides the following technical solution:

[0006] A system board includes: a circuit board and a main control chip, a memory module, a power module, a communication module and a clock module respectively disposed on the circuit board;

[0007] The communication module includes multiple Ethernet modules, half of which are located on the processing system PS side of the main control chip, and the other half are located on the programmable logic PL side of the main control chip, and both are communicatively connected to the main control chip.

[0008] The power module is electrically connected to the main control chip, the multiple Ethernet modules, the memory module, and the clock module, respectively.

[0009] The clock module is communicatively connected to the main control chip.

[0010] Preferably, the Ethernet module uses a gigabit Ethernet codec chip, communicates with the external network via a gigabit Ethernet interface, and communicates with the main control chip via a simplified gigabit media independent interface (RGMII).

[0011] Preferably, the communication module further includes a program download module, the chip of which has multiple configurable independent interfaces, one of which is configured as a Joint Test Working Group (JTAG) mode, and the other two are configured as Universal Asynchronous Receiver / Transmitter (UART) modes.

[0012] Preferably, the communication module further includes an I2C module for controlling the reading and writing of some internal registers of the power module chip.

[0013] Preferably, the memory module includes: a NOR gate array (Norflash) memory module, a NAND flash memory module, and multiple DDR4 memory modules;

[0014] Half of the DDR4 memory is located on the PS side of the main control chip, and the other half is located on the PL side of the main control chip, and both are used to store the running files of the main control chip;

[0015] Both the Norflash storage module and the Nandflash storage module are used to store the boot image file of the main control chip.

[0016] Preferably, the non-logic gate array (Norflash) storage module includes multiple 256MB flash memory chips and has a four-wire I / O interface and supports a read / write speed of 133MHz.

[0017] The non-linear flash memory module includes an 8GB embedded multimedia card (eMMC) and supports read / write speeds of 400MHz.

[0018] Preferably, the clock module includes: a fixed clock module and a programmable clock module;

[0019] The fixed clock module uses a clock tree chip to output the basic clock required by the main control chip;

[0020] The programmable clock module is used to provide the main control chip with the reference clock required for communication.

[0021] Preferably, it also includes a clock daughter card connector;

[0022] The clock daughter card connector is located on the circuit board and is used to connect the clock daughter card to provide a high-speed reference clock for the main control chip.

[0023] Preferably, it also includes an RF daughter card connector;

[0024] The RF daughter card connector is located on the circuit board and is used to connect the RF daughter card for analog-to-digital and digital-to-analog converter (ADC / DAC) sampling.

[0025] Preferably, the main control chip includes a ZU43DR chip.

[0026] As can be seen from the above technical solution, the system board provided by this utility model, with the main control chip as the core, includes a memory module, a communication module, a clock module, and a power module. It supports multi-channel Ethernet module data transmission, supports storing the main control chip's running files and boot image files, supports outputting the basic clock required by the main control chip, and supports providing the reference clock required for communication with the main control chip. These functional modules can basically meet the testing work of 4D millimeter-wave radar soft IP, and are therefore suitable for the use needs of FPGA engineers. In other words, this system board can provide a good hardware platform for the testing work of 4D millimeter-wave radar soft IP. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 Circuit block diagram of the system board provided in the embodiments of this utility model;

[0029] Figure 2 A circuit block diagram of a power supply module provided for an embodiment of this utility model;

[0030] Figure 3 A block diagram showing the functional module distribution of the TOP layer in the PCB file of the system board provided in this embodiment of the utility model;

[0031] Figure 4 A block diagram of the power module distribution in the TOP layer of the system board PCB file provided for an embodiment of this utility model;

[0032] Figure 5 A block diagram of the power module distribution in the BOTTOM layer of the PCB file provided for an embodiment of this utility model.

[0033] Where A is the power supply section and B is the communication section;

[0034] 1 is the main control chip; 2 is the PL-side DDR4; 3 is the PS-side DDR4; 4 is the Norflash storage module; 5 is the Nandflash storage module; 6 is the PS-side Ethernet module; 7 is the PL-side Ethernet module; 8 is the program download module; 9 is the I2C module; 10 is the programmable clock module; 11 is the fixed clock module; 12 is the reserved clock module; 13 is the clock daughter card connector; 14 is the RF daughter card connector; 15 is the power operation indicator module; 16 is the ZYNQ status indicator module; 17 is the ZYNQ boot mode selection module; 18 is the ZYNQ delay reset module; 19 is the power input module; 20 is the 5V DC-DC module; 21 is the 3.3V DC-DC module; 22 is the fan control module; 23 is the 1.8V... The following are the power supply modules for the ZYNQ internal analog mixed-signal power supply: 24 is the PMIC module for the ZYNQ core power supply; 25 is the DCDC module for the 0.85V core power supply; 26 is the DCDC module for the ZYNQ internal analog mixed-signal power supply; 27 is the PMIC module for power supply of some serial ports and functional modules; 28 is the DCDC module for the PS-side DRAM termination matching resistor pull-up power supply; 29 is the ZYNQ Gbit serial port power supply DCDC module; 30 is the ZYNQ PS-side partial port power supply DCDC module; 31 is the DRAM DCDC power supply module; 32 is the PMIC power supply module for some serial ports and other functional modules of the ZYNQ; 33 is the DCDC module for the PL-side DRAM termination matching resistor pull-up power supply; and 34-38 are the DCDC power supply modules for the ZYNQ internal ADC / DAC. Detailed Implementation

[0035] Current development boards are functionally redundant and expensive, thus there is a need to develop system boards suitable for FPGA engineers to perform data processing; therefore, this utility model provides a system board suitable for FPGA engineers to perform data processing.

[0036] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0037] The system board provided in this embodiment of the utility model, such as Figure 1 As shown, it includes: a circuit board and a main control chip 1, a memory module, a power module, a communication module and a clock module respectively disposed on the circuit board;

[0038] The communication module includes multiple Ethernet modules, half of which are located on the PS side of the main control chip 1 and the other half are located on the PL side of the main control chip 1, and both are connected to the main control chip 1 for communication.

[0039] The power module is electrically connected to the main control chip 1, the multi-channel Ethernet module, the memory module, and the clock module, respectively.

[0040] The clock module is connected to the main control chip 1 for communication.

[0041] It should be noted that the main control chip 1, as the core chip of this system board, transmits the collected data from each functional module to ZYNQ for data processing and analysis via the data interface; the communication module may include four Ethernet modules, two of which are located on the PS side of the main control chip 1, such as... Figure 3 As shown, and serving as the PS-side Ethernet module 6, the other two Ethernet modules are located on the PL side of the main control chip 1, as follows. Figure 3 As shown, and serving as the PL-side Ethernet module 7; wherein, both the PS-side Ethernet module 6 and the PL-side Ethernet module 7 have network ports for data transmission; of course, the communication module is also used for external communication of the main control chip 1; the memory module can be used to store the running files of the main control chip 1, and can be used to store the startup image file of the main control chip 1; the clock module can be used to output the basic clock required by the main control chip 1, and can be used to provide the reference clock required for communication of the main control chip 1; such as Figure 2 As shown, the power module includes numerous PMICs (Power Management Chips) and DC-DC converters, and is used to power other modules, as detailed below;

[0042] In other words, the system board provided by this solution is based on the main control chip 1 and includes a memory module, a communication module, a clock module, and a power module. It supports multi-channel Ethernet module data transmission, supports storing the main control chip 1's running files and boot image files, supports outputting the basic clock required by the main control chip 1, and supports providing the reference clock required for communication with the main control chip 1. These functional modules can basically meet the testing work of 4D millimeter-wave radar soft IP, and are therefore suitable for the use needs of FPGA engineers. In other words, this system board can provide a good hardware platform for the testing work of 4D millimeter-wave radar soft IP.

[0043] In this solution, the Ethernet module uses a gigabit Ethernet codec chip and communicates externally via a gigabit Ethernet interface, using RGMII to communicate with the main control chip 1. Specifically, each Ethernet module (i.e., each Ethernet channel module) uses a gigabit Ethernet codec chip and connects externally via an RJ45 port. Connections to the ZYNQ are both via RGMII. The main control chip 1 encodes and decodes the acquired data and transmits it to the ZYNQ via parallel signal lines. The use of gigabit Ethernet modules is primarily due to their faster transmission speed and backward compatibility with lower speeds. The RJ45 port allows for direct connection via network cable, eliminating the need for specialized Ethernet cabling and facilitating debugging. The connection method with the ZYNQ is determined by the Ethernet chip.

[0044] Specifically, such as Figure 3 As shown, the communication module also includes a program download module 8. The chip of program download module 8 has multiple configurable independent interfaces, one of which is configured in JTAG mode, and the other two are configured in UART mode. The chip used in program download module 8 can...

[0045] It has four configurable independent interfaces, one of which is configured in JTAG mode and two of which are configured in UART mode, thus enabling USB to JTAG and UART conversion; of course, the remaining independent interfaces can be left unused.

[0046] Furthermore, such as Figure 3 As shown, the communication module also includes an I2C module 9, which is used to control the reading and writing of some internal registers of the power module chip. In addition, the I2C module 9 can use an I2C expansion chip to control multiple modules through one I2C module 9 on the PS / PL side. At the same time, the I2C module 9 can also use a level conversion chip to match the different port voltages between different modules.

[0047] Furthermore, such as Figure 3 As shown, the memory module includes: Norflash storage module 4, Nandflash storage module 5, and multiple DDR4 memory modules;

[0048] Half of the multiple DDR4 memory modules are located on the PS side of the main controller chip 1, and the other half are located on the PL side of the main controller chip 1. Both are used to store the operating files of the main controller chip 1.

[0049] Both Norflash storage module 4 and Nandflash storage module 5 are used to store the boot image file of the main control chip 1.

[0050] It should be noted that the memory module may include: one or one Nandflash storage module 5, two or two Norflash storage modules 4, and eight or eight DDR4 memory modules; wherein, one Nandflash storage module 5 and two Norflash storage modules 4 are both used to store the boot image file of the main control chip 1; such as Figure 3 As shown, four of the eight DDR4 memory modules are located on the PS side of the main controller chip 1, serving as PS-side DDR43. Each of the four DDR4 modules on the PS side contains a 1GB DRAM chip. The high-speed signal data lines are connected to Bank 65 on the PL side of the ZYNQ, while the address, command, and control signal lines are connected to Bank 66. The entire module adopts a clamshell topology, and the high-speed signal ports of the DRAM chips placed on the PCB bottom layer are mirrored. The address, command, and control ports are connected to the last DRAM chip from the ZYNQ using the same signal line, with pull-up resistors connected afterward to eliminate echo. The other four DDR4 memory modules are located on the PL side of the main controller chip 1, serving as PL-side DDR42. Each of the four DDR4 modules on the PL side contains a 2GB DRAM chip and is connected to the corresponding preset port in Bank 504 of the ZYNQ. This module adopts a fly-by topology, requiring no mirroring, and the connection method of the address, command, and control ports is consistent with that on the PL side.

[0051] In this solution, the Norflash storage module 4 contains multiple 256MB flash memory chips and has a four-wire I / O interface and supports a read / write speed of 133MHz;

[0052] The Nandflash storage module 5 includes 8GB of eMMC and supports read and write speeds of 400MHz.

[0053] The Norflash storage module 4 can contain two or more 256MB flash memory chips, and has a four-wire I / O interface and supports a maximum read and write speed of 133MHz. It is used to store the boot image of ZYNQ. ZYNQ burns the system image file into the flash through the MIO interface. After the program is solidified, the program will not be erased when the board is powered off. In addition, the Nandflash storage module 5 can use an 8GB eMMC. Its function is basically the same as that of the Norflash storage module 4, but the read speed is faster and can support a read and write speed of up to 400MHz.

[0054] Specifically, such as Figure 3 As shown, the clock module includes: a fixed clock module 11 and a programmable clock module 10;

[0055] Fixed clock module 11 uses a clock tree chip to output the basic clock required by main control chip 1;

[0056] The programmable clock module 10 is used to provide the reference clock required for communication by the master control chip 1.

[0057] It should be noted that the fixed clock module 11 can use a clock tree chip to output the basic clock required by the main control chip 1. It can be controlled by an I2C module or SPI, using a low-frequency crystal oscillator as input, and outputting multiple differential clock signals of different frequencies to the ZYNQ chip. Of course, the fixed clock module 11 is designed in this way so that it can serve as a clock reference for different functional modules. Some high-speed signals require an accompanying clock, and it is necessary to identify when a 1 is sent and when a 0 is sent.

[0058] The programmable clock module 10 is mainly used to provide the reference clock required for certain communications by the main control chip 1. The programmable clock module 10 can output a clock to the ZYNQ chip through differential signals according to the usage requirements. In addition, the programmable clock module 10 is designed to emphasize flexibility, allowing the clock frequency to be changed in real time by writing registers according to some requirements. Secondly, it is mainly used for higher clock frequencies. Furthermore, the clock module may also include a reserved clock module 12, which can be connected using an RF plug-in when needed.

[0059] Furthermore, such as Figure 3 As shown, the system board provided in this embodiment of the present invention also includes a clock daughter card connector 13;

[0060] The clock daughter card connector 13 is mounted on the circuit board and is used to connect the clock daughter card, providing a high-speed reference clock for the main control chip 1. Specifically, the clock daughter card connector 13 connects the clock daughter card and can provide the main control chip 1 with a high-speed reference clock up to 4GHz; furthermore, the clock daughter card can achieve multiple frequency multiplications through a phase-locked loop, providing the ZYQN with a high-speed differential clock signal up to 4GHz.

[0061] Furthermore, such as Figure 3 As shown, the system board provided in this embodiment of the present invention also includes an RF daughter card connector 14;

[0062] The RF daughter card connector 14 is mounted on the circuit board and is used to connect the RF daughter card for ADC / DAC sampling. For example, Figure 3 As shown, one side of the RF daughter card connector 14 is the ADC section, and the other side is the DAC section, which can support 10GHz ADC / DAC sampling. Of course, this system board includes an RF daughter card and a clock daughter card. In addition, the multi-port data transmission of the multi-channel Ethernet module and the high-speed signal sampling mentioned above can provide hardware convenience for the development of various algorithms.

[0063] Specifically, the main control chip 1 includes the ZU43DR chip.

[0064] This solution provides a high-performance system board based on the ZU43DR chip, and in particular, it relates to a high-performance system board based on the Xilinx ZU43DR chip that supports multiple Gigabit Ethernet and RF modules.

[0065] In other words, the system board provided by this solution can be based on the Zynq UltraScale+RFSoC ZU43DR chip, and includes a variety of data interfaces and power modules. The board integrates 4 Gigabit Ethernet interfaces, USB to UART and JTAG modules, a fixed clock module, a programmable clock module, and retains a high-speed clock daughter card and 4 high-speed ADC / DAC interfaces. In terms of memory, it uses 8 DDR4 memory chips, 1 eMMC chip and 2 Norflash (QSPI) chips. These functional modules can basically meet the testing work of 4D millimeter wave radar soft IP.

[0066] In summary, this solution is based on the Zynq UltraScale+RFSoC ZU43DR chip, which includes multiple data interfaces and power modules. It supports 4-channel Gigabit Ethernet data transmission, USB 2.0, JTAG, and UART communication, Norflash and eMMC boot, and 20Gbit / s ADC / DAC acquisition. It can provide a good hardware platform for the testing of 4D millimeter-wave radar soft IP.

[0067] In addition, it should be noted that, Figure 1 This is the circuit block diagram of the system board for this solution;

[0068] The system board can be divided into a power supply section A and a communication section B. The power supply section A consists of various PMICs (Power Management Chips) and DC-DC converters (DC-DC converters) to power the ZYNQ and various modules. The communication section B includes four Gigabit Ethernet interfaces, two each on the PS (Processing System) side and PL (Programmable Logic Device) side, a USB to UART (Universal Asynchronous Receiver / Transmitter) and JTAG (Joint Test Group) module, a 64Gb eMMC Nand flash memory module, two 2Gb Norflash memory modules supporting QSPI, four DDR4 chips on the PS and PL sides of the main control chip, a CLK clock section including a fixed clock module, a programmable clock module, and a high-speed clock daughter card, an RF section including four ADCs and four DACs, and an I2C module used to control the reading and writing of some internal registers of the power supply module.

[0069] Figure 2 This is the circuit block diagram of the power supply section of this solution;

[0070] UBD is the 12V power input for the entire board, supplying power to the primary power supplies PMIC1-1 / 2, DCDC-core, and DCDC-1-1~8. DCDC-1-1 supplies power to the secondary power supply PMIC-2-1, and PMIC-2-1 also outputs PWM to control the output voltage of the DCDC-core. DCDC-1-2 supplies power to the secondary power supplies DCDC-2-1~5. Specifically, UBD is power input module 19, PMIC1-1 is 27, PMIC1-2 is 31, DCDC-core is 25 and 26, DCDC-1-1 is 3.3V, DCDC module 21 is 5V, DCDC module 20 is 1.8V, and DCDC-1-3 is 1.8V. DC-CDC module 23, DC-CDC-1-4 is 28, DC-CDC-1-5 is 29, DC-CDC-1-6 is 30, DC-CDC-1-7 is 31, DC-CDC-1-8 is 33, PMIC-2-1 is the PMIC module of ZYQN core power supply 24, DC-CDC-2-1 is 37, DC-CDC-2-2 is 34, DC-CDC-2-3 is 35, DC-CDC-2-4 is 36, DC-CDC-2-5 is 38;

[0071] Figure 3 The TOP layer structure of the entire system board PCB (Printed Circuit Board) includes ZYNQ, board-to-board connectors, various functional modules and their related power supplies: among them, 13 is the clock daughter card connector for connecting the high-speed clock daughter card, 14 is the RF daughter card connector for connecting the RF daughter card, and the rest are functional modules.

[0072] Figure 4 In the TOP layer structure of the entire system board PCB, apart from module 22 which is the fan control module for cooling, the remaining modules are power supply modules such as PMIC and DC-DC. Figure 5 This represents the bottom layer structure of the entire system board PCB. 34-38 are the power supply modules for the ZYNQ's internal ADC and DAC.

[0073] The part shown in 15 is the power operation indicator module, which uses three 8-channel voltage conversion chips to convert the power good output terminals of all power modules on the board, so that when the output is high, the corresponding LEDs are lit up to indicate the status.

[0074] The part shown in Figure 16 is the ZYNQ status indicator module, which controls several states of ZYNQ through 8 switches and drives the LED to turn on and off with the signal output from the GPIO port, which is used to characterize the working status of each module on ZYNQ.

[0075] The section shown in Figure 17 is the ZYNQ boot mode selection module. The boot mode is configured by pulling up or down the ZYNQ configuration mode pin using a switch.

[0076] The part shown in Figure 18 is the ZYNQ delayed reset module, which uses a delay chip to perform delayed power-on reset and system reset of ZYNQ, and also supports manual reset.

[0077] The section shown in Figure 19 is the power input module of the entire board, which uses an N-type MOSFET power transistor as a control switch and supplies power to the system board after filtering.

[0078] The part shown in Figure 20 is the 5V DC-DC module. This module converts 12V voltage to 5V voltage and has a maximum output current of 10A. It mainly supplies power to ZYNQ's ADC / DAC power supply, clock daughter card, and RF daughter card modules.

[0079] The part shown in 21 is the 3.3V DC-DC module, which converts 12V voltage to 3.3V voltage, with a maximum output current of 15A, and mainly powers most functional modules.

[0080] The part shown in Figure 22 is the fan control module, which is used to monitor the temperature of the ZYNQ chip and automatically adjust the fan speed to dissipate heat from the chip.

[0081] The part shown in 23 is the 1.8V DC-DC module, which converts 12V voltage to 1.8V voltage and has a maximum output current of 8A. It mainly powers the ZYNQ chip.

[0082] The part shown in Figure 24 is the PMIC module of the ZYQN core power supply. It uses a digital multi-directional buck controller designed specifically for CPU voltage regulation, which is powered by 3.3V, outputs PWM to the DC-DC converter, and precisely controls the output voltage through real-time feedback.

[0083] The part shown in Figure 25 is the DC-DC module with a core power supply of 0.85V (VCCINT). Due to the large output current, this module uses two identical DC-DC chips connected in parallel. Meanwhile, the part shown in Figure 26 is the ZYNQ internal analog mixed signal power supply DC-DC module, which uses the same DC-DC chip as the core power supply of 0.85V (VCCINT_AMS). All three DC-DC modules are monitored and controlled by the PMIC module 24.

[0084] The part shown in Figure 27 is the power supply PMIC module for some serial ports and functional modules. It uses one PMIC with a 12V input to provide 1.2V voltage to the Gbit serial data port on the ZYNQ and 2.5V voltage to some modules on the system board.

[0085] Part 28 shows the DC-DC power supply module for the PS-side DRAM termination matching resistor pull-up, which uses one DC-DC chip with a 12V input to provide a 0.6V pull-up voltage for the PS-side DRAM termination matching resistor; Part 33 shows the DC-DC power supply module for the PL-side DRAM termination matching resistor pull-up, which is the same as the module shown in 28, providing a 0.6V pull-up voltage for the PL-side DRAM termination matching resistor.

[0086] The part shown in 29 is the ZYNQ Gbit serial power supply DC-DC module, which uses one DC-DC chip with a 12V input to provide 0.9V voltage to the Gbit serial data port on the ZYNQ.

[0087] The section shown in Figure 30 is the power supply DC-DC module for the ZYNQ PS side. It uses one DC-DC chip with a 12V input to provide 0.85V voltage to the VCCINT_IO and BRAM ports on the ZYNQ PS side.

[0088] The part shown in 31 is the DC-DC power module for the DRAM. It uses one DC-DC chip with a 12V input to provide 1.2V voltage to the system board, mainly to power the DRAM chip.

[0089] The part shown in Figure 32 is the PMIC power module for some serial ports and other functional modules of ZYNQ. It uses one PMIC with a 12V input. One path provides 1.13V voltage to the PS-side Ethernet, two paths provide 1.8V voltage to other functional modules of the system board, and the last path provides 1.8V voltage to the Gbit serial data port on ZYNQ.

[0090] The sections shown in 34-38 are the DC-DC power supply modules for the ZYNQ's internal ADC / DAC. They all use DC-DC converters with a 5V input and output voltages of 0.925V, 1.8V, and 2.5V respectively to power the ZYNQ's internal ADC / DAC modules.

[0091] In addition, it should be noted that this system board has simplified some modules compared to existing development boards, as detailed below:

[0092] The DDR4 module connector is removed, the two sets of FPGA PL-side clamshell topology DDR4 on the board are reduced to one set, and a new set of Flyby topology DDR4 is added on the PS side, with four memory chips on each side;

[0093] Remove the USB module;

[0094] Remove the SD card module;

[0095] Remove the system controller module;

[0096] The number of expanders and switches on the I2C bus has been reduced;

[0097] Remove the M.2 connector;

[0098] Remove the high-speed interface expansion connector on the PL side;

[0099] In addition, a new clock generator (i.e., clock module) is added to this system board as a redundant backup for the FPGA clock signal.

[0100] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0101] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system board, characterized by, include: The circuit board and the main control chip (1), memory module, power module, communication module and clock module respectively disposed on the circuit board; The communication module includes a multi-channel Ethernet module, half of which is located on the processing system PS side of the main control chip (1), and the other half of which is located on the programmable logic PL side of the main control chip (1), and both are connected to the main control chip (1) for communication. The power module is electrically connected to the main control chip (1), the multiple Ethernet modules, the memory module and the clock module respectively; The clock module is connected to the main control chip (1) for communication.

2. The system board of claim 1, wherein, The Ethernet module uses a gigabit Ethernet codec chip and communicates with the main control chip (1) via a gigabit Ethernet interface. It uses a simplified gigabit media independent interface (RGMII) to communicate with the main control chip (1).

3. The system board of claim 1, wherein, The communication module also includes a program download module (8). The chip of the program download module (8) has multiple configurable independent interfaces, one of which is configured as the Joint Test Working Group (JTAG) mode, and the other two independent interfaces are configured as the Universal Asynchronous Receiver / Transmitter (UART) mode.

4. The system board of claim 1, wherein, The communication module also includes an I2C module (9) for controlling the reading and writing of some internal registers of the power module.

5. The system board of claim 1, wherein, The memory module includes: a NOR flash memory module (4), a NAND flash memory module (5), and multiple DDR4 memory modules; Half of the DDR4 memory is located on the PS side of the main control chip (1), and the other half is located on the PL side of the main control chip (1), and both are used to store the running files of the main control chip (1); The Norflash storage module (4) and the Nandflash storage module (5) are both used to store the boot image file of the main control chip (1).

6. The system board of claim 5, wherein, The non-logic gate array structure flash memory module (4) contains multiple 256MB flash memory chips and has a four-wire IO interface and supports a read and write speed of 133MHz; The non-linear flash memory module (5) includes an 8GB embedded multimedia card eMMC and supports a read / write speed of 400MHz.

7. The system board of claim 1, wherein, The clock module includes: a fixed clock module (11) and a programmable clock module (10). The fixed clock module (11) uses a clock tree chip to output the basic clock required by the main control chip (1); The programmable clock module (10) is used to provide the reference clock required for communication by the main control chip (1).

8. The system board of claim 1, wherein, It also includes a clock daughter card connector (13); The clock daughter card connector (13) is disposed on the circuit board and is used to connect the clock daughter card to provide a high-speed reference clock for the main control chip (1).

9. The system board of claim 1, wherein, It also includes an RF daughter card connector (14); The radio frequency sub-card connector (14) is arranged on the circuit board and is used for connecting a radio frequency sub-card for analog-digital and digital-analog conversion ADC / DAC sampling.

10. The system board of claim 1, wherein, The master control chip (1) comprises a ZU43DR chip.

Images