An MPS pin control circuit to prevent SBC reset function failure due to MCU crash.

Abstract

This utility model discloses an MPS pin control circuit to prevent MCU crashes from causing SBC reset function failure. It includes an SBC chip and a control circuit, which comprises a DC blocking capacitor C1, a diode D1, a capacitor C2, a field-effect transistor Q1, and a field-effect transistor Q2. This MPS pin control circuit utilizes the characteristic that an MCU only outputs a constant high or low level when it crashes. By constructing a specific circuit, it solves the problem that when the MCU crashes, the signals emitted by the MCU are uncontrolled, causing the MPS pin level to be pulled high and preventing the MCU from sending a reset signal.

Description

Technical Field

[0001] This utility model belongs to the field of MCU reset technology, specifically relating to an MPS pin control circuit that prevents the SBC reset function from failing due to MCU crash. Background Technology

[0002] The SBC chip TLF35584 is a system foundation chip that can power the MCU of the motor controller in new energy vehicles and also use its own watchdog circuit to monitor whether the MCU is working properly.

[0003] The MPS pin is a control pin of the TLF35584. During software development, connecting the MPS pin high puts the chip into debug mode, disabling its watchdog and fault monitoring functions. In this mode, even if the MCU malfunctions, the TLF35584 will not reset the MCU, and the fault register is retained, facilitating troubleshooting. After software development is complete and the product enters mass production, connecting the MPS pin low enables its watchdog and fault monitoring functions. In this mode, if the MCU malfunctions, the TLF35584 will reset the MCU, allowing the product to resume operation.

[0004] like Figure 2 As shown, an MPS control circuit is built using N-MOSFETs. When the MCU outputs a low level, the N-MOSFET is in the off state, the MPS pin is pulled high, and the TLF35584 enters debug mode. When the MCU outputs a high level, the N-MOSFET is in the on state, the MPS pin is pulled low, and the MCU status can be monitored. In case of a fault, the MCU can be reset by sending a Reset signal.

[0005] However, if the MCU malfunctions and crashes, the signals emitted by the MCU become uncontrollable, potentially remaining at a constant low or high level. If the MCU emits a low level at this time, the MPS pin will be pulled high, and the TLF35584 will enter debug mode, disabling its watchdog and fault monitoring functions. Under these conditions, the TLF35584 cannot detect the MCU malfunction, nor can it reset the MCU, preventing the product from resuming operation.

[0006] Therefore, further improvements will be made to address the aforementioned issues. Utility Model Content

[0007] The main purpose of this invention is to provide an MPS pin control circuit that prevents the SBC reset function from failing due to MCU crash. By utilizing the characteristic that the MCU will only send a constant high level or a constant low level when it crashes, a specific circuit is built to solve the problem that when the MCU crashes, the signal sent by the MCU is uncontrolled, causing the MPS pin level to be pulled high and unable to send a reset signal to the MCU.

[0008] To achieve the above objectives, this utility model provides an MPS pin control circuit to prevent MCU crashes from causing the SBC reset function to fail, including an SBC chip and a control circuit, wherein:

[0009] The control circuit includes a DC blocking capacitor C1, a diode D1, a capacitor C2, a field-effect transistor Q1, and a field-effect transistor Q2. The first end of the DC blocking capacitor C1 is electrically connected to the output terminal (MCU_Output) of the MCU, and the second end of the DC blocking capacitor C1 is electrically connected to the anode of the diode D1. One cathode of the diode D1 is grounded through the capacitor C2, and the other cathode is electrically connected to the gate of the field-effect transistor Q1.

[0010] The source of the field-effect transistor Q1 is grounded through resistor R1, and the drain of the field-effect transistor Q1 is electrically connected to the gate of the field-effect transistor Q2. The drain of the field-effect transistor Q2 is electrically connected to the MPS pin of the SBC chip, and the SBC chip is electrically connected to the reset pin of the MCU.

[0011] As a further preferred embodiment of the above technical solution, a resistor R2 is connected between the gate and source of the field-effect transistor Q2.

[0012] As a further preferred embodiment of the above technical solution, the source of the field-effect transistor Q2 is also connected to a power supply terminal (5V).

[0013] As a further preferred embodiment of the above technical solution, the drain of the field-effect transistor Q2 is also grounded through resistor R3.

[0014] As a further preferred technical solution to the above technical solution, the SBC chip model is TLF35584. Attached Figure Description

[0015] Figure 1 This is the control circuit diagram of this utility model.

[0016] Figure 2 It is an existing control circuit diagram. Detailed Implementation

[0017] The following description is intended to disclose the present invention so that those skilled in the art can implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the present invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.

[0018] This utility model discloses an MPS pin control circuit to prevent the SBC reset function from failing due to MCU crash. The specific embodiments of the utility model are further described below with reference to preferred embodiments.

[0019] In the embodiments of this utility model, those skilled in the art will note that the MCU and the like involved in this utility model can be considered as prior art.

[0020] Preferred embodiment.

[0021] like Figure 1 As shown, this utility model discloses an MPS pin control circuit to prevent the SBC reset function from failing due to MCU crashes, including an SBC chip and a control circuit, wherein:

[0022] The control circuit includes a DC blocking capacitor C1, a diode D1, a capacitor C2, a field-effect transistor Q1, and a field-effect transistor Q2. The first end of the DC blocking capacitor C1 is electrically connected to the output terminal (MCU_Output) of the MCU, and the second end of the DC blocking capacitor C1 is electrically connected to the anode of the diode D1. One cathode of the diode D1 is grounded through the capacitor C2, and the other cathode is electrically connected to the gate of the field-effect transistor Q1.

[0023] The source of the field-effect transistor Q1 is grounded through resistor R1, and the drain of the field-effect transistor Q1 is electrically connected to the gate of the field-effect transistor Q2. The drain of the field-effect transistor Q2 is electrically connected to the MPS pin of the SBC chip, and the SBC chip is electrically connected to the reset pin of the MCU.

[0024] Specifically, a resistor R2 is connected between the gate and source of the field-effect transistor Q2.

[0025] More specifically, the source of the field-effect transistor Q2 is also connected to a power supply terminal (5V).

[0026] Furthermore, the drain of the field-effect transistor Q2 is grounded through resistor R3.

[0027] Furthermore, the SBC chip model is TLF35584.

[0028] Regarding this utility model:

[0029] like Figure 1 As shown. During product development, the SBC chip needs to operate in debug mode. In this mode, the MCU outputs a PWM wave with a frequency of 1kHz and a duty cycle of 50%. The DC component in the PWM wave is filtered out by the DC blocking capacitor C1. After passing through the unidirectional conduction diode D1, capacitor C2 is charged. At this time, capacitor C2 acts as a DC voltage source. Appropriate parameters are selected to ensure that the voltage across capacitor C2 is stable at the Q1 turn-on voltage. VGSth Once the conduction conditions of Q1 are met, Q2 will conduct, the MPS pin will be pulled high to 5V, and the system will enter debug mode.

[0030] Table 1 MPS Output Status Table When SBC Chip is in Debug Mode

[0031]

[0032] When the product enters the mass production stage, the SBC needs to work in monitoring mode. At this time, the MCU will only send a constant low level or a constant high level, regardless of whether it is in normal working state or fault state. Due to the effect of the DC blocking capacitor C1, the signal cannot pass through C1, the gate voltage of Q1 is always 0, and both Q1 and Q2 will be in the off state. Therefore, the MPS pin is always low level, and the SBC works in monitoring mode.

[0033] Table 2 MPS Output Status Table When SBC Chip is in Monitoring Mode

[0034]

[0035] This invention effectively solves the problem that the output level is uncontrollable when the MCU crashes, causing the SBC to be unable to reset the MCU, thus increasing the stability and safety of new energy vehicles.

[0036] It is worth mentioning that the MCU and other technical features involved in this utility model patent application should be regarded as prior art. The specific structure, working principle, and possible control methods and spatial arrangement of these technical features can be adopted using conventional choices in the field, and should not be regarded as the inventive point of this utility model patent. This utility model patent will not elaborate further.

[0037] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. An MPS pin control circuit for preventing MCU hang causing SBC reset function failure, characterized in that, Includes the SBC chip and control circuitry, among which: The control circuit includes a DC blocking capacitor C1, a diode D1, a capacitor C2, a field-effect transistor Q1, and a field-effect transistor Q2. The first end of the DC blocking capacitor C1 is electrically connected to the output terminal of the MCU, and the second end of the DC blocking capacitor C1 is electrically connected to the anode of the diode D1. One cathode of the diode D1 is grounded through the capacitor C2, and the other cathode is electrically connected to the gate of the field-effect transistor Q1. The source of the field-effect transistor Q1 is grounded through resistor R1, and the drain of the field-effect transistor Q1 is electrically connected to the gate of the field-effect transistor Q2. The drain of the field-effect transistor Q2 is electrically connected to the MPS pin of the SBC chip, and the SBC chip is electrically connected to the reset pin of the MCU.

2. The MPS pin control circuit for preventing the SBC reset function from failing due to MCU hang according to claim 1, wherein, A resistor R2 is connected between the gate and source of the field-effect transistor Q2.

3. The MPS pin control circuit that prevents the MCU hang-up from causing the SBC reset function to fail according to claim 2, characterized in that, The source of the field-effect transistor Q2 is also connected to the power supply terminal.

4. The MPS pin control circuit for preventing the SBC reset function from failing due to MCU hang according to claim 3, wherein, The drain of the field-effect transistor Q2 is also grounded through resistor R3.

5. The MPS pin control circuit that prevents the MCU hang causing the SBC reset function from failing according to claim 4, wherein, The SBC chip model is TLF35584.

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