A debugging interface adapter

Abstract

This utility model relates to the field of PCIe card interface technology and discloses a debugging interface adapter device, including an adapter board. One side of the adapter board has an adapter connector, which includes multiple connection points. The adapter board has a JTAG interface unit, a UART interface unit, an RJ45 interface unit, and a USB interface unit. The terminals in the JTAG, UART, RJ45, and USB interface units used for communication are electrically connected to the connection points of the adapter connector. In practical use, this utility model connects electrically to the PCIe card via the adapter connector to achieve USB, UART, and network communication on the PCIe card. This eliminates the need to set up USB, UART, and network interfaces on the PCIe card, thus ensuring a simple layout. Furthermore, since each PCIe card does not need these interfaces, the circuitry on the PCIe card is reduced, resulting in lower costs. Finally, the absence of an RJ45 interface directly obstructing the heat dissipation channel of the PCIe card improves its heat dissipation performance.

Description

Technical Field

[0001] This utility model relates to the field of PCIE board interface technology, and specifically to a debugging interface adapter. Background Technology

[0002] PCIe cards are expansion cards based on the PCIe (Peripheral Component Interconnect Express) bus standard, used to enable high-speed data transmission and communication between computers and external devices, and are widely used in fields such as industrial automation.

[0003] The existing PCIe specification requires half-height, half-length PCIe boards to be no larger than 68.9mm x 167.6mm. However, in current half-height, half-length PCIe board designs, debugging interfaces such as JTAG (Joint Test Action Group), UART (Universal Asynchronous Receiver / Transmitter), RJ45, and USB are typically integrated directly onto the board's PCB. This leads to the following problems when using existing PCIe boards: First, debugging interfaces, such as RJ45 connectors, have a large physical size. Forcing them onto PCIe boards with limited edge space will occupy high-speed signal routing areas or critical component locations, making PCB layout difficult. Moreover, dense interface distribution will increase the structural complexity of the PCIe board and affect the expandability of other modules. Second: Protruding interfaces on PCIe cards, such as RJ45 interfaces, with a height greater than 13m, will block the horizontal airflow inside the chassis and reduce heat dissipation efficiency, especially in high-density servers with multiple PCIe cards installed in parallel. Third: In multi-PCIe board application scenarios, since each PCIe board needs to independently deploy debugging interface circuits including PHY chips, transformers and filters, this repetitive design leads to increased material costs, and the utilization rate of debugging interfaces is low in most scenarios. Fourth: Poor maintenance and expandability in actual use. When debugging applications with multiple PCIe cards, cables need to be connected separately, which is cumbersome and prone to errors. Utility Model Content

[0004] In view of the shortcomings of the prior art, the present invention provides a debugging interface adapter device that eliminates the need to integrate interfaces such as JTAG, UART, RJ45 and USB on the PCIe board, thereby making the layout of the PCIe board simpler, the heat dissipation better, the cost lower and the use more convenient.

[0005] To solve the above technical problems, this utility model provides the following technical solution: a debugging interface adapter, including an adapter board; an adapter is provided on one side of the adapter board, the adapter including multiple connection points; the adapter board is provided with a JTAG interface unit, a UART interface unit, an RJ45 interface unit and a USB interface unit, and the terminals of the JTAG interface unit, UART interface unit, RJ45 interface unit and USB interface unit used for communication are electrically connected to the connection points of the adapter.

[0006] In one embodiment, the adapter has a gold finger structure.

[0007] In one embodiment, the JTAG interface unit and the UART interface unit are located on the same side of the adapter board and are arranged opposite to the USB interface unit; the RJ45 interface unit is arranged opposite to the adapter on the adapter board.

[0008] In one embodiment, the RJ45 interface unit includes an RJ45 interface and a protocol conversion unit, wherein the RJ45 interface is electrically connected to the adapter point on the adapter through the protocol conversion unit.

[0009] In one embodiment, the protocol conversion unit includes a PHY chip of model RTL8211E.

[0010] In one embodiment, the USB interface unit includes a USB interface and a USB transceiver unit, wherein the USB interface is electrically connected to an adapter point on the adapter via the USB transceiver unit.

[0011] In one embodiment, the USB transceiver unit includes a USB transceiver chip U115 of model number USB3320C and a crystal oscillator unit. The crystal oscillator unit is used to provide clock signals to pins 25 and 26 of the USB transceiver chip U115; Pin 32 of the USB transceiver chip U115 is used to connect to a 1.8V DC voltage; pins 29, 2, 31, 1, 3, 4, 5, 6, 7, 9, 10, and 13 of the USB transceiver chip U115 are electrically connected to the adapter points on the adapter. Pin 24 of the USB transceiver chip U115 is electrically connected to one end of resistor R894, and the other end of resistor R894 and pin 33 of the USB transceiver chip U115 are both grounded. Pins 8, 11, 14, 28, and 30 of the USB transceiver chip U115 are used to input a 1.8V DC voltage; pin 21 of the USB transceiver chip U115 is used to input a 3.3V DC voltage. Pin 23 of the USB transceiver chip U115 is electrically connected to one end of resistor R892 and one end of resistor R893, respectively. The other end of resistor R892 is grounded, and the other end of resistor R893 is electrically connected to pin 20 of the USB transceiver chip U115 and grounded through capacitor C621. Pin 27 of the USB transceiver chip U115 is electrically connected to one end of resistor R890 and one end of capacitor C616, respectively. The other end of resistor R890 is used to input 1.8V DC voltage, and the other end of capacitor C616 is grounded. Pins 19 and 18 of the USB transceiver chip U115 are electrically connected to the D- and D+ terminals of the USB interface, respectively. Pin 22 of the USB transceiver chip U115 is electrically connected to one end of resistor R886. The other end of resistor R886 is electrically connected to one end of resistor R887 and the VCC terminal of the USB interface, and is grounded through capacitors C607 and C608, respectively. The other end of resistor R887 is electrically connected to pin 1 of the TPS2051BDBV switching power supply chip U114. Pin 3 of the switching power supply chip U114 is connected to a 3.3V DC voltage through resistor R888. Pin 5 of the switching power supply chip U114 is used to input a 5V DC voltage, and is grounded through capacitors C609, C622, and C623, respectively. Pin 4 of the switching power supply chip U114 is electrically connected to pin 17 of the USB transceiver chip U115, and is grounded through resistor R889. Pin 2 of the switching power supply chip U114 is grounded.

[0012] In one embodiment, the UART interface unit includes a four-terminal interface J7. Pins 1 and 2 of the four-terminal interface J7 are electrically connected to the adapter points on the adapter, and pin 3 of the four-terminal interface J7 is also electrically connected to the ground via a TVS diode D213. Pin 2 of the four-terminal interface J7 is also electrically connected to the ground via a TVS diode D216.

[0013] In one embodiment, the JTAG interface unit includes a connector J4 of model number 87832-1420. Pins 1, 3, 5, 7, 9, 11, and 13 of the connector J4 are all grounded. Pin 2 of the connector J4 is used to connect to a 3.3V DC voltage. Pins 4, 6, 8, and 10 of the connector J4 are pulled up and electrically connected to pin 2 of the connector J4 through resistors R280, R281, R282, and R283, respectively.

[0014] In one embodiment, the adapter board is also provided with a connector J10 of model number G97R21322HR. The connection terminals of the connector J10 are electrically connected to the adapter terminals on the adapter for LVDS communication and PCIE signal expansion. The connector J10 and the USB interface unit are located on the same side of the adapter board.

[0015] The advantages of this invention compared to existing technologies are as follows: In practical use, this invention connects to the PCIe board via an adapter to enable USB, UART, and Ethernet communication. This eliminates the need to install USB, UART, and Ethernet interfaces on the PCIe board itself, thus ensuring a simple layout. Furthermore, since these interfaces are not required on each PCIe board, the circuitry on the board is reduced, resulting in lower costs. Finally, the absence of an RJ45 interface directly obstructing the heat dissipation channel of the PCIe board improves its heat dissipation performance. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the present invention in the embodiments; Figure 2 This is a schematic diagram illustrating the connection between the present invention and the PCIe board in the embodiment; Figure 3 This is a circuit diagram of the protocol conversion unit in the embodiment; Figure 4 This is a circuit diagram of the RJ45 interface in the embodiment; Figure 5 This is a circuit diagram of some of the USB transceiver units and USB interfaces in the embodiment; Figure 6 This is a circuit diagram of the remaining USB transceiver unit in the embodiment; Figure 7 This is a circuit diagram of the UART interface unit in the embodiment; Figure 8 This is a circuit diagram of the JTAG interface unit in the embodiment; Figure 9 This is a circuit diagram of connector J10 in the embodiment; Figure 10 This is a schematic diagram of the terminal distribution of the adapter in the embodiment. Detailed Implementation

[0017] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the present invention, and therefore only show the components relevant to the present invention.

[0018] like Figure 1 As shown, this embodiment provides a debugging interface adapter device, including an adapter board 1; an adapter 2 is provided on one side of the adapter board 1, and the adapter 2 includes multiple adapter points; the adapter board 1 is provided with a JTAG interface unit 6, a UART interface unit 3, an RJ45 interface unit 4 and a USB interface unit 5, and the terminals in the JTAG interface unit 6, UART interface unit 3, RJ45 interface unit 4 and USB interface unit 5 used for communication are electrically connected to the adapter points of the adapter.

[0019] Specifically, in this embodiment, the adapter 2 is a gold finger structure, and its adapter point distribution and definition are as follows: Figure 10 As shown, there are a total of 74 transfer points.

[0020] Specifically, in this embodiment, the adapter board 1 is also equipped with a connector J10, the connection terminals of which are electrically connected to the adapter terminals on the adapter 2 for LVDS communication and PCIe signal expansion. Furthermore, the circuitry of connector J10 is as follows: Figure 9 As shown, the model number is G97R21322HR.

[0021] In this embodiment, the distribution of JTAG interface unit 6, UART interface unit 3, RJ45 interface unit 4, USB interface unit 5, and connector J10 on adapter board 1 is as follows: JTAG interface unit 6 and UART interface unit 3 are located on the same side of the adapter board 1 and are opposite to USB interface unit 5. Connector J10 and USB interface unit 5 are located on the same side of the adapter board 1. RJ45 interface unit 4 is opposite to the adapter on the adapter board.

[0022] A schematic diagram of the connection between this utility model and a PCIe board is shown below. Figure 2As shown, in practical use, this invention connects to the PCIe board via adapter 2 to enable USB, UART, and Ethernet communication. This eliminates the need to install USB, UART, and Ethernet interfaces on the PCIe board itself, thus keeping the layout simple. Furthermore, since each PCIe board does not require these interfaces, the circuitry on the board is reduced, resulting in lower costs. Finally, the absence of an RJ45 connector directly obstructing the PCIe board improves heat dissipation.

[0023] Specifically, in this embodiment, in Figure 1 In the middle, the RJ45 interface unit 4 includes an RJ45 interface and a protocol conversion unit. The RJ45 interface is electrically connected to the conversion point on the adapter 2 through the protocol conversion unit.

[0024] More specifically, in this embodiment, the circuit of the protocol conversion unit is as follows: Figure 3 As shown, it includes a PHY chip of model RTL8211E; the RJ45 interface circuit is as follows. Figure 4 As shown, its model number is HR911130A.

[0025] In one implementation, other models of PHY chips and other models of RJ45 interfaces can be selected according to actual needs.

[0026] Specifically, in this embodiment, in Figure 1 In the middle, the USB interface unit 5 includes a USB interface and a USB transceiver unit. The USB interface is electrically connected to the adapter point on the adapter through the USB transceiver unit.

[0027] More specifically, in this embodiment, the circuit of the USB transceiver unit is as follows: Figure 6 and 7 As shown, the USB transceiver unit package includes a USB transceiver chip U115 (model USB3320C) and a crystal oscillator unit 50. The crystal oscillator unit 50 is used to provide clock signals to pins 25 and 26 of the USB transceiver chip U115; Pin 32 of the USB transceiver chip U115 is used to connect to a 1.8V DC voltage; pins 29, 2, 31, 1, 3, 4, 5, 6, 7, 9, 10, and 13 of the USB transceiver chip U115 are electrically connected to the adapter points on the adapter. Pin 24 of the USB transceiver chip U115 is electrically connected to one end of resistor R894, while the other end of resistor R894 and pin 33 of the USB transceiver chip U115 are both grounded. Pins 8, 11, 14, 28, and 30 of the USB transceiver chip U115 are used to input a 1.8V DC voltage; pin 21 of the USB transceiver chip U115 is used to input a 3.3V DC voltage. Pin 23 of the USB transceiver chip U115 is electrically connected to one end of resistor R892 and one end of resistor R893 respectively. The other end of resistor R892 is grounded, and the other end of resistor R893 is electrically connected to pin 20 of the USB transceiver chip U115 and grounded through capacitor C621. Pin 27 of the USB transceiver chip U115 is electrically connected to one end of resistor R890 and one end of capacitor C616, respectively. The other end of resistor R890 is used to input 1.8V DC voltage, and the other end of capacitor C616 is grounded. Pins 19 and 18 of the USB transceiver chip U115 are electrically connected to the D- and D+ terminals of the USB interface, respectively. Pin 22 of the USB transceiver chip U115 is electrically connected to one end of resistor R886. The other end of resistor R886 is electrically connected to one end of resistor R887 and the VCC terminal of the USB interface, and is grounded through capacitors C607 and C608, respectively. The other end of resistor R887 is electrically connected to pin 1 of the TPS2051BDBV switching power supply chip U114. Pin 3 of the switching power supply chip U114 is connected to a 3.3V DC voltage through resistor R888. Pin 5 of the switching power supply chip U114 is used to input a 5V DC voltage, and is grounded through capacitors C609, C622, and C623, respectively. Pin 4 of the switching power supply chip U114 is electrically connected to pin 17 of the USB transceiver chip U115, and is grounded through resistor R889. Pin 2 of the switching power supply chip U114 is grounded.

[0028] In one implementation, other models of USB transceiver chips can be selected based on actual needs.

[0029] Specifically, in this embodiment, the circuit of the UART interface unit 3 is as follows: Figure 7 As shown, it includes a four-terminal interface J7. Pins 1 and 2 of the four-terminal interface J7 are electrically connected to the adapter points on the adapter. The four-terminal interface J7 is also electrically connected to pin 3 of the four-terminal interface J7 through a TVS diode D213 and is grounded. Pin 2 of the four-terminal interface J7 is electrically connected to pin 4 of the four-terminal interface J7 through a TVS diode D216 and is grounded.

[0030] Specifically, in this embodiment, the circuit of the JTAG interface unit 6 is as follows: Figure 8As shown, connector J4, model number 87832-1420, has pins 1, 3, 5, 7, 9, 11, and 13 grounded. Pin 2 of connector J4 is used to connect to a 3.3V DC voltage. Pins 4, 6, 8, and 10 of connector J4 are pulled up and electrically connected to pin 2 of connector J4 through resistors R280, R281, R282, and R283, respectively.

[0031] Based on the above description and inspired by this utility model, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A debugging interface adapter, characterized in that, The adapter board includes an adapter plate; one side of the adapter board is provided with an adapter, which includes multiple connection points; the adapter board is provided with a JTAG interface unit, a UART interface unit, an RJ45 interface unit and a USB interface unit, and the terminals of the JTAG interface unit, UART interface unit, RJ45 interface unit and USB interface unit used for communication are electrically connected to the connection points of the adapter.

2. The debug interface tap device of claim 1, wherein, The adapter has a gold finger structure.

3. The debug interface tap device of claim 1, wherein, The JTAG interface unit and the UART interface unit are located on the same side of the adapter board and are opposite to the USB interface unit; the RJ45 interface unit is opposite to the adapter on the adapter board.

4. A debug interface conversion device according to any one of claims 1 to 3, characterized in that, The RJ45 interface unit includes an RJ45 interface and a protocol conversion unit. The RJ45 interface is electrically connected to the adapter point on the adapter through the protocol conversion unit.

5. A debug interface conversion device according to claim 4, wherein, The protocol conversion unit includes a PHY chip of model RTL8211E.

6. A debug interface conversion device according to any one of claims 1 to 3, wherein The USB interface unit includes a USB interface and a USB transceiver unit, and the USB interface is electrically connected to the adapter point on the adapter through the USB transceiver unit.

7. The debug interface tap device of claim 5, wherein, The USB transceiver unit includes a USB transceiver chip U115 (model USB3320C) and a crystal oscillator unit. The crystal oscillator unit is used to provide clock signals to pins 25 and 26 of the USB transceiver chip U115; Pin 32 of the USB transceiver chip U115 is used to connect to a 1.8V DC voltage; pins 29, 2, 31, 1, 3, 4, 5, 6, 7, 9, 10, and 13 of the USB transceiver chip U115 are electrically connected to the adapter points on the adapter. Pin 24 of the USB transceiver chip U115 is electrically connected to one end of resistor R894, and the other end of resistor R894 and pin 33 of the USB transceiver chip U115 are both grounded. Pins 8, 11, 14, 28, and 30 of the USB transceiver chip U115 are used to input a 1.8V DC voltage; pin 21 of the USB transceiver chip U115 is used to input a 3.3V DC voltage. Pin 23 of the USB transceiver chip U115 is electrically connected to one end of resistor R892 and one end of resistor R893, respectively. The other end of resistor R892 is grounded, and the other end of resistor R893 is electrically connected to pin 20 of the USB transceiver chip U115 and grounded through capacitor C621. Pin 27 of the USB transceiver chip U115 is electrically connected to one end of resistor R890 and one end of capacitor C616, respectively. The other end of resistor R890 is used to input 1.8V DC voltage, and the other end of capacitor C616 is grounded. Pins 19 and 18 of the USB transceiver chip U115 are electrically connected to the D- and D+ terminals of the USB interface, respectively. Pin 22 of the USB transceiver chip U115 is electrically connected to one end of resistor R886. The other end of resistor R886 is electrically connected to one end of resistor R887 and the VCC terminal of the USB interface, and is grounded through capacitors C607 and C608, respectively. The other end of resistor R887 is electrically connected to pin 1 of the TPS2051BDBV switching power supply chip U114. Pin 3 of the switching power supply chip U114 is connected to a 3.3V DC voltage through resistor R888. Pin 5 of the switching power supply chip U114 is used to input a 5V DC voltage, and is grounded through capacitors C609, C622, and C623, respectively. Pin 4 of the switching power supply chip U114 is electrically connected to pin 17 of the USB transceiver chip U115, and is grounded through resistor R889. Pin 2 of the switching power supply chip U114 is grounded.

8. A debugging interface adapter according to any one of claims 1-3, characterized in that, The UART interface unit includes a four-terminal interface J7. Pins 1 and 2 of the four-terminal interface J7 are electrically connected to the adapter points on the adapter. Pin 3 of the four-terminal interface J7 is also electrically connected to the adapter via a TVS diode D213 and is grounded. Pin 2 of the four-terminal interface J7 is also electrically connected to pin 4 of the four-terminal interface J7 via a TVS diode D216 and is grounded.

9. A debug interface conversion device according to any one of claims 1 to 3, wherein The JTAG interface unit includes a connector J4 with model number 87832-1420. Pins 1, 3, 5, 7, 9, 11, and 13 of the connector J4 are all grounded. Pin 2 of the connector J4 is used to connect to a 3.3V DC voltage. Pins 4, 6, 8, and 10 of the connector J4 are pulled up and electrically connected to pin 2 of the connector J4 through resistors R280, R281, R282, and R283, respectively.

10. A debug interface conversion device according to any one of claims 1 to 3, wherein The adapter board is also equipped with a connector J10 of model G97R21322HR. The connection terminals of the connector J10 are electrically connected to the adapter terminals on the adapter for LVDS communication and PCIE signal expansion. The connector J10 and the USB interface unit are located on the same side of the adapter board.

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