A communication module control circuit

Abstract

This utility model relates to the field of communication technology, and in particular to a communication module control circuit, including a first communication module for level conversion and bidirectional communication with a first bus, having a first bus A line and a first bus B line; a second communication module for level conversion and dual-channel communication with a second bus; a first external interface electrically connected to the A and B lines of the first communication module; a second external interface electrically connected to the transmit / receive path of the second communication module; and a control power supply, connected to the first and second communication modules respectively, providing DC power. The first and second communication modules can be adapted to external devices of different bus types, and flexible docking with external devices is achieved through the first and second external interfaces. At the same time, the control power supply provides unified power to both modules, simplifying the circuit structure, improving integration, and reducing wiring complexity and design costs.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, and in particular to a communication module control circuit. Background Technology

[0002] In multi-bus communication scenarios, achieving compatible control across different buses is a key requirement for device interconnection. Traditional solutions often employ independent designs for communication functions on different buses: each bus has its own communication module, including independent level conversion components, signal interfaces, and power supply circuits. This distributed architecture results in multiple independent power supply, signal processing, and interface units within the circuit, leading to a bulky overall structure, large space occupation, and hindering device miniaturization. Furthermore, the lack of collaborative design between modules, with dispersed power supply circuits and cluttered signal interface layouts, increases wiring complexity and electromagnetic interference risks, affecting communication stability. The redundant design of independent modules also increases hardware costs and maintenance difficulty. These problems are particularly pronounced in scenarios requiring simultaneous support for two bus communications: the parallel setup of two independent communication modules results in low circuit integration and poor resource utilization, failing to meet the requirements of modern devices for compact structure, stable performance, and low cost. Therefore, how to integrate the communication functions of two buses into a single control circuit through integrated design, sharing power supply and interface resources, simplifying the structure, and improving stability has become the core direction for solving the multi-bus compatibility control problem. Utility Model Content

[0003] The purpose of this invention is to provide a communication module control circuit to solve the problems existing in the prior art.

[0004] The above-mentioned technical objective of this utility model is achieved through the following technical solution:

[0005] A communication module control circuit, comprising:

[0006] The first communication module is used to realize level conversion and bidirectional communication with the first bus, and is provided with a first bus A line and a first bus B line;

[0007] The second communication module is used to realize level conversion and dual-channel communication with the second bus;

[0008] The first external interface is electrically connected to the A and B lines of the first communication module;

[0009] The second external interface is electrically connected to the transmit / receive path of the second communication module;

[0010] The control power supply is connected to the first communication module and the second communication module respectively, providing DC power.

[0011] By adopting the above technical solution, the first communication module and the second communication module can be adapted to external devices of different bus types respectively. They can flexibly connect with external devices through the first external interface and the second external interface. At the same time, the control power supply provides unified power to the two modules, which simplifies the circuit structure, improves the integration, and reduces the wiring complexity and design cost.

[0012] In a further embodiment, the first communication module includes a first chip with pin 17 receiving output terminal, pin 18 power supply terminal, pin 19 receiving enable terminal, pin 20 bus B terminal, pin 21 drive enable terminal, pin 22 bus A terminal, and pin 24 ground terminal; a first capacitor for power supply filtering of the first chip; a first resistor, one end of which is connected to pin 17 of the first chip; a second resistor, one end of which is connected to pin 20 of the first chip; a third resistor, one end of which is connected to pin 22 of the first chip; a fourth resistor, one end of which is connected to pin 19 of the first chip; a fifth resistor, one end of which is connected to pin 21 of the first chip; a sixth resistor, one end of which is connected to pin 20 of the first chip; a seventh resistor, one end of which is connected to pin 22 of the first chip; an eighth resistor, one end of which is connected to the other end of the seventh resistor; a first diode, one pin of which is connected to the first bus A line; and a second diode, one pin of which is connected to the first bus B line.

[0013] By adopting the above technical solution, the first chip serves as the core to realize level conversion, the first capacitor realizes power supply filtering to ensure stable operation of the chip, the first to fifth resistors respectively provide current limiting protection for each key pin of the chip, the sixth to eighth resistors play a role in voltage division and stabilization, the first and second diodes realize overvoltage protection for bus signals, and the overall structure can reliably realize bidirectional communication with the first bus, improving the stability and anti-interference capability of the circuit.

[0014] In a further embodiment, the other end of the first resistor is led out; one end of the first chip pin 18 is connected to the control power supply, the other end of the first chip is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; the other end of the fourth resistor is led out; the other end of the second resistor is connected to the first bus line B, and the other end of the sixth resistor is grounded; the other end of the fifth resistor is led out; the other end of the third resistor is connected to the first bus line A, and the other end of the eighth resistor is grounded; the first chip pin 24 is grounded; the other two pins of the first diode are connected to the control power supply and ground, respectively; the other two pins of the second diode are connected to the control power supply and ground, respectively.

[0015] In a further embodiment, the second communication module includes: a second chip, the second chip having pins 1 (charge pump positive terminal), 2 (charge pump positive voltage terminal), 3 (charge pump negative terminal), 4 (charge pump positive terminal), 5 (charge pump negative terminal), 6 (charge pump negative voltage terminal), 7 (first receive output terminal), 8 (second receive output terminal), 10 (second transmit input terminal), 11 (first transmit input terminal), 15 (ground terminal), and 16 (power supply terminal); a second capacitor, one end of the second capacitor being connected to pin 1 of the second chip; a third capacitor, one end of the third capacitor being connected to pin 4 of the second chip; a fourth capacitor, one end of the fourth capacitor being connected to pin 2 of the second chip; a fifth capacitor, one end of the fifth capacitor being connected to pin 2 of the second chip; a sixth capacitor, one end of the sixth capacitor being connected to pin 6 of the second chip; a ninth resistor, one end of the ninth resistor being connected to pin 7 of the second chip; a tenth resistor, one end of the tenth resistor being connected to pin 8 of the second chip; an eleventh resistor, one end of the eleventh resistor being connected to pin 11 of the second chip; and a twelfth resistor, one end of the twelfth resistor being connected to pin 10 of the second chip.

[0016] By adopting the above technical solution, the components of the second communication module work together to realize dual-channel communication of the second bus: the second chip is the core, and its charge pump related pins, together with the second and third capacitors, form a charge pump circuit. The fourth, fifth, and sixth capacitors assist in realizing voltage conversion to meet the level conversion requirements. The ninth to twelfth resistors respectively provide current limiting protection for the chip's receiving and transmitting pins. The overall structure can adapt to the dual-channel communication requirements of the second bus and ensure the accuracy and stability of signal conversion.

[0017] In a further embodiment, the other end of the second capacitor is connected to pin 3 of the second chip; the other end of the third capacitor is connected to pin 5 of the second chip; the other end of the fifth capacitor is grounded; the other end of the fourth capacitor is connected to pin 6 of the second chip; the other end of the sixth capacitor is grounded; the other end of the ninth resistor is led out; the other end of the tenth resistor is led out; the other end of the eleventh resistor is led out; the other end of the twelfth resistor is led out; pin 15 of the second chip is grounded; and pin 16 of the second chip is connected to the output terminal of the control power supply.

[0018] In a further embodiment, the output terminal of the control power supply is connected to pin 18 of the first chip, and the ground terminal of the control power supply is connected to pin 24 of the first chip.

[0019] In a further embodiment, the first transmitting terminal of the second external interface is electrically connected to the other end of the eleventh resistor; the second transmitting terminal of the second external interface is electrically connected to the other end of the twelfth resistor; the first receiving terminal of the second external interface is electrically connected to the other end of the ninth resistor; and the second receiving terminal of the second external interface is electrically connected to the other end of the tenth resistor.

[0020] By adopting the above technical solution, each terminal of the second external interface is directly electrically connected to the corresponding resistor lead of the second communication module, which clarifies the signal transmission path between the second communication module and the external device. This enables the dual-channel receiving and transmitting signals of the second communication module to be smoothly transmitted through the second external interface, achieving reliable docking with the external device and ensuring the effectiveness of the dual-channel communication of the second bus.

[0021] In summary, this utility model has the following beneficial effects:

[0022] 1. The first chip serves as the core for level conversion, the first capacitor filters the power supply to ensure stable chip operation, the first to fifth resistors provide current limiting protection for each key pin of the chip, the sixth to eighth resistors provide voltage division stabilization, and the first and second diodes provide overvoltage protection for the bus signal. The overall structure can reliably achieve bidirectional communication with the first bus, improving the stability and anti-interference capabilities of the circuit. Attached Figure Description

[0023] Figure 1 This is a circuit diagram of the second communication module of this utility model;

[0024] Figure 2 This is a circuit diagram of the first communication module of this utility model;

[0025] Figure 3 This is the circuit diagram of the first external interface of this utility model. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings.

[0027] Identical parts are indicated by the same reference numerals. It should be noted that the terms "front," "rear," "left," "right," "upper," and "lower" used in the following description refer to the attached figures. Figure 1 In this specification, the terms "bottom surface" and "top surface," "inner" and "outer" refer to the direction toward or away from the geometry of a specific component. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this specification, "a plurality of" means two or more, unless otherwise explicitly and specifically defined by the direction of the center.

[0028] Example 1:

[0029] like Figures 1-3As shown, a communication module control circuit includes a first communication module for level conversion and bidirectional communication with a first bus, and includes a first bus A line and a first bus B line; a second communication module for level conversion and dual-channel communication with a second bus; a first external interface electrically connected to the A line and B line of the first communication module; a second external interface electrically connected to the transmit / receive path of the second communication module; and a control power supply connected to the first communication module and the second communication module respectively to provide DC power supply.

[0030] The first communication module includes a first chip with pin 17 (receive output), pin 18 (power supply), pin 19 (receive enable), pin 20 (bus B), pin 21 (drive enable), pin 22 (bus A), and pin 24 (ground); a first capacitor for power supply filtering; a first resistor, one end of which is connected to pin 17 of the first chip; a second resistor, one end of which is connected to pin 20 of the first chip; a third resistor, one end of which is connected to pin 22 of the first chip; a fourth resistor, one end of which is connected to pin 19 of the first chip; a fifth resistor, one end of which is connected to pin 21 of the first chip; a sixth resistor, one end of which is connected to pin 20 of the first chip; a seventh resistor, one end of which is connected to pin 22 of the first chip; an eighth resistor, one end of which is connected to the other end of the seventh resistor; a first diode, one pin of which is connected to the first bus A line; and a second diode, one pin of which is connected to the first bus B line.

[0031] The other end of the first resistor is led out; one end of pin 18 of the first chip is connected to the control power supply, and the other end is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; the other end of the fourth resistor is led out; the other end of the second resistor is connected to the first bus line B, and the other end of the sixth resistor is grounded; the other end of the fifth resistor is led out; the other end of the third resistor is connected to the first bus line A, and the other end of the eighth resistor is grounded; pin 24 of the first chip is grounded; the other two pins of the first diode are connected to the control power supply and ground respectively; the other two pins of the second diode are connected to the control power supply and ground respectively.

[0032] The second communication module includes: a second chip, which has pins 1 (charge pump positive terminal), 2 (charge pump positive voltage terminal), 3 (charge pump negative terminal), 4 (charge pump positive terminal), 5 (charge pump negative terminal), 6 (charge pump negative voltage terminal), 7 (first receive output terminal), 8 (second receive output terminal), 10 (second transmit input terminal), 11 (first transmit input terminal), 15 (ground terminal), and 16 (power supply terminal); a second capacitor, one end of which is connected to pin 1 of the second chip; a third capacitor, one end of which is connected to pin 4 of the second chip; a fourth capacitor, one end of which is connected to pin 2 of the second chip; a fifth capacitor, one end of which is connected to pin 2 of the second chip; a sixth capacitor, one end of which is connected to pin 6 of the second chip; a ninth resistor, one end of which is connected to pin 7 of the second chip; a tenth resistor, one end of which is connected to pin 8 of the second chip; an eleventh resistor, one end of which is connected to pin 11 of the second chip; and a twelfth resistor, one end of which is connected to pin 10 of the second chip.

[0033] The other end of the second capacitor is connected to pin 3 of the second chip; the other end of the third capacitor is connected to pin 5 of the second chip; the other end of the fifth capacitor is grounded; the other end of the fourth capacitor is connected to pin 6 of the second chip; the other end of the sixth capacitor is grounded; the other end of the ninth resistor is led out; the other end of the tenth resistor is led out; the other end of the eleventh resistor is led out; the other end of the twelfth resistor is led out; pin 15 of the second chip is grounded; pin 16 of the second chip is connected to the output terminal of the control power supply.

[0034] The output terminal of the control power supply is connected to pin 18 of the first chip, the ground terminal of the control power supply is connected to pin 24 of the first chip, the first transmitting terminal of the second external interface is electrically connected to the other end of the eleventh resistor; the second transmitting terminal of the second external interface is electrically connected to the other end of the twelfth resistor; the first receiving terminal of the second external interface is electrically connected to the other end of the ninth resistor; and the second receiving terminal of the second external interface is electrically connected to the other end of the tenth resistor.

[0035] Specific implementation process: When the dual-bus communication circuit is working, the control power supply first provides a stable +3.3V DC power supply to the first and second communication modules to ensure that each chip and component is powered on and working. For the first communication module, external devices are connected to the first bus lines A and B through the first external interface to achieve bidirectional communication: When receiving external signals, the signals are transmitted through the first bus lines A or B, and enter the first chip's pin 22 (bus A terminal) or pin 20 (bus B terminal) through the third or second resistor. The sixth, seventh, and eighth resistors respectively play a voltage division and stabilization role, while the first and second diodes provide overvoltage protection for the bus signals to prevent damage to the chip from voltages above the control power supply. After being processed internally by the first chip, the signals are output from the receiving output terminal at pin 17 through the first resistor. When sending signals, the control signals control the receiving enable terminal at pin 19 and the driving enable terminal at pin 21 of the first chip through the fourth and fifth resistors respectively, enabling the chip to enter the sending state. After being processed by the first chip, the signals are output from pin 22 or 20 to the first bus lines A and B, and then transmitted to the external devices through the first external interface. The first capacitor provides filtering for the power supply pin 18 of the first chip to ensure stable power supply. For the second communication module, the second chip connects to the second and third capacitors via pins 1 and 3, and pins 4 and 5 respectively, forming a charge pump circuit. This circuit, along with the fourth, fifth, and sixth capacitors connected to the positive and negative terminals of the charge pump (pin 2 and pin 6 respectively), performs voltage conversion, providing the necessary voltage for signal level conversion. External devices are connected via the second external interface. When receiving a signal, the external signal is transmitted to the ninth and tenth resistors via the first and second receiving terminals of the second external interface, respectively, and then enters the first receiving output terminal (pin 7) and the second receiving output terminal (pin 8) of the second chip. After processing by the chip, the signal is output from these two pins. When transmitting a signal, the signal is input to the first transmitting input terminal (pin 11) and the second transmitting input terminal (pin 10) of the second chip via the eleventh and twelfth resistors, respectively. After processing by the chip, the signal is transmitted to the external device via the first and second transmitting terminals of the second external interface. Pin 15 of the second chip is grounded, and pin 16 is connected to a +3.3V power supply to ensure normal operation. Throughout the process, the two communication modules operate independently, communicating with external devices through their respective buses, controlling the power supply to provide continuous power, and ensuring that the circuit can stably and reliably complete level conversion and data transmission through the coordinated action of resistors, capacitors, and diodes.

[0036] In the embodiments disclosed in this utility model, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; "linking" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments disclosed in this utility model according to the specific circumstances.

[0037] This specific embodiment is merely an explanation of the present utility model and is not intended to limit the present utility model. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but as long as they are within the scope of the claims of the present utility model, they are protected by patent law.

Claims

1. A communication module control circuit, characterized by, include: The first communication module is used to realize level conversion and bidirectional communication with the first bus, and is provided with a first bus A line and a first bus B line; The second communication module is used to realize level conversion and dual-channel communication with the second bus; The first external interface is electrically connected to the A and B lines of the first communication module; The second external interface is electrically connected to the transmit / receive path of the second communication module; The control power supply is connected to the first communication module and the second communication module respectively, providing DC power. The first communication module includes a first chip with pin 17 receiving output terminal, pin 18 power supply terminal, pin 19 receiving enable terminal, pin 20 bus B terminal, pin 21 drive enable terminal, pin 22 bus A terminal, and pin 24 ground terminal; a first capacitor for power supply filtering of the first chip; a first resistor with one end connected to pin 17 of the first chip; and a second resistor with one end connected to pin 20 of the first chip. A third resistor, one end of which is connected to pin 22 of the first chip; a fourth resistor, one end of which is connected to pin 19 of the first chip; The fifth resistor has one end connected to pin 21 of the first chip; the sixth resistor has one end connected to pin 20 of the first chip; the seventh resistor has one end connected to pin 22 of the first chip; the eighth resistor has one end connected to the other end of the seventh resistor; the first diode has one pin connected to the first bus line A; and the second diode has one pin connected to the first bus line B.

2. A communication module control circuit according to claim 1, characterized in that: The other end of the first resistor is led out; one end of pin 18 of the first chip is connected to the control power supply, and the other end is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; the other end of the fourth resistor is led out; the other end of the second resistor is connected to the first bus line B, and the other end of the sixth resistor is grounded; the other end of the fifth resistor is led out; the other end of the third resistor is connected to the first bus line A, and the other end of the eighth resistor is grounded; pin 24 of the first chip is grounded; the other two pins of the first diode are connected to the control power supply and ground respectively; the other two pins of the second diode are connected to the control power supply and ground respectively.

3. The communication module control circuit of claim 1, wherein: The second communication module includes: a second chip, which has pins 1 (charge pump positive terminal), 2 (charge pump positive voltage terminal), 3 (charge pump negative terminal), 4 (charge pump positive terminal), 5 (charge pump negative terminal), 6 (charge pump negative voltage terminal), 7 (first receive output terminal), 8 (second receive output terminal), 10 (second transmit input terminal), 11 (first transmit input terminal), 15 (ground terminal), and 16 (power supply terminal); a second capacitor, one end of which is connected to pin 1 of the second chip; a third capacitor, one end of which is connected to pin 4 of the second chip; a fourth capacitor, one end of which is connected to pin 2 of the second chip; a fifth capacitor, one end of which is connected to pin 2 of the second chip; a sixth capacitor, one end of which is connected to pin 6 of the second chip; a ninth resistor, one end of which is connected to pin 7 of the second chip; a tenth resistor, one end of which is connected to pin 8 of the second chip; an eleventh resistor, one end of which is connected to pin 11 of the second chip; and a twelfth resistor, one end of which is connected to pin 10 of the second chip.

4. A communications module control circuit according to claim 3, characterised in that: The other end of the second capacitor is connected to pin 3 of the second chip; the other end of the third capacitor is connected to pin 5 of the second chip; the other end of the fifth capacitor is grounded; the other end of the fourth capacitor is connected to pin 6 of the second chip; the other end of the sixth capacitor is grounded; the other end of the ninth resistor is led out; the other end of the tenth resistor is led out; the other end of the eleventh resistor is led out; the other end of the twelfth resistor is led out; pin 15 of the second chip is grounded; pin 16 of the second chip is connected to the output terminal of the control power supply.

5. The communication module control circuit of claim 1, wherein: The output terminal of the control power supply is connected to pin 18 of the first chip, and the ground terminal of the control power supply is connected to pin 24 of the first chip.

6. A communication module control circuit according to claim 1, characterized in that: The first transmitting terminal of the second external interface is electrically connected to the other end of the eleventh resistor; the second transmitting terminal of the second external interface is electrically connected to the other end of the twelfth resistor; the first receiving terminal of the second external interface is electrically connected to the other end of the ninth resistor; and the second receiving terminal of the second external interface is electrically connected to the other end of the tenth resistor.

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