A microprocessor architecture and computer device

Abstract

This application provides a microprocessor architecture and computer device. The microprocessor architecture includes a control unit, functional units, and a clock signal source. The clock signal source includes an initial clock unit and a frequency modulation unit. The control unit is configured with first configuration information, first gating information, and second gating information. The initial clock unit generates at least two initial clock signals according to the first configuration information. The frequency modulation unit includes a first gating unit and a second gating unit. The first gating unit outputs the initial clock signal indicated by the first gating information as a target clock signal. The second gating unit outputs the target clock signal and the backup clock signal indicated by the second gating information. The backup clock signal is a clock signal that ensures the reliable operation of the functional units. By configuring the gating information, the selection of different clock frequencies under normal operation and the provision of a backup clock signal under abnormal conditions can be realized, ensuring the safe operation of the functional units and the microprocessor architecture.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a microprocessor architecture and computer device. Background Technology

[0002] In modern computer technology, microprocessor architectures consist of multiple functional units, such as processor cores and GPU (Graphics Processing Unit) cores. These functional units all operate under the drive of clock signals provided by a clock signal source. During the microprocessor architecture design process, in order to meet the performance and power consumption requirements of different scenarios, the clock frequency of the functional units can be dynamically adjusted.

[0003] Therefore, how to meet the application requirements of different clock signals of each functional unit in the microprocessor architecture and ensure the operational safety of the functional units and the microprocessor architecture has become one of the technical problems that urgently need to be solved by those skilled in the art. Utility Model Content

[0004] The purpose of this application is to provide a microprocessor architecture and computer device that provides clock signals of different clock frequencies for each functional unit, thereby meeting the different application requirements of the functional units and ensuring the operational safety of the functional units and the microprocessor architecture.

[0005] In a first aspect, this application provides a microprocessor architecture, including:

[0006] At least one functional unit, said functional unit being used to implement a preset function of the microprocessor architecture;

[0007] At least one clock signal source, each of the clock signal sources being connected to one or more of the functional units;

[0008] The control unit is used to configure first configuration information, first strobe information, and second strobe information;

[0009] The clock signal source includes: an initial clock unit and a frequency modulation unit, wherein,

[0010] The initial clock unit is used to generate at least two initial clock signals according to the first configuration information;

[0011] The frequency modulation unit includes: a first gating unit and a second gating unit, wherein...

[0012] The first gating unit receives the at least two initial clock signals and the first gating information, and outputs the initial clock signal indicated by the first gating information as the target clock signal.

[0013] The second strobe unit receives the target clock signal, the second strobe information, and the backup clock signal, and outputs the clock signal indicated by the second strobe information in the target clock signal and the backup clock signal, so that the functional unit operates based on the clock signal output by the second strobe unit. The backup clock signal is provided by other clock signal sources and is a clock signal that ensures the reliable operation of the functional unit under abnormal conditions.

[0014] Based on the above, the microprocessor architecture provided in this application generates at least two initial clock signals according to the first configuration information. The clock frequencies of each initial clock signal are different. The desired clock frequency can be selected through the first strobe information, and the target clock signal or backup clock signal can be selected through the second strobe unit and finally output to the functional unit. The backup clock signal is a clock signal that ensures the reliable operation of the functional unit under abnormal conditions. With this setting, by configuring the first strobe information and the second strobe information, the selection of different clock frequency clock signals under normal operation and the provision of backup clock signals to the functional unit under abnormal conditions can be realized, ensuring the reliable operation of the functional unit and the microprocessor architecture.

[0015] In one optional implementation, the frequency modulation unit operates within the voltage domain corresponding to the connected functional unit;

[0016] The frequency modulation unit further includes:

[0017] At least two timing sensors are connected to the initial clock unit, and each timing sensor receives an initial clock signal and feeds back the timing characteristic parameters of the initial clock signal when it is transmitted within the corresponding voltage domain.

[0018] The control unit is used to determine the first gating information based on the timing characteristic parameters.

[0019] In the microprocessor architecture provided in this application, the frequency modulation unit includes at least two timing sensors and operates within the voltage domain of the functional unit. The timing sensors feed back the timing characteristic parameters of the received initial clock signal transmitted within the voltage domain to determine the first gating information, and then determine the target clock signal among each initial clock signal. The clock signal source adjusts the clock frequency based on the actual timing characteristic parameters of the clock signal, no longer relying on the voltage / frequency table. Therefore, it can overcome the shortcomings caused by the limitations of the voltage / frequency table. Specifically, the limitations are reflected in the fact that the clock frequencies corresponding to each voltage in the voltage / frequency table have too much timing margin, and the excessively high operating voltage will also cause power consumption waste and accelerate device aging. However, the microprocessor architecture provided in this application adjusts the clock frequency based on the actual timing characteristic parameters. This implementation can make full use of the timing margin under different operating voltages. Under a certain operating voltage, the clock frequency is adjusted as much as possible so that the functional unit operates at the adjusted clock frequency. This implementation can give full play to the performance of the functional unit. Furthermore, the above implementation method can minimize the probability of increased operating voltage, reduce the power consumption and aging rate of the microprocessor architecture, and improve the processor's operating performance.

[0020] In one optional implementation, the initial clock unit includes:

[0021] A first configuration unit, connected to the control unit, is used to store the first configuration information, which includes at least two clock frequencies.

[0022] At least two initial signal generation units, each of which generates an initial clock signal based on one of the clock frequencies.

[0023] In the microprocessor architecture provided in this application, the initial clock unit is provided with a first configuration unit and at least two initial signal generation units. Each initial signal generation unit can generate a corresponding initial clock signal according to a clock frequency, thereby providing a variety of initial clock signals with different clock frequencies. By configuring the clock frequency in the first configuration information, the output of different initial clock signals can be realized. The adjustment process is simple and easy to implement, and can meet the application requirements of different clock frequencies in different scenarios.

[0024] In one optional implementation, the initial clock unit further includes:

[0025] The clock backup unit, as the other clock signal source, is connected to the first configuration unit and generates the backup clock signal based on the first configuration information.

[0026] In the microprocessor architecture provided in this application, the initial clock unit includes a clock backup unit. The backup clock signal provided by the clock backup unit can ensure that the functional unit can still operate reliably under abnormal conditions, thereby improving the safety and reliability of the functional unit operation.

[0027] In one optional implementation, the frequency modulation unit further includes:

[0028] The second configuration unit is used to store the timing characteristic parameters, the first gating information, and the second gating information.

[0029] In the microprocessor architecture provided in this application, an optional implementation of the frequency modulation unit is provided, which includes a second configuration unit. The second configuration unit can realize the acquisition of the aforementioned timing characteristic parameters and the configuration of the first gating unit, thereby determining the timing characteristics of each initial clock signal and the final selection of the target clock signal. The configuration process is simple and easy to implement, and can realize customized clock signal configuration for different functional units, thereby meeting the different clock frequency application requirements of different functional units.

[0030] In one optional implementation, the initial clock unit is used to generate at least two initial clock signals based on the first configuration information;

[0031] The initial clock unit includes:

[0032] A unit-level configuration unit, connected to the control unit, is used to store the first configuration information, which includes at least two clock frequencies;

[0033] At least two initial signal generation units, each of which generates an initial clock signal based on a clock frequency and a base clock signal.

[0034] In the microprocessor architecture provided in this application, an optional implementation of the initial clock unit is provided, which includes a unit-level configuration unit and at least two initial signal generation units. The configuration of the aforementioned first configuration information is implemented through the unit-level configuration unit, thereby completing the clock frequency setting of each initial clock signal. The configuration process is simple and easy to implement. Each initial signal generation unit generates an initial clock signal according to the first configuration information and the basic clock signal, which effectively simplifies the clock frequency adjustment process, improves the clock frequency adjustment efficiency, and meets the needs of practical applications.

[0035] In one optional implementation, the clock signal source further includes:

[0036] A base clock unit is connected to the initial clock unit and provides the base clock signal to the initial clock unit.

[0037] In the microprocessor architecture provided in this application, the clock signal source includes a basic clock unit. This basic clock unit is a dedicated signal source for the clock signal source provided in this application, specifically used to provide a basic clock signal. This configuration can ensure the stability and anti-interference capability of the basic clock signal, thereby improving the overall stability of the clock signal source and ensuring that a stable and reliable clock signal can be provided to the subsequent functional units.

[0038] In one optional implementation, the control unit is further configured to configure second configuration information;

[0039] The basic clock unit includes:

[0040] A system-level configuration unit, connected to the control unit, is used to store the second configuration information;

[0041] A basic signal generation unit generates the basic clock signal according to the second configuration information.

[0042] In the microprocessor architecture provided in this application, an optional implementation of a basic clock unit is provided. The basic signal generation unit generates a basic clock signal according to the second configuration information stored in the system-level configuration unit, which satisfies the requirement of each initial signal generation unit connected to the subsequent stage of the basic clock unit to output the initial clock signal. Users can adjust the basic clock signal by updating the second configuration information, which effectively simplifies the adjustment process of the basic clock signal and helps to improve the adjustment efficiency of the clock frequency.

[0043] In one optional implementation, the basic signal generation unit is connected to the second gating unit;

[0044] The base clock signal serves as the backup clock signal.

[0045] In the microprocessor architecture provided in this application, a base clock unit is connected to a second strobe unit. The base clock signal provided by the base clock unit is used as a backup clock signal. In case of an anomaly, the base clock signal can be selected to be output to the functional unit by configuring the second strobe information, thereby ensuring the reliable operation of the functional unit. In other words, this application provides a security protection mechanism to meet the risk avoidance requirements under anomaly warning conditions. Furthermore, by reusing the base clock signal, the clock signal source used to provide the backup clock signal can be omitted, which helps to reduce the design complexity of the microprocessor architecture, improve design efficiency, and reduce the overall cost of the microprocessor architecture.

[0046] In one optional implementation, the system-level configuration unit is connected to the gating control terminal of the second gating unit, and the system-level configuration unit is also used to store the second gating information.

[0047] In the microprocessor architecture provided in this application, the second strobe information is stored by the system-level configuration unit. The control unit uses the system-level configuration unit as an intermediate medium to update the second strobe information stored in the system-level configuration unit, thereby controlling the strobe state of the second strobe unit and outputting the target clock signal or the basic clock signal, ensuring the overall operational safety of the microprocessor architecture and meeting the needs of practical applications.

[0048] In one optional implementation, the basic signal generation unit includes a phase-locked loop (PLL), and the initial signal generation unit includes any one of a PLL, a delay phase-locked loop (DLL), a digital phase-locked loop (DPLL), and an all-digital phase-locked loop (ADPLL).

[0049] In the microprocessor architecture provided in this application, the basic signal generation unit is used to provide the basic clock signal. When a PLL is selected for implementation, its advantages of low jitter and stable performance can be fully utilized, which helps to improve the reliability of the basic clock signal. The initial signal generation unit is used to provide the initial clock signal. When an ADPLL is selected for implementation, its advantages of small area and low power consumption can be fully utilized, which helps to reduce the overall area and power consumption of the clock signal source.

[0050] In one optional implementation, in the microprocessor architecture provided by any of the foregoing implementations, the frequency modulation unit further includes:

[0051] The early warning unit is connected to the gating control terminal of the second gating unit and is used to output a preset gating signal in response to the early warning event of the functional unit. The preset gating signal is used to instruct the second gating unit to output the backup clock signal.

[0052] In the microprocessor architecture provided in this application, an early warning unit is set in the frequency modulation unit. The early warning unit detects early warning events of the functional unit and outputs a preset gating signal when an early warning event occurs. The second gating unit responds to the preset gating signal and outputs a backup clock signal. By reducing the clock frequency, the operation safety of the functional unit is ensured. Since the preset gating signal is directly triggered by the early warning unit, a rapid response to early warning events can be achieved, which helps to improve the operation safety of the functional unit.

[0053] In one optional implementation, the microprocessor architecture provided in any of the foregoing implementations further includes:

[0054] The inter-core communication unit is connected to the control unit and each of the functional units respectively, and the inter-core communication unit serves as an intermediary medium for the interaction between the control unit and each of the functional units.

[0055] In a second aspect, this application provides a computer device including a microprocessor architecture as provided in any of the foregoing embodiments. Attached Figure Description

[0056] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a structural block diagram of a first microprocessor architecture provided in an embodiment of this application.

[0058] Figure 2 This is a structural block diagram of a second microprocessor architecture provided in an embodiment of this application.

[0059] Figure 3 This is a schematic diagram illustrating the voltage domain partitioning effect of microprocessor architecture in related technologies.

[0060] Figure 4 This is a structural block diagram of a third microprocessor architecture provided in an embodiment of this application.

[0061] Figure 5 This is a structural block diagram of a fourth microprocessor architecture provided in an embodiment of this application.

[0062] Figure 6 This is a structural block diagram of the fifth microprocessor architecture provided in the embodiments of this application.

[0063] Figure 7 This is a structural block diagram of the sixth microprocessor architecture provided in the embodiments of this application.

[0064] Figure 8 This is a structural block diagram of the seventh microprocessor architecture provided in the embodiments of this application.

[0065] Figure 9 This is a structural block diagram of the eighth microprocessor architecture provided in the embodiments of this application. Detailed Implementation

[0066] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0067] As mentioned above, in order to meet the application requirements of different clock signals of various functional units in the microprocessor architecture and ensure the operational safety of the functional units and the microprocessor architecture, this application provides a microprocessor architecture in which the initial clock unit generates at least two initial clock signals according to the first configuration information. The clock frequencies of each initial clock signal are different. The clock signal of the required clock frequency can be selected through the first strobe information, and the target clock signal or the backup clock signal can be selected through the second strobe unit and finally output to the functional unit. The backup clock signal is the clock signal that ensures the reliable operation of the functional unit in abnormal conditions. With this setting, by configuring the first strobe information and the second strobe information, the selection of clock signals of different clock frequencies under normal operation and the provision of backup clock signals to the functional unit in abnormal conditions can be realized, thus ensuring the reliable operation of the functional unit and the microprocessor architecture.

[0068] Based on the above, this application provides a microprocessor architecture, including a control unit, at least one functional unit, and at least one clock signal source. Each clock signal source is connected to one or more functional units and provides a clock signal to the connected functional units. The functional units are used to implement preset functions of the microprocessor architecture. Based on this, in Figure 1 In the microprocessor architecture provided in the embodiment shown, a clock signal source is shown as an example, labeled as clock signal source 20. Correspondingly, a functional unit is also shown as an example, labeled as functional unit 30. The clock signal source 20 includes an initial clock unit 21 and a frequency modulation unit 22.

[0069] Control unit 10 is used to configure first configuration information, first strobe information, and second strobe information, in combination with Figure 1 As shown, the control unit 10 is connected to the initial clock unit 21 and the frequency modulation unit 22 in the clock signal source 20, respectively. Based on this connection, the control unit 10 can configure the initial clock unit 21 with first configuration information and configure the frequency modulation unit 22 with first gating information and second gating information.

[0070] In one optional embodiment, the control unit 10 may be a dedicated control module for the clock signal source 20, controlling the operation of the clock signal source 20. In another optional embodiment, the control unit 10 may also be a control module shared with other functional units in a microprocessor architecture, that is, the control unit 10 can not only control the clock signal source 20 to work, but also implement other control functions.

[0071] In one optional implementation, the first configuration information configured in the control unit 10 includes the clock frequencies required for the initial clock unit 21 to generate each initial clock signal. It is understood that the first configuration information includes at least two clock frequencies, each used to generate an initial clock signal, and the clock frequency of each initial clock signal can be configured according to frequency modulation requirements. By adjusting the clock frequencies in the first configuration information, the initial clock unit 21 can be instructed to output clock signals of different clock frequencies. Of course, the first configuration information may also include other information for instructing the initial clock unit 21 to generate initial clock signals; these will not be listed here, but are also within the scope of protection of this application as long as they do not exceed the core concept of this application.

[0072] The specific configuration process of the first and second gating information will be discussed in detail in the subsequent content in conjunction with the specific implementation of the frequency modulation unit 22, and will not be described in detail here.

[0073] The input terminal of the initial clock unit 21 is connected to the control unit 10, and receives first configuration information, which includes at least two clock frequencies. The initial clock unit 21 generates at least two initial clock signals based on the first configuration information. In an optional embodiment, the initial clock unit 21 is configured with multiple output terminals, each of which is used to output an initial clock signal. It should be noted that in... Figure 1 In the illustrated embodiment, the initial clock unit 21 is shown as having two output terminals. The initial clock unit 21 is used to output two initial clock signals with different clock frequencies.

[0074] The frequency modulation unit 22 includes a first gating unit 221 and a second gating unit 222. The first gating unit 221 includes at least two gating input terminals, one gating output terminal, and a gating control terminal. Each gating input terminal is connected to one output terminal of the initial clock unit 21 to receive an initial clock signal. The gating control terminal of the first gating unit 221 is connected to the control unit 10 to receive the first gating information configured by the control unit 10. In response to the obtained first gating information, the first gating unit 221 outputs the initial clock signal indicated by the first gating information in each initial clock signal provided by the initial clock unit 21 as the target clock signal.

[0075] Similar to the first gating unit 221, the second gating unit 222 includes two gating input terminals, namely the first gating input terminal and the second gating input terminal, combined with... Figure 1As shown, the first gating input terminal of the second gating unit 222 is connected to the output terminal of the first gating unit 221, receiving the target clock signal output by the first gating unit 221. The second gating input terminal of the second gating unit 222 is used to receive backup clock signals provided by other clock signal sources. Further, the gating control terminal of the second gating unit 222 is connected to the control unit 10, used to receive the aforementioned second gating information. The gating output terminal of the second gating unit 222 serves as the output terminal of the frequency modulation unit 22, connected to the subsequent functional unit 30. In response to the second gating information, the second gating unit 222 uses... The second strobe information indicates the clock signal in the target clock signal and the backup clock signal and outputs it to the functional unit 30. The backup clock signal is the clock signal that ensures the reliable operation of the functional unit 30 in case of abnormality. Based on this, when the functional unit 30 is operating normally, the second strobe information can be used to instruct the second strobe unit 222 to output the target clock signal to provide the target clock signal required for the normal operation of the functional unit 30. Correspondingly, when an abnormal situation occurs, the second strobe information can be used to instruct the second strobe unit 222 to output the backup clock signal to ensure the reliable operation of the functional unit 30.

[0076] As an optional implementation, both the first gating unit 221 and the second gating unit 222 can be implemented using a MUX (multiplexer). For example, the MUX can be a glitch-free clock switch. The first gating information provided by the control unit 10 may include the gating configuration value of the MUX. By configuring a certain gating input terminal in the MUX to be connected to a gating output terminal through the gating configuration value, the clock signal received by the gating input terminal is output. Taking the second strobing unit 222 as an example, the second strobing information includes a running configuration value or a risk mitigation configuration value. The running configuration value instructs the second strobing unit 222 to output a target clock signal, while the risk mitigation configuration value instructs it to output a backup clock signal. Specifically, in abnormal situations, such as insufficient timing margin in the current clock signal of functional unit 30 requiring emergency risk mitigation, the second strobing information is the risk mitigation configuration value. The second strobing unit 222 responds to this value by outputting a backup clock signal, ensuring that functional unit 30 can operate reliably without timing corruption due to insufficient timing margin. Conversely, when functional unit 30 is operating normally, the second strobing information is the running configuration value, and the second strobing unit 222 responds to this value by outputting a target clock signal to functional unit 30, ensuring its normal operation. Based on the foregoing, it can be understood that there is no specific size requirement between the running configuration value and the risk mitigation configuration value; simply selecting different configuration values ​​is sufficient. Of course, the first gating unit 221 and the second gating unit 222 can also be implemented in other ways, which will not be described in detail here. As long as they do not exceed the core idea of ​​this application, they also fall within the scope of protection of this application. In practical applications, the abnormal situations mentioned in this application, in addition to the insufficient timing margin mentioned above, also include the operation of functional units over-temperature and abnormal switching of power supply in the microprocessor architecture, which will not be described in detail here.

[0077] Functional unit 30 can be any functional unit in the microprocessor architecture, used to implement the preset functions of the microprocessor architecture. After receiving the target clock signal or backup clock signal provided by the frequency modulation unit 22, functional unit 30 can run under the drive of the obtained clock signal. For example, functional unit 30 can be a processor core. After receiving the target clock signal output by the frequency modulation unit 22, the processor core runs under the target clock signal. For another example, functional unit 30 can be a GPU core. After receiving the target clock signal output by the frequency modulation unit 22, the GPU core can execute preset image processing tasks, etc.

[0078] In summary, the microprocessor architecture provided in this application allows the initial clock unit to generate at least two initial clock signals based on the first configuration information. The clock frequency of each initial clock signal can be set according to frequency modulation requirements. The desired clock frequency is selected through the first strobe information, and the target clock signal or backup clock signal is selected through the second strobe unit and finally output to the functional unit. The backup clock signal is a clock signal that ensures the reliable operation of the functional unit under abnormal conditions. With this configuration, by configuring the first and second strobe information, the selection of different clock frequency signals under normal operation and the provision of backup clock signals to the functional unit under abnormal conditions can be realized, ensuring the reliable operation of the functional unit and the microprocessor architecture.

[0079] Furthermore, the clock frequency of the initial clock signal output by the initial clock unit can be adjusted by configuring the first configuration information. In conjunction with the first strobe information, the selection of initial clock signals with different clock frequencies can be realized. The frequency modulation process is simple and easy to implement.

[0080] This application further provides another microprocessor architecture. Compared to the previous embodiments, in the microprocessor architecture provided in this embodiment, the frequency modulation unit in the clock signal source further includes at least two timing sensors, and the frequency modulation unit operates within the voltage domain range corresponding to the connected functional unit. See [link to relevant documentation]. Figure 2 As shown, Figure 2 The embodiment shown is illustrated by including two timing sensors, namely timing sensor 1 and timing sensor 2.

[0081] For information on voltage domain partitioning in microprocessor architecture, please refer to [link / reference]. Figure 3 As shown above, the microprocessor architecture includes functional units for implementing different preset functions. For example, these functional units may include processor core 0, processor core 1, processor core 2, processor core 3, and interface modules. In practical applications, these functional units often operate at different voltages. To provide efficient power management, the operating voltages of the various functional units in the microprocessor architecture can be divided into different voltage domains. Functional units within the same voltage domain can correspond to the same or similar operating voltages. Figure 2As shown in the example, processor cores 0 and 1 operate in voltage domain 0, processor cores 2 and 3 operate in voltage domain 1, and the interface module operates in voltage domain 2. Of course, in practical applications, the microprocessor architecture can include more functional units, thus resulting in more voltage domains. These will not be detailed here. For the voltage domain division in the microprocessor architecture, please refer to the relevant implementations in the prior art; this application does not limit this. To accurately detect whether the target clock signal output to functional unit 30 meets the timing requirements of functional unit 30, the clock signal source provided in this embodiment sets the frequency modulation unit 22 within the voltage domain range corresponding to functional unit 30; that is, the frequency modulation unit 22 operates within the voltage domain range corresponding to functional unit 30.

[0082] Combination Figure 2 As shown, the input terminal of each timing sensor in the frequency modulation unit 22 is connected to one output terminal of the initial clock unit 21, receiving the initial clock signal output from the connected output terminal. Furthermore, the output terminal of each timing sensor is connected to the control unit 10, feeding back to the control unit 10 the timing characteristic parameters of the received initial clock signal transmitted within the voltage domain corresponding to the functional unit 30. In an optional embodiment, the timing sensor is implemented based on a scan chain constructed from multiple buffers. The timing characteristic parameters fed back by the timing sensor are the number of logic levels through which the received initial clock signal propagates under the current operating voltage. The number of logic levels refers to the number of logic units the initial clock signal passes through during transmission in the scan chain. Of course, in practical applications, the timing characteristic parameters fed back by the timing sensor will vary depending on the implementation principle of the timing sensor. These will not be detailed here. For the specific implementation of the timing sensor and its specific feedback timing characteristic parameters, please refer to relevant technologies.

[0083] Generally, the frequency modulation unit 22 operates within the voltage domain corresponding to the functional unit 30. The timing characteristics of the timing sensor in the frequency modulation unit 22 in response to the initial clock signal are basically consistent with the timing characteristics of the functional unit 30 in response to the initial clock signal. Therefore, for any initial clock signal, the timing characteristic parameters fed back by the timing sensor can be used to determine whether the functional unit 30 can meet the timing margin requirements when operating based on the initial clock signal. Based on this, the control unit 10 obtains the timing characteristic parameters fed back by each timing sensor and determines the first gating information according to the obtained timing characteristic parameters to instruct the first gating unit 221 to determine the target clock signal among each initial clock signal and output the target clock signal to the second gating unit 222. Following the previous example, the control unit 10 obtains the logic level corresponding to each initial clock signal, and can determine the target clock signal according to the size relationship of the logic levels of each initial clock signal, and then outputs the first gating information to instruct the first gating unit 221 to determine the target clock signal among each initial clock signal. The process by which the control unit 10 determines the target clock signal from multiple initial clock signals based on timing characteristic parameters can be implemented in accordance with relevant technologies.

[0084] Referring to the foregoing, when the functional unit 30 is operating normally, the second gating information provided by the control unit 10 includes the operating configuration value. The second gating unit 222 outputs the target clock signal provided by the first gating unit 221 to the functional unit 30 according to the indication of the second gating information, so that the functional unit 30 operates under the drive of the target clock signal.

[0085] Of course, as another optional implementation, the initial clock unit 21 can also operate within the voltage domain range corresponding to the functional unit 30, that is, the initial clock unit, the frequency modulation unit, and the functional unit connected to the frequency modulation unit operate within the same voltage domain range.

[0086] It should be noted that during any round of frequency modulation, the target clock signal output by the first gating unit 221 is only the preferred clock signal among the initial clock signals obtained in the current frequency modulation process. For the functional unit 30, this target clock signal may not be a clock signal that can fully utilize its timing margin. Therefore, in practical applications, multiple rounds of frequency modulation may be required to achieve the best effect.

[0087] In summary, the microprocessor architecture provided in this application adjusts the clock frequency based on the actual timing characteristics of the clock signal, rather than relying on the voltage / frequency table used in related technologies. This overcomes the limitations of the voltage / frequency table, which specifically includes excessive timing margins for each voltage in the table, and excessively high operating voltages leading to wasted power and accelerated device aging. In contrast, the microprocessor architecture provided in this application adjusts the clock frequency based on actual timing characteristics. This approach fully utilizes the timing margins under different operating voltages. With a fixed operating voltage, the clock frequency is adjusted as high as possible to maximize the performance of functional units, or with a fixed operating frequency, the operating voltage is lowered as much as possible to conserve power. This also minimizes the probability of increased operating voltage, thereby reducing the power consumption and aging rate of the microprocessor architecture and improving performance or energy efficiency.

[0088] This application also provides another microprocessor architecture, see [link to application]. Figure 4 As shown, compared to the previous embodiments, in the microprocessor architecture provided in this embodiment, the initial clock unit 21 in the clock signal source 20 includes a first configuration unit 211 and two initial signal generation units. For example, the two initial signal generation units include initial signal generation unit 1 and initial signal generation unit 2 (of course, more than two initial signal generation units may also be included). Furthermore, it also includes a backup signal unit 212. The frequency modulation unit 22 includes a second configuration unit 223.

[0089] Combination Figure 4 As shown, the first configuration unit 211 is connected to the control unit 10, the backup signal unit 212 and each initial signal generation unit respectively. As mentioned above, the control unit 10 configures the first configuration information to the initial clock unit 21. Based on this, the first configuration unit 211 can serve as an intermediate medium between the control unit 10 and each initial signal generation unit and the backup signal unit 212, storing the first configuration information provided by the control unit 10.

[0090] In one optional implementation, the first configuration unit 211 can be implemented using a register group. The register group serves as an intermediary for the interaction of first configuration information between the control unit 10 and each initial signal generation unit and backup signal unit. In practical applications, the intermediary function of the first configuration unit 211 is mainly reflected in the following: the control unit 10 writes the first configuration information into the first configuration unit 211, which stores it. Each initial signal generation unit and backup signal unit 212 can obtain the first configuration information by accessing the first configuration unit 211. Of course, other methods for enabling information interaction between the control unit 10 and each initial signal generation unit and backup signal unit are also optional, and will not be detailed here.

[0091] In this embodiment of the application, the initial signal generation unit 1 and the initial signal generation unit 2 have the same physical structure and are used to generate an initial clock signal according to the first configuration information. As mentioned above, as an optional implementation, the first configuration information includes a clock frequency that corresponds to each initial signal generation unit. The initial signal generation unit generates an initial clock signal according to its own corresponding clock frequency, so that initial clock signals with different clock frequencies can be obtained.

[0092] In practical applications, the initial signal generation unit can be implemented in various ways, such as choosing a PLL (Phase-Locked Loop), a DLL (Delay-Locked Loop, also known as a digital phase-locked loop), a DPLL (Digital Phase-Locked Loop), or an ADPLL (All Digital Phase-Locked Loop). Any type of phase-locked loop (PLL) is available. PLLs offer advantages such as low jitter and reliability, and their analog filters effectively suppress high-frequency noise. They are widely used in traditional chip architectures. However, they occupy a large area in the microprocessor architecture and consume a lot of power. Furthermore, the analog components in PLLs have high power requirements, making power supply relatively complex, resulting in poor dynamic response performance, and the output clock signal requires a long lock-in time. DPLLs have characteristics similar to PLLs but with faster lock-in times and smaller footprint. Compared to PLLs or DPLLs, DLLs are often used for precise clock frequency output, offering advantages such as accurate zero-delay control, faster lock-in times, and highly stable clock signals. However, their multiplication factor is usually fixed, and frequency adjustment granularity is inflexible. Furthermore, ADPLLs employ a fully digital structure, making them more suitable for advanced miniaturization processes. They have no analog components internally, resulting in a smaller footprint. They are also less sensitive to power supply noise, have higher stability, require no external power supply, and their lock-in time can be optimized to a minimum, reaching several nanoseconds. Specific implementation details for various PLLs can be found in relevant technical documentation and will not be elaborated here.

[0093] It should be noted that when the initial signal generation unit is implemented based on phase-locked loop (PLL) technology, the initial clock signal output by the initial signal generation unit still needs to use the base clock signal, combined with... Figure 4 As shown, each initial signal generation unit in the initial clock unit 21 receives the basic clock signal and its corresponding clock frequency, and generates a corresponding initial clock signal based on the obtained clock frequency and the basic clock signal. The basic clock signal is provided by other clock signal sources.

[0094] Based on the above, this embodiment provides multiple optional implementations of the initial signal generation unit. By using different forms of phase-locked loops to implement the initial signal generation unit, the existing advantages of the corresponding phase-locked loop technology can be utilized to simplify the design and improve the design efficiency. Furthermore, the initial signal generation unit is used to provide the initial clock signal. When using a PLL for implementation, its low jitter and stable technical advantages can be fully utilized, which helps to improve the reliability of the initial clock signal.

[0095] Furthermore, based on the technical principle of phase-locked loops, given a fixed base clock signal, the clock frequency of the final output clock signal of the phase-locked loop can be adjusted by changing the division ratio of the phase-locked loop. Therefore, as an optional implementation method, the first configuration information may also include the division ratio corresponding to each initial signal generation unit. Each initial signal generation unit can output the corresponding initial clock signal based on the base clock signal and its own corresponding division ratio.

[0096] In this embodiment, a first configuration unit and two initial signal generation units are set in the initial clock unit. Each initial signal generation unit can generate a corresponding initial clock signal according to the base clock signal and a clock frequency. This can provide a variety of initial clock signals with different clock frequencies. The user configures the clock frequency or division ratio in the first configuration information. After the control unit obtains the first configuration information configured by the user, it stores the first configuration information in the first configuration unit. Each initial signal generation unit obtains the first configuration information and can output different initial clock signals according to the base clock signal and the first configuration information. The adjustment process is simple and easy to implement, and can meet the application requirements of different clock frequencies in different scenarios.

[0097] Furthermore, the initial clock unit 21 also includes a backup signal unit 212, combined with... Figure 4 As shown, the backup signal unit 212 is connected to the first configuration unit 211, obtains the first configuration information configured by the control unit 10 stored in the first configuration unit 211, and generates a backup clock signal based on the first configuration information. The backup clock signal is a clock signal that ensures the reliable operation of the functional unit 30 under abnormal conditions. In other words, the first configuration information also includes backup configuration information for generating the backup clock signal. Based on the foregoing, the backup configuration information can be a backup clock frequency or a backup division ratio. Of course, it can also be other information that can instruct the backup signal unit 212 to generate the backup clock signal and ensure the reliable operation of the functional unit 30, which will not be detailed here.

[0098] By including a backup signal unit in the initial clock unit, the backup clock signal provided by the backup signal unit can ensure that the functional unit can still operate reliably under abnormal conditions, thereby improving the safety and reliability of the functional unit operation.

[0099] It should be noted that although the backup clock signal provided by the backup signal unit can ensure that the functional unit can still operate reliably under abnormal conditions, it is also necessary to collect the timing characteristic parameters of the backup clock signal when it is transmitted in the voltage domain range corresponding to the functional unit. Therefore, as an optional implementation, a timing sensor for receiving the backup clock signal can also be set in the frequency modulation unit. Of course, this timing sensor is also connected to the control unit to feed back the timing characteristic parameters of the backup clock signal when it is transmitted in the voltage domain range corresponding to the functional unit to the control unit.

[0100] Combination Figure 4 As shown, as an optional implementation, the backup signal unit 212 is implemented based on phase-locked loop technology, that is, it can be any of the aforementioned PLL, DPLL, DLL, ADPLL. In this case, the backup signal unit 212 needs to receive the basic clock signal and generate a backup clock signal based on the backup configuration information in the first configuration information and the basic clock signal. Taking the backup signal unit implemented using a PLL as an example, the backup configuration information includes the division ratio. A typical PLL structure includes a phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator (VCO), and a frequency divider. The first input of the phase detector receives the base clock signal. The output of the phase detector, the charge pump, the low-pass filter, and the VCO are connected in series. The output of the VCO serves as the output of the PLL. The input of the frequency divider is connected to the output of the VCO, and the output of the frequency divider is connected to the second input of the phase detector, forming a closed control path. The frequency divider acquires the clock signal output by the VCO and divides the current clock signal output by the VCO according to the division ratio configured in the backup configuration information to obtain the divided sampled clock signal. The phase detector adjusts the control signal output to the charge pump based on the phase and frequency deviations between the sampled clock signal and the base clock signal, ultimately adjusting the clock signal output by the VCO until the deviation between the base clock signal and the sampled clock signal is within a preset deviation range. At this point, the PLL completes the locking of the output clock signal and outputs the backup clock signal. As for the specific process by which the PLL outputs a backup clock signal based on the base clock signal and the division ratio, it can be found in relevant technologies and will not be detailed here.

[0101] Furthermore, the frequency modulation unit 22 includes a second configuration unit 223, which is connected to each timing sensor, the first gating unit 221, the second gating unit 222, and the control unit 10, respectively. The second configuration unit 223 serves as an intermediate medium between the control unit 10 and each timing sensor, the first gating unit 221, and the second gating unit 222, storing timing characteristic parameters fed back by the timing sensors and first gating information sent by the control unit 10. Further, in this embodiment, the control unit 10 is also used to configure second gating information to the second configuration unit 223 in the frequency modulation unit 22. The second gating information is used to instruct the second gating unit 222 to output a target clock signal or a backup clock signal. In response to the second gating information, the second gating unit 222 outputs the target clock signal or the backup clock signal.

[0102] As can be seen from the foregoing, the first gating unit 221 is mainly used to meet the clock frequency adjustment requirements of the functional unit 30. The adjustment of the clock frequency may cause the functional unit 30 to become unstable, especially in the case of frequency increase or overclocking. An excessively high clock frequency may cause the functional unit 30 to have insufficient timing margin, which may lead to timing disorder, abnormal operation and other problems. Of course, the functional unit 30 may also experience abnormal operation due to other reasons when it is running under non-overclocking conditions, such as excessively high ambient temperature, unstable power supply, sudden load change, etc. In order to ensure the safe operation of the functional unit 30, this embodiment includes a backup signal unit 212 in the initial clock unit 21. The backup signal unit 212 provides a backup clock signal that can ensure the reliable operation of the functional unit 30 in the case of abnormal warning. The control unit 10 controls the second gating unit 222 to output the target clock signal or the backup clock signal by configuring the second gating information to the second configuration unit 223.

[0103] It is understandable that the process of configuring the second strobe information through the control unit 10 is a software operation. In practical applications, sometimes due to signal transmission delays and other issues, the efficiency of the second strobe unit in switching the target clock signal to the backup clock signal may be reduced, and the abnormality may be further amplified due to the operation delay.

[0104] To address the aforementioned issues, this application further provides another microprocessor architecture, see [link to relevant documentation]. Figure 5 As shown, based on the aforementioned embodiments, the frequency modulation unit 22 in the clock signal source provided in this embodiment includes an early warning unit 224.

[0105] Combination Figure 5As shown, the early warning unit 224 is connected to the gating input terminal of the second gating unit 222. The early warning unit 224 is used to detect early warning events of the functional unit 30, such as insufficient timing margin or excessive temperature of the functional unit 30. In response to the detected early warning event, the early warning unit 224 outputs a preset gating signal. In response to the preset gating signal, the second gating unit 222 outputs a backup clock signal to the functional unit 30, thereby reducing the clock frequency of the functional unit 30. Compared to the previous embodiment where the second gating unit 222 is controlled by the control unit 10, in this embodiment, the second gating unit 222 is directly controlled by the early warning unit 224. The two are connected by hardware lines, which can realize instantaneous transmission of the preset gating signal, thereby enabling a rapid response to early warning events and helping to improve the operational safety of the functional unit.

[0106] Of course, as an optional implementation, when the warning unit 224 is provided, the second configuration unit 223 can also be connected to the gating control terminal of the second gating unit 222. The control unit 10 can still configure the second gating information to the second gating unit 222 through the second configuration unit 223. The two methods are used together. In practical applications, both the control unit 10 and the warning unit 224 can control the gating status of the second gating unit 222. The specific control process can be referred to the above content and will not be repeated here.

[0107] Furthermore, as an optional implementation, the clock signal source 20 is also provided with a basic clock unit 23, combined with... Figure 5 As shown, the basic clock unit 23 is connected to each initial signal generation unit and the backup signal unit 212. The basic clock unit 23 serves as another clock signal source mentioned in the previous embodiments, used to generate the basic clock signal. Referring to the relevant content of the initial signal generation unit in the previous embodiments, the basic clock unit 23 can be any one of PLL, DPLL, DLL, and ADPLL. Of course, the basic clock unit 23 can also be implemented using other related technologies, which will not be detailed here. This embodiment provides multiple optional implementation methods for the basic clock unit. By using different forms of phase-locked loops to implement the basic clock unit, the existing advantages of the corresponding phase-locked loop technology can be utilized to simplify the design and improve design efficiency. Furthermore, the basic clock unit is used to provide the basic clock signal. When using PLL for implementation, its low jitter and stable technical advantages can be fully utilized, which helps to improve the reliability of the basic clock signal.

[0108] By including a basic clock unit in the initial clock unit, which is a dedicated signal source for the clock signal source provided in this application and is specifically used to provide a basic clock signal, the stability and anti-interference capability of the basic clock signal can be ensured, thereby improving the overall stability of the clock signal source and ensuring that a stable and reliable clock signal can be provided to the subsequent functional units.

[0109] This application also provides another microprocessor architecture, see [link to application]. Figure 6 As shown, compared to the aforementioned Figure 1 In the embodiment shown, the microprocessor architecture provided in this embodiment includes an initial clock unit 21 for generating at least two initial clock signals based on the first configuration information provided by the control unit 10. Based on this, the initial clock unit 21 includes a unit-level configuration unit 213 and at least two initial signal generation units. This embodiment takes N initial signal generation units as an example, where N≥2.

[0110] Combination Figure 6 As shown, the unit-level configuration unit 213 is connected to the control unit 10 and each initial signal generation unit, respectively, and is used to store first configuration information to realize the interaction of the first configuration information between the control unit 10 and each initial signal generation unit. The first configuration information includes at least three clock frequencies. Furthermore, the unit-level configuration unit 213 is also connected to the first gating unit 221 to store first gating information. The first gating unit 221 obtains the first gating information through the unit-level configuration unit 213.

[0111] Each initial signal generation unit in the initial clock unit 21 generates an initial clock signal based on a clock frequency and a base clock signal. The base clock signal can be provided by other clock signal sources. The output of each initial signal generation unit is connected to the gating input of the first gating unit 221. In the initial clock unit 21 provided in this embodiment, each initial signal generation unit generates its corresponding initial clock signal according to the first configuration information and the base clock signal. The first configuration information includes the clock frequency corresponding to each initial signal generation unit. Each initial signal generation unit generates an initial clock signal of the corresponding clock frequency according to its own clock frequency and the base clock signal. In this embodiment and subsequent embodiments, the clock frequencies included in the first configuration information can be configured according to frequency modulation requirements. The process by which any initial signal generation unit generates its initial clock signal can be referred to the relevant content of the backup signal unit in the foregoing embodiments, and will not be repeated here.

[0112] The first gating unit 221 has at least two gating input terminals, one gating output terminal, and one gating control terminal, combined with Figure 6As shown, each gating input segment of the first gating unit 221 is connected to an initial signal generation unit and receives the initial clock signal generated by the connected initial signal generation unit. The control unit 10 outputs first gating information, which is used to indicate the target initial signal generation unit in each initial signal generation unit, so that the initial clock signal output by the target initial signal generation unit is used as the target clock signal. In other words, the first gating information is used to indicate the target clock signal in each initial clock signal. The first gating unit 221 determines the target clock signal in each initial clock signal according to the first gating information and outputs the target clock signal to the second gating unit 222.

[0113] As for the functions of other components of the microprocessor architecture in this embodiment and their interconnections, please refer to the relevant content of the foregoing embodiments, which will not be repeated here.

[0114] In summary, the microprocessor architecture provided in this application includes an initial clock unit comprising a unit-level configuration unit and at least two parallel initial signal generation units. Each initial signal generation unit generates its corresponding initial clock signal based on the first configuration information and the aforementioned basic clock signal. The first gating unit outputs the initial clock signal generated by the initial signal generation unit indicated by the first gating information as a target clock signal to the functional unit, so that the functional unit operates based on the target clock signal. Compared with related technologies, the clock signal source provided in this application can select clock signals of different clock frequencies by configuring the first configuration information and the first gating information, effectively simplifying the clock frequency adjustment process, improving the clock frequency adjustment efficiency, and meeting the needs of practical applications.

[0115] This application also provides another microprocessor architecture, see [link to application]. Figure 7 As shown, compared to the previous embodiments, the microprocessor architecture provided in this embodiment also includes a basic clock unit 23, which serves as another clock signal source mentioned in the previous embodiments and is used to provide a basic clock signal. The basic clock unit 23 includes a system-level configuration unit 231 and a basic signal generation unit 232.

[0116] Combination Figure 2 As shown, the system-level configuration unit 231 is connected to the control unit 10 and the basic signal generation unit 232 respectively. The control unit 10 is also used to configure the second configuration information to the basic clock unit 23. Based on this, the system-level configuration unit 231 can be used to store the second configuration information. Referring to the optional implementation of the first configuration information mentioned above, the second configuration information mentioned in this embodiment can be the clock frequency or the frequency division ratio. Of course, it can also be other configuration information used to instruct the basic signal generation unit 232 to generate the basic clock signal, which will not be listed here.

[0117] In an optional implementation, referring to the aforementioned implementation of the unit-level configuration unit 213, the system-level configuration unit 231 can be implemented using a register group. The register group serves as an intermediary for the interaction of the second configuration information between the control unit 10 and the basic signal generation unit 232. In practical applications, the intermediary role of the system-level configuration unit 231 is mainly manifested in the following ways: the control unit 10 writes the second configuration information into the system-level configuration unit 231, which stores it; the basic signal generation unit 232 can obtain the second configuration information by accessing the system-level configuration unit 231. Of course, other methods for realizing information interaction between the control unit 10 and the basic signal generation unit 232 are also optional, and will not be detailed here.

[0118] The basic signal generation unit 232 receives a reference clock signal and second configuration information stored in the system-level configuration unit 231, and generates a basic clock signal based on the second configuration information and the reference clock signal. The reference clock signal can be provided by other clock signal sources in the microprocessor architecture or by a crystal oscillator; this application does not limit the specific source of the reference clock signal.

[0119] This embodiment provides an optional implementation of a basic clock unit, which includes a system-level configuration unit and a basic signal generation unit. The basic signal generation unit generates a basic clock signal based on the second configuration information stored in the system-level configuration unit and the reference clock signal, thereby meeting the requirements of the initial signal generation units connected to the subsequent stage of the basic clock unit to output initial clock signals. The basic clock signal can be adjusted by configuring the second configuration information, which effectively simplifies the adjustment process of the basic clock signal and helps to improve the adjustment efficiency of the clock frequency.

[0120] In one optional implementation, referring to the aforementioned implementation of the initial signal generation unit, the basic signal generation unit 232 can be selected from any one of PLL, DPLL, DLL, and ADPLL. Of course, the basic signal generation unit 232 can also be implemented using other related technologies, which will not be detailed here. As for the specific process by which the basic signal generation unit 232 generates the basic clock signal according to the second configuration information and the reference clock signal, it can be referred to the aforementioned backup clock signal generation process. This embodiment provides multiple optional implementations of the basic signal generation unit. By using different forms of phase-locked loops to implement the basic signal generation unit, the existing advantages of the corresponding phase-locked loop technology can be utilized to simplify the design difficulty and improve the design efficiency. Furthermore, the basic signal generation unit is used to provide the basic clock signal. When using PLL for implementation, its low jitter and stable technical advantages can be fully utilized, which helps to improve the reliability of the basic clock signal.

[0121] Furthermore, the second gating input terminal of the second gating unit 222 is connected to the output terminal of the basic signal generation unit 232 in the basic clock unit 23, and receives the basic clock signal output by the basic signal generation unit 232, that is, the basic clock signal is used as a backup clock signal to ensure the safe operation of the functional unit 30 under abnormal conditions. The gating control terminal of the second gating unit 222 is connected to the system-level configuration unit 231 in the basic clock unit 23, and the gating output terminal of the second gating unit 222 is connected to the functional unit 30.

[0122] Based on the above connection relationship, the control unit 10 is also used to configure the second gating information, that is, to configure the second gating information in the system-level configuration unit 231. The second gating information is used to instruct the second gating unit to output the basic clock signal or the target clock signal determined by the first gating unit 221 to the functional unit 30.

[0123] Understandably, in order to meet the clock frequency requirements of each functional unit in the microprocessor architecture, each initial signal generation unit in the initial clock unit 21 will perform frequency upsampling on the basic clock signal. In other words, the clock frequency of the initial clock signal output by each initial signal generation unit is higher than the clock frequency of the basic clock signal. Correspondingly, the clock frequency of the target clock signal determined in each initial clock signal is also higher than the clock frequency of the basic clock signal. Therefore, the basic clock signal can be used as the clock signal for emergency avoidance of the functional unit. The basic clock signal is a clock signal that can ensure the safe and stable operation of the functional unit under abnormal conditions.

[0124] Based on the above, in one optional implementation, the second strobe information includes an operating configuration value or a risk avoidance configuration value. The operating configuration value instructs the second strobe unit 222 to output a target clock signal, while the risk avoidance configuration value instructs the second strobe unit 222 to output a base clock signal. Specifically, when the timing margin of the current clock signal of the functional unit 30 is insufficient, requiring frequency reduction for emergency risk avoidance, the second strobe information is the risk avoidance configuration value. The second strobe unit 222 responds to the risk avoidance configuration value by outputting a base clock signal, ensuring that the functional unit 30 can operate safely without timing chaos due to insufficient timing margin. Conversely, when the functional unit 30 is operating normally, the second strobe information is the operating configuration value, and the second strobe unit 222 responds to the operating configuration value by outputting a target clock signal to the functional unit 30, ensuring normal operation of the functional unit 30. It is understood from the foregoing that in practical applications, there is no specific requirement for the magnitude of the operating configuration value and the risk avoidance configuration value; simply selecting different configuration values ​​is sufficient.

[0125] In this embodiment, the target clock signal or the base clock signal is selected to be output to the functional unit through the second gating unit. As mentioned above, adjusting the clock frequency may cause abnormal operation of the functional unit or even the microprocessor architecture. Based on this, in the event of an abnormality, the base clock signal can be selected to be output to the functional unit by configuring the second gating information, thereby ensuring the safe operation of the functional unit. In other words, this application provides a safety protection mechanism that realizes the switching between the target clock signal and the base clock signal by configuring the second gating information to meet the risk avoidance requirements in abnormal situations.

[0126] As for Figure 7 The functions of the other components of the clock signal source and their interconnections in the illustrated embodiment can be found by referring to... Figure 1 The relevant content of the illustrated embodiment will not be repeated here.

[0127] This application also provides another microprocessor architecture, see [link to application]. Figure 8 As shown, compared to the previous embodiments, the microprocessor architecture provided in this embodiment also includes an early warning unit 224 in the frequency modulation unit 22.

[0128] The early warning unit 224 is used to detect early warning events of the functional unit 30, such as insufficient timing margin or excessive temperature of the functional unit 30. The early warning unit 224 is connected to the gating control terminal of the first gating unit 221. In response to a detected early warning event, the early warning unit 224 outputs a preset gating signal. The first gating unit 221, in response to the preset gating signal, determines the initial clock signal with the lowest clock frequency among the obtained initial clock signals as the target clock signal and outputs it to the functional unit 30, thereby reducing the clock frequency of the functional unit 30. Compared to the aforementioned system-level risk avoidance mechanism based on the system-level configuration unit 231 and the second gating unit 222, the risk avoidance measure based on the cooperation of the early warning unit 224 and the first gating unit 221 can be defined as a unit-level risk avoidance mechanism. That is, it ensures the operational safety of the functional unit 30 by reducing the clock frequency. Furthermore, since the preset gating signal is directly triggered by the early warning unit, a rapid response to early warning events can be achieved, which helps improve the operational safety of the functional unit.

[0129] Furthermore, combining Figure 8 As shown, the gating control terminal of the first gating unit 221 is connected to the unit-level configuration unit 213 and the early warning unit 224 respectively. In practical applications, both the control unit 10 and the early warning unit 224 can control the gating status of the first gating unit 221. The specific control process can be referred to the above content and will not be repeated here.

[0130] As for Figure 8The functions of the other components of the clock signal source and their interconnections in the illustrated embodiment can be found by referring to... Figure 1 The relevant content of the illustrated embodiment will not be repeated here.

[0131] This application also provides another microprocessor architecture, see [link to application]. Figure 9 As shown, compared to the previous embodiments, the microprocessor architecture provided in this embodiment also includes an inter-core communication unit 40.

[0132] Combination Figure 9 As shown, the inter-core communication unit is connected to the control unit and each of the functional units respectively, and the inter-core communication unit serves as an intermediary when the control unit and each of the functional units interact.

[0133] The inter-core communication unit 40 is connected to both the control unit 10 and the functional units 30. The inter-core communication unit 40 acts as an intermediary for interaction between the control unit 10 and each functional unit 30, transmitting interactive data between them. For example, a functional unit 30 can send a frequency modulation request to the control unit 10 through the inter-core communication unit 40. In response to the received frequency modulation request, the control unit 10 provides clock signals of different clock frequencies to the functional unit 30 according to the frequency modulation process described in the aforementioned embodiments. The specific implementation of the inter-core communication unit can be found in relevant technologies and will not be detailed here.

[0134] As an optional implementation, the early warning unit 224 can also be connected to the gating control terminal of the second gating unit 222. As mentioned above, the early warning unit 224 responds to the early warning event of the functional unit 30 by outputting a preset gating signal, instructing the second gating unit to output a backup clock signal. Figure 9 In the illustrated embodiment, the backup clock signal is the basic clock signal provided by the basic clock unit 23. As mentioned earlier, the clock frequency of the basic clock signal is usually lower than the clock frequency of each initial clock signal provided by the initial clock unit 21. Therefore, when a warning event occurs, the basic clock signal is output, and the operation safety of the functional unit can be ensured by reducing the clock frequency. Since the preset strobe signal is directly triggered by the warning unit, a rapid response to the warning event can be achieved, which helps to improve the operation safety of the functional unit.

[0135] As for Figure 9 The functions of the other components of the clock signal source and their interconnections in the illustrated embodiment can be found by referring to... Figure 1 The relevant content of the illustrated embodiment will not be repeated here.

[0136] This application also provides a computer device including the microprocessor architecture provided in any of the foregoing embodiments.

[0137] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0138] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0139] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.

[0140] Those skilled in the art will understand that all or part of the steps in the above methods can be executed by a computer program requesting relevant hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.

[0141] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0142] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A microprocessor architecture, characterized in that, include: At least one functional unit, said functional unit being used to implement a preset function of the microprocessor architecture; At least one clock signal source, each of the clock signal sources being connected to one or more of the functional units; The control unit is used to configure first configuration information, first strobe information, and second strobe information; The clock signal source includes: an initial clock unit and a frequency modulation unit, wherein, The initial clock unit is used to generate at least two initial clock signals according to the first configuration information; The frequency modulation unit includes: a first gating unit and a second gating unit, wherein... The first gating unit receives the at least two initial clock signals and the first gating information, and outputs the initial clock signal indicated by the first gating information as the target clock signal. The second gating unit receives the target clock signal, the second gating information, and the backup clock signal, and outputs the clock signal indicated by the second gating information in the target clock signal and the backup clock signal, so that the functional unit operates based on the clock signal output by the second gating unit. The backup clock signal is provided by other clock signal sources and is a clock signal that ensures the reliable operation of the functional unit in case of abnormal warning.

2. The microprocessor architecture according to claim 1, characterized in that, The frequency modulation unit operates within the voltage domain corresponding to the connected functional unit; The frequency modulation unit further includes: At least two timing sensors are connected to the initial clock unit respectively. Each timing sensor receives an initial clock signal and feeds back the timing characteristic parameters of the initial clock signal when it is transmitted within the corresponding voltage domain. The control unit is used to determine the first gating information based on the timing characteristic parameters.

3. The microprocessor architecture according to claim 2, characterized in that, The initial clock unit includes: A first configuration unit, connected to the control unit, is used to store the first configuration information, which includes at least two clock frequencies. At least two initial signal generation units, each of which generates an initial clock signal based on one of the clock frequencies.

4. The microprocessor architecture according to claim 3, characterized in that, The initial clock unit further includes: The clock backup unit, as the other clock signal source, is connected to the first configuration unit and generates the backup clock signal based on the first configuration information.

5. The microprocessor architecture according to claim 2, characterized in that, The frequency modulation unit further includes: The second configuration unit is used to store the timing characteristic parameters, the first gating information, and the second gating information.

6. The microprocessor architecture according to claim 1, characterized in that, The initial clock unit is used to generate at least two initial clock signals according to the first configuration information; The initial clock unit includes: A unit-level configuration unit, connected to the control unit, is used to store the first configuration information, which includes at least two clock frequencies; At least two initial signal generation units, each of which generates an initial clock signal based on a clock frequency and a base clock signal.

7. The microprocessor architecture according to claim 6, characterized in that, The clock signal source also includes: A base clock unit is connected to the initial clock unit and provides the base clock signal to the initial clock unit.

8. The microprocessor architecture according to claim 7, characterized in that, The control unit is also used to configure second configuration information; The basic clock unit includes: A system-level configuration unit, connected to the control unit, is used to store the second configuration information; A basic signal generation unit generates the basic clock signal according to the second configuration information.

9. The microprocessor architecture according to claim 8, characterized in that, The basic signal generation unit is connected to the second gating unit; The base clock signal serves as the backup clock signal.

10. The microprocessor architecture according to claim 8, characterized in that, The system-level configuration unit is connected to the gating control terminal of the second gating unit, and the system-level configuration unit is also used to store the second gating information.

11. The microprocessor architecture according to claim 8, characterized in that, The basic signal generation unit includes a phase-locked loop (PLL), and the initial signal generation unit includes any one of a phase-locked loop (PLL), a delayed phase-locked loop (DLL), a digital phase-locked loop (DPLL), and a fully digital phase-locked loop (ADPLL).

12. The microprocessor architecture according to any one of claims 1 to 11, characterized in that, The frequency modulation unit further includes: The early warning unit is connected to the gating control terminal of the second gating unit and is used to output a preset gating signal in response to the early warning event of the functional unit. The preset gating signal is used to instruct the second gating unit to output the backup clock signal.

13. The microprocessor architecture according to any one of claims 1 to 11, characterized in that, Also includes: The inter-core communication unit is connected to the control unit and each of the functional units respectively, and the inter-core communication unit serves as an intermediary when the control unit and each of the functional units interact.

14. A computer device, characterized in that, Including the microprocessor architecture as described in any one of claims 1 to 13.

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