Display devices and electronic devices

Abstract

A display device and an electronic device are disclosed. The display device includes a display panel. A main circuit board has a recessed portion recessed in the thickness direction of the display panel. A connecting circuit board is electrically connected to the display panel on a first side of the connecting circuit board and electrically connected to the main circuit board on a second side of the connecting circuit board opposite to the first side. A driver chip is mounted on the second side of the connecting circuit board and disposed in the recessed portion. The main circuit board includes a shielding layer superimposed on the recessed portion. The display device protects the driver chip included therein from external electrostatic discharge.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0088763, filed on July 5, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Research is currently underway to develop various types of display devices. These devices are used in a wide range of multimedia equipment, including televisions, mobile phones, tablet computers, navigation systems, and game consoles. A display device includes a display panel for displaying images and a circuit board integrated with the display panel to provide drive signals to it. The display panel includes a display portion for displaying images and a panel pad disposed on the outside of the display panel to provide drive signals to the display portion.

[0003] Circuit boards can be electrically connected to each other via pads. For example, when the pads of the circuit board, the pads of the display panel, and the pads of each of the interconnected circuit boards are fully electrically connected to each other, control signals and image signals can be transmitted to the display panel without distortion. Background Technology

[0004] This disclosure relates herein to a display device, and more specifically, to a display device with improved reliability. Utility Model Content

[0005] This disclosure provides a display device capable of protecting the driver chip included therein from external electrostatic discharge.

[0006] According to an embodiment of the present invention, the display device includes a display panel. A main circuit board has a recessed portion recessed in the thickness direction of the display panel. A connecting circuit board is electrically connected to the display panel on a first side of the connecting circuit board and electrically connected to the main circuit board on a second side of the connecting circuit board opposite to the first side. A driver chip is mounted on the second side of the connecting circuit board and disposed in the recessed portion. The main circuit board includes a shielding layer stacked with the recessed portion.

[0007] According to an embodiment of the present invention, the display device includes a display panel. A main circuit board has a recessed portion recessed in the thickness direction of the display panel. A connecting circuit board is electrically connected to the display panel on a first side of the connecting circuit board and electrically connected to the main circuit board on a second side of the connecting circuit board opposite to the first side. A driver chip is mounted on the second side of the connecting circuit board and disposed in the recessed portion. The main circuit board includes a shielding pattern surrounding the driver chip on a plane.

[0008] According to an embodiment of the present invention, a display device includes a display panel comprising a first region to a third region spaced apart from each other. The first region includes pixels. A second region is flexible relative to a virtual axis extending in a first direction. A third region includes a driver chip mounted thereon. The driver chip is electrically connected to the pixels. A main circuit board includes a recessed portion recessed in the thickness direction of the display panel. The driver chip is disposed in the recessed portion. The main circuit board includes a shielding layer superimposed on the recessed portion.

[0009] According to an embodiment of the present invention, an electronic device includes a display device. An electronic module is stacked with the display device. A housing accommodates the display device. The display device includes a display panel. A main circuit board has a recessed portion recessed in the thickness direction of the display panel. A connecting circuit board is electrically connected to the display panel on a first side of the connecting circuit board and electrically connected to the main circuit board on a second side of the connecting circuit board opposite to the first side. A driver chip is mounted on the second side of the connecting circuit board and disposed in the recessed portion. The main circuit board includes a shielding layer stacked with the recessed portion.

[0010] The display device according to the embodiments of the present invention can protect the driver chip included therein from external static electricity. Attached Figure Description

[0011] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0012] Figure 1 This is a perspective view of an electronic device according to an embodiment of the present invention.

[0013] Figure 2 This is an exploded perspective view of an electronic device according to an embodiment of the present invention.

[0014] Figure 3 This is a plan view of a display device according to an embodiment of the present invention.

[0015] Figure 4A and Figure 4B Each of these is a cross-sectional view showing an embodiment of a display device according to the present invention.

[0016] Figure 5 This is a cross-sectional view of a display module according to an embodiment of the present invention.

[0017] Figure 6 This is an embodiment based on the concept of the present utility model. Figure 4B A magnified view of region AA' shown in the image;

[0018] Figure 7A and Figure 7B This is a view from a third party of an embodiment based on the present invention. Figure 6 Plan view of area AA';

[0019] Figure 8A This is an enlarged view showing a display device according to an embodiment of the present invention.

[0020] Figure 8B This is a view from a third party of an embodiment based on the present invention. Figure 8A Plan view of area AA';

[0021] Figure 9A and Figure 9B Each of these is a cross-sectional view showing an embodiment of a display device according to the present invention.

[0022] Figure 10A and Figure 10B These are cross-sectional views of display devices according to embodiments of the present invention; and

[0023] Figure 11 This is a diagram illustrating an electronic device according to an embodiment of the present invention. Detailed Implementation

[0024] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. However, the present invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein.

[0025] In this specification, it will be understood that when an element (or region, layer, portion, etc.) is referred to as being "on" another element, "connected to" or "bonded to" another element, the element may be directly disposed on, directly connected to or directly bonded to the other element, or an intermediary element may be disposed between the element and the other element. When an element is referred to as being "directly on" another element, "directly connected to" or "directly bonded to" another element, no intermediary element may be disposed between the element and the other element.

[0026] The same reference numerals or designations always denote the same elements. In the accompanying drawings, the thickness, scale, and dimensions of elements may be exaggerated in order to effectively describe the technical content.

[0027] As used herein, the term “and / or” includes any and all combinations of one or more of the relevant listed items.

[0028] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or segment from another element, component, region, layer, or segment. Therefore, without departing from the scope of the inventive concept, the first element, first component, first region, first layer, or first segment discussed below may be referred to as the second element, second component, second region, second layer, or second segment. Similarly, the second element, second component, second region, second layer, or second segment may be referred to as the first element, first component, first region, first layer, or first segment. Unless the context clearly indicates otherwise, in this specification, "a," "an," and "the" are also intended to include the plural forms.

[0029] Additionally, terms such as "below," "under," "above," and "on top" can be used to describe the relationships between the elements shown in the accompanying drawings. These terms are relative and are based on the directions indicated in the drawings.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless so explicitly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formalized sense.

[0031] It will also be understood that when the terms “comprising / including” and / or “having / possessing” are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, components and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0032] In the following description, embodiments of the present invention will be described with reference to the accompanying drawings.

[0033] This invention relates to a display device including a main circuit board with a recessed portion in which a driver chip is disposed. A shielding layer may be stacked on a plane with the driver chip disposed in the recessed portion. Multiple shielding patterns may surround the driver chip disposed in the recessed portion on a plane. The driver chip disposed in the recessed portion can be protected from external electrostatic discharge by the multiple shielding patterns and the shielding layer. Furthermore, the display device may not require a separate covering space for protecting the driver chip. Therefore, the display device can have improved reliability and a simplified manufacturing process.

[0034] Figure 1 This is a perspective view of an electronic device according to an embodiment of the present invention. Figure 2 This is an exploded perspective view of an electronic device according to an embodiment of the present invention.

[0035] The electronic device ED can be activated in response to an electrical signal. The electronic device ED can include various embodiments. For example, in some embodiments, the electronic device ED can be applied to electronic devices such as mobile phones, smartwatches, tablet computers, laptop computers, computers, and smart TVs. The display device according to the embodiments of the present inventive concept is not limited to the above examples and can also be used in another electronic device, as long as it does not depart from the present inventive concept. In this embodiment, the electronic device ED is exemplarily shown as a mobile phone.

[0036] The electronic device ED can display an image IM on a display surface FS parallel to each of the first direction DR1 and the second direction DR2, facing a third direction DR3. The display surface FS on which the image IM is displayed can correspond to the front surface of the display device DD. The image IM can include at least one still image and / or at least one moving image (e.g., a motion image). Figure 1 The illustrations show software application icons and clock, temperature, and calendar windows as examples of image-based instant messaging (IM). However, embodiments of this inventive concept are not limited to these, and image-based IMs can have a variety of different themes.

[0037] In this embodiment, the front surface (e.g., upper surface) and rear surface (e.g., lower surface) of each component are defined based on the direction along which the displayed image IM is traversed. The front and rear surfaces may be opposite each other on a third direction DR3, and the normal direction of each of the front and rear surfaces may be parallel to the third direction DR3. The distance between the front and rear surfaces on the third direction DR3 may correspond to the thickness of the display device DD on the third direction DR3. In this specification, "on a plane" may mean when viewed from the third direction DR3. The directions indicated from the first direction to the third directions DR1, DR2, and DR3 may have a relative concept and therefore may be changed to other directions.

[0038] The electronic device (ED) can detect external inputs applied from the outside (e.g., the external environment). External inputs can include various types of inputs provided from outside the electronic device (ED). For example, in embodiments, external inputs can include not only external inputs applied through contact with a part of the user's body (such as a hand), but also external inputs applied near or adjacent to the electronic device (ED) at a predetermined distance (e.g., hovering). Furthermore, external inputs can take various forms such as electricity, pressure, temperature, and light.

[0039] An electronic device ED may include a window (WM) and a housing (HU). The window (WM) and the housing (HU) may be combined with each other to form the appearance of the electronic device ED.

[0040] The window WM can be divided into a transmission area TA and a frame area BZA. The front surface of the electronic device ED can correspond to the transmission area TA and the frame area BZA of the window WM.

[0041] The transmissive region TA can be the area where the image IM is displayed. The transmissive region TA can be an optically transparent area. Users can view the image IM through the transmissive region TA.

[0042] In this embodiment, the transmission region TA is shown as a quadrilateral shape with rounded corners. However, embodiments of the present invention are not limited to this, and the transmission region TA can have various different shapes.

[0043] The border area BZA can be an area with relatively low light transmittance compared to the transmissive area TA. For example, the border area BZA can be an area printed with a material containing a predetermined color.

[0044] The border region BZA can be a region adjacent to the transmission region TA. The border region BZA can (e.g., in a plan view) surround the transmission region TA. Therefore, the shape of the transmission region TA can be substantially defined by the border region BZA. However, embodiments of this disclosure are not limited to this; the border region BZA can also be disposed adjacent only to one side of the transmission region TA, and the border region BZA can also be omitted.

[0045] Refer to together Figure 1 and Figure 2 In an embodiment, the electronic device ED may include a display device DD, an electronic module EM, a power module PSM, and a housing HU. Figure 2 The electronic device ED is briefly shown, and the electronic device ED may also include a mechanical structure (e.g., a hinge) for controlling the operation of the display device DD (e.g., folding or rolling).

[0046] In this embodiment, the display device DD includes a window WM, a display module DM, a lower component LM, a driver chip DIC, a connection circuit board CF, and a main circuit board MB. The display module DM may include a display panel DP and an input sensing layer ISL.

[0047] The window WM can be disposed on the display module DM (e.g., directly disposed on the display module DM on a third-party DR3). The window WM can protect the display module DM. The window WM can include optically transparent materials. For example, in an embodiment, the window WM can include glass, sapphire, plastic, etc. The image IM provided from the display module DM can be provided to the user through the window WM.

[0048] Window WMs can have a single-layer or multi-layer structure. For example, a window WM may include multiple plastic films bonded together, or a glass substrate and plastic films bonded together.

[0049] The display module DM may include a front surface IS having an active area AA and a peripheral area NAA. The active area AA may be an area activated in response to an electrical signal. In an embodiment, the active area AA may be an area for displaying an image IM and simultaneously an area for detecting external input.

[0050] The transmission region TA can be (e.g., on a third-direction DR3) superimposed on at least a portion of the effective region AA. Therefore, a user can view the image IM through the transmission region TA, or provide external input through the transmission region TA. However, embodiments of the present invention are not limited to this; the area displaying the image IM and the area detecting external input can also be separated within the effective region AA.

[0051] The peripheral region NAA can be the area covered by the border region BZA. The peripheral region NAA is adjacent to the active region AA (e.g., adjacent to the active region AA in the first direction DR1 and / or the second direction DR2). The peripheral region NAA can (e.g., in a plan view) surround the active region AA. The drive circuitry, drive wiring, etc., used to drive the active region AA can be located in the peripheral region NAA.

[0052] The display panel DP according to embodiments of the present invention can be a liquid crystal display panel or an emissive display panel. However, embodiments of the present invention are not limited to this. For example, in embodiments, the emissive display panel can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots, quantum rods, etc.

[0053] In this embodiment, the display panel DP can be flexible. "Flexible" can indicate bendability and can encompass everything from fully foldable to partially bendable structures. For example, the display panel DP can be a bendable display panel or a foldable display panel. However, embodiments of this inventive concept are not limited to this; the display panel DP can also be a rigid display panel.

[0054] The input sensing layer (ISL) can be disposed on the display panel (DP). In an embodiment, such as... Figure 2 As shown, the input sensing layer ISL can be directly disposed on the display panel DP (e.g., directly disposed on the display panel DP on the third-party DR3). For example, the input sensing layer ISL can be formed on the display panel DP through a continuous process, and the adhesive film may not be disposed between the input sensing layer ISL and the display panel DP (e.g., not disposed between the input sensing layer ISL and the display panel DP on the third-party DR3). However, embodiments of the present invention are not limited to this; in some embodiments, the adhesive film can be disposed between the input sensing layer ISL and the display panel DP. For example, the input sensing layer ISL can be manufactured in a process separate from the process of the display panel DP, and then fixed to the upper surface of the display panel DP by the adhesive film.

[0055] The input sensing layer (ISL) can detect external inputs applied from the outside (e.g., the external environment). As previously described, the input sensing layer (ISL) can detect external inputs provided to the window (WM).

[0056] The connecting circuit board CF can connect (e.g., electrically connect) the display panel DP and the main circuit board MB to each other. In an embodiment, the connecting circuit board CF can be electrically connected to the display panel DP on the side adjacent to the display panel DP (e.g., a first side). The connecting circuit board CF can also be electrically connected to the main circuit board MB on the other side adjacent to the main circuit board MB (e.g., a second side opposite to the first side). For example, in an embodiment, the upper side of the connecting circuit board CF (e.g., the upper side in the direction opposite to the second direction DR2) can be physically and electrically connected to the first side of the display panel DP, and the lower side of the connecting circuit board CF (e.g., the lower side in the second direction DR2) can be physically and electrically connected to the second side of the main circuit board MB.

[0057] In this embodiment, a connecting circuit board CF is shown connecting the display panel DP and the main circuit board MB to each other. However, the embodiments of the present invention are not limited to this. Multiple connecting circuit boards CF can be provided to connect the display panel DP and the main circuit board MB to each other (e.g., electrical connection).

[0058] In this embodiment, the connecting circuit board CF can be a flexible printed circuit board. The connecting circuit board CF can provide electrical signals to the display panel DP to drive the display panel PD. The electrical signals can be generated from the connecting circuit board CF or from the main circuit board MB.

[0059] In one embodiment, the driver chip DIC may be mounted under the connection circuit board CF (e.g., directly under the connection circuit board CF in the direction opposite to the third-direction DR3). However, unlike what is shown in the figures, in some embodiments, the driver chip DIC may be mounted on the connection circuit board CF (e.g., directly on the connection circuit board CF on the third-direction DR3). The driver chip DIC may be mounted on a flexible printed circuit board to form a chip on film (COF). In one embodiment, the driver chip DIC may be mounted on a second side of the connection circuit board CF.

[0060] The driver chip DIC may include driving elements for driving pixels of the display panel DP. In an embodiment, the driver chip DIC may include a driving circuit, and the driving circuit may be configured as an integrated circuit. The driving circuit may include a drive controller, a data driver, a voltage generator, etc.

[0061] The main circuit board (MB) may include a main controller. In an embodiment, the main circuit board (MB) may include signal wiring for transmitting control signals and image signals received from the main controller to the connection circuit board (CF) and the display panel (DP). The main circuit board (MB) may be a rigid printed circuit board or a flexible printed circuit board.

[0062] In this embodiment, an input circuit board electrically connected to the input sensing layer ISL may also be included. The input circuit board can connect the input sensing layer ISL and the main circuit board MB to each other (e.g., electrically). In this embodiment, the input circuit board may be configured as a flexible circuit film, thus enabling the connection (e.g., electrical connection) between the input sensing layer ISL and the main circuit board MB. The input circuit board provides electrical signals to the input sensing layer ISL for driving the input sensing layer ISL. Electrical signals can be generated from the input circuit board or from the main circuit board MB.

[0063] In this embodiment, both the connection circuit board CF and the input circuit board can be connected to a main circuit board MB. Either the connection circuit board CF or the input circuit board may not be connected to the main circuit board MB, and this configuration is not limited to any embodiment of the present invention.

[0064] The lower component LM can be disposed below the display panel DP (e.g., disposed below the display panel DP in the direction opposite to the third direction DR3). In embodiments, the lower component LM may include a protective film protecting the display panel DP, a support component supporting the display panel DP, a digitizer, etc.

[0065] In this embodiment, the electronic module EM may include a control module, a wireless communication module, an image input module, a sound input module, a sound output module, a memory, an external interface module, etc. The electronic module EM may include a main circuit board, and the module may be mounted on the main circuit board or electrically connected to the main circuit board via a flexible printed circuit board. The electronic module EM is electrically connected to the power module PSM.

[0066] In this embodiment, the electronic device ED may further include an electro-optical module. The electro-optical module may be an electronic component that outputs or receives optical signals. The electro-optical module may include a camera module and / or a proximity sensor. The camera module may capture external images through a portion of the display panel DP.

[0067] Figure 2 The housing HU shown is integrated with the display device DD (specifically, with the window WM) to accommodate the aforementioned different modules. The housing HU is shown as having a single, integral form. However, embodiments of the present invention are not necessarily limited to this. For example, in an embodiment, the housing HU may include multiple portions (e.g., side boundary portions and bottom portions) that are joined together. The housing HU can protect the display module DM housed within the internal space from external impacts and can prevent foreign objects or moisture from penetrating the display module DM.

[0068] Figure 3 This is a plan view of a display device according to an embodiment of the present invention.

[0069] Reference Figure 3 The display area DA and the non-display area NDA can be defined in a plane within the display panel DP. The display area DA can be the area where an image is displayed. The non-display area NDA can be the area where no image is displayed. The non-display area NDA can be adjacent to the display area DA (e.g., adjacent to the display area DA in a first direction DR1 and / or a second direction DR2). The non-display area NDA can (e.g., in a plan view) surround the display area DA, but its shape is not necessarily limited to this.

[0070] In an embodiment, the display panel DP may include multiple pixels PX, a scan drive circuit SDC, multiple signal lines, and multiple panel pads (also referred to as "soldering pads") PP. In an embodiment, the signal lines included in the display panel DP may include scan lines SL, transmit lines EL, data lines DL, scan control lines SCL, initialization voltage lines VINTL, and voltage lines VL.

[0071] Each pixel PX may include a display element and a thin-film transistor electrically connected to the display element. The display element may include, for example, an organic light-emitting diode. Pixels PX may be disposed in the display area DA. However, embodiments of the present invention are not limited thereto, and some of the pixels PX may also be disposed in the non-display area NDA.

[0072] In one embodiment, pixels PX can be arranged in a matrix along a first direction DR1 and a second direction DR2 that are perpendicular to each other. In another embodiment of this inventive concept, pixels PX may include first to third pixels that respectively display red, green, and blue. In yet another embodiment, pixels PX may also include some pixels that respectively display white, cyan, and magenta. However, embodiments of this inventive concept are not limited to these limitations, and the color of the light emitted by pixels PX can vary.

[0073] The scan drive circuit SDC can be configured to be adjacent to one side of the non-display area NDA. For example, as Figure 3 As shown, the scan drive circuit SDC can be positioned adjacent to the left side of the non-display area NDA (e.g., on the left side in the direction opposite to the first direction DR1). However, embodiments of the present invention are not limited to this; the positioning of the scan drive circuit SDC can vary, and the scan drive circuit SDC can also be positioned within the display area DA. The scan drive circuit SDC can generate multiple scan signals, and the generated scan signals can be output sequentially via the scan lines SL, which will be described later. The scan drive circuit SDC can also output other control signals to the drive circuit of the pixel PX.

[0074] In this embodiment, scan lines SL can extend laterally from the scan driving circuit SDC along the first direction DR1, and each can be connected to a corresponding pixel among the plurality of pixels PX. Emitting lines EL can extend laterally from the scan driving circuit SDC along the first direction DR1, and each can be arranged next to a corresponding scan line among the scan lines SL. Scan lines SL and EL can be connected to the scan driving circuit SDC.

[0075] In this embodiment, the data lines DL can extend longitudinally along the second direction DR2 and can all be connected to the corresponding pixel PX among the multiple pixels PX. The scan control line SCL can provide control signals to the scan drive circuit SDC.

[0076] An initialization voltage line VINTL can provide initialization voltage to multiple pixels PX. The voltage line VL can be connected to multiple pixels PX and can provide voltage to multiple pixels PX. In an embodiment, the voltage line VL may include multiple lines extending laterally along a first direction DR1 and multiple lines extending longitudinally along a second direction DR2.

[0077] Some of the scan lines SL, DL, EL, SCL, VINTL, and VL can be set on the same layer as each other, while others can be set on different layers.

[0078] Panel pads (PPs) can be arranged in the non-display area (NDA). In an embodiment, the panel pads (PPs) can be arranged side-by-side along a first direction (DR1). In this embodiment, the panel pads (PPs) are shown and described as arranged in a row along the first direction (DR1). However, embodiments of the present invention are not limited to this. For example, the panel pads (PPs) can be arranged in two or more rows, or in an interleaved manner. The panel pads (PPs) can be connected to the data line (DL), scan control line (SCL), initialization voltage line (VINTL), and voltage line (VL).

[0079] In an embodiment, the connecting circuit board CF may include a connecting substrate layer CF-F, multiple panel connection pads CP-A, and multiple board connection pads CP-C.

[0080] The bonding substrate layer CF-F can be an insulating layer on which multiple panel bonding pads CP-A and multiple board bonding pads CP-C are disposed. The bonding substrate layer CF-F may include a flexible film.

[0081] In an embodiment, the panel connection pad CP-A may be arranged along the first direction DR1 on the side adjacent to the display panel DP (e.g., the first side) (e.g., on the upper side in the direction opposite to the second direction DR2). The panel connection pad CP-A may be connected to the panel pads PP of the display panel DP that correspond to the panel connection pad CP-A.

[0082] In one embodiment, the panel pad PP can be disposed on the front surface of the display panel DP, and the panel connection pad CP-A can be disposed on the rear surface of the connection substrate layer CF-F. However, the embodiments of the present invention are not limited to this. In some embodiments, the panel pad PP can be disposed on the rear surface of the display panel DP, and the panel connection pad CP-A can be disposed on the front surface of the connection substrate layer CF-F.

[0083] The board connection pad CP-C can be disposed along the first direction DR1 on the opposite side (e.g., the second side) adjacent to the main circuit board MB (e.g., on the lower side in the second direction DR2). The board connection pad CP-C can be spaced apart from the panel connection pad CP-A along the second direction DR2. In an embodiment, the board connection pad CP-C can be disposed on the rear surface of the connection substrate layer CF-F. However, embodiments of the present invention are not limited thereto; in some embodiments, the board connection pad CP-C can be disposed on the front surface of the connection substrate layer CF-F.

[0084] In one embodiment, the connection board CF may include multiple wirings. Each of the multiple wirings can transmit electrical signals to components connected to one end and the other end. The multiple wirings may include wiring that electrically connects panel connection pad CP-A to driver chip DIC, and wiring that electrically connects board connection pad CP-C to driver chip DIC. The multiple wirings may be disposed on the connection substrate layer CF-F.

[0085] The main circuit board (MB) may include multiple pads (MP). In an embodiment, the main circuit board (MB) may include multiple traces connected to the pads (MP).

[0086] The pad MP can be arranged along the first direction DR1 on the side adjacent to the connecting circuit board CF (e.g., on the underside in the second direction DR2). In an embodiment, the pad MP can be arranged on the front surface of the main circuit board MB. However, embodiments of the present invention are not limited thereto; in some embodiments, the pad MP can be arranged on the rear surface of the main circuit board MB.

[0087] Board pads MP can be connected to board connection pads CP-C, each corresponding to a board pad MP, on the connecting circuit board CF. In an embodiment, each of the board connection pads CP-C can be electrically connected to the main controller via wiring and can receive control signals and image signals from the main controller. The board pad MP can transmit the received signals to the board connection pads CP-C.

[0088] To make it easier to understand the connection between panel pad PP and panel connector pad CP-A, and the connection between board pad MP and board connector pad CP-C. Figure 3 The pads are shown arranged in an alternating manner. However, embodiments of the present invention are not limited to this, and the pads can be connected to the corresponding pads by stacking them on top of each other (e.g., on a third-direction DR3).

[0089] When the panel pad PP and the panel connector pad CP-A are fully and completely connected (e.g., electrically connected), control signals and image signals transmitted from the drive circuit of the driver chip DIC can be transmitted to the display panel DP without distortion. When the board pad MP and the board connector pad CP-C are fully and completely connected, control signals and image signals received from the main controller of the main circuit board MB can be transmitted to the drive circuit of the driver chip DIC without distortion.

[0090] Figure 4A and Figure 4B These are cross-sectional views of display devices, each illustrating an embodiment of the present invention. Specifically, Figure 4A It shows Figure 3 The cross-section of the display device DD shown in the figure. Figure 4B It is shown Figure 4A A diagram showing the bent state of the display device DD. Repeated or previously described content will be omitted in the following text.

[0091] Reference Figure 4A The lower component LM may include a lower membrane PF (e.g., a protective film) and a cover plate CP. According to embodiments of the present invention, the lower component LM may also include a support plate and a digitizer.

[0092] The cover plate CP can be disposed below the lower film PF (e.g., disposed below the lower film PF in the direction opposite to the third direction DR3). The cover plate CP can increase resistance to compressive forces generated by external pressing. Therefore, the cover plate CP can be used to prevent deformation of the display module DM. In embodiments, the cover plate CP can comprise a flexible plastic material such as polyimide or polyethylene terephthalate. Alternatively, the cover plate CP can be a colored film with low light transmittance. The cover plate CP can absorb light incident from the outside (e.g., the external environment). For example, in embodiments, the cover plate CP can be a black synthetic resin film.

[0093] In an embodiment, the support plate may be further disposed below the cover plate CP (e.g., disposed below the cover plate CP in a direction opposite to the third direction DR3). The support plate may comprise a metal material with relatively high strength. The support plate may also comprise a reinforcing fiber composite material. The support plate may comprise reinforcing fibers disposed within the matrix portion. The reinforcing fibers may be carbon fibers or glass fibers. The matrix portion may comprise a polymer resin. The matrix portion may comprise a thermoplastic resin. For example, in an embodiment, the matrix portion may comprise a polyamide resin or a polypropylene resin. For example, the reinforcing fiber composite material may be carbon fiber reinforced plastic (CFRP) or glass fiber reinforced plastic (GFRP).

[0094] According to an embodiment of the present invention, the recessed portion DEP can be defined within the main circuit board MB. (For example, when the connecting circuit board CF is in an unbent state,) the recessed portion DEP can be recessed from the upper surface MB-U of the main circuit board MB in a direction opposite to the third direction DR3. The recessed portion DEP can be recessed in the thickness direction of the display module DM. In an embodiment, the recessed portion DEP can have a quadrilateral shape in cross-sectional view. However, the embodiments of the present invention are not limited to this, and the recessed portion DEP can have various shapes such as hemispherical or triangular shapes in cross-sectional view. A driver chip DIC (such as a driver chip DIC mounted on the second side of the connecting circuit board CF) can be disposed within the recessed portion DEP. In an embodiment, the depth of the recessed portion DEP (e.g., the depth of the recessed portion DEP in the third direction DR3) can be greater than the thickness of the driver chip DIC (e.g., the thickness of the driver chip DIC in the third direction DR3), such that the entire driver chip DIC is disposed within the recessed portion DEP. This will be described in detail later.

[0095] Refer to together Figure 4A and Figure 4B According to an embodiment of the present invention, the connecting circuit board CF can be bent with a predetermined curvature in a direction toward the rear surface of the display panel DP. For example, in an embodiment, the connecting circuit board CF can be bent relative to a bending axis FX parallel to the first direction DR1. In this case, the main circuit board MB can be disposed on the rear surface of the display panel DP. For example, in an embodiment, when the connecting circuit board CF is in a bent state, the main circuit board MB can be disposed on the rear surface CP-B of the cover plate CP.

[0096] According to an embodiment of the present invention, the main circuit board MB may include an upper surface MB-U and a rear surface MB-B that are opposite to each other (e.g., opposite to each other on a third-direction DR3). When the connecting circuit board CF is bent in a direction toward the rear surface of the display panel DP, the rear surface MB-B of the main circuit board MB may face the rear surface CP-B of the cover plate CP to connect with each other (e.g., directly connected to the rear surface CP-B of the cover plate CP).

[0097] The display device DD according to an embodiment of the present invention may further include a shielding film SHF disposed on a connecting circuit board CF (e.g., directly disposed on the connecting circuit board CF). For example, when the connecting circuit board CF is in an unbent state, the shielding film SHF may be directly disposed on the upper surface of the connecting circuit board CF. The shielding film SHF may be stacked on a plane with the driver chip DIC. In an embodiment, the shielding film SHF may face the driver chip DIC, and the connecting circuit board CF is located between the shielding film SHF and the driver chip DIC (e.g., the connecting circuit board CF is located between the shielding film SHF and the driver chip DIC on a third-direction DR3). (See reference...) Figure 4B Because the shielding film SHF is superimposed on the driver chip DIC on a plane, it can protect the driver chip DIC from [damage / damage]. Figure 2 The effects of static electricity generated by electronic modules (EM), power modules (PSM), etc., are shown in the figure.

[0098] The display device DD according to an embodiment of the present invention may further include a conductive adhesive component. The conductive adhesive component may be disposed between the display panel DP and the connecting circuit board CF, and between the connecting circuit board CF and the main circuit board MB. The conductive adhesive component can... Figure 3 The panel pad PP and the panel connector pad CP-A of the connecting circuit board CF shown are bonded to each other. Additionally, conductive adhesive components can... Figure 3 The main circuit board MB shown in the figure has board pad MP and board connection pad CP-C of the connecting circuit board CF bonded to each other.

[0099] Figure 5 This is a cross-sectional view of a display module according to an embodiment of the present invention. For example, Figure 5 The display module DM is shown with Figure 3 The cross-section corresponding to the pixel PX.

[0100] Reference Figure 5 The pixel driving circuit PC that drives the light-emitting element LD may include multiple pixel driving elements. In an embodiment, the pixel driving circuit PC may include multiple transistors S-TFT and O-TFT, as well as a capacitor Cst. The multiple transistors S-TFT and O-TFT may include silicon transistor S-TFT and oxide transistor O-TFT. Figure 5 Exemplary examples are shown of silicon transistor S-TFT and oxide transistor O-TFT. However, embodiments of the present invention are not limited thereto, and the pixel driving circuit can be combined with... Figure 5 The pixel driving circuit PC shown is different. The pixel driving circuit PC may also include any one of silicon transistor S-TFT or oxide transistor O-TFT.

[0101] exist Figure 5In the diagram, the substrate layer BL is shown as a single layer. The substrate layer BL may include a synthetic resin such as polyimide. In an embodiment, a synthetic resin layer may be applied to a working substrate (e.g., a carrier substrate) to form the substrate layer BL. The working substrate may be removed after subsequent processes are performed and the display module DM is completed.

[0102] A first shielding electrode BML1 (e.g., a shielding electrode) may be disposed on the substrate layer BL (e.g., directly disposed on the substrate layer BL on the third-direction DR3). The first shielding electrode BML1 may receive a bias voltage. The first shielding electrode BML1 may also receive a first electrical voltage. The first shielding electrode BML1 may prevent the potential influence of polarization on the silicon transistor S-TFT. The first shielding electrode BML1 may block external light from reaching the silicon transistor S-TFT. According to embodiments of the present invention, the first shielding electrode BML1 may also be a floating electrode electrically isolated from all other electrodes or wiring. The first shielding electrode BML1 may be disposed corresponding to the silicon transistor S-TFT. For example, the first shielding electrode BML1 may be stacked with the silicon transistor S-TFT (e.g., stacked with the silicon transistor S-TFT on the third-direction DR3). The first shielding electrode BML1 may include a metal (e.g., molybdenum).

[0103] A barrier layer BRL can be disposed on the substrate layer BL and the first shielding electrode BML1 (e.g., directly disposed on the substrate layer BL and the first shielding electrode BML1). The barrier layer BRL prevents foreign matter from entering from the outside (e.g., the external environment). The barrier layer BRL may include at least one inorganic layer. In an embodiment, the barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in multiples, and the silicon oxide layer and the silicon nitride layer may be stacked alternately (e.g., alternately stacked on a third-direction DR3).

[0104] A buffer layer BFL can be disposed on a barrier layer BRL (e.g., directly on the barrier layer BRL on a third-direction DR3). The buffer layer BFL prevents metal atoms or impurities from diffusing from the substrate layer BL to the first semiconductor pattern SC1 above it. In embodiments, the buffer layer BFL may include at least one inorganic layer. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer.

[0105] The first semiconductor pattern SC1 may be disposed on the buffer layer BFL (e.g., directly disposed on the buffer layer BFL on the third-party DR3). The first semiconductor pattern SC1 may include a silicon semiconductor. For example, in an embodiment, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern SC1 may include low-temperature polycrystalline silicon.

[0106] The first semiconductor pattern SC1 can differ in electrical properties depending on whether it is doped. The first semiconductor pattern SC1 may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a region doped with a P-type dopant, and an N-type transistor may include a region doped with an N-type dopant. The second region may be an undoped region or a region doped at a lower concentration than the first region. In this embodiment, the first semiconductor pattern SC1 may be an N-type transistor.

[0107] The conductivity of the first region can be higher than that of the second region, and the first region can be substantially used as an electrode or signal line. The second region can substantially correspond to the channel region (e.g., the active region) of the transistor. For example, a portion of the first semiconductor pattern SC1 can be the channel of the transistor, another portion can be the source or drain of the transistor, and this other portion can be a connection electrode or a connection signal line.

[0108] The source region SE1, channel region AC1 (e.g., active region), and drain region DE1 of a silicon transistor S-TFT can be formed by a first semiconductor pattern SC1. In a cross-sectional view, the source region SE1 and the drain region DE1 can extend from the channel region AC1 in opposite directions to each other.

[0109] The first insulating layer 10 may be disposed on the buffer layer BFL (e.g., directly disposed on the buffer layer BFL on the third-direction DR3). The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may be a single-layer silicon oxide layer. In embodiments, not only the first insulating layer 10 but also other inorganic layers of the circuit layer DP-CL, which will be described later, may have a single-layer or multi-layer structure and may include at least one of the materials described above. However, embodiments of the present invention are not necessarily limited thereto.

[0110] The gate GT1 (e.g., gate electrode) of the silicon transistor S-TFT is disposed on the first insulating layer 10 (e.g., directly disposed on the first insulating layer 10 on the third-direction DR3). The gate GT1 may be part of a metal pattern. The gate GT1 is stacked with the channel region AC1 (e.g., stacked with the channel region AC1 on the third-direction DR3). In the process of doping the first semiconductor pattern SC1, the gate GT1 may be a mask. The first electrode CE10 of the storage capacitor Cst is disposed on the first insulating layer 10 (e.g., directly disposed on the first insulating layer 10 on the third-direction DR3). However, embodiments of the present invention are not limited thereto. For example, with Figure 5 As shown in the diagram, the first electrode CE10 can be integrated with the gate GT1.

[0111] The second insulating layer 20 can be disposed on the first insulating layer 10 (e.g., directly disposed on the first insulating layer 10) and cover the gate GT1. According to an embodiment of the present invention, the upper electrode stacked with the gate GT1 can be further disposed on the second insulating layer 20 (e.g., directly disposed on the second insulating layer 20 on the third-direction DR3). The second electrode CE20 stacked with the first electrode CE10 can be disposed on the second insulating layer 20 (e.g., directly disposed on the second insulating layer 20 on the third-direction DR3). In embodiments, the upper electrode can also be integral with the second electrode CE20.

[0112] The second shielding electrode BML2 is disposed on the second insulating layer 20 (e.g., directly disposed on the second insulating layer 20 on the third-direction DR3). The second shielding electrode BML2 may be disposed corresponding to the oxide transistor O-TFT. For example, the second shielding electrode BML2 may be stacked with the oxide transistor O-TFT (e.g., stacked with the oxide transistor O-TFT on the third-direction DR3). However, embodiments of the present invention are not limited thereto. For example, in embodiments of the present invention, the second shielding electrode BML2 may be omitted. According to embodiments of the present invention, the first shielding electrode BML1 may also extend to the lower part of the oxide transistor O-TFT to replace the second shielding electrode BML2.

[0113] The third insulating layer 30 may be disposed on the second insulating layer 20 (e.g., directly disposed on the second insulating layer 20 on the third-direction DR3). The second semiconductor pattern SC2 may be disposed on the third insulating layer 30 (e.g., directly disposed on the third insulating layer 30 on the third-direction DR3). The second semiconductor pattern SC2 may include the channel region AC2 of an oxide transistor O-TFT. The second semiconductor pattern SC2 may include a metal oxide semiconductor. In embodiments, the second semiconductor pattern SC2 may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), and zinc oxide (ZnO). x Transparent conductive oxides (TCOs) of indium oxide (In2O3) or indium oxide (In2O3).

[0114] The metal-oxide-semiconductor (MOS) can include multiple regions SE2, AC2, and DE2, defined by whether the transparent conductive oxide is reduced. The regions where the transparent conductive oxide is reduced (hereinafter, reduced regions) have higher conductivity than the regions where it is not reduced (hereinafter, unreduced regions). The reduced regions essentially serve as the source / drain of a transistor or signal lines. The unreduced regions essentially correspond to the semiconductor regions (e.g., channels) of the transistor. For example, a portion of the second semiconductor pattern SC2 can be a semiconductor region of the transistor, another portion can be the source region SE2 / drain region DE2 of the transistor, and this other portion can be a signal transmission region.

[0115] The fourth insulating layer 40 can be disposed on the third insulating layer 30 (e.g., directly disposed on the third insulating layer 30 on the third-direction DR3). Figure 5 As shown, the fourth insulating layer 40 can cover the second semiconductor pattern SC2. According to an embodiment of the present invention, the fourth insulating layer 40 can also be an insulating pattern that is stacked with the gate GT2 of the oxide transistor O-TFT and exposes the source region SE2 and drain region DE2 of the oxide transistor O-TFT.

[0116] The gate GT2 of the oxide transistor O-TFT is disposed on the fourth insulating layer 40 (e.g., directly disposed on the fourth insulating layer 40 on the third-direction DR3). The gate GT2 of the oxide transistor O-TFT may be part of a metal pattern. The gate GT2 of the oxide transistor O-TFT is stacked with the channel region AC2 (e.g., stacked with the channel region AC2 on the third-direction DR3).

[0117] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 (e.g., directly disposed on the fourth insulating layer 40), and the fifth insulating layer 50 may cover the gate GT2. The first insulating layer 10 to the fifth insulating layer 50 may all be inorganic layers.

[0118] A conductive layer may be disposed on the fifth insulating layer 50 (e.g., directly disposed on the fifth insulating layer 50 on the third-direction DR3). According to embodiments of the present invention, the conductive layer may include a first connection pattern CNP1 and a second connection pattern CNP2. In embodiments, the first connection pattern CNP1 and the second connection pattern CNP2 may be formed using the same process, and therefore may have the same material and the same stacking structure. In embodiments, the first connection pattern CNP1 may be connected to the drain region DE1 of the silicon transistor S-TFT via a first pixel contact hole PCH1 passing through the first insulating layer to the fifth insulating layers 10, 20, 30, 40, and 50. The second connection pattern CNP2 may be connected to the source region SE2 of the oxide transistor O-TFT via a second pixel contact hole PCH2 passing through the fourth insulating layer 40 and the fifth insulating layer 50. However, embodiments of the present invention are not limited to this; the connection relationships between the first connection pattern CNP1 and the silicon transistor S-TFT, and between the second connection pattern CNP2 and the oxide transistor O-TFT, may vary.

[0119] A sixth insulating layer 60 may be disposed on the fifth insulating layer 50 (e.g., directly disposed on the fifth insulating layer 50 on the third-direction DR3). A third connection pattern CNP3 may be disposed on the sixth insulating layer 60 (e.g., directly disposed on the sixth insulating layer 60 on the third-direction DR3). The third connection pattern CNP3 may be connected to the first connection pattern CNP1 through a third pixel contact hole PCH3 passing through the sixth insulating layer 60. A data line DL may be disposed on the sixth insulating layer 60 (e.g., directly disposed on the sixth insulating layer 60 on the third-direction DR3). A seventh insulating layer 70 may be disposed on the sixth insulating layer 60 (e.g., directly disposed on the sixth insulating layer 60) and covers the third connection pattern CNP3 and the data line DL. In an embodiment, the third connection pattern CNP3 and the data line DL may be formed using the same process, and therefore may have the same material and the same stacking structure. In an embodiment, both the sixth insulating layer 60 and the seventh insulating layer 70 may be organic layers.

[0120] In an embodiment, the first shielding electrode BML1, the gate GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate GT2 of the oxide transistor O-TFT may comprise molybdenum (Mo), a molybdenum-containing alloy, titanium (Ti), or a titanium-containing alloy, all of which have good heat resistance. The first connection pattern CNP1 and the second connection pattern CNP2 may comprise aluminum, which has high conductivity. In an embodiment, the first connection pattern CNP1 and the second connection pattern CNP2 may have a titanium / aluminum / titanium three-layer stacked structure.

[0121] The light-emitting element layer DP-ED can be disposed on the circuit layer DP-CL and can include a light-emitting element LD and a pixel defining film PDL. The light-emitting element LD can include an anode AE ​​(e.g., a first electrode), a light-emitting layer EML, and a cathode CE (e.g., a second electrode). The anode AE ​​of the light-emitting element LD can be disposed on a seventh insulating layer 70 (e.g., directly disposed on the seventh insulating layer 70 on a third-direction DR3). The anode AE ​​can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. In an embodiment, the anode AE ​​can include a stacked structure of sequentially stacked ITO / Ag / ITO. The position of the anode AE ​​can be interchanged with the position of the cathode CE.

[0122] The pixel-defining film (PDL) can be disposed on the seventh insulating layer 70 (e.g., directly disposed on the seventh insulating layer 70 on the third-party DR3). The pixel-defining film (PDL) can be an organic layer. The pixel-defining film (PDL) can have light-absorbing properties; for example, the pixel-defining film (PDL) can be made of a black material. The pixel-defining film (PDL) can include a black colorant. The black colorant can include a black dye or a black pigment. The black colorant can include carbon black, a metal such as chromium, or an oxide thereof. The pixel-defining film (PDL) can correspond to a light-shielding pattern with light-shielding properties.

[0123] The pixel-defining film (PDL) may cover a portion of the anode AE. For example, an opening PDL-OP exposing a portion of the anode AE ​​may be defined within the pixel-defining film (PDL). For example, in an embodiment, the pixel-defining film (PDL) may cover a side end of the anode AE ​​and may have an opening PDL-OP exposing a central portion of the anode AE. The light-emitting region LA may be defined corresponding to the opening PDL-OP. According to an embodiment of the present invention, a hole control layer may be disposed between the anode AE ​​and the light-emitting layer (EML) (e.g., disposed between the anode AE ​​and the light-emitting layer (EML) on a third-direction DR3). The hole control layer may include a hole transport layer and may also include a hole injection layer. An electron control layer may be disposed between the light-emitting layer (EML) and the cathode (CE) (e.g., disposed between the light-emitting layer (EML) and the cathode (CE) on a third-direction DR3). The electron control layer may include an electron transport layer and may also include an electron injection layer.

[0124] The encapsulation layer TFE can cover the light-emitting element (LD). In an embodiment, the encapsulation layer TFE may include a first encapsulation insulating layer IL1, a second encapsulation insulating layer IL2, and a third encapsulation insulating layer IL3. However, the embodiments of this inventive concept are not limited to this, and the encapsulation layer TFE may also include multiple inorganic and organic layers.

[0125] The first encapsulation insulating layer IL1 can be an inorganic layer. The first encapsulation insulating layer IL1 can prevent external moisture or oxygen from penetrating the light-emitting element (LD). For example, in an embodiment, the first encapsulation insulating layer IL1 may include silicon nitride, silicon oxide, or a compound thereof. The first encapsulation insulating layer IL1 can be formed by a chemical vapor deposition process.

[0126] The second encapsulation insulating layer IL2 can be an organic layer. The second encapsulation insulating layer IL2 can be disposed on the first encapsulation insulating layer IL1 (e.g., directly disposed on the first encapsulation insulating layer IL1) to directly contact the first encapsulation insulating layer IL1. The second encapsulation insulating layer IL2 can provide a planarized surface to the first encapsulation insulating layer IL1. Curved surfaces formed on the upper surface of the first encapsulation insulating layer IL1, particles present on the first encapsulation insulating layer IL1, etc., can be covered by the second encapsulation insulating layer IL2, thereby preventing the surface condition of the upper surface of the first encapsulation insulating layer IL1 from affecting the components formed on the second encapsulation insulating layer IL2. Additionally, the second encapsulation insulating layer IL2 can alleviate stress between layers in direct contact with it. In embodiments, the second encapsulation insulating layer IL2 can be formed using solution processes such as spin coating, slot coating, and inkjet printing.

[0127] A third encapsulation insulating layer IL3 is disposed on the second encapsulation insulating layer IL2 (e.g., directly disposed on the second encapsulation insulating layer IL2) and covers the second encapsulation insulating layer IL2. Compared to embodiments in which the third encapsulation insulating layer IL3 is disposed on the first encapsulation insulating layer IL1, the third encapsulation insulating layer IL3 can be stably formed on a relatively planarized surface. The third encapsulation insulating layer IL3 encapsulates moisture and the like released from the second encapsulation insulating layer IL2 to prevent moisture and the like from leaking out.

[0128] In this embodiment, the third encapsulation insulating layer IL3 may be optically transparent. For example, the third encapsulation insulating layer IL3 may have a visible light transmittance of about 90% or higher. The third encapsulation insulating layer IL3 may have a higher transmittance than the first encapsulation insulating layer IL1. The third encapsulation insulating layer IL3 may be an inorganic layer. In this embodiment, the third encapsulation insulating layer IL3 may include silicon oxide (SiO2). x The first encapsulation insulating layer IL1, the second encapsulation insulating layer IL2, and the third encapsulation insulating layer IL3 may each comprise multiple layers, and are not necessarily limited to any one embodiment.

[0129] The input sensing layer ISL may include at least one conductive layer (e.g., at least one sensor conductive layer) and at least one insulating layer (e.g., at least one sensor insulating layer). In an embodiment, the input sensing layer ISL may include a first insulating layer IS-IL1, a first conductive layer ICL1, a second insulating layer IS-IL2, a second conductive layer ICL2, and a third insulating layer IS-IL3. Figure 5 The conductive lines of the first conductive layer ICL1 and the second conductive layer ICL2 are briefly shown.

[0130] The first insulating layer IS-IL1 can be directly disposed on the display panel DP (e.g., directly disposed on the display panel DP on the third-direction DR3). In an embodiment, the first insulating layer IS-IL1 can be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Both the first conductive layer ICL1 and the second conductive layer ICL2 can have a single-layer structure or a structure with multiple layers stacked along the third-direction DR3. The first conductive layer ICL1 and the second conductive layer ICL2 can include conductive lines defining electrodes in a grid pattern. In an embodiment, the conductive lines of the first conductive layer ICL1 and the second conductive layer ICL2 can be connected by passing through contact holes in the second insulating layer IS-IL2, or they can be unconnected. For example, the connection relationship between the conductive lines of the first conductive layer ICL1 and the conductive lines of the second conductive layer ICL2 can be determined according to the type of sensor forming the input sensing layer ISL.

[0131] Both the first conductive layer ICL1 and the second conductive layer ICL2, which are single-layer structures, can comprise a metal layer or a transparent conductive layer. In embodiments, the metal layer can comprise molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer can comprise materials such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). x Transparent conductive oxides such as indium zinc tin oxide (IZTO) or indium zinc tin oxide (IZTO) can also be used. Alternatively, transparent conductive layers can include conductive polymers such as PEDOT, metal nanowires, and graphene.

[0132] The first conductive layer ICL1 and the second conductive layer ICL2, which are in a multilayer structure, may include metal layers. In an embodiment, the metal layers may have a three-layer structure, such as titanium / aluminum / titanium. The conductive layers in the multilayer structure may include at least one metal layer and at least one transparent conductive layer. The second insulating layer IS-IL2 may be disposed between the first conductive layer ICL1 and the second conductive layer ICL2 (e.g., disposed between the first conductive layer ICL1 and the second conductive layer ICL2 on a third-direction DR3). The third insulating layer IS-IL3 may cover the second conductive layer ICL2. However, embodiments of the present invention are not limited thereto. For example, in embodiments of the present invention, the third insulating layer IS-IL3 may be omitted. Both the second insulating layer IS-IL2 and the third insulating layer IS-IL3 may include inorganic or organic layers.

[0133] Figure 6 yes Figure 4B A magnified view of region AA' shown in the image. Specifically, Figure 6 This is an enlarged view showing the main circuit board MB and the driver chip DIC according to an embodiment of the present invention. Figure 7A and Figure 7B It was viewed from a third party to DR3. Figure 6 Plan view of area AA'.

[0134] Reference Figure 6 In this embodiment, the main circuit board (MB) may include a substrate film (BF), a shielding layer (SHL), and a shielding pattern (SHP). The main circuit board (MB) may be composed of multiple layers. Both the shielding layer (SHL) and the shielding pattern (SHP) may be one of the multiple layers.

[0135] The substrate film (BF) may include insulating layers having a single-layer or multi-layer structure. The substrate film (BF) may include multiple wirings. These multiple wirings may be disposed between multiple insulating layers. For example, in embodiments, the multiple insulating layers may include synthetic resin materials (e.g., polyimide) or inorganic materials (e.g., silicon nitride, silicon oxide, or mixtures thereof).

[0136] Refer to together Figure 6 and Figure 7AThe shielding layer SHL can be in direct contact with the cover plate CP and disposed below the cover plate CP (e.g., disposed below the cover plate CP in the direction opposite to the third direction DR3). The shielding layer SHL can be stacked on a plane with the recessed portion DEP. In an embodiment, (e.g., when the connection circuit board CF is bent), the shielding layer SHL can provide the lower surface of the recessed portion DEP. Because the shielding layer SHL is stacked on a plane with the recessed portion DEP, the shielding layer SHL can be stacked on a plane with the driver chip DIC disposed in the recessed portion DEP. For example, in an embodiment, the shielding layer SHL can be stacked on a plane with the entire recessed portion DEP.

[0137] The shielding layer SHL can protect the driver chip DIC from external electrostatic discharge (ESD). In embodiments, the shielding layer SHL may comprise a highly conductive metal and thus can absorb or reflect external radio waves. For example, in embodiments, the shielding layer SHL may comprise iron or nickel to absorb external magnetic fields, or may comprise copper or aluminum to reflect external magnetic fields. For example, the shielding layer SHL may be stacked on a plane with the driver chip DIC, so that the driver chip DIC can be protected from external ESD by the shielding layer SHL. However, embodiments of the present invention are not limited to this; magnetic fields, etc., generated from the driver chip DIC can be shielded so as not to be emitted to the outside (e.g., the external environment).

[0138] Refer to together Figure 6 and Figure 7B The shielding pattern SHP can be disposed along the boundary of the recessed portion DEP. For example, the width of the recessed portion DEP (e.g., width in a plan view) can be greater than the width of the driver chip DIC disposed therein (e.g., width in a plan view). In an embodiment, the shielding pattern SHP can be arranged to surround the driver chip DIC disposed in the recessed portion DEP on a plane. For example, the shielding pattern SHP can be arranged along the boundary of the recessed portion DEP (e.g., along the boundary of the recessed portion DEP in a plan view). In an embodiment, the shape of the shielding pattern SHP can correspond to the shape of the driver chip DIC. For example, in an embodiment where the driver chip DIC has a quadrilateral shape on a plane, the shielding pattern SHP can have a corresponding quadrilateral ring shape. However, embodiments of the present invention are not limited to this; the shielding pattern SHP can have the shape of a ring, a pentagonal ring, or a polygonal ring with more than pentagons, or can have various other shapes.

[0139] According to embodiments of the present invention, multiple shielding patterns SHP can be configured and arranged in the recessed direction of the recessed portion DEP, the recessed direction of which is the direction in which the recessed portion DEP is recessed from the surface of the main circuit board MB. For example, in an embodiment, the shielding patterns SHP may include a first shielding pattern SHP1 and a second shielding pattern SHP2 arranged along a third direction DR3. The first shielding pattern SHP1 and the second shielding pattern SHP2 may be spaced apart from each other on the third direction DR3. In an embodiment, the first shielding pattern SHP1 and the second shielding pattern SHP2 may have the same shape on a plane. For example, the first shielding pattern SHP1 and the second shielding pattern SHP2 may be superimposed on each other on a plane.

[0140] Both the first shielding pattern SHP1 and the second shielding pattern SHP2 can (e.g., in a planar view) surround the driver chip DIC. For example, both the first shielding pattern SHP1 and the second shielding pattern SHP2 can be superimposed on the driver chip DIC in the first direction DR1 and the second direction DR2. Both the first shielding pattern SHP1 and the second shielding pattern SHP2 can protect the driver chip DIC from the effects of external electrostatic discharge. In an embodiment, the first shielding pattern SHP1 and the second shielding pattern SHP2 may include a highly conductive metal, thus absorbing or reflecting external radio waves.

[0141] In one embodiment, the first shielding pattern SHP1 and the second shielding pattern SHP2 may comprise the same material as each other. However, embodiments of the present invention are not limited to this; both the first shielding pattern SHP1 and the second shielding pattern SHP2 may comprise the same material as the shielding layer SHL. For example, in one embodiment, both the first shielding pattern SHP1 and the second shielding pattern SHP2 may comprise iron or nickel to absorb external magnetic fields, or both may comprise copper or aluminum to reflect external magnetic fields.

[0142] The first shielding pattern SHP1 and the second shielding pattern SHP2 can be electrically connected to each other. Additionally, the second shielding pattern SHP2 and the shielding layer SHL can be electrically connected to each other. For example, in an embodiment, the first shielding pattern SHP1 and the second shielding pattern SHP2 can be electrically connected to each other via a first contact hole CH1 formed through the substrate film BF (e.g., on the third-direction DR3), and the second shielding pattern SHP2 and the shielding layer SHL can be electrically connected to each other via a second contact hole CH2 formed through the substrate film BF (e.g., on the third-direction DR3). Figure 7BAs shown in the embodiments, multiple first contact holes CH1 can be provided, and the multiple first contact holes CH1 can be arranged (e.g., in a plan view) along the boundary of the recessed portion DEP. In the embodiments, multiple second contact holes CH2 can also be provided, and the multiple second contact holes CH2 can be arranged (e.g., in a plan view) along the boundary of the recessed portion DEP.

[0143] Refer to together Figures 6 to 7B Since the driver chip DIC is housed in a recessed portion DEP within the main circuit board MB according to an embodiment of the present invention, it is not necessary to form a separate covering space for protecting the driver chip DIC, thereby simplifying the display device DD (see Figure 2 The manufacturing process of the main circuit board MB according to the present invention includes a shielding layer SHL stacked on a plane with the driver chip DIC and a first shielding pattern SHP1 and a second shielding pattern SHP2 surrounding the driver chip DIC on a plane, thus protecting the driver chip DIC from external static electricity. Therefore, a display device DD with improved reliability can be provided.

[0144] Figure 8A This is an enlarged view showing a portion of a display device according to an embodiment of the present invention. For example, Figure 8A yes Figure 4B The enlarged view of region AA' shown in the image. Figure 8B It was viewed from a third party to DR3. Figure 8A Plan view of area AA'.

[0145] Refer to together Figure 8A and Figure 8B In this embodiment, the main circuit board MBa may include a substrate film BFa, a shielding layer SHL, and a shielding pattern SHPa. A recessed portion DEPa may be defined within the main circuit board MBa, and a driver chip DIC may be disposed within the recessed portion DEPa. (For example, when the connecting circuit board CF is in an unbent state,) the recessed portion DEPa may be recessed from the upper and side surfaces of the substrate film BFa.

[0146] According to an embodiment of the present invention, the recessed portion DEPa can be recessed from three surfaces of the substrate film BFa. (For example, when the connecting circuit board CF is in an unbent state,) for example, the recessed portion DEPa can be formed by being recessed in the opposite direction of the third direction DR3 relative to the upper surface of the substrate film BFa, and simultaneously recessed in the opposite direction of the second direction DR2 relative to the side surface of the substrate film BFa. (For example, when the connecting circuit board CF is in a bent state,) the driver chip DIC can be exposed to the outside in the second direction DR2, which is the opposite direction along which the main circuit board MBa extends.

[0147] The shielding pattern SHPa can be set along the boundary of the recessed portion DEPa. For example, the shielding pattern SHPa can be set on a plane around the driver chip DIC disposed in the recessed portion DEPa. Since the recessed portion DEPa is formed by being recessed in the opposite direction to the second direction DR2 relative to the side surface of the substrate film BFa, it is similar to... Figure 6 Compared to the embodiment shown, the shielding pattern SHPa can be formed by omitting the right-hand portion on the plane.

[0148] In an embodiment, the shielding pattern SHPa may include a first shielding pattern SHP1a and a second shielding pattern SHP2a disposed on the third-direction DR3. The first shielding pattern SHP1a and the second shielding pattern SHP2a may be configured to be spaced apart from each other on the third-direction DR3. The first shielding pattern SHP1a and the second shielding pattern SHP2a may have the same shape on the plane. For example, the first shielding pattern SHP1a and the second shielding pattern SHP2a may be superimposed on each other on the plane.

[0149] Figure 9A and Figure 9B Each of these is a cross-sectional view showing an embodiment of a display device according to the present invention. In the following text, for ease of description, repeated or previously described content may be omitted.

[0150] Refer to together Figure 9A and Figure 9B The main circuit board MB can be disposed on the upper surface of the connecting circuit board CF (e.g., directly disposed on the upper surface of the connecting circuit board CF on the third direction DR3). The connecting circuit board CF can be bent with a predetermined curvature in a direction toward the rear surface of the display panel DP. For example, in an embodiment, the connecting circuit board CF can be bent relative to a bending axis FX parallel to the first direction DR1. In this case, when the connecting circuit board CF is in a bent state, the main circuit board MB can be disposed on the rear surface of the display panel DP. Figure 4B The display device DD shown is different. Figure 9BThe display device DDA shown may include a main circuit board MB positioned on the third-direction DR3 and spaced apart from the rear surface CP-B of the cover plate CP. The rear surface CP-B of the cover plate CP may be in direct contact with the shielding film SHF. For example, when the connecting circuit board CF is in a bent state, the shielding film SHF may be directly disposed between the rear surface CP-B of the cover plate CP and the connecting circuit board CF (e.g., directly disposed on the third-direction DR3 between the rear surface CP-B of the cover plate CP and the connecting circuit board CF).

[0151] Figure 10A and Figure 10B These are cross-sectional views of display devices according to embodiments of the present invention.

[0152] Refer to together Figure 10A and Figure 10B The display device DDb according to an embodiment of the present invention may include a flexible display panel DPa. For example, the display panel DPa may include a first region AA1, a second region AA2, and a flexible region BA that are separated from each other (e.g., spaced apart) in a second direction DR2. Figure 10A As shown, when the display device DDb is in the unfolded state, at least a portion of the first region AA1 and the second region AA2 of the display panel DPa installed in the display device DDb are disposed on different planes. For example, when the display device DDb is in the unfolded state, at least a portion of the upper surfaces of the first region AA1 and the second region AA2 of the display panel DPa are disposed on different planes from each other. (For example, when the display panel DPa is in the unbent state,) the bent region BA is disposed between the first region AA1 and the second region AA2 (for example, disposed between the first region AA1 and the second region AA2 in the second direction DR2).

[0153] The first region AA1 can be included Figure 3 The display area DA corresponds to the pixel PX shown. The curved area BA is bendable relative to the bending axis FXa parallel to the first direction DR1. The driver chip DIC can be mounted in the second area AA2. The main circuit board MB (e.g., a circuit board) can be connected to one side of the second area AA2. For example, in the second area AA2, the driver chip DIC can be disposed in the recessed portion DEP defined in the main circuit board MB. When the display panel DPa is in an unbent state, the main circuit board MB can be disposed on the upper surface of the second area AA2 of the display panel DPa (e.g., directly disposed on the upper surface of the second area AA2 of the display panel DPa on the third direction DR3).

[0154] The lengths of the curved region BA and the second region AA2 in the second direction DR2 can be less than the length of the first region AA1. The second region AA2 and the curved region BA can be non-display regions NDA (see...). Figure 3 (part of the area).

[0155] The driver chip can be disposed in a recessed portion within a main circuit board included in an embodiment of the display device according to the present invention. Therefore, a separate covering space for protecting the driver chip is not required, thereby simplifying the manufacturing process of the display device according to an embodiment of the present invention.

[0156] Furthermore, since the main circuit board according to the embodiment of the present invention includes a shielding layer superimposed on the driver chip on a plane and a shielding pattern surrounding the driver chip on a plane, the driver chip can be protected from the effects of external static electricity. Therefore, a display device with improved reliability can be provided.

[0157] Electronic devices

[0158] Figure 11 This is a diagram illustrating an electronic device according to an embodiment of the present invention. (Refer to...) Figure 11 According to an embodiment of the present invention, the electronic device 1000 can be connected to a display module 1140 (which can be connected to...). Figure 2 The display module DM shown outputs various information (e.g., images, text, music, etc.), and the electronic device 1000 can, for example, be connected to... Figure 1 The electronic device ED shown corresponds to this. When the processor 1110 executes the application stored in the memory 1120, the display module 1140 can provide application information to the user through the display panel 1141.

[0159] In some embodiments, electronic device 1000 may be configured as a smartphone, camera, smart TV, monitor, smartwatch, tablet, automotive display, or AR / VR headset. For example, electronic device 1000 may be a smartphone including a touch-sensitive display area DA for interaction and a non-display area NDA including sensors and circuitry for enhanced functionality. For example, electronic device 1000 may be a TV or monitor including a large display area DA for high-definition video playback and a non-display area NDA containing drive circuitry or connection modules for external input. For example, electronic device 1000 may be a smartwatch including a display area DA optimized for compact and high-definition vision and a non-display area NDA integrating biometric sensors for health monitoring. In some cases, electronic device 1000 is an AR / VR headset.

[0160] In some embodiments, memory 1120 may store information such as software code for operating application 1123. Application 1123 may include software designed to perform specific tasks or provide functionality to a user. Application 1123 may operate under the control of processor 1110 and uses data stored in memory 1120 to deliver a wide range of features such as productivity tools, multimedia streaming and playback, file or mail transfer, or communication services. Application 1123 interacts seamlessly with user interface 1161 or touchscreen 1142, allowing users to launch, navigate, and use the program via user input such as touch, tap, gestures, or voice interaction.

[0161] When a user selects an application via touchscreen 1142 or user interface 1161, processor 1110 can execute application program 1123 corresponding to the selected application retrieved from memory 1120 to perform the application's functions. For example, when a user selects a camera application by tapping an icon (or camera application icon) presented on display panel 1141, processor 1110 activates the camera module. Processor 1110 can then transfer image data corresponding to a captured image obtained by the camera module to display module 1140. Display module 1140 can then display the image corresponding to the captured image via display panel 1141.

[0162] As another example, when a user wishes to make a phone call, the user taps a phone icon displayed on display module 1140, and processor 1110 can execute a phone application stored in memory 1120. A phone keypad can be displayed on display panel 1141 for the user to enter the phone number to call.

[0163] As another example, the display module 1140 can be integrated into an electronic device 1000 such as a laptop computer, smart TV, or tablet computer. Users wishing to access multimedia streaming applications (e.g., watching music videos or movies) can do so by tapping the corresponding icon. This action activates the application, allowing the user to watch the streaming content.

[0164] Processor 1110 may include a main processor 1111 and an auxiliary processor or coprocessor 1112. The main processor 1111 may include a central processing unit (CPU). The main processor 1111 may also include one or more of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP).

[0165] The coprocessor 1112 may include a controller 1112-1. The controller 1112-1 may include interface conversion circuitry and timing control circuitry. The controller 1112-1 may receive image signals from the main processor 1111, convert the data format of the image signals to match the interface specification of the display module 1140, and output the image data. The controller 1112-1 may output various control signals for driving the display module 1140. For example, the controller 1112-1 may drive the display module 1140 to display icons on a screen suitable for user selection, thereby enabling the execution of application program 1123.

[0166] Memory 1120 may store one or more applications 1123 and various data used by at least one component of electronic device 1000 (e.g., processor 1110 or user interface 1161), as well as input or output data for commands associated with them. Examples include camera applications, GPS applications, augmented reality and virtual reality applications, and other applications that may be executed by processor 1110 when a user selects a corresponding icon displayed on a screen (or display panel 1141) via touchscreen 1142 or user interface 1161. Additionally, various setting data corresponding to user settings may be stored in memory 1120. Memory 1120 may include volatile memory 1121 and non-volatile memory 1122.

[0167] Display module 1140 can output visual information (images) to a user. Display module 1140 may include a display panel 1141, a gate driver, a source driver, a voltage generation circuit, and a touchscreen 1142. Display module 1140 may also include a window, a chassis, and a bracket to protect the display panel 1141. Display module 1140 may include... Figure 1 The electronic device ED shown represents at least a portion of the structure.

[0168] User interface 1161 serves as an interaction medium between the user and electronic device 1000. User interface 1161 can detect input from a part of the user's body (e.g., a finger) or from a pen or mouse, and generate electrical signals or data values ​​corresponding to the input. User interface 1161 includes a fingerprint sensor 1162, an input sensor 1163, and a digitizer 1164.

[0169] The fingerprint sensor 1162 can sense a fingerprint used for a user's biometric identification and can also measure one or more biometric signals such as blood pressure, humidity, or weight.

[0170] Input sensor 1163 can sense user interactions including touch, tap, gesture, motion, verbal commands, and eye movements. Input sensor 1163 includes optical sensors for image capture, eye tracking, or motion and gesture detection. The optical sensors can be infrared photodetectors or semiconductor photodetectors. Input sensor 1163 includes audio sensors and acoustic sensors, which can be MEMS microphones for voice recognition or voice-based interaction. The audio sensors and acoustic sensors can be mounted as part of user interface 1161 or embedded in display panel 1141.

[0171] The digitizer 1164 can generate data values ​​corresponding to coordinate information input via a pen or mouse to control cursor movement on the screen. The digitizer 1164 can also generate electromagnetic changes caused by input as data values. The digitizer 1164 can detect input from a passive pen or use an active pen or remote control to send and receive data.

[0172] At least one of the fingerprint sensor 1162, the input sensor 1163, and the digitizer 1164 can be implemented as a sensor layer formed on the top layer of the display panel 1141 by a process that is continuous with the process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 1141.

[0173] Additionally, the user interface 1161 may include, for example, a gesture sensor, a gyroscope sensor for sensing rotational motion, an accelerometer sensor for tracking translational motion, a grip sensor, a pressure sensor, a proximity sensor, a color sensor, an infrared (IR) emitter and camera sensor for tracking gaze direction and eye movement, a temperature sensor, or a light sensor. For example, the gyroscope sensor, accelerometer sensor, and infrared emitter and camera sensor may be particularly suitable for AR / VR headset functionality.

[0174] Touchscreen 1142 includes a touch sensor embedded in a semiconductor layer of display panel 1141 to sense pressure applied to the top layer (screen) of display panel 1141. The touch sensor can be capacitive or resistive. Touchscreen 1142 can be used as a primary interface for user selection and navigation applications, control of electronic device 1000, and interaction with electronic device 1000.

[0175] The display panel 1141 (or display) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of display panel 1141 is not specifically limited. The display panel 1141 may be rigid or flexible, capable of being rolled up or folded. The display module 1140 may also include supports, brackets, heat dissipation components, etc., for supporting the display panel 1141. The display panel 1141 may be included in... Figure 1The electronic device ED shown is included.

[0176] Power module 1150 can supply power to the components of electronic device 1000. Power module 1150 may include a battery charged with a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 1150 may include a power management integrated circuit (PMIC). The PMIC can supply optimized power to each of the aforementioned components, including display module 1140.

[0177] Although embodiments of the present invention have been described, it is understood that the present invention should not be limited to these embodiments, and those skilled in the art can make various changes and modifications within the spirit and scope of the claimed present invention.

[0178] Therefore, the technical scope of this invention should not be limited to the content described in the detailed description of the specification, but should be defined by the claims.

Claims

1. A display device, characterized by comprising: The display device includes: Display panel; The main circuit board has a recessed portion that is recessed in the thickness direction of the display panel; A connecting circuit board is electrically connected to the display panel on a first side of the connecting circuit board, and electrically connected to the main circuit board on a second side of the connecting circuit board opposite to the first side. The driver chip is mounted on the second side of the connection circuit board and is disposed in the recessed portion. The main circuit board includes a shielding layer that is stacked with the recessed portion.

2. The display device according to claim 1, wherein The main circuit board also includes a shielding pattern surrounding the driver chip on a plane.

3. The display device according to claim 2, characterized in that: The shielding pattern includes multiple shielding patterns; and The plurality of shielding patterns are arranged in the concave direction of the recessed portion.

4. The display device according to claim 3, wherein The main circuit board includes contact holes that connect the plurality of shielding patterns to each other.

5. The display device according to claim 4, characterized in that: The contact hole includes multiple contact holes; and The plurality of contact holes are arranged along the boundary of the recessed portion.

6. The display device according to claim 2, characterized in that: The width of the recessed portion is greater than the width of the driver chip; and The shielding pattern is set along the boundary of the recessed portion.

7. The display device according to claim 1, characterized in that: The main circuit board extends in the extending direction; and The driver chip is exposed to the outside in the opposite direction to the extension direction of the main circuit board.

8. The display device according to claim 1, characterized in that: The connecting circuit board is flexible relative to a virtual axis extending in a first direction, wherein the main circuit board is disposed below the display panel in a bent state.

9. The display device of claim 8, wherein, The display device also includes a cover plate disposed under the display panel. The main circuit board is in direct contact with the cover plate.

10. The display device according to claim 1, characterized in that: The driver chip is disposed on the upper surface of the connection circuit board; and The display device further includes a shielding film disposed on the lower surface of the upper surface of the connecting circuit board facing the connecting circuit board.

11. The display device according to claim 1, wherein The depth of the recessed portion is greater than the thickness of the driver chip.

12. The display device according to claim 1, wherein The shielding layer is superimposed on the entire recessed portion.

13. A display device comprising: The display device includes: Display panel; The main circuit board has a recessed portion that is recessed in the thickness direction of the display panel; A connecting circuit board is electrically connected to the display panel on a first side of the connecting circuit board, and electrically connected to the main circuit board on a second side of the connecting circuit board opposite to the first side. The driver chip is mounted on the second side of the connection circuit board and is disposed in the recessed portion. The main circuit board includes a shielding pattern surrounding the driver chip on a plane.

14. The display device according to claim 13, characterized in that: The shielding pattern includes multiple shielding patterns; and The plurality of shielding patterns are arranged in the concave direction of the recessed portion.

15. The display device of claim 14, wherein, The main circuit board includes contact holes that connect the plurality of shielding patterns to each other.

16. The display device according to claim 14, characterized in that: The width of the recessed portion is greater than the width of the driver chip; and The shielding pattern is set along the boundary of the recessed portion.

17. The display device of claim 13, wherein, The main circuit board also includes a shielding layer stacked with the recessed portion.

18. The display device of claim 17, wherein, The shielding layer and the shielding pattern are made of the same material as each other.

19. The display device of claim 13, wherein, The depth of the recessed portion is greater than the thickness of the driver chip.

20. An electronic device, comprising: The electronic device includes: Display device; An electronic module, stacked with the display device; and Housing that houses the display device. The display device includes: a display panel; a main circuit board having a recessed portion in the thickness direction of the display panel; a connecting circuit board electrically connected to the display panel on a first side and electrically connected to the main circuit board on a second side of the connecting circuit board opposite to the first side; and a driver chip mounted on the second side of the connecting circuit board and disposed in the recessed portion. The main circuit board includes a shielding layer that is stacked with the recessed portion.

Images