A 1t1p fc ferroelectric memory cell, memory array

Abstract

This application relates to the field of in-memory computing memory technology, and more particularly to a 1T1PFC paraferroelectric memory cell and memory array. The 1T1PFC paraferroelectric memory cell includes: a silicon substrate, an active device region on the silicon substrate, a memory transistor formed on the active device region, a memory gate line formed on the gate stack of the memory transistor, and a paraferroelectric capacitor formed on the memory gate line. The 1T1PFC paraferroelectric memory cell of this application uses a dedicated memory gate line to prevent spontaneous charge dissipation after writing to the 1T1PFC paraferroelectric memory cell, thereby enhancing data retention capability.

Description

Technical Field

[0001] This application relates to the field of in-memory computing memory technology, and in particular to a 1T1PFC paraferroelectric memory cell and memory array. Background Technology

[0002] The evolution of artificial intelligence (AI) and neuromorphic computing has driven the demand for memory systems that not only need to be high-speed and high-density, but also support non-volatile, in-memory computing (CIM). Traditional memory technologies, such as SRAM and DRAM, while fast, suffer from volatility and significant energy consumption. Ferroelectric field-effect transistors (FeFETs) and single-transistor single-capacitor (1T1C) ferroelectric structures have emerged as viable candidates for non-volatile memory.

[0003] However, these architectures often exhibit reduced durability, charge retention issues, and limited resilience to read / write interference during high-frequency operation.

[0004] Compared to FeFET, the ferroelectric metal field-effect transistor (FeMFET) structure has better durability. FeMFET is compatible with CMOS back-end process (BEOL) and is well-suited for embedded memory and AI applications due to its multi-bit capability (similar to FeFET).

[0005] However, the ferroelectric metal field-effect transistor (FeMFET) structure suffers from charge leakage during use due to its floating gate characteristics, which affects its data retention capability. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the purpose of this application is to provide a 1T1PFC paraferroelectric memory cell and memory array, which uses a dedicated memory gate line to prevent spontaneous charge dissipation after writing to the 1T1PFC paraferroelectric memory cell and enhance data retention capability.

[0007] To achieve the above objectives, this application provides a 1T1PFC ferroelectric storage unit, comprising: A silicon substrate, wherein an active device region is provided on the silicon substrate, and a storage transistor is formed on the active device region; Storage gate lines are formed on the gate stack of the storage transistors; A paraferroelectric capacitor is formed on the storage gate line.

[0008] Furthermore, a drain diffusion region and a source diffusion region are formed on the active device region, and the gate stack of the storage transistor is located between the drain diffusion region and the source diffusion region.

[0009] Furthermore, the drain diffusion region is connected to a bit line via a drain contact.

[0010] Furthermore, the source diffusion region is connected to the active line via a source contact.

[0011] Furthermore, a storage gate pad is formed on the gate stack of the storage transistor, a storage gate pad is formed above the storage gate pad through a storage gate contact, and the storage gate line is formed on the storage gate pad.

[0012] Further, the paraferroelectric capacitor includes: The bottom electrode is connected to the gate of the storage transistor; The paraferroelectric layer, disposed on the upper part of the bottom electrode, is composed of a quantum well paraelectric layer structure formed by hafnium silicon oxide and a transition material and a ferroelectric layer; The top electrode is disposed on the paraferroelectric layer and is electrically connected to a plate wire.

[0013] Furthermore, the storage gate line is connected to the bottom electrode of the paraferroelectric capacitor via a through-hole pad.

[0014] Furthermore, it also includes shallow trench isolation with deposited oxides; the shallow trench isolation is arranged around the active device area.

[0015] Furthermore, the gate stack comprises, from bottom to top, a gate oxide layer, a high dielectric constant dielectric layer, and a TiN layer.

[0016] To achieve the above objectives, this application also provides a memory array, including 1T1PFC ferroelectric memory cells arranged in an array as described above, wherein 1T1PFC ferroelectric memory cells in the same row are configured to have the same bit line, the same board line and the same source line, and 1T1PFC ferroelectric memory cells in the same column are configured to have the same memory gate line.

[0017] The 1T1PFC paraferroelectric memory cell provided in this application uses a dedicated memory gate line to control the charge flow after writing, which prevents charge dissipation after writing and enhances non-volatility and data retention capabilities.

[0018] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description

[0019] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the structure of the 1T1PFC ferroelectric storage unit in Embodiment 1 of this application; Figure 2 This is a top view of the 1T1PFC ferroelectric storage cell of Embodiment 1 of this application.

[0020] Figure label: 10-Silicon substrate, 11-Active device region, 12-Shallow trench isolation, 13-Drain diffusion region, 14-Source diffusion region, 15-Gate stack, 151-Memory gate pad, 16-Drain contact, 17-Memory gate contact, 18-Source contact, 19-Bit line, 20-Source line, 21-Memory gate contact pad, 22-Memory gate line, 23-Through hole pad, 24-Bottom electrode, 25-Parferroelectric layer, 26-Top electrode, 27-Board line. Detailed Implementation

[0021] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application.

[0022] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0023] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0024] It should be noted that the terms "first" and "second" may be used in this application only to distinguish different devices, components or parts, and are not used to define the order of functions performed by these devices, components or parts or their interdependence.

[0025] It should be noted that the terms "one" and "more" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "More" should be understood as two or more.

[0026] Example 1 In the embodiments of this application, a 1T1PFC paraferroelectric storage unit is provided. Figure 1This is a schematic diagram of the structure of the 1T1PFC ferroelectric memory cell in Embodiment 1 of this application. Figure 2 This is a top view of the 1T1PFC ferroelectric memory cell of Embodiment 1 of this application. The following will be combined with... Figure 1 and Figure 2 The 1T1PFC ferroelectric storage cell of this application will be described in further detail.

[0027] The 1T1PFC ferroelectric storage unit of this application embodiment includes: A silicon substrate 10, an active device region 11 disposed on the silicon substrate 10, and the silicon substrate 10 also having a shallow trench isolation 12 surrounding the active device region 11, the shallow trench isolation 12 being filled with oxide to isolate the active device region 11.

[0028] A drain diffusion region 13 and a source diffusion region 14 are formed on the active device region 11. A gate stack 15 of a storage transistor is formed between the drain diffusion region 13 and the source diffusion region 14. The drain diffusion region 13 is electrically connected to a bit line (BL) 19 through a drain contact 16, and the source diffusion region 14 is electrically connected to an active line (SL) 20 through a source contact 18.

[0029] In this embodiment, both the drain diffusion region 13 and the source diffusion region 14 are N+ diffusion regions (representing highly doped N-type semiconductor regions).

[0030] In this embodiment, the gate stack 15 and the gate stack 15 of the storage transistor both include, from bottom to top, a gate oxide layer, a high dielectric constant (K) dielectric layer and a TiN layer.

[0031] In this embodiment, a storage gate pad 151 is formed on the gate stack 15 of the storage transistor, and a storage gate pad 21 is formed above the storage gate pad 151 through the storage gate contact 17. A storage gate line (SGL) 22 is formed on the storage gate pad 21.

[0032] It should be noted that the drain contact 16, the source contact 18 and the storage gate contact 17 are all composed of interlayer dielectric, contact holes formed on the interlayer dielectric, and conductive metal (Cu or W) filled in the contact holes.

[0033] In this embodiment, the paraferroelectric capacitor comprises a bottom electrode 24, a paraferroelectric layer 25, and a top electrode 26, with a plate line (PL) 27 electrically connected to the top electrode 26. The paraferroelectric layer 25 consists of a quantum well layered structure formed from hafnium silicon oxide and a transition material, and a ferroelectric layer. The transition material can be HfO2, ZrO2, TiO2, TiN, TaN, Al2O3, or TaO. X The ferroelectric dielectric layer is HfZrO2.

[0034] In this embodiment, a TiN layer is also disposed on the upper and lower surfaces of the paraferroelectric layer 25.

[0035] In this embodiment, the storage gate line 22 is connected to the bottom electrode 24 of the paraferroelectric capacitor through the through-hole pad 23, and the through-hole pad 23 is filled with conductive material.

[0036] The write operation of the 1T1PFC paraferroelectric memory cell in this application embodiment is as follows: During writing, a 0V voltage is applied to the memory gate line 22, and a +Vpp or -Vpp programming voltage is applied to the board line 27, causing opposite polarization voltages to be formed across the paraferroelectric capacitors, causing the paraferroelectric capacitors to be polarized in opposite directions, thereby realizing the writing of logic 1 and logic 0 respectively.

[0037] This application provides an enhanced data retention operation. After writing is completed, the storage gate line 22 is configured to float or enhance the retention voltage (0V~0.2V) to block the charge discharge path of the bottom electrode 24, thereby forming charge isolation between the gate of the storage transistor and the bottom electrode 24 of the paraferroelectric capacitor.

[0038] It is understandable that after polarization, paraferroelectric capacitors will modulate and change the threshold voltage of the storage transistor. Different polarization directions will modulate and generate the corresponding threshold voltage of the storage transistor.

[0039] The read operation of the 1T1PFC ferroelectric memory cell in this application embodiment is as follows: During reading, a read voltage of 0.7-0.9V is applied to the board line 27, a Vdd voltage of 0.2-0.7V is applied to the bit line 19, and a floating voltage is applied to the memory gate line 22, thereby realizing the read operation.

[0040] Understandably, during reading, the logic state of the 1T1PFC paraferroelectric memory cell is determined based on the drain-to-source current of the storage transistor, i.e., the drain current (Ids): a high drain current (on-state) indicates that the polarization configuration of the paraferroelectric capacitor results in a low effective threshold voltage; a low drain current (off-state) indicates that the polarization configuration of the paraferroelectric capacitor 40 results in a high threshold voltage. High drain current means that when the gate voltage exceeds the threshold voltage, the channel of the storage transistor is fully open, and the drain-to-source current reaches its saturation value. Low drain current means that when the gate voltage is below the threshold voltage, the channel has not formed a conductive path, and the drain-to-source current drops to an extremely low value.

[0041] In embodiments of this application, the 1T1PFC paraferroelectric memory cell allows for non-destructive reading, programmable writing, compatibility with back-end process (BEOL) 3D integration, and in-memory computation by modulating the threshold voltage of the memory transistor through the ferroelectric polarization state.

[0042] Example 2 In the embodiments of this application, a memory array is also provided, including a plurality of 1T1PFC ferroelectric memory cells as described in Embodiment 1, which are arranged in an array. The plurality of 1T1PFC ferroelectric memory cells run in-memory computing operations in parallel. The 1T1PFC ferroelectric memory cells in the same row are configured to have the same bit line, the same board line and the same source line, and the 1T1PFC ferroelectric memory cells in the same column are configured to have the same memory gate line, so as to realize write and read operations on the selected 1T1PFC ferroelectric memory cells.

[0043] In this embodiment, when writing "1" to the selected 1T1PFC ferroelectric memory cell, the corresponding board line is configured to Vpp programming voltage, the corresponding memory gate line is configured to 0V, other board lines are configured to graded voltage 1 / 3Vpp, other memory gate lines are configured to another graded voltage 2 / 3Vpp, and all bit lines and source lines are configured to 0V.

[0044] In this embodiment, when writing "0" to the selected 1T1PFC ferroelectric memory cell, its corresponding board line is configured with a programming voltage of -Vpp, its corresponding memory gate line is configured with 0V, other board lines are configured with a graded voltage of -1 / 3Vpp, other memory gate lines are configured with another graded voltage of -2 / 3Vpp, and all bit lines and source lines are configured with 0V.

[0045] In this embodiment, after a write operation, all board lines, bit lines, source lines, and memory gate lines are configured to 0V to enhance data retention capability.

[0046] In this embodiment, when performing a read operation on the selected 1T1PFC ferroelectric memory cell, the corresponding bit line is configured with a Vd voltage of 0.2-0.7V, the corresponding board line is configured with a Vread voltage of less than 1 / 3Vpp, the corresponding memory gate line SGL (4) is configured as a floating voltage, and other memory gate lines, other board lines, other source lines and other bit lines are configured as 0V.

[0047] In this embodiment, 2 / 3Vpp - Vdd <Vc<Vdd,Vpp<3Vdd。

[0048] The memory array in this application embodiment can be used for: AI inference accelerator: Storing synaptic weights in a non-volatile and analog computing manner; Edge devices: Reduce power consumption by minimizing DRAM access and maintaining weights locally; Neuromorphic systems: non-volatile components that enable programmability, analog-like design, and high durability.

[0049] Example 3 In the embodiments of this application, an AI chip is also provided, including a memory array as described in Embodiment 2. AI chips employing this memory array significantly improve area efficiency and signal tolerance.

[0050] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A 1T1P FC ferroelectric memory cell, comprising: include: silicon substrate; An active device region is provided on the silicon substrate, a storage transistor is formed on the active device region, a drain diffusion region and a source diffusion region are formed on the active device region, and the gate stack of the storage transistor is located between the drain diffusion region and the source diffusion region. Storage gate lines are formed on the gate stack of the storage transistors; A paraferroelectric capacitor is formed on the storage gate line.

2. The 1T1P FC ferroelectric memory cell of claim 1, wherein, The drain diffusion region is connected to a bit line via a drain contact.

3. The 1T1P FC ferroelectric memory cell of claim 1, wherein, The source diffusion region is connected to the active line through a source contact.

4. The 1T1P FC ferroelectric memory cell of claim 1, wherein, A storage gate pad is formed on the gate stack of the storage transistor, and a storage gate pad is formed above the storage gate pad through a storage gate contact. The storage gate line is formed on the storage gate pad.

5. The 1T1P FC ferroelectric memory cell of claim 1, wherein, The ferroelectric capacitor includes: The bottom electrode is connected to the gate of the storage transistor; The paraferroelectric layer, disposed on the upper part of the bottom electrode, is composed of a quantum well paraelectric layer structure formed by hafnium silicon oxide and a transition material and a ferroelectric layer; The top electrode is disposed on the paraferroelectric layer and is electrically connected to a plate wire.

6. The 1T1P FC ferroelectric memory cell of claim 5, wherein, The storage gate line is connected to the bottom electrode of the paraferroelectric capacitor via a through-hole pad.

7. The 1T1P FC ferroelectric memory cell of claim 1, wherein, It also includes shallow trench isolation with deposited oxides; the shallow trench isolation is arranged around the active device area.

8. The 1T1P FC ferroelectric memory cell of claim 1, wherein, The gate stack, from bottom to top, comprises: a gate oxide layer, a high dielectric constant dielectric layer, and a TiN layer.

9. A memory array, comprising: The invention includes multiple 1T1PFC ferroelectric memory cells as described in any one of claims 1-8 arranged in an array, wherein 1T1PFC ferroelectric memory cells in the same row are configured to have the same bit line, the same board line and the same source line, and 1T1PFC ferroelectric memory cells in the same column are configured to have the same memory gate line.

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