Non-isolated PoE protection circuits and power supply protection devices

Abstract

This invention provides a non-isolated PoE protection circuit and power supply protection device, relating to the field of power electronics technology. The circuit includes a PoE input circuit and a power input circuit, wherein: the positive terminal of the PoE input circuit is connected to the PoE input port, and the negative terminal of the PoE input circuit is connected to the power input port; the positive terminal of the power input circuit is connected to the power input port, and the negative terminal of the power input circuit is connected to the PoE input port; the power connection status of the PoE input port controls the negative terminal on / off state of the PoE input circuit; the power connection status of the power input port controls the negative terminal on / off state of the power input circuit; the PoE input circuit and the power input circuit are time-divisionally activated. This invention ensures that the PoE input port and the power input port will not have power input simultaneously, preventing damage to components of the power supply protection device due to common ground overload.

Description

Technical Field

[0001] This utility model relates to the field of power electronics technology, and in particular to a non-isolated PoE protection circuit and power supply protection device. Background Technology

[0002] The pursuit of cost reduction has driven changes in product architecture. Traditional PoE (Power Over Ethernet) circuits using the AF protocol, which employed isolated flyback circuits equipped with expensive chips, are gradually being replaced by lower-cost circuits. For example, protocols are being built using MOS (Metal Oxide Semiconductor Field Effect Transistor) and DC / DC (Direct Current / Direct Current) power chips for power conversion, forming a non-isolated PoE circuit. This means that the GND (Ground) of the PoE circuit is not isolated from the GND of the subsequent load.

[0003] However, in the aforementioned non-isolated PoE circuit, when the PD device (Power Device) supports dual power supply backup of PoE power and DC / DC power, if multiple non-isolated PD devices are connected to the same PSE (Power Sourcing Equipment) chip, and a DC / DC power chip is also connected, the negative terminals of the DC / DC power chips of multiple PD devices are interconnected, causing all PD devices and PSE devices to share a common ground. This results in the PoE power supply current randomly flowing back from the ports of different devices, ultimately causing the switching transistor on one of the PD devices to overload and be damaged. Utility Model Content

[0004] This utility model provides a non-isolated PoE protection circuit and power supply protection device to solve the defect in the prior art where all PD devices and PSE devices share a common ground when PD devices support dual power supply backup of PoE power and DC / DC power, which leads to overload and damage of the switching transistor of a certain PD device.

[0005] This utility model provides a non-isolated PoE protection circuit, including: a PoE input circuit and a power input circuit, wherein:

[0006] The positive terminal of the PoE input circuit is connected to the PoE input port, and the negative terminal of the PoE input circuit is connected to the power input port.

[0007] The positive terminal of the power input circuit is connected to the power input port, and the negative terminal of the power input circuit is connected to the PoE input port.

[0008] The power connection status of the PoE input port is used to control the negative terminal on / off state of the PoE input circuit; the power connection status of the power input port is used to control the negative terminal on / off state of the power input circuit; the PoE input circuit and the power input circuit are time-divisionally turned on.

[0009] According to the non-isolated PoE protection circuit provided by this utility model, the PoE input circuit includes a first detection circuit, a processor, and a power input control circuit connected in series, wherein:

[0010] The first detection circuit is connected to the PoE input port, and the power input control circuit is connected to the power input port;

[0011] The first detection circuit generates a first input access signal based on the power access status of the PoE input port; the processor generates a first control signal based on the first input access signal; the first control signal controls the on / off state of the power input control circuit.

[0012] According to the non-isolated PoE protection circuit provided by this utility model, the power input circuit includes a second detection circuit, a processor, and a PoE input control circuit connected in series, wherein:

[0013] The second detection circuit is connected to the power input port, and the PoE input control circuit is connected to the PoE input port;

[0014] The second detection circuit generates a second input access signal based on the power access status of the power input port; the processor generates a second control signal based on the second input access signal; the second control signal controls the on / off state of the PoE input control circuit.

[0015] According to the non-isolated PoE protection circuit provided by this utility model, the first detection circuit includes a pull-up resistor and a first transistor, wherein:

[0016] The base of the first transistor is connected to the PoE input port, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the first end of the pull-up resistor and the first receiving end of the processor, and the second end of the pull-up resistor is connected to the power supply end; the collector of the first transistor is used to output the first input access signal to the first receiving end of the processor.

[0017] According to the non-isolated PoE protection circuit provided by this utility model, the circuit structure of the second detection circuit is the same as that of the first detection circuit.

[0018] According to the non-isolated PoE protection circuit provided by this utility model, when the power input control circuit or the PoE input control circuit includes a MOSFET, the power input control circuit or the PoE input control circuit includes a pull-down resistor and a MOSFET, wherein:

[0019] The gate of the MOS transistor is connected to the first terminal of the pull-down resistor and the first output terminal of the processor. The drain of the MOS transistor and the second terminal of the pull-down resistor are both connected to the device ground. The source of the MOS transistor is connected to the input ground.

[0020] According to the non-isolated PoE protection circuit provided by this utility model, when the power input control circuit or the PoE input control circuit includes a relay, the power input control circuit or the PoE input control circuit includes a relay, a second transistor, and a diode, wherein:

[0021] The base of the second transistor is connected to the second output terminal of the processor, the emitter of the second transistor is connected to the device ground, the collector of the second transistor is connected to the fifth pin of the relay and the first terminal of the diode, the second terminal of the diode is connected to the power supply terminal and the second pin of the relay, the third and fourth pins of the relay are both connected to the device ground, the first pin of the relay is a normally open terminal, and the sixth pin of the relay is connected to the input ground.

[0022] According to the non-isolated PoE protection circuit provided by this utility model, the processor includes a CPU, a DSP chip, or a SoC chip.

[0023] This utility model also provides a power supply protection device, including: a PoE chip and / or a power chip, and a non-isolated PoE protection circuit as described in any of the above.

[0024] This utility model provides a non-isolated PoE protection circuit and power supply protection device. It controls the on / off state of the PoE input circuit and the power input circuit by controlling the power supply status of the power input port, and also controls the PoE input circuit and the power input circuit to conduct in a time-sharing manner. In this utility model, the power supply mode of the power supply protection device is determined by the on / off states of the PoE input circuit and the power input circuit, ensuring that the PoE input port and the power input port do not have power input simultaneously. This ensures that the non-isolated PoE protection circuit does not experience a common ground phenomenon, preventing damage to the components of the power supply protection device due to common ground overload. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of the non-isolated PoE protection circuit provided in this embodiment of the utility model.

[0027] Figure 2 This is a schematic diagram of the PoE input circuit provided in an embodiment of the present invention.

[0028] Figure 3 This is a schematic diagram of the power input circuit provided in an embodiment of the present invention.

[0029] Figure 4 This is a schematic diagram of the structure of the first detection circuit provided in this embodiment of the utility model.

[0030] Figure 5 This is a schematic diagram of the structure of the second detection circuit provided in an embodiment of the present invention.

[0031] Figure 6 This is one of the structural schematic diagrams of the power input control circuit or PoE input control circuit provided in the embodiments of this utility model.

[0032] Figure 7 This is the second schematic diagram of the power input control circuit or PoE input control circuit provided in this embodiment of the utility model.

[0033] Figure label:

[0034] 110: PoE input circuit; 111: First detection circuit; 112: Processor; 113: Power input control circuit; 120: Power input circuit; 121: Second detection circuit; 122: PoE input control circuit; 200: PoE input port; 300: Power input port. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0036] To address the problem in existing technologies where PD devices support dual power supply backup of PoE and DC / DC power, all PD devices and PSE devices share a common ground, leading to overload and damage to the switching transistor of one PD device, this utility model provides a non-isolated PoE protection circuit. Figure 1 This is a schematic diagram of the non-isolated PoE protection circuit provided in an embodiment of this utility model, as shown below. Figure 1 As shown, the non-isolated PoE protection circuit includes: a PoE input circuit 110 and a power input circuit 120.

[0037] The positive terminal of the PoE input circuit 110 is connected to the PoE input port 200, and the negative terminal of the PoE input circuit 110 is connected to the power input port 300.

[0038] The positive terminal of the power input circuit 120 is connected to the power input port 300, and the negative terminal of the power input circuit 120 is connected to the PoE input port 200.

[0039] The power supply status of the PoE input port 200 is used to control the negative terminal on / off state of the PoE input circuit 110; the power supply status of the power input port 300 is used to control the negative terminal on / off state of the power input circuit 120; the PoE input circuit 110 and the power input circuit 120 are time-divisionally connected.

[0040] Specifically, in the prior art, the common ground phenomenon is caused by multiple power supply protection devices (i.e., PD devices) simultaneously connecting to the PoE chip and the power chip. Therefore, in this embodiment of the present invention, a PoE input circuit 110 and a power input circuit 120 are provided in the power supply protection device. The positive terminal of the PoE input circuit 110 is connected to the PoE input port 200 of the power supply protection device, and the negative terminal of the PoE input circuit 110 is connected to the power input port 300 of the power supply protection device. Simultaneously, the positive terminal of the power input circuit 120 is connected to the power input port 300, and the negative terminal of the power input circuit 120 is connected to the PoE input port 200. Then, the on / off state of the negative terminal of the PoE input circuit 110 is controlled according to the power connection status of the PoE input port 200. This negative terminal on / off state refers to the on / off state of the negative terminal. For example, when a PoE chip is connected to the PoE input port 200 (i.e., the positive terminal of the PoE input circuit 110 is connected to the PoE chip), the negative terminal of the PoE input circuit 110 can be controlled to be in an open state, i.e., the power input port 300 is controlled to be in an open state. When a PoE chip is not connected to the PoE input port 200 (i.e., the positive terminal of the PoE input circuit 110 is not connected to the PoE chip), the negative terminal of the PoE input circuit 110 can be controlled to be in a conducting state, i.e., the power input port 300 is controlled to be in a conducting state. Furthermore, the on / off state of the negative terminal of the power input circuit 120 can be controlled according to the power connection status of the power input port 300. For example, when a power chip is connected to the power input port 300 (i.e., the positive terminal of the power input circuit 120 is connected to the power chip), the negative terminal of the power input circuit 120 can be controlled to be in an open state, i.e., the PoE input port 200 is controlled to be in an open state. When the power input port 300 is not connected to a power chip, that is, when the positive terminal of the power input circuit 120 is not connected to a power chip, the negative terminal of the power input circuit 120 can be controlled to be in a conducting state, that is, the PoE input port 200 can be controlled to be in a conducting state. Based on this, this embodiment of the present invention can ensure that the power supplies connected to the PoE input port 200 and the power input port 300 will not be input simultaneously, thereby avoiding the common ground phenomenon that could lead to overload and damage to the device components.

[0041] Optionally, the PoE chip connected to the PoE input port 200 can be a PSE device, which includes multiple RJ45 ports and can provide PoE power to power protection devices. The power chip connected to the power input port 300 can be a non-isolated power supply such as a DC / DC power chip.

[0042] Furthermore, Figure 2 This is a schematic diagram of the PoE input circuit provided in an embodiment of the present invention, as shown below. Figure 2As shown, the PoE input circuit 110 includes a first detection circuit 111, a processor 112, and a power input control circuit 113 connected in series.

[0043] The first detection circuit 111 is connected to the PoE input port 200, and the power input control circuit 113 is connected to the power input port 300.

[0044] The first detection circuit 111 is used to generate a first input access signal Detection1 based on the power access status of the PoE input port 200; the processor 112 is used to generate a first control signal based on the first input access signal Detection1; the first control signal is used to control the on / off state of the power input control circuit 113.

[0045] Specifically, in the PoE input circuit 110, a first detection circuit 111 is set at the positive terminal of the input. Based on the power connection status of the PoE input port 200, the signal state of the input terminal of the first detection circuit 111 is changed, thereby controlling the level state of the first input access signal Detection1 output by the first detection circuit 111. The level state of the first input access signal Detection1 is used to determine whether the PoE input port 200 is connected to a PoE chip. For example, when the PoE input port 200 is not connected to a PoE chip, the input terminal of the first detection circuit 111 receives a low-level signal Input1, thereby controlling the first input access signal Detection1 output by the first detection circuit 111 to be a high-level signal. When the PoE input port 200 is connected to a PoE chip, the input terminal of the first detection circuit 111 switches from a low-level signal to a high-level signal, thereby controlling the first input access signal Detection1 output by the first detection circuit 111 to switch from a high-level signal to a low-level signal. Afterwards, the first detection circuit 111 sends the first input access signal Detection1 to the processor 112, which generates a first control signal. When the first control signal is low, it indicates that the PoE input port 200 is not connected to a PoE chip; when the first control signal is high, it indicates that the PoE input port 200 is connected to a PoE chip. Furthermore, a power input control circuit 113 is provided at the negative terminal of the PoE input circuit 110. The on / off state of this power input control circuit 113 is controlled by the first control signal to control the on / off state of the power input port 300. For example, when the first control signal is low, the power input control circuit 113 is in a conducting state, controlling the power chip to output power when the PoE input port 200 is not connected to a PoE chip and the power input port 300 is connected to a power chip. When the first control signal is high, the power input control circuit 113 is in a disconnected state, controlling the power chip to stop outputting power if the power input port 300 is connected to a power chip when the PoE input port 200 is connected to a PoE chip, thus preventing the PoE chip and the power chip from simultaneously outputting power and avoiding a common ground phenomenon.

[0046] Furthermore, Figure 3 This is a schematic diagram of the power input circuit provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the power input circuit 120 includes a second detection circuit 121, a processor 112, and a PoE input control circuit 122 connected in series.

[0047] The second detection circuit 121 is connected to the power input port 300, and the PoE input control circuit 122 is connected to the PoE input port 200.

[0048] The second detection circuit 121 is used to generate a second input access signal Detection2 based on the power access status of the power input port 300; the processor 112 is used to generate a second control signal based on the second input access signal Detection2; the second control signal is used to control the on / off state of the PoE input control circuit 122.

[0049] Specifically, in the power input circuit 120, a second detection circuit 121 is set at the positive terminal of the input. Based on the power connection status of the power input port 300, the signal state of the input terminal of the second detection circuit 121 is changed, thereby controlling the level state of the second input connection signal Detection2 output by the second detection circuit 121. The level state of the second input connection signal Detection2 is used to determine whether the power input port 300 is connected to a power chip. For example, when the power input port 300 is not connected to a power chip, the input terminal of the second detection circuit 121 receives a low-level signal Input2, thereby controlling the output second input connection signal Detection2 of the second detection circuit 121 to be a high-level signal. When the power input port 300 is connected to a power chip, the input terminal of the second detection circuit 121 switches from a low-level signal to a high-level signal, thereby controlling the output second input connection signal Detection2 of the second detection circuit 121 to switch from a high-level signal to a low-level signal. Afterwards, the second detection circuit 121 sends the second input connection signal Detection2 to the processor 112, which generates a second control signal. When the second control signal is low, it indicates that the power input port 300 is not connected to the power chip; when the second control signal is high, it indicates that the power input port 300 is connected to the power chip. Furthermore, a PoE input control circuit 122 is provided at the negative terminal of the power input circuit 120. The on / off state of this PoE input control circuit 122 is controlled by the second control signal to control the on / off state of the PoE input port 200. For example, when the second control signal is low, the PoE input control circuit 122 is in a conducting state, controlling the PoE chip to output power when the power input port 300 is not connected to the power chip and the PoE input port 200 is connected to the PoE chip. When the second control signal is high, the PoE input control circuit 122 is in a disconnected state, controlling the PoE chip to stop outputting power if the PoE input port 200 is connected to the PoE chip when the power input port 300 is connected to the power chip, thus avoiding simultaneous power output from the PoE chip and the power chip and preventing common grounding.

[0050] Optionally, the processor 112 may include a CPU (Central Processing Unit), a DSP (Digital Signal Processing) chip, or a SoC (System on Chip) chip.

[0051] Furthermore, Figure 4 This is a schematic diagram of the structure of the first detection circuit provided in this embodiment of the utility model, as shown below. Figure 4 As shown, the first detection circuit 111 includes a first pull-up resistor R1 and a first transistor Q1, wherein:

[0052] The base of the first transistor Q1 is connected to the PoE input port 200, the emitter of the first transistor Q1 is grounded, the collector of the first transistor Q1 is connected to the first end of the first pull-up resistor R1 and the first receiving end of the processor 112, and the second end of the first pull-up resistor R1 is connected to the power supply terminal VCC; the collector of the first transistor Q1 is used to output the first input access signal Detection1 to the first receiving end of the processor 112.

[0053] Specifically, when the PoE input port 200 is not connected to a PoE chip, a low-level signal is input to the input terminal of the first detection circuit 111, controlling the first transistor Q1 to be in the off state. The power supply terminal VCC pulls the collector signal of the first transistor Q1 high to a high-level signal through the first pull-up resistor R1. That is, the first input access signal Detection1 output by the first detection circuit 111 is a high-level signal. When the PoE input port 200 is connected to a PoE chip, the input terminal of the first detection circuit 111 switches from a low-level signal to a high-level signal, controlling the first transistor Q1 to be in the on state. The ground terminal pulls the first input access signal Detection1 low to a low-level signal.

[0054] Furthermore, the circuit structure of the second detection circuit 121 is the same as that of the first detection circuit 111. Figure 5 This is a schematic diagram of the structure of the second detection circuit provided in an embodiment of the present invention, as shown below. Figure 5 As shown, the second detection circuit 121 includes a second pull-up resistor R2 and a third transistor Q3, wherein:

[0055] The base of the third transistor Q3 is connected to the power input port 300, the emitter of the third transistor Q3 is grounded, the collector of the third transistor Q3 is connected to the first end of the second pull-up resistor R2 and the second receiving end of the processor 112, and the second end of the second pull-up resistor R2 is connected to the power supply terminal VCC; the collector of the third transistor Q3 is used to output the second input access signal Detection2 to the second receiving end of the processor 112.

[0056] When the power input port 300 is not connected to the power chip, a low-level signal is input to the input terminal of the second detection circuit 121, controlling the third transistor Q3 to be in the off state. The power supply terminal VCC pulls the collector signal of the third transistor Q3 high to a high-level signal through the second pull-up resistor R2. That is, the second input access signal Detection2 output by the second detection circuit 121 is a high-level signal. When the power input port 300 is connected to the power chip, the input terminal of the second detection circuit 121 switches from a low-level signal to a high-level signal, controlling the third transistor Q3 to be in the on state. The ground terminal pulls the second input access signal Detection2 low to a low-level signal.

[0057] Furthermore, Figure 6 This is one of the structural schematic diagrams of the power input control circuit or PoE input control circuit provided in the embodiments of this utility model, such as... Figure 6 As shown, when the power input control circuit 113 or the PoE input control circuit 122 includes a MOSFET Q4, the power input control circuit 113 or the PoE input control circuit 122 includes a pull-down resistor R3 and a MOSFET Q4, wherein:

[0058] The gate of the MOS transistor Q4 is connected to the first terminal of the pull-down resistor R3 and the first output terminal of the processor 112. The drain of the MOS transistor Q4 and the second terminal of the pull-down resistor R3 are both connected to the device ground GND. The source of the MOS transistor Q4 is connected to the input ground GND1.

[0059] Specifically, initially, MOSFET Q4 is in the ON state. The ON / OFF state of MOSFET Q4 can be controlled by the target control signal Control, thereby controlling the ON / OFF state of the power input control circuit 113 or the PoE input control circuit 122. For example, when the target control signal Control is low, MOSFET Q4 is controlled to be in the ON state, thus controlling the power input control circuit 113 or the PoE input control circuit 122 to be in the ON state. When the target control signal Control is high, MOSFET Q4 is controlled to be in the OFF state, thus controlling the power input control circuit 113 or the PoE input control circuit 122 to be in the OFF state.

[0060] Furthermore, Figure 7 This is a second schematic diagram of the power input control circuit or PoE input control circuit provided in this embodiment of the utility model, as shown below. Figure 7 As shown, when the power input control circuit 113 or the PoE input control circuit 122 includes a relay K1, the power input control circuit 113 or the PoE input control circuit 122 includes a relay K1, a second transistor Q2, and a diode D1, wherein:

[0061] The base of the second transistor Q2 is connected to the second output terminal of the processor 112, the emitter of the second transistor Q2 is connected to the device ground GND, the collector of the second transistor Q2 is connected to the fifth pin of the relay K1 and the first terminal of the diode D1, the second terminal of the diode D1 is connected to the power supply terminal VCC and the second pin of the relay K1, the third and fourth pins of the relay K1 are both connected to the device ground GND, the first pin of the relay K1 is a normally open terminal, and the sixth pin of the relay K1 is connected to the input ground GND1.

[0062] Specifically, in the initial state, the relay K1 is switched to pin 6, which is a normally closed port and connected to the input ground GND1. A coil is installed between pins 2 and 5 of relay K1, and pin 2 is connected to the power supply VCC. When the target control signal Control is low, the control transistor Q2 is off, there is no potential difference across the coil, and therefore the coil is de-energized, keeping the relay K1 switched to pin 6, i.e., keeping relay K1 on, thus controlling the power input control circuit 113 or the PoE input control circuit 122 to be on. When the target control signal Control is high, the control transistor Q2 is on, and the device ground GND pulls down the voltage at pin 5 of relay K1, creating a potential difference across the coil, energizing the coil, and attracting the relay K1 to switch from pin 6 to pin 1, i.e., keeping relay K1 off, thus controlling the power input control circuit 113 or the PoE input control circuit 122 to be off.

[0063] It should be noted that the target control signal Control corresponding to the power input control circuit 113 is the first control signal, and the target control signal Control corresponding to the PoE input control circuit 122 is the second control signal.

[0064] The non-isolated PoE protection circuit provided in this embodiment controls the on / off state of the PoE input circuit 110 based on the power supply status of the PoE input port 200, and controls the on / off state of the power input circuit 120 based on the power supply status of the power input port 300, and controls the PoE input circuit 110 and the power input circuit 120 to be turned on in a time-sharing manner. In this embodiment, the power supply mode of the power protection device is determined by the on / off state of the PoE input circuit 110 and the power input circuit 120, ensuring that the PoE input port 200 and the power input port 300 do not have power input at the same time, thereby ensuring that the non-isolated PoE protection circuit does not experience a common ground phenomenon and avoiding damage to the components of the power protection device due to common ground overload.

[0065] This utility model also provides a power supply protection device, including: a PoE chip and / or a power chip, and a non-isolated PoE protection circuit as described in any of the above.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A non-isolated PoE protection circuit, characterized in that, include: PoE input circuit and power input circuit, wherein: The positive terminal of the PoE input circuit is connected to the PoE input port, and the negative terminal of the PoE input circuit is connected to the power input port. The positive terminal of the power input circuit is connected to the power input port, and the negative terminal of the power input circuit is connected to the PoE input port. The power connection status of the PoE input port is used to control the negative terminal on / off state of the PoE input circuit; the power connection status of the power input port is used to control the negative terminal on / off state of the power input circuit; the PoE input circuit and the power input circuit are time-divisionally turned on.

2. The non-isolated PoE protection circuit of claim 1, wherein, The PoE input circuit includes a first detection circuit, a processor, and a power input control circuit connected in series, wherein: The first detection circuit is connected to the PoE input port, and the power input control circuit is connected to the power input port; The first detection circuit generates a first input access signal based on the power access status of the PoE input port; the processor generates a first control signal based on the first input access signal; the first control signal controls the on / off state of the power input control circuit.

3. The non-isolated PoE protection circuit of claim 2, wherein, The power input circuit includes a second detection circuit, a processor, and a PoE input control circuit connected in series, wherein: The second detection circuit is connected to the power input port, and the PoE input control circuit is connected to the PoE input port; The second detection circuit generates a second input access signal based on the power access status of the power input port; the processor generates a second control signal based on the second input access signal; the second control signal controls the on / off state of the PoE input control circuit.

4. The non-isolated PoE protection circuit of claim 3, wherein, The first detection circuit includes a pull-up resistor and a first transistor, wherein: The base of the first transistor is connected to the PoE input port, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the first end of the pull-up resistor and the first receiving end of the processor, and the second end of the pull-up resistor is connected to the power supply end; the collector of the first transistor is used to output the first input access signal to the first receiving end of the processor.

5. The non-isolated PoE protection circuit of claim 4, wherein, The circuit structure of the second detection circuit is the same as that of the first detection circuit.

6. The non-isolated PoE protection circuit of any of claims 3-5, wherein, When the power input control circuit or the PoE input control circuit includes a MOSFET, the power input control circuit or the PoE input control circuit includes a pull-down resistor and a MOSFET, wherein: The gate of the MOS transistor is connected to the first terminal of the pull-down resistor and the first output terminal of the processor. The drain of the MOS transistor and the second terminal of the pull-down resistor are both connected to the device ground. The source of the MOS transistor is connected to the input ground.

7. The non-isolated PoE protection circuit of any of claims 3-5, wherein, When the power input control circuit or the PoE input control circuit includes a relay, the power input control circuit or the PoE input control circuit includes a relay, a second transistor, and a diode, wherein: The base of the second transistor is connected to the second output terminal of the processor, the emitter of the second transistor is connected to the device ground, the collector of the second transistor is connected to the fifth pin of the relay and the first terminal of the diode, the second terminal of the diode is connected to the power supply terminal and the second pin of the relay, the third and fourth pins of the relay are both connected to the device ground, the first pin of the relay is a normally open terminal, and the sixth pin of the relay is connected to the input ground.

8. The non-isolated PoE protection circuit of any of claims 2-5, wherein, The processor includes a CPU, a DSP chip, or a SoC chip.

9. A power supply protection device, characterized in that, include: PoE chip and / or power chip, and non-isolated PoE protection circuit as described in any one of claims 1-8.

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