A control circuit of a super capacitor management unit and an energy storage system
By using the control circuit of the supercapacitor management unit to cyclically control the power supply status of the simulated front-end chip, the problems of static power consumption and module self-discharge of the simulated front-end chip are solved, thereby improving the energy utilization efficiency of the supercapacitor energy storage system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN TIG TECHNOLOGY CO LTD
- Filing Date
- 2025-06-20
- Publication Date
- 2026-07-31
AI Technical Summary
In existing supercapacitor energy storage systems, the static power consumption of the analog front-end chip and the self-discharge of the module result in low energy utilization, especially in long-term standby or low-utilization scenarios.
Design a control circuit for a supercapacitor management unit. The control unit cyclically outputs control signals to the switch control module, so that only one analog front-end chip is turned on at any time, while other chips are turned off, thus avoiding redundant power consumption by multiple chips.
It effectively reduces the dynamic power consumption of analog front-end chips and the superimposed losses from self-discharge of overcapacitive modules, thereby improving energy utilization efficiency.
Smart Images
Figure CN224582871U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of supercapacitor energy storage technology, specifically to a control circuit and energy storage system for a supercapacitor management unit. Background Technology
[0002] With the rapid development of new energy technologies, double-layer supercapacitors, due to their superior characteristics such as high power density, long cycle life, and rapid charge and discharge, have been widely used in fields such as energy recovery in rail transit, auxiliary power supplies for new energy vehicles, backup power supplies for grid peak shaving, and backup power supplies for consumer electronics. Supercapacitor energy storage systems typically consist of multiple individual supercapacitors connected in series to form modules to meet high voltage requirements. To achieve individual cell status monitoring, equalization control, and system protection, a Capacitance Management Unit (CMU) is required. The Analog Front End (AFE), as the core component of the CMU, undertakes key functions such as individual cell voltage acquisition, temperature monitoring, equalization control signal generation, and communication with the main controller, directly affecting the operational safety and energy management efficiency of the energy storage system.
[0003] However, the electrochemical characteristics of double-layer supercapacitors in existing technologies differ fundamentally from those of traditional secondary batteries. Their state of charge is approximately linearly related to their terminal voltage, and their self-discharge rate is significantly affected by the voltage level. Even without active charging and discharging, the terminal voltage of a single supercapacitor will slowly decrease due to internal leakage current when the system is idle or operating at low power. At the same time, in order to maintain basic functions (such as periodic voltage acquisition and communication wake-up), the analog front-end chip in the CMU needs to continuously draw power from the module. Its static power consumption and dynamic operating power consumption will further accelerate the module's power consumption. At this time, the power demand of the analog front-end chip and the module's own power decay form a "superimposed loss": on the one hand, the analog front-end chip continuously consumes power as the "load" of the module; on the other hand, the module's usable capacity is reduced due to self-discharge. The combined effect of these two factors significantly reduces the system's energy utilization rate, especially in long-term standby or low-utilization scenarios, where this problem is more prominent. Utility Model Content
[0004] In view of the above problems, in a first aspect, the present invention provides a control circuit for a supercapacitor management unit, the control circuit of which includes: a control unit;
[0005] At least two analog front-end chips, each of which has a voltage acquisition terminal for connecting to a different individual capacitor of the supercapacitor module;
[0006] A switch control module corresponding to the number of analog front-end chips, with each switch control module connected between the power supply pin and the power input terminal of the analog front-end chip;
[0007] The control signal output terminal of the control unit is connected to the control terminal of each switch control module, and the control unit is used to cyclically output control signals to the control terminal of each switch control module.
[0008] In one possible implementation, the switch control module includes a drive unit, an isolation unit, and a switch unit connected in sequence;
[0009] The input terminal of the drive unit is connected to the control signal output terminal of the control unit and is used to receive the control signal;
[0010] The input terminal of the isolation unit is connected to the output terminal of the drive unit, and the output terminal of the isolation unit is connected to the control terminal of the switch unit.
[0011] The first power terminal of the switching unit is connected to the power input terminal, and the second power terminal is connected to the power supply pin of the analog front-end chip.
[0012] In one possible implementation, the switching unit includes a MOSFET switching device, the drain of which is connected to the power input terminal, the source of which is connected to the power supply pin, and the gate of which is connected to the output terminal of the isolation unit.
[0013] In one possible implementation, a voltage clamping module is connected in parallel between the gate and source of the MOSFET switching device, the voltage clamping module being used to limit the voltage between the gate and source.
[0014] In one possible implementation, the voltage clamping module includes a resistor and a diode connected in parallel, the anode of the diode being connected to the gate of the MOSFET switching device, and the cathode of the diode being connected to the source of the MOSFET switching device.
[0015] In one possible implementation, the isolation unit is an optocoupler, and a bleed diode and an absorption capacitor are connected in parallel between the collector and emitter of the secondary output stage transistor of the optocoupler.
[0016] In one possible implementation, the driving unit includes a switching transistor, the control electrode of which is connected to the control signal output terminal of the control unit via a current-limiting resistor to receive the control signal, the emitter of which is grounded, and the collector of which is connected to the cathode of the input terminal of the isolation unit; the anode of the input terminal of the isolation unit is connected to a power supply via a resistor.
[0017] In one possible implementation, a pull-down resistor is connected between the control electrode of the switching transistor and ground.
[0018] Secondly, embodiments of the present invention provide an energy storage device, including a control circuit for a supercapacitor management unit as described above.
[0019] The above-described one or more technical solutions in the embodiments of this utility model have at least one or more of the following technical effects:
[0020] The control circuit of the supercapacitor management unit provided in this embodiment of the invention cyclically outputs control signals to each switch control module through the control unit, ensuring that only one switch control module is turned on at any given time. This allows only the corresponding analog front-end chip to obtain power through its power supply pin, while the other analog front-end chips are in a power-off state because their corresponding switch control modules are turned off. This design avoids redundant power consumption from multiple analog front-end chips operating simultaneously, directly reducing the combined losses from the dynamic power consumption of the analog front-end chips themselves and the self-discharge of the supercapacitor module, thereby reducing the overall acquisition power consumption of the CMU and effectively improving the energy utilization efficiency of the supercapacitor module.
[0021] The above description is merely an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this utility model more obvious and understandable, specific embodiments of this utility model are given below. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a schematic diagram of the module composition structure of the control circuit of the supercapacitor management unit in an embodiment of this utility model;
[0024] Figure 2 This is a schematic diagram of the switching control module of the control circuit of the supercapacitor management unit in this embodiment of the present invention.
[0025] Figure 3 This is a schematic diagram of the switching control module of the control circuit of the supercapacitor management unit in this embodiment of the present invention.
[0026] Explanation of reference numerals in the attached figures: 100, control unit; 200, analog front-end chip; 300, supercapacitor module; 310, single capacitor; 400, switch control module; 410, drive unit; 420, isolation unit; 430, switch unit; 500, power input terminal. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of this utility model clearer, the embodiments of this utility model will be described in further detail below with reference to the accompanying drawings.
[0028] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this invention as detailed in the appended claims.
[0029] The overall concept of the technical solution provided by this utility model is as follows:
[0030] Please see Figure 1 The control circuit of the supercapacitor management unit includes:
[0031] Control unit 100; the control unit 100 is a control component used to output control signals to control the on and off states of the switch control module 400.
[0032] At least two analog front-end chips 200 are provided, and the voltage acquisition terminal of each analog front-end chip 200 is used to connect to different individual capacitors 310 in the supercapacitor module 300. The analog front-end chip 200 is a key component in the supercapacitor management unit and is responsible for interacting with each individual capacitor 310 in the supercapacitor module 300. The voltage acquisition terminal of each analog front-end chip 200 is used to connect to different individual capacitors 310 in the supercapacitor module 300 to monitor the voltage of each individual capacitor 310 in real time. The number of analog front-end chips 200 can be configured according to the number of individual capacitors in the supercapacitor module 300.
[0033] A switch control module 400 is provided for each analog front-end chip 200. Each switch control module 400 is connected between the power supply pin of the analog front-end chip 200 and the power input terminal 500. Each analog front-end chip 200 corresponds to one switch control module 400. For example, if there are two analog front-end chips 200 in the control circuit, two switch control modules 400 need to be configured. This one-to-one design ensures that the power supply state of each analog front-end chip 200 can be controlled independently. One end of the switch control module 400 is connected to the power supply pin of the analog front-end chip 200 and is responsible for controlling the power supply. The other end of the switch control module 400 is connected to the power input terminal 500 and is responsible for obtaining power from the power input terminal 500.
[0034] More specifically, the voltage signal input at the power input terminal 500 is a voltage signal generated internally by each analog front-end chip 200. Its core function is to provide the low-voltage power required for the internal circuit of the corresponding analog front-end chip 200 to wake up or operate. If the chip cannot directly generate a power supply that meets the requirements, it needs to be linearly stepped down through the high-voltage section to obtain the voltage to be supplied to the chip itself for wake-up. The voltage signals input at the power input terminal 500 of each analog front-end chip 200 are isolated and completely unrelated.
[0035] The control signal output terminal of the control unit 100 is connected to the control terminal of each switch control module 400. The control unit 100 is used to cyclically output control signals to the control terminals of each switch control module 400. The control signal output terminal of the control unit 100 is connected to the control terminal of each switch control module 400, enabling the control unit 100 to independently send control signals to each switch control module 400, thereby achieving independent control of each analog front-end chip 200. The control signals are typically digital signals, which can be high / low levels, pulse signals, or other forms of digital instructions. These signals are used to indicate when the switch control module 400 turns on or off the corresponding analog front-end chip 200.
[0036] Specifically, the control unit 100 typically includes a microcontroller (MCU). Multiple general-purpose I / O ports (GPIOs) of the microcontroller are connected to the control terminals (such as the gates of MOSFETs) of each switch control module 400. Each I / O port corresponds to the power supply control of an analog front-end chip 200. For example, a timer interrupt service routine can be set in the microcontroller program to cyclically control the on / off state of the switch control modules. Example steps are as follows: 1) Initialize the timer, setting the counting period to 10ms; 2) Set the interrupt trigger condition to count overflow; 3) Define an index variable to record the number of the switch control module to be activated; 4) When the timer count overflows, an interrupt is triggered, the microcontroller executes the interrupt service routine, sets the GPIO port corresponding to the current index to a high level, and activates the target analog front-end chip; 5) After a 5ms delay, the GPIO port is set to a low level, and the analog front-end chip enters sleep mode; 6) The index variable is incremented to switch to the next switch control module; 7) The timer interrupt flag is cleared, and the system waits for the next interrupt trigger.
[0037] Optionally, for cost-sensitive scenarios or those requiring extremely high timing accuracy (such as industrial energy storage systems), dedicated timing control chips (such as Siemens' S7-1200 PLC timing modules or Cypress's CY8C20xx series programmable on-chip systems) can be used. These chips have built-in multi-channel programmable timers and can directly generate time-division control signals through hardware configuration (such as setting the on / off time and cycle period of each channel) without the need for MCU intervention. For example, a certain type of timing chip supports the configuration of 8 independent timing channels, each of which can be set with an "on time" (such as 10ms) and an "off time" (such as 990ms), with a total cycle period of 1000ms. After configuring the timing parameters of each channel through hardware registers, the chip will automatically and sequentially turn on each switch control module 400 in a cyclic manner, achieving the control objective of only one switch being turned on at any given time.
[0038] For example, according to sample data, when completing the same data upload task, the old solution uses four analog front-end chips (200) to upload sequentially, taking a total time of 200ms and consuming a total of 1.6mAh of energy. The corresponding average power consumption per unit time is 200ms / 1.6mAh = 8mA. The new solution provided by this invention, after adopting time-sharing power supply control, shortens the total upload time to 80ms and reduces the total energy consumption to 0.64mAh. The corresponding average power consumption per unit time is 80ms / 0.64mAh = 8mA. While the average power consumption values appear the same, the actual reduction in total energy consumption is due to the shorter total task time. More intuitively, the old solution consumes 1.6mAh of total energy, while the new solution only requires 0.64mAh, a 60% reduction in total energy consumption. Therefore, the new solution improves the module's energy utilization efficiency by 60% throughout the entire data upload cycle.
[0039] By cyclically outputting control signals to each switch control module 400 from the control unit 100, only one switch control module 400 can be turned on at any given time. This ensures that only the corresponding analog front-end chip 200 can obtain power through its power supply pin, while the other analog front-end chips 200 remain powered off because their corresponding switch control modules 400 are turned off. This design avoids redundant power consumption from multiple analog front-end chips 200 operating simultaneously, directly reducing the combined losses from the dynamic power consumption of the analog front-end chips 200 and the self-discharge of the supercapacitor module. This reduces the overall acquisition power consumption of the CMU and effectively improves the energy utilization efficiency of the supercapacitor module.
[0040] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0041] Please see Figure 2 The switch control module 400 includes a drive unit 410, an isolation unit 420 and a switch unit 430 connected in sequence;
[0042] The input terminal of the drive unit 410 is connected to the control signal output terminal of the control unit 100 and is used to receive the control signal; the input terminal of the drive unit 410 is directly connected to the control signal output terminal of the control unit 100 and is used to receive the digital control signal sent by the control unit 100. Its core function is to amplify or shape the weak signal output by the control unit 100 into a drive signal suitable for the input requirements of the isolation unit 420.
[0043] The input terminal of the isolation unit 420 is connected to the output terminal of the drive unit 410, and the output terminal of the isolation unit 420 is connected to the control terminal of the switch unit 430. The core function of the isolation unit 420 is to achieve electrical isolation between the "control unit 100 side" and the "switch unit 430 side," preventing high-voltage noise from coupling to the low-voltage control circuit and preventing low-voltage signals from interfering with high-voltage power devices. Preferably, the isolation unit 420 uses an optocoupler isolation scheme. The high-level signal output by the drive unit 410 drives the LED of the optocoupler to conduct, and the phototransistor inside the optocoupler is excited by light and conducts. The output side generates a level signal with logic opposite to that of the input side. When the drive unit 410 outputs a low level, the LED of the optocoupler is cut off, the phototransistor is also cut off, and the output side remains high. This design achieves electrical isolation through optical signal transmission, with an isolation voltage reaching several kilovolts, meeting the high-voltage requirements of the supercapacitor module 300.
[0044] The first power terminal of the switching unit 430 is connected to the power input terminal 500, and the second power terminal is connected to the power supply pin of the analog front-end chip 200. The first power terminal (drain / collector) of the switching unit 430 is connected to the power input terminal 500, and the second power terminal (source / emitter) is connected to the power supply pin of the analog front-end chip 200. Its core function is to connect or disconnect the power supply path between the power input terminal 500 and the analog front-end chip 200 according to the control signal transmitted by the isolation unit 420, thereby controlling the operating state of the analog front-end chip 200 (such as normal operation / sleep).
[0045] For further details, please refer to Figure 3 The switching unit 430 includes a MOSFET switching device Q43. The drain of the MOSFET switching device Q43 is connected to the power input terminal 500, the source of the MOSFET switching device Q43 is connected to the power supply pin, and the gate of the MOSFET switching device Q43 is connected to the output terminal of the isolation unit 420. The on and off states of the MOSFET switching device Q43 are determined by the voltage difference between the gate (G) and the source (S) (i.e., the gate-source voltage Vgs).
[0046] For example, when the output of the isolation unit 420 outputs a low-level control signal to the gate of the MOSFET switch Q43, the gate voltage is lower than the source voltage, and the MOSFET switch Q43 enters the on state. At this time, the output of the power input 500 provides operating power to the power supply pin of the analog front-end chip 200 through the drain-source channel of the MOSFET switch Q43. The analog front-end chip 200 starts up and performs functions such as single-cell voltage acquisition and temperature monitoring. When the output of the isolation unit 420 outputs a high-level control signal to the gate of the MOSFET switch Q43, the gate voltage is higher than the source voltage, and the MOSFET switch Q43 enters the off state. At this time, the conduction path between the drain and source of the MOSFET switch Q43 is cut off, the power supply link between the power input 500 and the power supply pin of the analog front-end chip 200 is disconnected, and the analog front-end chip 200 enters the sleep mode due to the loss of power supply, with static power consumption approaching zero.
[0047] Furthermore, a voltage clamping module is connected in parallel between the gate and source of the MOSFET switching device Q43. The voltage clamping module is used to limit the voltage between the gate and source and to limit the voltage amplitude between the gate and source, so as to ensure that the MOSFET switching device Q43 operates within a safe voltage range and avoid device damage or functional failure due to abnormal voltage.
[0048] Specifically, the voltage clamping module includes a resistor and a diode connected in parallel. The anode of the diode is connected to the gate of the MOSFET switching device Q43, and the cathode of the diode is connected to the source of the MOSFET switching device Q43. (See also...) Figure 3 The voltage clamping module is implemented by a clamping circuit consisting of diode D35 and resistor R346 connected in parallel. Its two ends are directly connected in parallel between the gate and source of MOSFET switching device Q43. During the conduction or cutoff of MOSFET switching device Q43, if the gate-source voltage exceeds the safe operating range of MOSFET switching device Q43 due to circuit fluctuations (such as abnormal output signal of isolation unit 420, sudden change in power supply voltage, etc.), the voltage clamping module will limit Vgs within the set safe threshold through its own clamping characteristics. For example, when Vgs is too high, diode D35 in the clamping module will quickly conduct to shunt the excess voltage and stabilize Vgs at the safe upper limit. When Vgs is too low, the clamping module can provide reverse clamping to prevent Vgs from falling below the minimum withstand voltage of MOSFET switching device Q43. This design effectively improves the operational reliability of the MOSFET switching device Q43, preventing gate breakdown damage caused by overvoltage and avoiding incomplete conduction or false turn-off caused by undervoltage, thus ensuring the stable time-sharing control function of the switching unit 430 under different operating conditions (such as system startup, load change, electromagnetic interference, etc.).
[0049] For further details, please refer to Figure 3 The isolation unit 420 is an optocoupler U16. A bleeder diode D36 and an absorption capacitor C252 are connected in parallel between the collector and emitter of the secondary output stage transistor of the optocoupler U16. The bleeder diode D36 and the absorption capacitor C252 work together to solve the problem that the secondary side cannot be reliably disconnected during the frequency switching process of the optocoupler U16 because the parasitic capacitance energy between the collector and emitter of the secondary output stage transistor cannot be released in time, and to suppress the peak voltage at both ends of the secondary side.
[0050] Please see Figure 3 The driving unit 410 includes a switching transistor Q42. The control electrode of the switching transistor Q42 is connected to the control signal output terminal of the control unit 100 via a current-limiting resistor R343 to receive the control signal. The emitter of the switching transistor Q42 is grounded, and the collector of the switching transistor Q42 is connected to the cathode of the input terminal of the isolation unit 420. The anode of the input terminal of the isolation unit 420 is connected to the power supply via a resistor R345. The isolation unit 420 is an optocoupler U16.
[0051] More specifically, when the control unit 100 outputs a high-level signal, current flows into the base of the switching transistor Q42 through the current-limiting resistor R343. At this time, the base and emitter junction of the switching transistor Q42 is turned on, the collector potential is pulled low, the potential of the cathode at the input terminal of the optocoupler U16 decreases, causing the internal light-emitting diode to conduct due to the positive voltage formed across its terminals, and the light-emitting diode emits light. The phototransistor on the output side of the optocoupler is excited by the light and turns on, the output terminal of the isolation unit 420 is turned on, and the output signal is the opposite of the input side logic. When the control unit 100 outputs a low-level signal, there is not enough current at the base of the switching transistor Q42, so the switching transistor Q42 is turned off, its collector potential is pulled up to the power supply voltage, the cathode potential at the input terminal of the optocoupler U16 increases, causing the light-emitting diode to be turned off due to the lack of positive voltage across its terminals, and the phototransistor on the output side of the optocoupler is not illuminated, and its output terminal is turned off. Among them, the current-limiting resistor R343 limits the base current of the switching transistor Q42 to prevent the switching transistor Q42 from over-saturating or damaging the output port of the control unit 100 due to excessive control signal. At the same time, it ensures that the switching transistor Q42 operates in the amplification region rather than the saturation region, ensuring linear signal transmission. Resistor R345 provides current-limiting protection for the light-emitting diode on the input side of the optocoupler, avoiding burnout of the light-emitting diode due to excessive current caused by power supply voltage fluctuations or optocoupler parameter deviations, thus extending the service life of the optocoupler. The optocoupler U16 is used to realize the electrical isolation between the "low-voltage side of the control unit 100" and the "high-voltage side of the isolation unit 420", blocking the interference of high-voltage side noise on the low-voltage side control circuit, and converting the control signal into a level signal suitable for driving the high-voltage side switching unit 430.
[0052] For further details, please refer to Figure 3 A pull-down resistor R344 is connected between the control electrode of the switching transistor Q42 and ground. Under certain abnormal operating conditions (such as a disconnected signal line, a malfunction of the control unit 100, or incomplete initialization), the control signal output terminal of the control unit 100 may enter a "floating" state (i.e., no clear high / low level output). In this case, the base potential of the switching transistor Q42 may fluctuate randomly due to surrounding stray capacitance, electromagnetic induction, or circuit noise. If the potential rises to the conduction threshold of the switching transistor Q42, it may cause the switching transistor Q42 to mis-turn on, thereby unexpectedly triggering the optocoupler U16 and ultimately affecting the time-sharing control logic of the MOSFET switching device Q43. The pull-down resistor R344, by providing a low-impedance ground path, can force the base potential of the switching transistor Q42 down to near ground potential, ensuring that the switching transistor Q42 is stably turned off when there is no effective control signal, thus avoiding malfunction.
[0053] This utility model embodiment also provides an energy storage system, including a control circuit for a supercapacitor management unit as described in the foregoing embodiments. Various variations and specific embodiments in the foregoing embodiments are also applicable to the energy storage system of this embodiment. Through the foregoing detailed description of the control circuit for a supercapacitor management unit, those skilled in the art can clearly understand the implementation method of the energy storage system in this embodiment. For the sake of brevity, it will not be described in detail here.
[0054] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.
[0055] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this utility model without departing from the spirit and scope of the embodiments of this utility model. Therefore, if these modifications and variations to the embodiments of this utility model fall within the scope of the claims of this utility model and their equivalents, then this utility model also intends to include these modifications and variations.
Claims
1. A control circuit of a supercap management unit, characterized in that, include: Control unit; At least two analog front-end chips, each of which has a voltage acquisition terminal for connecting to a different individual capacitor of the supercapacitor module; A switch control module corresponding to the number of analog front-end chips, with each switch control module connected between the power supply pin and the power input terminal of each corresponding analog front-end chip; The control signal output terminal of the control unit is connected to the control terminal of each switch control module, and the control unit is used to cyclically output control signals to the control terminal of each switch control module.
2. A control circuit for a supercap management unit according to claim 1, characterized in that, The switch control module includes a drive unit, an isolation unit, and a switch unit connected in sequence. The input terminal of the drive unit is connected to the control signal output terminal of the control unit and is used to receive the control signal; The input terminal of the isolation unit is connected to the output terminal of the drive unit, and the output terminal of the isolation unit is connected to the control terminal of the switch unit. The first power terminal of the switching unit is connected to the power input terminal, and the second power terminal is connected to the power supply pin of the analog front-end chip.
3. A control circuit for a supercap management unit according to claim 2, wherein, The switching unit includes a MOSFET switching device, the drain of which is connected to the power input terminal, the source of which is connected to the power supply pin, and the gate of which is connected to the output terminal of the isolation unit.
4. A control circuit for a supercap management unit according to claim 3, wherein, A voltage clamping module is connected in parallel between the gate and the source of the MOSFET switching device. The voltage clamping module is used to limit the voltage between the gate and the source.
5. A control circuit for a supercap management unit according to claim 4, wherein, The voltage clamping module includes a resistor and a diode connected in parallel. The anode of the diode is connected to the gate of the MOSFET switching device, and the cathode of the diode is connected to the source of the MOSFET switching device.
6. The control circuit of a supercap management unit according to claim 2, characterized in that, The isolation unit is an optocoupler, and a discharge diode and an absorption capacitor are connected in parallel between the collector and emitter of the secondary output stage transistor of the optocoupler.
7. The control circuit of a supercap management unit according to claim 2, characterized in that, The driving unit includes a switching transistor. The control electrode of the switching transistor is connected to the control signal output terminal of the control unit via a current-limiting resistor to receive the control signal. The emitter of the switching transistor is grounded, and the collector of the switching transistor is connected to the cathode of the input terminal of the isolation unit. The anode of the input terminal of the isolation unit is connected to the power supply via a resistor.
8. A control circuit for a supercap management unit according to claim 7, characterized in that A pull-down resistor is connected between the control electrode of the switching transistor and ground.
9. An energy storage system characterized by, The control circuit of a supercapacitor management unit as described in any one of claims 1-8 is included.