An ORINGMOS detection and control circuit and a power supply parallel system

Abstract

This utility model discloses an ORINGMOS detection and control circuit and a power supply parallel system. The ORINGMOS detection and control circuit includes: an ORINGMOS switch, one end of which is connected to a power input terminal in the power supply parallel system, and the other end connected to the bus voltage of the power supply parallel system; a detection circuit, whose first input terminal is connected to one end of the ORINGMOS switch and its second input terminal is connected to the other end of the ORINGMOS switch; when the voltage at the first input terminal is greater than or equal to the voltage at the second input terminal, its output terminal outputs a first level; otherwise, its output terminal outputs a second level; a control circuit, including a first switch, one end of which is connected to an auxiliary voltage and the other end to the control terminal of the ORINGMOS switch, the control circuit being controlled by the level signal output by the detection circuit; when the level signal output by the detection circuit is the first level, the first switch is turned on; when the level signal output by the detection circuit is the second level, the first switch is turned off. This utility model can improve light-load efficiency.

Description

Technical Field

[0001] This utility model relates to the field of power supply technology, and in particular to an ORINGMOS detection and control circuit and a power supply parallel system. Background Technology

[0002] The rapid upgrading of communication equipment poses greater challenges to the reliability and cost of power supply systems in parallel operation. To improve power supply reliability, power supply systems typically employ redundant backup designs. In this case, the power supply system generally includes dual power inputs, with the outputs of each power supply connected to a bus voltage, thus forming a single bus voltage that supplies power to subsequent circuits. In parallel power supply systems with multiple power supplies connected in parallel, a failure in one power supply can easily lead to a situation where the bus voltage is higher than the input voltage of that power supply. Figure 1 As shown, an ORING detection and control circuit is connected between the input terminal of each power supply and the bus voltage. When a power supply in the parallel power supply system fails, the ORING detection and control circuit can promptly disconnect it from the parallel power supply system loop to reduce the risk to the parallel power supply system caused by the failure of a single power supply.

[0003] Under normal operating conditions of the power system, each ORING detection and control circuit will detect and compare the input voltage of the corresponding power supply with the bus voltage. If the input voltage of a power supply is higher than the bus voltage, it means that the input voltage port voltage of the power supply is not too high. The corresponding ORING detection and control circuit will send an on signal to turn on the ORING transistor. Otherwise, it will turn off the ORING transistor to prevent the input voltage port voltage from being too high and causing voltage backflow.

[0004] Early solutions for ORING detection and control circuits used the unidirectional conduction characteristic of diodes to achieve the ORING function. When one of the power supplies fails and stops outputting, the diode connected in series in the output circuit is reverse-biased and turned off, achieving redundant parallel operation. However, the forward conduction voltage drop of the diode is large, especially at high current output. As the conduction current increases, the forward conduction loss of the diode increases linearly, which greatly reduces the power supply efficiency of the parallel power supply system and causes serious heat dissipation problems in the parallel power supply system.

[0005] Currently, ORING detection and control circuits are typically implemented using field-effect transistors and operational amplifiers (or comparators). Figure 2The existing ORING detection and control circuit uses a field-effect transistor (FET) and an operational amplifier (op-amp). The input voltage INPUT is connected to the source of FET M1, and the output voltage OUTPUT is connected to the drain of FET M1. The on / off state of the FET is controlled by the op-amp U1, thus realizing the control function of the ORING detection and control circuit. The advantages of this scheme are simple peripheral circuitry and high reliability; the disadvantage is that the op-amp itself is expensive, making it unsuitable for low-cost applications.

[0006] Another method is to implement the ORING detection and control circuit by integrating an ORING control chip, see [reference]. Figure 3 The input voltage Vin is connected to the source of the field-effect transistor Q2, and the output voltage Vout is connected to the drain of Q2. The switching on and off of Q2 is controlled by an integrated chip, such as the commercially available TI5050-1 ORING control chip, thus realizing the ORING control circuit function. The advantages of this solution are simple peripheral circuitry and high reliability; the disadvantages are higher cost and reduced efficiency in light-load applications with low output current.

[0007] The inventors of this application discovered through research that Figure 3 The reason for the reduced efficiency under light load is that the ORING control chip provides a drive voltage (typically a target value of 12V) to the gate of the MOSFET (i.e., field-effect transistor Q2) through an internal charge pump. However, the start-up of the charge pump depends on the voltage drop Vsd across the MOSFET. Assuming the threshold voltage for charge pump start-up is 22mV, when Vsd < 22mV, the charge pump does not work or the output power is insufficient, resulting in a low drive voltage VGS for the MOSFET, which is measured to be about 3–4V. When Vsd > 22mV, the charge pump works at full capacity, and the drive voltage of the MOSFET rises to 11–12V, making the MOSFET fully conduct. According to Ohm's law, Vsd is the current flowing through the MOSFET multiplied by the MOSFET's internal resistance. Because the current flowing through the MOSFET is small under light load conditions, Vsd will be very small, causing the charge pump to not work or have insufficient output power. Therefore, the drive voltage of the MOSFET Q2 is very low. In this case, the on-resistance Rdson of the MOSFET Q2 will increase significantly, and the conduction loss generated on the ORINGMOSFET will increase, resulting in low power supply efficiency under light load. Utility Model Content

[0008] The technical problem to be solved by this utility model is an ORINGMOS detection and control circuit and a power supply parallel system, which at least partially solves one of the technical problems existing in the prior art.

[0009] As the first aspect of this utility model, the technical solution of the provided ORINGMOS detection and control circuit is as follows:

[0010] An ORINGMOS detection and control circuit is applied to a power supply parallel system, wherein the ORINGMOS detection and control circuit includes:

[0011] The ORINGMOS switching transistor has one end connected to the input terminal of a power source in the power parallel system, and the other end connected to the bus voltage of the power parallel system.

[0012] The detection circuit has a first input terminal connected to one end of the ORINGMOS switch and a second input terminal connected to the other end of the ORINGMOS switch. When the voltage at the first input terminal is greater than or equal to the voltage at the second input terminal, its output terminal outputs a first level; when the voltage at the first input terminal is less than the voltage at the second input terminal, its output terminal outputs a second level.

[0013] The control circuit includes a first switching transistor, one end of which is connected to an auxiliary voltage and the other end of which is connected to the control terminal of the ORINGMOS switching transistor. The control circuit is controlled by the level signal output by the output terminal of the detection circuit. When the level signal output by the output terminal of the detection circuit is a first level, the first switching transistor is turned on; when the level signal output by the output terminal of the detection circuit is a second level, the first switching transistor is turned off.

[0014] Optionally, the detection circuit includes transistors Q1D, Q2D, and Q3D, resistors R1, R2, R3, R4, and R5; transistors Q1D and Q2D are NPN transistors, and transistor Q3D is a PNP transistor; the collector of transistor Q1D and the base of transistor Q3D are connected together and then connected to an auxiliary voltage via resistor R3; the collector of transistor Q2D and the emitter of transistor Q3D are connected together and then connected to an auxiliary voltage via resistor R4; the base of transistor Q1D is connected to one end of the ORINGMOS switch via resistor R1; the base of transistor Q2D is connected to the other end of the RINGMOS switch via resistor R2; and the emitters of transistors Q1D and Q2D are connected together and then connected to ground via resistor R5.

[0015] Furthermore, a first voltage regulator circuit is connected between the base and emitter of the transistor Q1D; and / or a second voltage regulator circuit is connected between the base and emitter of the transistor Q2D; and / or a third voltage regulator circuit is connected between the base and emitter of the transistor Q3D.

[0016] Optionally, each voltage regulator circuit includes a Zener diode, with the anode of the Zener diode connected to the base of the corresponding transistor and the cathode connected to the emitter of the corresponding transistor.

[0017] Optionally, the first switching transistor is a transistor Q4D, with the emitter of the transistor Q4D being one end of the first switching transistor and the collector of the transistor Q4D being the other end of the first switching transistor.

[0018] Optionally, the control circuit further includes a controllable precision voltage regulator, resistors R6, R7, R8, and R9. One end of resistor R9 is connected to the auxiliary voltage, and the other end is connected to one end of resistor R6 and the emitter of transistor Q4D. The other end of resistor R6 is connected to one end of resistor R7 and the base of transistor Q4D. The other end of resistor R7 is connected to the cathode of the controllable precision voltage regulator. The reference terminal of the controllable precision voltage regulator and one end of resistor R8 are connected together to receive the level signal output by the detection circuit. The anode of the controllable precision voltage regulator and the other end of resistor R8 are connected together for grounding. The collector of transistor Q4D is connected to the other end of the ORINGMOS switch.

[0019] Optionally, the control circuit further includes a transistor Q9, resistors R6, R7, R8, and R9. One end of resistor R9 is used to connect to the auxiliary voltage, and the other end is connected to one end of resistor R6 and the emitter of transistor Q4D. The other end of resistor R6 is connected to one end of resistor R7 and the base of transistor Q4D. The other end of resistor R7 is connected to the collector of transistor Q9. The base of transistor Q9 and one end of resistor R8 are connected together to receive the level signal output by the detection circuit. The emitter of transistor Q9 and the other end of resistor R8 are connected together for grounding. The collector of transistor Q4D is connected to the other end of the ORINGMOS switch.

[0020] Optionally, the transistor Q9 can be replaced with a MOSFET, with the drain of the MOSFET connected to the other end of resistor R7, the source used for grounding, and the gate connected to one end of resistor R8.

[0021] As a second aspect of this utility model, the technical solution of the provided power supply parallel system is as follows:

[0022] A power supply parallel system, wherein: in the power supply parallel system, at least one power supply input terminal and the bus voltage are connected to the ORINGMOS detection and control circuit described in any of the first aspects above.

[0023] This utility model not only solves the problem of voltage backflow caused by high port voltage in a parallel power supply system, but also has the following beneficial effects compared with the prior art:

[0024] 1. The ORINGMOS detection and control circuit of this utility model selects the output of a first level or a second level through the detection circuit. The first level or the second level controls the first switching transistor to control whether the auxiliary power supply provides a driving voltage to the ORINGMOS switching transistor. Therefore, it can ensure that the driving voltage of the ORINGMOS switching transistor is maintained at the set voltage value throughout the entire load range, thereby improving the light load efficiency of the power supply in the power supply parallel system.

[0025] 2. The specific implementation circuit of the ORINGMOS detection and control circuit in this embodiment of the utility model is very simple, which is beneficial to controlling the cost of the power supply parallel system. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the power supply system including the ORING detection and control circuit in the prior art;

[0027] Figure 2 This is an existing ORING detection and control circuit implemented using field-effect transistors and operational amplifiers;

[0028] Figure 3 This refers to the existing technology that implements an ORING detection and control circuit by integrating an ORING control chip.

[0029] Figure 4 This is a first specific circuit diagram of the ORING detection and control circuit of this utility model;

[0030] Figure 5 This is a second specific circuit diagram of the ORING detection and control circuit of this utility model;

[0031] Figure 6 This is the third specific circuit diagram of the ORING detection and control circuit of this utility model;

[0032] Figure 7 This is the fourth specific circuit diagram of the ORING detection and control circuit of this utility model. Detailed Implementation

[0033] To make the above-mentioned objectives, features, and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0034] It should be noted that the terms "comprising" and "having" and any variations thereof described in the specification and claims of this application are intended to cover non-exclusive inclusion. For example, including a series of components, unit circuits or control timings is not necessarily limited to those components, unit circuits or control timings that are explicitly listed, but may include components, unit circuits or control timings that are not explicitly listed or that are inherent to these circuits.

[0035] Furthermore, unless otherwise specified, the embodiments and features described in this application may be combined with each other.

[0036] It should be understood that, in the specification and claims, when an element is described as being "connected" to another element, that element may be "directly connected" to that other element or "connected" to that other element through a third element; when a step is described as being connected to another step, that step may be connected directly to that other step or connected to that other step through a third step.

[0037] See Figure 4 This invention presents a first specific circuit diagram for an ORING detection and control circuit, applicable to a parallel power supply system. The ORINGMOS detection and control circuit includes:

[0038] ORINGMOS switch Q1, one end of which is used to connect to the input terminal VIN of a power supply in the power parallel system, and the other end is used to connect to the bus voltage of the power parallel system.

[0039] The detection circuit has its first input terminal connected to one end of the ORINGMOS switch Q1 and its second input terminal connected to the other end of the ORINGMOS switch Q1. When the voltage at its first input terminal is greater than or equal to the voltage at its second input terminal, its output terminal outputs a first level; when the voltage at its first input terminal is less than the voltage at its second input terminal, its output terminal outputs a second level.

[0040] The control circuit includes a first switching transistor Q4D. One end of the first switching transistor Q4D is connected to the auxiliary voltage VCC, and the other end is connected to the control terminal of the ORINGMOS switching transistor Q1. The control circuit is controlled by the level signal output by the detection circuit. When the level signal output by the detection circuit is a first level, the first switching transistor Q4D is turned on; when the level signal output by the detection circuit is a second level, the first switching transistor Q4D is turned off.

[0041] Please continue reading Figure 4Among them, the ORINGMOS switch Q1 is a field-effect transistor. Its operating characteristics are as follows: when the voltage difference between the gate voltage and the source voltage is greater than the turn-on threshold voltage Vgs(th) of the field-effect transistor, the source and drain of the field-effect transistor Q1 are turned on; when the voltage difference between the gate voltage and the source voltage is less than the turn-on threshold voltage Vgs(th) of the field-effect transistor, the source and drain of the field-effect transistor Q1 are turned off.

[0042] Please continue reading Figure 4 The detection circuit includes transistors Q1D, Q2D, and Q3D, and resistors R1, R2, R3, R4, and R5. Transistors Q1D and Q2D are NPN transistors, and transistor Q3D is a PNP transistor. The collector of transistor Q1D and the base of transistor Q3D are connected together and then connected to the auxiliary voltage VCC via resistor R3. The collector of transistor Q2D and the emitter of transistor Q3D are connected together and then connected to the auxiliary voltage VCC via resistor R4. The base of transistor Q1D is connected to one end of the RINGMOS switch via resistor R1, and the base of transistor Q2D is connected to the other end of the RINGMOS switch via resistor R2. The emitters of transistors Q1D and Q2D are connected together and then connected to ground via resistor R5.

[0043] Please continue reading Figure 4 The circuit includes a first switching transistor, Q4D, with its emitter at one end and its collector at the other. The control circuit also includes a controllable precision voltage regulator IC1, resistors R6, R7, R8, and R9. One end of resistor R9 is connected to the auxiliary voltage, and the other end is connected to both one end of resistor R6 and the emitter of transistor Q4D. The other end of resistor R6 is connected to both one end of resistor R7 and the base of transistor Q4D. The other end of resistor R7 is connected to the cathode of the controllable precision voltage regulator. The reference terminal of the controllable precision voltage regulator is connected to one end of resistor R8 to receive the level signal output from the detection circuit. The anode of the controllable precision voltage regulator is connected to the other end of resistor R8 for grounding. The collector of transistor Q4D is connected to the other end of the ORINGMOS switching transistor. The controllable precision voltage regulator IC1 can be an AZ431.

[0044] In this embodiment of the invention, the example is taken with a base-emitter saturation voltage Vbe(sat) of 0.7V and a voltage drop between the collector and emitter of 0.3V during saturation conduction.

[0045] Transistors Q1D and Q2D are NPN transistors. The operating characteristic of an NPN transistor is that when the base voltage is greater than the base-emitter saturation voltage of 0.7V, the collector and emitter of the transistor are connected; otherwise, they are disconnected.

[0046] Transistor Q3D and switching transistor Q4D are PNP transistors. The operating characteristic of a PNP transistor is that when the base voltage is less than the base-emitter saturation voltage of 0.7V, the emitter and collector of the transistor are connected; otherwise, the emitter and collector are disconnected.

[0047] The following is about Figure 4 The working principle of the detection circuit is explained using a specific example. Resistors R1 and R2 are sampling resistors; resistors R3 and R4 are for impedance matching; resistor R5 is the negative feedback resistor; resistor R9 is the current-limiting resistor; and resistors R6, R7, and R8 are also for impedance matching. The required values ​​for each resistor are as follows: resistors R1, R2, R3, R4, R5, R7, and R8 are in the kΩ range, with resistors R1 and R2 having the same value, and resistors R3 and R4 having the same value; resistors R6 and R9 are in the Ω range.

[0048] (1) When the power supply parallel system is working normally, assume that the input voltage VIN of one of the power supplies is 12.5V, the output voltage VOUT is 12.2V, and the auxiliary voltage VCC of the auxiliary power supply is 24V.

[0049] Since the auxiliary voltage VCC is much higher than the input voltage VIN and the output voltage VOUT, and the input voltage VIN is greater than the output voltage VOUT, the transistor Q1D with a higher base-emitter voltage will reach the conduction threshold earlier and enter the conduction state first. The auxiliary voltage VCC will form a circuit through the collector of transistor Q1D, the emitter of transistor Q1D, and resistor R5.

[0050] Since transistors are devices that drive large currents with small currents, the current flowing through resistor R1 is very small. Neglecting the voltage drop across resistor R1, the base voltage of transistor Q1D is approximately equal to the input voltage of 12.5V. Therefore, when transistor Q1D is in the conducting state, its emitter voltage is 12.5 - 0.7 = 11.8V. Consequently, the emitter voltage of transistor Q2D is also 11.8V, while the base voltage of transistor Q2D is 12.2V. Therefore, the voltage difference between the base and emitter voltages of transistor Q2D is (12.2V - 11.8V) = 0.4V, which is less than 0.7V. Thus, transistor Q2D will be in the cutoff state.

[0051] When transistor Q1D is turned on, its collector voltage is approximately equal to the voltage across resistor R5 after the auxiliary voltage VCC is divided by resistors R3 and R5 in series. When transistor Q2D is turned off, its collector voltage is approximately equal to VCC. Therefore, the collector voltage of transistor Q1D is less than that of transistor Q2D, resulting in a base-emitter voltage of 0.7V for transistor Q3D. Since Q3D is an NPN transistor, it is saturated and conducting. Because the emitter voltage of Q3D is clamped by the base voltage during saturation, and because Q1D is also saturated at this time, assuming the resistances of resistors R3 and R4 are 1kΩ... The resistance of resistor R5 is 5KΩ. Therefore, the collector voltage of transistor Q1D is approximately 24*5 / (1+5) = 20V. The base voltage of transistor Q3D is equal to the collector voltage of transistor Q1D. Therefore, the emitter voltage of transistor Q3D is approximately 20 + 0.7 = 20.7V. That is, the emitter voltage of transistor Q3D is clamped to 20.7V by the low base voltage. Since the voltage drop between the collector and emitter is 0.3V when the transistor is saturated, the collector voltage of transistor Q3D is 20.7V - 0.3V = 20.4V, which is much greater than 2.5V. That is, the collector output of transistor Q3D is greater than 2.5V. This invention refers to it as a high-level signal.

[0052] (2) When the parallel power supply system malfunctions, assume that the input voltage VIN of one of the power supplies is 0.5V, the output voltage VOUT is 12.2V, and the auxiliary voltage VCC of the auxiliary power supply is 24V.

[0053] When two prototype units are connected in parallel, if one of the two input voltages VIN has an overvoltage output while the other outputs normally, the input voltage VIN of the faulty power supply will be lower than its output voltage VOUT. Similarly, if one of the input voltages VIN is short-circuited (i.e., one power supply's input voltage VIN is short-circuited while the other's input voltage VIN is normal), the input voltage VIN of the short-circuited power supply will also be lower than its output voltage VOUT. For the faulty power supply, assume its input voltage VIN is 0.5V, its output voltage VOUT is 12.2V, and its auxiliary voltage VCC is 24V.

[0054] Since the auxiliary voltage VCC is much higher than the input voltage VIN and the output voltage VOUT, and the input voltage VIN is less than the output voltage VOUT, the transistor Q2D with a higher base-emitter voltage will reach the conduction threshold earlier and enter the conduction state first. The auxiliary voltage VCC forms a circuit through the collector of transistor Q2D, the emitter of transistor Q2D, and R5.

[0055] Since transistors are devices that drive large currents with small currents, the current flowing through resistor R2 is very small. Neglecting the voltage drop across resistor R2, the base voltage of transistor Q2D is approximately equal to the output voltage VOUT, which is 12.2V. Therefore, when transistor Q2D is in the conducting state, its emitter voltage is 12.2 - 0.7 = 11.5V. Consequently, the emitter voltage of transistor Q1D is also 11.5V. Meanwhile, the base voltage of transistor Q1D is approximately equal to the input voltage VIN, which is 0.5V. Since the base voltage of transistor Q1D is less than 0.7V (i.e., the base-emitter saturation voltage), transistor Q1D will be in the off state.

[0056] When transistor Q1D is off and transistor Q2D is on, similar to the above analysis, the collector voltage of transistor Q1D is much greater than the collector voltage of transistor Q2D. Consequently, the base voltage of transistor Q3D is much greater than the base-emitter saturation voltage of 0.7V. Since transistor Q3D is an NPN transistor, it is cut off, and the collector output of transistor Q3D is a low-level voltage much less than 2.5V, which is referred to as a low-level signal in this invention.

[0057] The following is about Figure 4 The working principle of the control circuit is explained below. The control circuit selectively turns the gate of the field-effect transistor Q1 on or off based on the high or low signal output by the transistor Q3D:

[0058] (1) When transistor Q3D outputs a high-level signal

[0059] When transistor Q3D outputs a high-level signal, since this high-level signal is greater than 2.5V, which is greater than the reference voltage of the controllable precision voltage regulator IC1, the cathode of the controllable precision voltage regulator IC1 has a low impedance. The auxiliary voltage VCC forms a conduction loop through the controllable precision voltage regulator IC1 to GND, pulling down the base voltage of transistor Q4D so that it is less than the base-emitter saturation voltage of 0.7V. Since transistor Q4D is a PNP transistor, when the base voltage of transistor Q4D is less than the base-emitter saturation voltage of 0.7V, transistor Q4D is saturated and conducts, connecting the auxiliary voltage VCC to the gate of field-effect transistor Q1, making field-effect transistor Q1 conduct. Current flows from the input voltage VIN to the output voltage VOUT, injecting into the combined bus voltage.

[0060] (2) When transistor Q3D outputs a low-level signal

[0061] When transistor Q3D outputs a low-level signal, since this low-level signal is less than 2.5V, which is less than the reference voltage of the controllable precision voltage regulator IC1, the cathode of the controllable precision voltage regulator IC1 has a high impedance. The auxiliary voltage VCC cannot form a conducting loop through the controllable precision voltage regulator IC1 to GND. Therefore, the base voltage of transistor Q4D is approximately equal to the emitter voltage, so transistor Q4D does not conduct. As a result, the field-effect transistor Q1 is turned off, which allows the input voltage VIN and the combined bus voltage to be disconnected in time.

[0062] Figure 5 This is a second specific circuit diagram of the ORING detection and control circuit of this utility model, and... Figure 4 The difference lies in replacing the controllable precision voltage regulator IC1 with transistor Q9, as... Figure 4 Another equivalent replacement is to replace the controllable precision voltage regulator IC1 with a MOSFET.

[0063] Figure 6 This is a third specific circuit diagram of the ORING detection and control circuit of this utility model, and... Figure 4 The difference lies in that a voltage regulator circuit is connected between the base and emitter of each of the transistors Q1D, Q2D, and Q3D. Specifically, each voltage regulator circuit consists of a Zener diode ZD1, a Zener diode ZD2, and a Zener diode ZD3.

[0064] Figure 7 This is the fourth specific circuit diagram of the ORING detection and control circuit of this utility model, and... Figure 4 The difference lies in replacing the controllable precision voltage regulator IC1 with transistor Q9, and connecting a voltage regulator circuit between the base and emitter of transistors Q1D, Q2D, and Q3D.

[0065] Figure 5 , Figure 6 and Figure 7 Specific working principle and Figure 4 The same applies, so I won't go into details here.

[0066] This utility model embodiment also provides a power supply parallel system, in which at least one of the above-mentioned ORINGMOS detection and control circuits is connected between the input terminal of at least one power supply and the bus voltage.

[0067] It should be noted that the above-described embodiments are only for the purpose of facilitating understanding by those skilled in the art and are not intended to limit the scope of protection of this utility model. Any obvious substitutions and improvements made by those skilled in the art without departing from the inventive concept of this utility model are within the scope of protection of this utility model.

Claims

1. An ORING MOS detection control circuit applied to a power supply and connection system, characterized in that, The ORINGMOS detection and control circuit includes: The ORINGMOS switching transistor has one end connected to the input terminal of a power source in the power parallel system, and the other end connected to the bus voltage of the power parallel system. The detection circuit has a first input terminal connected to one end of the ORINGMOS switch and a second input terminal connected to the other end of the ORINGMOS switch. When the voltage at the first input terminal is greater than or equal to the voltage at the second input terminal, its output terminal outputs a first level; when the voltage at the first input terminal is less than the voltage at the second input terminal, its output terminal outputs a second level. The control circuit includes a first switching transistor, one end of which is connected to an auxiliary voltage and the other end of which is connected to the control terminal of the ORINGMOS switching transistor. The control circuit is controlled by the level signal output by the output terminal of the detection circuit. When the level signal output by the output terminal of the detection circuit is a first level, the first switching transistor is turned on; when the level signal output by the output terminal of the detection circuit is a second level, the first switching transistor is turned off.

2. The ORING MOS detection control circuit according to claim 1, wherein The detection circuit includes transistors Q1D, Q2D, and Q3D, resistors R1, R2, R3, R4, and R5. Transistors Q1D and Q2D are NPN transistors, and transistor Q3D is a PNP transistor. The collector of transistor Q1D and the base of transistor Q3D are connected together and then connected to an auxiliary voltage via resistor R3. The collector of transistor Q2D and the emitter of transistor Q3D are connected together and then connected to an auxiliary voltage via resistor R4. The base of transistor Q1D is connected to one end of the RINGMOS switch via resistor R1, and the base of transistor Q2D is connected to the other end of the RINGMOS switch via resistor R2. The emitters of transistors Q1D and Q2D are connected together and then connected to ground via resistor R5.

3. The ORING MOS detection control circuit according to claim 2, wherein: A first voltage regulator circuit is connected between the base and emitter of transistor Q1D; and / or a second voltage regulator circuit is connected between the base and emitter of transistor Q2D; and / or a third voltage regulator circuit is connected between the base and emitter of transistor Q3D.

4. The ORINGMOS detection and control circuit according to claim 3, characterized in that: Each voltage regulator circuit includes a Zener diode, with the anode of the Zener diode connected to the base of the corresponding transistor and the cathode connected to the emitter of the corresponding transistor.

5. The ORINGMOS detection and control circuit according to claim 1, characterized in that: The first switching transistor is a transistor Q4D, with the emitter of the transistor Q4D being one end of the first switching transistor and the collector of the transistor Q4D being the other end of the first switching transistor.

6. The ORINGMOS detection and control circuit according to claim 5, characterized in that: The control circuit also includes a controllable precision voltage regulator, resistors R6, R7, R8, and R9. One end of resistor R9 is connected to the auxiliary voltage, and the other end is connected to one end of resistor R6 and the emitter of transistor Q4D. The other end of resistor R6 is connected to one end of resistor R7 and the base of transistor Q4D. The other end of resistor R7 is connected to the cathode of the controllable precision voltage regulator. The reference terminal of the controllable precision voltage regulator and one end of resistor R8 are connected together to receive the level signal output by the detection circuit. The anode of the controllable precision voltage regulator and the other end of resistor R8 are connected together for grounding. The collector of transistor Q4D is connected to the other end of the ORINGMOS switch.

7. The ORINGMOS detection and control circuit according to claim 5, characterized in that: The control circuit also includes a transistor Q9, resistors R6, R7, R8, and R9. One end of resistor R9 is connected to the auxiliary voltage, and the other end is connected to one end of resistor R6 and the emitter of transistor Q4D. The other end of resistor R6 is connected to one end of resistor R7 and the base of transistor Q4D. The other end of resistor R7 is connected to the collector of transistor Q9. The base of transistor Q9 and one end of resistor R8 are connected together to receive the level signal output by the detection circuit. The emitter of transistor Q9 and the other end of resistor R8 are connected together for grounding. The collector of transistor Q4D is connected to the other end of the ORINGMOS switch.

8. The ORINGMOS detection and control circuit according to claim 7, characterized in that: Replace the transistor Q9 with a MOSFET. The drain of the MOSFET is connected to the other end of resistor R7, the source is grounded, and the gate is connected to one end of resistor R8.

9. A power supply parallel connection system, characterized in that: In the power supply parallel system, at least one power supply input terminal and the bus voltage are connected to the ORINGMOS detection and control circuit according to any one of claims 1 to 8.

Images