A half-bridge driving circuit of FPGA switching power supply

Abstract

This utility model relates to the field of switching power supply driving technology, specifically a half-bridge driving circuit for an FPGA switching power supply. It includes a driving circuit, an input terminal electrically connected to a power management chip, an isolation circuit electrically connected to the driving circuit, and an FPGA controller electrically connected to the isolation circuit. The FPGA controller is electrically connected to the power management chip. An NMOS transistor Q1 and an NMOS transistor Q2 are connected in parallel between a transformer T1 and the power management chip. The driving circuit, power management chip, isolation circuit, and FPGA controller of this utility model constitute a complete power control system. The FPGA controller sends control signals to the driving circuit through the isolation circuit, and the driving circuit then controls the operation of the power management chip, thereby achieving efficient power conversion and management. The isolation circuit ensures that the control signals are not affected by power supply noise, improving the stability and safety of the system.

Description

Technical Field

[0001] This utility model relates to a half-bridge drive circuit, and more particularly to a half-bridge drive circuit for an FPGA switching power supply, belonging to the field of switching power supply drive technology. Background Technology

[0002] With the development of new energy technologies, various topologies of switching power supplies have been widely used. Half-bridge switching power supplies are high-efficiency, high-power-density DC-DC conversion topologies, widely used in industrial power supplies, communication equipment, new energy and other fields. Combined with FPGA control, they can realize high-precision PWM modulation, digital closed-loop regulation and flexible protection functions.

[0003] Existing switching power supplies that use half-bridge converters as the main components have the characteristics of high output power, high efficiency, and each switching transistor only bears half of the input voltage, so they are widely used. However, the drive control is relatively complex, and the feedback control uses a lot of components, which is not conducive to the stability of the switching power supply and the safety is also low.

[0004] Therefore, it is urgent to improve the half-bridge drive circuit of the FPGA switching power supply to solve the above-mentioned problems. Utility Model Content

[0005] The purpose of this invention is to provide a half-bridge drive circuit for an FPGA switching power supply. The drive circuit, power management chip, isolation circuit, and FPGA controller can form a complete power control system. The power management chip is responsible for regulating and distributing power to ensure that all parts of the system receive a stable power supply. The FPGA controller sends control signals to the drive circuit through the isolation circuit, and the drive circuit then controls the operation of the power management chip, thereby achieving efficient power conversion and management. The isolation circuit ensures that the control signals are not affected by noise in the power supply section, improving the stability and safety of the system.

[0006] To achieve the above objectives, the main technical solutions adopted by this utility model include: A half-bridge drive circuit for an FPGA switching power supply includes a drive circuit, an input terminal of which is electrically connected to a power management chip, an isolation circuit electrically connected to the drive circuit, an FPGA controller electrically connected to the isolation circuit, and the FPGA controller being electrically connected to the power management chip. The driving circuit includes a transformer T1, and an NMOS transistor Q1 and an NMOS transistor Q2 are connected in parallel between the transformer T1 and the power management chip. The NMOS transistor Q1 is electrically connected to the DRV-HI pin of the power management chip, and the NMOS transistor Q2 is electrically connected to the DRV-LO pin of the power management chip. A diode D7 is electrically connected to NMOS transistor Q1, and a diode D8 is electrically connected to NMOS transistor Q2. NMOS transistors Q1 and Q2 are electrically connected to one end of transformer T1 through capacitor C5. The other end of transformer T1 is electrically connected to capacitor C3 and grounded.

[0007] Preferably, the other end of the capacitor C5 is electrically connected to the Bridge pin of the power management chip, and diodes D1 and D2 are connected in parallel on the side of the transformer T1 away from the capacitor C5, with the output through inductor L0 on diode D1.

[0008] Preferably, diodes D5 and D6 are connected in series in the middle of the transformer T1 and output the diodes. One side of diode D5 is grounded through resistor R3. Resistor R2 and capacitor C6 are connected in parallel between diodes D5 and D6.

[0009] Preferably, one side of the capacitor C3 is electrically connected to the isolation circuit, the isolation circuit is electrically connected to the driving circuit through a resistor R1, and one pin of the isolation circuit is grounded through a diode D3.

[0010] Preferably, a diode D4 is electrically connected to the VBOOT pin of the power management chip and connected to the power supply Vcc, and the VBOOT pin of the power management chip is electrically connected to the Bridge pin of the power management chip.

[0011] Preferably, a capacitor C2 is electrically connected between the driving circuit and the power management chip and grounded.

[0012] Preferably, the NMOS transistors Q1 and Q2 are connected to the DC bus voltage through capacitor C1, and capacitor C1 is grounded.

[0013] This utility model has at least the following beneficial effects: 1. A complete power control system can be formed by a driver circuit, a power management chip, an isolation circuit, and an FPGA controller. The power management chip is responsible for regulating and distributing power to ensure that all parts of the system receive a stable power supply. The FPGA controller sends control signals to the driver circuit through the isolation circuit, and the driver circuit then controls the operation of the power management chip, thereby achieving efficient power conversion and management. The isolation circuit ensures that the control signals are not affected by noise in the power supply section, improving the stability and safety of the system.

[0014] 2. Adding a series capacitor C5 to the primary winding of transformer T1 will filter out the DC bias voltage that is proportional to the unbalanced volt-second value. In this way, the volt-second value of the voltage will be balanced during the conduction of the transistor, thus achieving the purpose of eliminating the bias magnetism. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the present invention; Figure 2 This is the circuit diagram of this utility model.

[0016] In the diagram, 1 is the driver circuit; 2 is the power management chip; 3 is the isolation circuit; and 4 is the FPGA controller. Detailed Implementation

[0017] The following will describe in detail the implementation of this application with reference to the accompanying drawings and embodiments, so that the implementation process of how this application uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0018] like Figures 1-2 As shown, the half-bridge drive circuit of the FPGA switching power supply provided in this embodiment includes a drive circuit 1, a power management chip 2 electrically connected to the input terminal of the drive circuit 1, an isolation circuit 3 electrically connected to the drive circuit 1, an FPGA controller 4 electrically connected to the isolation circuit 3, and the FPGA controller 4 electrically connected to the power management chip 2. The drive circuit 1, the power management chip 2, the isolation circuit 3, and the FPGA controller 4 can constitute a complete power control system. The power management chip 2 is responsible for regulating and distributing power to ensure that all parts of the system receive a stable power supply. The FPGA controller 4 sends control signals to the drive circuit 1 through the isolation circuit 3, and the drive circuit 1 then controls the operation of the power management chip 2, thereby achieving efficient power conversion and management. At the same time, the isolation circuit 3 ensures that the control signal is not affected by power supply noise, improving the stability and safety of the system. The drive circuit 1 includes a transformer T1. NMOS transistors Q1 and Q2 are connected in parallel between the transformer T1 and the power management chip 2. NMOS transistor Q1 is electrically connected to the DRV-HI pin of the power management chip 2, and NMOS transistor Q2 is electrically connected to the DRV-LO pin of the power management chip 2. The low-power PWM signal output by the FPGA controller 4 is amplified to a high-current signal that can drive power devices. It is usually used to amplify control signals to drive high-power devices. They convert low-power control signals into high-current drive signals to control the switching operation of the power converter. When NMOS transistor Q1 is turned off and NMOS transistor Q2 is turned off, the two windings on the secondary side of the transformer are in a short-circuit state because the two rectifier diodes are simultaneously freewheeling, and the primary winding is also in a short-circuit state. NMOS transistor Q1 is turned off, and NMOS transistor Q2 is turned on. At this time, the voltage applied across the transformer is approximately half of the bus voltage, and energy is transferred from the primary side to the secondary side, with the two diodes on the secondary side completing commutation. A diode D7 is electrically connected to NMOS transistor Q1, and a diode D8 is electrically connected to NMOS transistor Q2. NMOS transistors Q1 and Q2 are electrically connected to one end of transformer T1 through capacitor C5. The other end of transformer T1 is electrically connected to capacitor C3 and grounded. By adding a series capacitor C5 to the primary winding of transformer T1, the DC bias voltage proportional to the unbalanced volt-second value will be filtered out by the capacitor. In this way, the volt-second value of the voltage will be balanced during the conduction of the transistors, thus achieving the purpose of eliminating the bias magnetism.

[0019] Furthermore, such as Figure 2 As shown, the other end of capacitor C5 is electrically connected to the Bridge pin of power management chip 2. Diodes D1 and D2 are connected in parallel on the side of transformer T1 away from capacitor C5. Diode D1 outputs through inductor L0. On transformer T1, diodes D1 and D2 may be used for rectification, converting AC to DC. The diodes connected in parallel on transformer T1 may serve as rectification, protection, or clamping functions. Connecting diodes in parallel on the secondary winding of the transformer can protect the switching transistor from reverse voltage impact. Diodes D5 and D6 are connected in series in the middle of transformer T1 and output. One side of diode D5 is grounded through resistor R3. Resistor R2 and capacitor C6 are connected in parallel between diodes D5 and D6. Capacitor C6 has the ability to store charge and can provide transient current or filtering in the circuit. Resistor R2 is used to limit current, divide voltage, or provide specific impedance. When capacitor C6 and resistor R2 are connected in parallel, they can jointly affect the performance of the circuit and achieve specific functions, such as filtering, coupling, bypassing, or providing a specific time constant, while also serving to adjust the dead time.

[0020] Furthermore, such as Figure 2 As shown, one side of capacitor C3 is electrically connected to isolation circuit 3. Isolation circuit 3 is electrically connected to drive circuit 1 through resistor R1. One pin of isolation circuit 3 is grounded through diode D3. Isolation circuit 3 is used for electrical isolation to prevent current or voltage interference between different circuit parts. Isolation circuit 3 is an optocoupler used to improve the safety and reliability of the system.

[0021] Furthermore, such as Figure 2As shown, a diode D4 is electrically connected to the VBOOT pin of the power management chip 2 and connected to the power supply Vcc. The VBOOT pin of the power management chip 2 is also electrically connected to the Bridge pin of the power management chip 2. A capacitor C2 is electrically connected between the drive circuit 1 and the power management chip 2 and grounded. NMOS transistors Q1 and Q2 are connected to the DC bus voltage through capacitor C1, and capacitor C1 is grounded. The structure is simple and improves the safety and reliability of the system.

[0022] like Figures 1-2 As shown, the principle of the half-bridge drive circuit for the FPGA switching power supply provided in this embodiment is as follows: The input terminal of the drive circuit 1 is electrically connected to a power management chip 2. An isolation circuit 3 is electrically connected to the drive circuit 1, and an FPGA controller 4 is electrically connected to the isolation circuit 3. The FPGA controller 4 is electrically connected to the power management chip 2. The drive circuit 1, power management chip 2, isolation circuit 3, and FPGA controller 4 can form a complete power control system. The power management chip 2 is responsible for regulating and distributing power to ensure that all parts of the system receive a stable power supply. The FPGA controller 4 sends control signals to the drive circuit 1 through the isolation circuit 3, and the drive circuit 1 then controls the operation of the power management chip 2, thereby achieving efficient power conversion and management. At the same time, the isolation circuit 3 ensures that the control signal is not affected by power supply noise, improving the stability and safety of the system.

[0023] If certain terms are used in the specification and claims to refer to specific components, those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function. The term "comprising" as used throughout the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to." "Approximately" means that within an acceptable margin of error, those skilled in the art can solve the technical problem and substantially achieve the technical effect within a certain margin of error.

[0024] It should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a product or system comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a product or system. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the product or system that includes that element.

[0025] The foregoing description illustrates and describes several preferred embodiments of the present invention. However, as previously stated, it should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the inventive concept described herein through the foregoing teachings or techniques or knowledge in related fields. Any modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A half-bridge driver circuit for an FPGA switching power supply comprising a driver circuit (1), characterized in that, The input terminal of the driving circuit (1) is electrically connected to a power management chip (2), the driving circuit (1) is electrically connected to an isolation circuit (3), the isolation circuit (3) is electrically connected to an FPGA controller (4), and the FPGA controller (4) is electrically connected to the power management chip (2). The driving circuit (1) includes a transformer T1. An NMOS transistor Q1 and an NMOS transistor Q2 are connected in parallel between the transformer T1 and the power management chip (2). The NMOS transistor Q1 is electrically connected to the DRV-HI pin of the power management chip (2), and the NMOS transistor Q2 is electrically connected to the DRV-LO pin of the power management chip (2). A diode D7 is electrically connected to NMOS transistor Q1, and a diode D8 is electrically connected to NMOS transistor Q2. NMOS transistors Q1 and Q2 are electrically connected to one end of transformer T1 through capacitor C5. The other end of transformer T1 is electrically connected to capacitor C3 and grounded.

2. The half bridge driving circuit of the FPGA switching power supply according to claim 1, characterized in that: The other end of the capacitor C5 is electrically connected to the Bridge pin of the power management chip (2). A diode D1 and a diode D2 are connected in parallel on the side of the transformer T1 away from the capacitor C5. The diode D1 is output through the inductor L0.

3. The half bridge driving circuit of the FPGA switching power supply according to claim 1, characterized in that: A diode D5 and a diode D6 are connected in series in the middle of the transformer T1 and output. One side of the diode D5 is grounded through a resistor R3. A resistor R2 and a capacitor C6 are connected in parallel between the diodes D5 and D6.

4. The half bridge driving circuit of the FPGA switching power supply according to claim 1, characterized in that: One side of the capacitor C3 is electrically connected to the isolation circuit (3), the isolation circuit (3) is electrically connected to the driving circuit (1) through the resistor R1, and one pin of the isolation circuit (3) is grounded through the diode D3.

5. The half bridge driving circuit of the FPGA switching power supply according to claim 1, characterized in that: The power management chip (2) has a diode D4 electrically connected to its VBOOT pin and connected to the power supply Vcc. The power management chip (2) also has a VBOOT pin electrically connected to its Bridge pin.

6. The half bridge driving circuit of the FPGA switching power supply according to claim 1, characterized in that: A capacitor C2 is electrically connected between the driving circuit (1) and the power management chip (2) and grounded.

7. The half bridge driving circuit of the FPGA switching power supply according to claim 1, characterized in that: The NMOS transistors Q1 and Q2 are connected to the DC bus voltage through capacitor C1, and capacitor C1 is grounded.

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