A radio frequency amplifier chip that suppresses time-domain waveform oscillations during turn-on.

Abstract

This utility model relates to the field of microwave integrated circuit technology, specifically to a radio frequency amplifier chip that suppresses time-domain waveform oscillations during turn-on. It significantly improves and enhances the electrical performance of monolithic microwave integrated chips using heterojunction dual-carrier transistor technology, which is affected by bias voltage fluctuations. When the bias voltage fluctuates significantly, it ensures the stability of the static current of the radio frequency transistor base, minimizing the impact of bias voltage fluctuations on the chip's electrical performance. The bias circuit structure of this utility model requires only minor modifications to the existing current mirror bias architecture and will not have any additional impact on other electrical performance indicators of the chip.

Description

Technical Field

[0001] This utility model relates to the field of microwave integrated circuit technology, and more specifically, to a radio frequency amplifier chip that suppresses time-domain waveform oscillations at the moment of power-on. Background Technology

[0002] Existing power amplifiers or general monolithic microwave integrated circuits typically use an LDO (Low Voltage Regulator) chip and a traditional current mirror as the bias circuit architecture for RF transistors. In this architecture, the conventional ammeter provides bias current to the RF transistor, thereby controlling the transistor's operating state, while the LDO provides a stable voltage to the conventional current mirror bias structure. This structure can provide a stable quiescent operating point for the RF transistor when external voltage fluctuates, thus stabilizing the various electrical performance characteristics of the entire RF transistor.

[0003] For power amplifier chips or other microwave integrated chips using heterojunction bicarrier transistor (HBT) technology, fluctuations in the bias voltage will cause significant fluctuations in the static base current provided by the bias circuit.

[0004] In practical systems, many low-power RF amplifier chips, designed to suppress time-domain waveform oscillations, share the same power supply (VCC) and bias voltage (Vbias) for their RF transistors to reduce costs. Furthermore, the internal bias circuit does not use a separate LDO power supply. Under these conditions, when the amplifier uses its internal EN control for rapid switching (on the nanosecond scale), the ICC change slope is significant, causing fluctuations in the VCC voltage (damped oscillations). This, in turn, leads to fluctuations in the bias voltage (Vbias). These Vbias fluctuations alter the operating state of the RF transistors, resulting in RF amplifier gain fluctuations. These fluctuations manifest as synchronous fluctuations in the system's time-domain waveform with VCC, impacting overall system performance and degrading signal communication quality in the milliseconds before switching. The impact is more pronounced for amplifier chips with higher stage counts, higher gain, and larger current requirements. Utility Model Content

[0005] This invention addresses the problem of severe oscillations in the time-domain waveform of an amplifier's radio frequency (RF) signal caused by small fluctuations in external voltage when the amplifier is switched on. It proposes an RF amplifier chip that suppresses these oscillations at the moment of switching on. By setting up a first bias circuit and a second bias circuit, the slope of the conduction current is adjusted according to the input bias voltage. This suppresses time-domain waveform oscillations at the moment the RF amplifier is switched on, maintaining a constant bias current. When there are large fluctuations in the bias voltage, it ensures the stability of the static current at the base of the RF transistor, minimizing the impact of bias voltage fluctuations on the chip's electrical properties.

[0006] The specific implementation details of this utility model are as follows: A radio frequency (RF) amplifier chip for suppressing instantaneous time-domain waveform oscillations upon power-on includes an input matching network, a driver amplifier Q4, an interstage matching network, a final stage amplifier Q8, an output matching network, inductors L1 and L2. The input matching network receives an RF signal at its input terminal and its output terminal is connected to the base of the driver amplifier Q4. The emitter of the driver amplifier Q4 is connected to ground, and its collector is connected to a power supply VCC1 via inductor L1. The input terminal of the interstage matching network is connected between inductor L1 and the collector of the driver amplifier Q4, and its output terminal is connected to the base of the final stage amplifier Q8. The emitter of the final stage amplifier Q8 is connected to ground, and its collector is connected to a power supply VCC2 via inductor L2. The input terminal of the output matching network is connected between inductor L2 and the collector of the final stage amplifier, and its output terminal outputs the amplified RF signal. The chip also includes a first bias circuit and a second bias circuit. The first bias circuit receives a bias voltage at its input terminal and its output terminal is connected between the input matching network and the base of the driver amplifier Q4. The second bias circuit receives a bias voltage at its input terminal and its output terminal is connected between the interstage matching network and the base of the final stage amplifier Q8. The first bias circuit and the second bias circuit are used to adjust the slope of the conduction current according to the input bias voltage, suppress time-domain waveform oscillation at the moment the RF amplifier is turned on, and keep the bias current constant.

[0007] To better realize this utility model, both the first bias circuit and the second bias circuit include a bias unit; The bias unit includes bias transistor Q1, bias transistor Q2, and bias transistor Q3; The base of the bias transistor Q1 is fed with a bias voltage, the emitter of the bias transistor Q1 is connected to the collector of the bias transistor Q2, and the collector of the bias transistor Q1 is connected to the base of the bias transistor Q3. The emitter of the bias transistor Q2 is connected to ground, and the base of the bias transistor Q2 is connected to the collector of the bias transistor Q2 and the emitter of the bias transistor Q1. The emitter of the bias transistor Q3 is connected between the output of the input matching network and the base of the driver amplifier Q4. The base of the bias transistor Q3 is supplied with a bias voltage, and the collector of the bias transistor Q3 is supplied with a bias voltage.

[0008] To better realize this utility model, the bias unit further includes resistor R1, resistor R4, capacitor C1, capacitor C2, and capacitor C3; The input terminal of the resistor R4 is fed with a bias voltage, and the output terminal of the resistor R4 is connected to the base of the bias transistor Q1. One end of the capacitor C1 is connected between the bias voltage and the resistor R4, and the other end is connected to ground. The input terminal of the resistor R1 is fed with a bias voltage, and the output terminal of the resistor R1 is connected between the collector of the bias transistor Q1 and the base of the bias transistor Q3. One end of the capacitor C2 is connected between the bias voltage and the resistor R1, and the other end is connected to ground. One end of the capacitor C3 is connected between the bias voltage and the collector of the bias transistor Q3, and the other end is connected to ground.

[0009] To better realize this utility model, both the first bias circuit and the second bias circuit further include a temperature compensation unit; the temperature compensation unit includes resistor R2, resistor R3, resistor R5, and transistor Q5; The emitter of transistor Q5 is connected to the collector of bias transistor Q3, the base of transistor Q5 is connected to the collector of transistor Q5, and the collector of transistor Q5 is connected between capacitor C3 and the bias voltage. One end of resistor R3 is connected between resistor R4 and the base of bias transistor Q1, and the other end of resistor R3 is connected to resistor R5. One end of resistor R2 is connected between resistor R5 and the collector of bias transistor Q1, and the other end of resistor R2 is connected between resistor R1 and the base of bias transistor Q1.

[0010] To better realize this utility model, the biasing unit further includes a capacitor C4; One end of the capacitor C4 is connected to the base of resistors R1 and R2 and bias transistor Q3, and the other end is connected to ground.

[0011] To better realize this utility model, the resistor R5 is further described as a mesa resistor.

[0012] To better realize this utility model, the radio frequency amplifier chip for suppressing time-domain waveform oscillation further includes resistors R6 and R7; The input terminal of resistor R6 is connected to the output terminal of the first bias unit, and the output terminal of resistor R6 is connected between the input matching network and the base of the driver amplifier Q4. The input terminal of resistor R7 is connected to the output terminal of the second bias unit, and the output terminal of resistor R7 is connected between the interstage matching network and the base of the final stage amplifier Q4.

[0013] This utility model has the following beneficial effects: (1) This utility model significantly improves and enhances the phenomenon of decreased electrical performance of a single microwave integrated chip due to bias voltage fluctuations in heterojunction dual-carrier transistor technology; when the bias voltage fluctuates greatly, it can ensure the stability of the static current of the base of the radio frequency transistor, so that the electrical performance of the chip is not affected by the bias voltage fluctuations to the greatest extent.

[0014] (2) The bias circuit structure of this utility model can be achieved by making a small modification to the bias architecture of the original current mirror, and will not have an additional impact on other electrical performance indicators of the chip. Attached Figure Description

[0015] Figure 1 This is a circuit diagram for peripheral use in a conventional amplification system.

[0016] Figure 2 This is a time-domain plot of a traditional amplifier at the moment of RF turn-on.

[0017] Figure 3 This is an example diagram of the bias circuit and application layout of a traditional current mirror structure.

[0018] Figure 4 Example diagram of the bias circuit structure and application layout provided by this utility model.

[0019] Figure 5 This is a schematic diagram showing the simulation results of bias current versus bias voltage.

[0020] Figure 6 This is a schematic diagram showing the simulation results of the collector current of an RF transistor as a function of bias voltage. Detailed Implementation

[0021] To more clearly illustrate the technical solutions of the embodiments of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of this utility model, not all embodiments, and therefore should not be regarded as a limitation on the scope of protection. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0022] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0023] as follows Figure 1 As shown, this is an example of a typical system-level peripheral circuit for driving an amplifier. The amplifier's Vbias (bias power supply), VCC1 (first-stage amplifier power supply), and VCC2 (second-stage amplifier power supply) are connected to the same power supply VDD inside the system.

[0024] At this point, the RF amplifier can be understood as a load on the power supply VDD. When VEN switches rapidly, the load's current draw changes instantaneously (the RF amplifier's switching time is on the order of nanoseconds). This will cause a change in the power supply output VDD, i.e. Figure 2 The blue curve represents the voltage, which momentarily deviates from the set value. At this time, the internal voltage Vbias of the chip fluctuates with VDD. Figure 3 This is a bias circuit based on a classic current mirror architecture. According to the basic principle of a current mirror, currents I1 and I2 are of the same magnitude (assuming transistors Q1, Q2, and Q3 have the same size). The base voltage V of transistor Q3 can be changed by adjusting the resistor R1, thereby adjusting the bias current I1 and thus changing the static bias of RF transistor Q4. However, when the bias voltage (Vbias) fluctuates, the base voltage V of transistor Q3 in this circuit architecture will also fluctuate, causing significant fluctuations in the bias current I1. Since heterojunction bicarrier transistors are mainly controlled by the base bias current to turn on or off, even a small change in bias current I1 will cause a significant change in the operating state of RF transistor Q4, and similarly, it will also affect the operating state of Q8. For example... Figure 5 As shown, the curves of the static bias current of the chip driver stage and the final stage changing with the Vbias voltage can be observed, resulting in changes in the bias current. Figure 6 As shown, the RF amplifier gain varies with Vbias voltage. Therefore, when the amplifier switches rapidly, VDD changes, causing the RF amplifier's time-domain waveform to resemble... Figure 2 The blue curve fluctuates.

[0025] Example 1: This embodiment proposes a radio frequency amplifier chip that suppresses time-domain waveform oscillations at the moment of power-on, such as... Figure 4As shown, the system includes an input matching network, a driver amplifier Q4, an interstage matching network, a final stage amplifier Q8, an output matching network, inductors L1 and L2. The input matching network receives a radio frequency (RF) signal at its input terminal and its output terminal is connected to the base of the driver amplifier Q4. The emitter of the driver amplifier Q4 is connected to ground, and its collector is connected to power supply VCC1 via inductor L1. The input terminal of the interstage matching network is connected between inductor L1 and the collector of the driver amplifier Q4, and its output terminal is connected to the base of the final stage amplifier Q8. The emitter of the final stage amplifier Q8 is connected to ground, and its collector is connected to power supply VCC2 via inductor L2. The input terminal of the output matching network is connected between inductor L2 and the collector of the final stage amplifier, and its output terminal outputs the amplified RF signal. The system also includes a first bias circuit and a second bias circuit. The first bias circuit receives a bias voltage at its input terminal and its output terminal is connected between the input matching network and the base of the driver amplifier Q4. The second bias circuit receives a bias voltage at its input terminal and its output terminal is connected between the interstage matching network and the base of the final stage amplifier Q8. The first bias circuit and the second bias circuit are used to adjust the slope of the conduction current according to the input bias voltage, suppress time-domain waveform oscillation at the moment the RF amplifier is turned on, and keep the bias current constant.

[0026] Furthermore, the RF amplifier chip for suppressing time-domain waveform oscillations also includes resistors R6 and R7; The input terminal of resistor R6 is connected to the output terminal of the first bias unit, and the output terminal of resistor R6 is connected between the input matching network and the base of the driver amplifier Q4. The input terminal of resistor R7 is connected to the output terminal of the second bias unit, and the output terminal of resistor R7 is connected between the interstage matching network and the base of the final stage amplifier Q4.

[0027] Working principle: The bias architecture and application proposed in this embodiment can save the use of LDOs in the system or amplification module and achieve the same effect. This embodiment sets up a first bias circuit and a second bias circuit, and adjusts the slope of the conduction current according to the input bias voltage. It suppresses time-domain waveform oscillation at the moment the RF amplifier is turned on and keeps the bias current constant. When the bias voltage fluctuates greatly, it can ensure the stability of the static current of the RF transistor base, so that the electrical properties of the chip are not affected by the bias voltage fluctuation to the greatest extent.

[0028] Example 2: This embodiment is based on the above embodiment 1, such as... Figure 4As shown, the specific structure of the bias circuit is described in detail with reference to a specific embodiment.

[0029] Both the first bias circuit and the second bias circuit include a bias unit; The bias unit includes bias transistor Q1, bias transistor Q2, and bias transistor Q3; The base of the bias transistor Q1 is fed with a bias voltage, the emitter of the bias transistor Q1 is connected to the collector of the bias transistor Q2, and the collector of the bias transistor Q1 is connected to the base of the bias transistor Q3. The emitter of the bias transistor Q2 is connected to ground, and the base of the bias transistor Q2 is connected to the collector of the bias transistor Q2 and the emitter of the bias transistor Q1. The emitter of the bias transistor Q3 is connected between the output of the input matching network and the base of the driver amplifier Q4. The base of the bias transistor Q3 is supplied with a bias voltage, and the collector of the bias transistor Q3 is supplied with a bias voltage.

[0030] Furthermore, the bias unit also includes resistors R1 and R4, and capacitors C1, C2, and C3; The input terminal of the resistor R4 is fed with a bias voltage, and the output terminal of the resistor R4 is connected to the base of the bias transistor Q1. One end of the capacitor C1 is connected between the bias voltage and the resistor R4, and the other end is connected to ground. The input terminal of the resistor R1 is fed with a bias voltage, and the output terminal of the resistor R1 is connected between the collector of the bias transistor Q1 and the base of the bias transistor Q3. One end of the capacitor C2 is connected between the bias voltage and the resistor R1, and the other end is connected to ground. One end of the capacitor C3 is connected between the bias voltage and the collector of the bias transistor Q3, and the other end is connected to ground.

[0031] Furthermore, the bias unit also includes a capacitor C4; One end of the capacitor C4 is connected to the base of resistors R1 and R2 and bias transistor Q3, and the other end is connected to ground.

[0032] Working principle: In this circuit architecture, the base voltage of bias transistor Q1 increases with increasing bias voltage and decreases with decreasing bias voltage, thus changing its control current. As the bias voltage increases, the base current of bias transistor Q1 changes with a positive slope, enhancing its conduction capability, and the conduction current I2 also changes with a positive slope. At the same time, the base voltage V of bias transistor Q3 also changes with a positive slope as the bias voltage fluctuates, ensuring that the base current I of control bias transistor Q3 remains constant despite voltage fluctuations. Therefore, the base current of RF transistor Q4 does not change significantly with bias voltage fluctuations, preventing the chip's electrical performance from being degraded or altered by bias voltage fluctuations, and maintaining its ability to meet system requirements.

[0033] Figure 5 The simulation results show the bias current I1 fluctuating with the bias voltage. Figure 6 The figure shows the simulation results of the collector current of RF transistor Q4 fluctuating with bias voltage. The blue curve represents the simulation results of the traditional current mirror architecture. As can be observed from the figure, the bias current I1 changes with a large positive slope as the bias voltage increases. Since the heterojunction bicarrier transistor controls its collector current (Ids) through the base current (Ib), the collector current (ICC) of RF transistor Q4 also changes with a large positive slope as the bias current I1 increases. Figure 4 As shown by the blue curve.

[0034] The bias architecture proposed in this embodiment can effectively suppress the slope change of the bias current with voltage fluctuation, such as... Figure 5 As shown by the red curve in the diagram, this ensures that the collector current of the RF transistor does not change with fluctuations in bias voltage, thereby minimizing the impact of bias voltage fluctuations on the chip's electrical performance. Meanwhile... Figure 6 The curve shows the variation of ICC current with bias voltage Vbias from -40° to 105°, which also demonstrates the applicability of this circuit in various temperature ranges.

[0035] The other parts of this embodiment are the same as those in Embodiment 1 above, so they will not be described again.

[0036] Example 3: Based on any one of Embodiments 1-2 above, this embodiment further includes a temperature compensation unit for both the first bias circuit and the second bias circuit; the temperature compensation unit includes resistor R2, resistor R3, resistor R5, and transistor Q5; The emitter of transistor Q5 is connected to the collector of bias transistor Q3, the base of transistor Q5 is connected to the collector of transistor Q5, and the collector of transistor Q5 is connected between capacitor C3 and the bias voltage. One end of resistor R3 is connected between resistor R4 and the base of bias transistor Q1, and the other end of resistor R3 is connected to resistor R5. One end of resistor R2 is connected between resistor R5 and the collector of bias transistor Q1, and the other end of resistor R2 is connected between resistor R1 and the base of bias transistor Q1.

[0037] Furthermore, the resistor R5 is a mesa resistor.

[0038] Working principle: In this embodiment, resistors R2, R3, and R5 are used to adjust the slope of the conduction current I. At the same time, R5 is a mesa resistor, and its resistance value has a positive slope with temperature. R5 can provide temperature compensation within the operating range of -40° to +105°, ensuring that the bias current of Vbais voltage fluctuation will not be affected at various temperatures.

[0039] The other parts of this embodiment are the same as any one of the above embodiments 1-2, so they will not be described again.

[0040] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present utility model shall fall within the protection scope of the present utility model.

Claims

1. A radio frequency amplifier chip for suppressing instantaneous time-domain waveform oscillations upon power-on, comprising an input matching network, a driver amplifier Q4, an interstage matching network, a final stage amplifier Q8, an output matching network, an inductor L1, and an inductor L2; the input terminal of the input matching network receives a radio frequency signal, and its output terminal is connected to the base of the driver amplifier Q4; the emitter of the driver amplifier Q4 is connected to ground, and the collector of the driver amplifier Q4 is connected to a power supply VCC1 through the inductor L1; the input terminal of the interstage matching network is connected between the inductor L1 and the collector of the driver amplifier Q4, and the output terminal of the interstage matching network is connected to the base of the final stage amplifier Q8; the emitter of the final stage amplifier Q8 is connected to ground, and the collector of the final stage amplifier Q8 is connected to a power supply VCC2 through the inductor L2; the input terminal of the output matching network is connected between the inductor L2 and the collector of the final stage amplifier, and the output terminal of the output matching network outputs an amplified radio frequency signal; characterized in that... It also includes a first bias circuit and a second bias circuit; The input terminal of the first bias circuit receives a bias voltage, and the output terminal is connected between the input matching network and the base of the driver amplifier Q4. The second bias circuit receives a bias voltage at its input terminal and its output terminal is connected between the interstage matching network and the base of the final stage amplifier Q8. The first bias circuit and the second bias circuit are used to adjust the slope of the conduction current according to the input bias voltage, suppress time-domain waveform oscillation at the moment the RF amplifier is turned on, and keep the bias current constant.

2. The radio frequency amplifier chip of claim 1, wherein, Both the first bias circuit and the second bias circuit include a bias unit; The bias unit includes bias transistor Q1, bias transistor Q2, and bias transistor Q3; The base of the bias transistor Q1 is fed with a bias voltage, the emitter of the bias transistor Q1 is connected to the collector of the bias transistor Q2, and the collector of the bias transistor Q1 is connected to the base of the bias transistor Q3. The emitter of the bias transistor Q2 is connected to ground, and the base of the bias transistor Q2 is connected to the collector of the bias transistor Q2 and the emitter of the bias transistor Q1. The emitter of the bias transistor Q3 is connected between the output of the input matching network and the base of the driver amplifier Q4. The base of the bias transistor Q3 is supplied with a bias voltage, and the collector of the bias transistor Q3 is supplied with a bias voltage.

3. The radio frequency amplifier chip of claim 2, wherein, The bias unit also includes resistor R1, resistor R4, capacitor C1, capacitor C2, and capacitor C3; The input terminal of the resistor R4 is fed with a bias voltage, and the output terminal of the resistor R4 is connected to the base of the bias transistor Q1. One end of the capacitor C1 is connected between the bias voltage and the resistor R4, and the other end is connected to ground. The input terminal of the resistor R1 is fed with a bias voltage, and the output terminal of the resistor R1 is connected between the collector of the bias transistor Q1 and the base of the bias transistor Q3. One end of the capacitor C2 is connected between the bias voltage and the resistor R1, and the other end is connected to ground. One end of the capacitor C3 is connected between the bias voltage and the collector of the bias transistor Q3, and the other end is connected to ground.

4. The radio frequency amplifier chip of claim 3, wherein, Both the first bias circuit and the second bias circuit further include a temperature compensation unit; the temperature compensation unit includes resistors R2, R3, and R5, and transistor Q5; The emitter of transistor Q5 is connected to the collector of bias transistor Q3, the base of transistor Q5 is connected to the collector of transistor Q5, and the collector of transistor Q5 is connected between capacitor C3 and the bias voltage. One end of resistor R3 is connected between resistor R4 and the base of bias transistor Q1, and the other end of resistor R3 is connected to resistor R5. One end of resistor R2 is connected between resistor R5 and the collector of bias transistor Q1, and the other end of resistor R2 is connected between resistor R1 and the base of bias transistor Q1.

5. The radio frequency amplifier chip of claim 4, wherein, The biasing unit also includes a capacitor C4; One end of the capacitor C4 is connected to the base of resistors R1 and R2 and bias transistor Q3, and the other end is connected to ground.

6. The radio frequency amplifier chip of claim 4, wherein, The resistor R5 is a mesa resistor.

7. The radio frequency amplifier chip of claim 1, wherein, The radio frequency amplifier chip for suppressing time-domain waveform oscillations also includes resistors R6 and R7; The input terminal of resistor R6 is connected to the output terminal of the first bias unit, and the output terminal of resistor R6 is connected between the input matching network and the base of the driver amplifier Q4. The input terminal of resistor R7 is connected to the output terminal of the second bias unit, and the output terminal of resistor R7 is connected between the interstage matching network and the base of the final stage amplifier Q4.

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