An edge filtering circuit

Abstract

This utility model relates to the field of signal filtering technology and discloses an edge filtering circuit, including an inverter INV10, a switch P10, a switch N10, a capacitor C10, a comparator CMP10, and an AND gate AND10. In practical use, the edge filtering single channel of this utility model can control the switch P10 or the switch P20 to turn on based on the signal to be filtered, so that the bias current I2 charges the capacitor. When the voltage on the capacitor is greater than the reference voltage VREF, the output of the comparator flips, thereby achieving filtering. The filtering time is the charging time of the capacitor. Since the charging time of the capacitor and the magnitude of the bias current I2 are related to the magnitude of the reference voltage VREF, the filtering time can be adjusted by adjusting the magnitude of the bias current I2 and the magnitude of the reference voltage VREF.

Description

Technical Field

[0001] This utility model relates to the field of signal filtering technology, specifically to an edge filtering circuit. Background Technology

[0002] During chip operation, signal glitches can occur due to factors such as power supply fluctuations and electromagnetic interference in the environment. Although these glitches are very short, often ranging from tens of picoseconds to tens of nanoseconds, failure to address them can lead to timing errors in the chip's CPU section, resulting in logical calculation errors. Furthermore, glitches can be either incorrect rising or falling edges.

[0003] To avoid the impact of glitches on the chip, analog filters are often set up inside the chip to filter glitches. Among them, digital filters use high-frequency clock signals for filtering. The advantage of this structure is that the filtering time is fixed, which is generally an integer period of the high-frequency clock. The disadvantage is that it requires a very high-speed clock signal, and the filtering time must be adjusted to be a multiple of the period of the high-speed clock signal, making the filtering time setting inflexible. Utility Model Content

[0004] In view of the shortcomings of the background technology, the present invention provides an edge filtering circuit. The technical problem to be solved is that the existing analog filters do not have flexible filtering time settings and need to be a multiple of the clock signal.

[0005] To solve the above technical problems, in the first aspect, this utility model provides the following technical solution: an edge filtering circuit, including an inverter INV10, a switching transistor P10, a switching transistor N10, a capacitor C10, a comparator CMP10, and an AND gate AND10; The input terminal of the inverter INV10 is the signal input terminal, used to input the signal. The output terminal of the inverter INV10 is electrically connected to the control terminals of the switching transistors P10 and N10, respectively. The input terminal of the switching transistor P10 is used to input the bias current I2. The output terminal of the switching transistor P10 is electrically connected to the input terminal of the switching transistor N10, one end of the capacitor C10, and the positive input terminal of the comparator CMP10, respectively. The other end of the capacitor C10 and the output terminal of the switching transistor N10 are both grounded. The negative input terminal of the comparator CMP10 is used to input the reference voltage VREF. The output terminal of the comparator CMP10 is electrically connected to one input terminal of the AND gate AND10, and the other input terminal of the AND gate AND10 is electrically connected to the signal input terminal. The output terminal of the AND gate AND10 outputs the first filtered signal.

[0006] In one embodiment of the first aspect, the control terminal of the switching transistor P10 is turned on when a low-level control signal is input and turned off when a high-level control signal is input. The control terminal of the switching transistor N10 is turned on when a high-level control signal is input and turned off when a low-level control signal is input.

[0007] In one embodiment of the first aspect, the switch P10 is a PMOS transistor, the source of the PMOS transistor is the input terminal of the switch P10, the gate of the PMOS transistor is the control terminal of the switch P10, and the drain of the PMOS transistor is the output terminal of the switch P10. The switch N10 is an NMOS transistor. The drain of the NMOS transistor is the input terminal of the switch N10, the gate of the NMOS transistor is the control terminal of the switch N10, and the source of the NMOS transistor is the output terminal of the switch N10.

[0008] Secondly, this utility model also provides an edge filtering circuit with another structure, including a switching transistor P20, a switching transistor N20, a capacitor C20, a comparator CMP20, an inverter INV20, and an OR gate OR20. The control terminal of switch P20 is electrically connected to the control terminal of switch N20, serving as the signal input terminal. The input terminal of switch P20 is used to input the bias current I2. The output terminal of switch P20 is electrically connected to the input terminal of switch N20, one end of capacitor C20, and the positive input terminal of comparator CMP20. The output terminal of switch N20 and the other end of capacitor C20 are both grounded. The negative input terminal of comparator CMP20 is used to input the reference voltage VREF. The output terminal of comparator CMP20 is electrically connected to the input terminal of inverter IN20. The output terminal of inverter INV20 is electrically connected to one input terminal of OR gate OR20. The other input terminal of OR gate OR20 is electrically connected to the signal input terminal. The output terminal of OR gate OR20 outputs the second filtered signal.

[0009] In one embodiment of the second aspect, the control terminal of the switching transistor P20 is turned on when a low-level control signal is input and turned off when a high-level control signal is input. The control terminal of the switching transistor N20 is turned on when a high-level control signal is input and turned off when a low-level control signal is input.

[0010] In one embodiment of the second aspect, the switch P20 is a PMOS transistor, the source of the PMOS transistor is the input terminal of the switch P20, the gate of the PMOS transistor is the control terminal of the switch P20, and the drain of the PMOS transistor is the output terminal of the switch P20. The switch N20 is an NMOS transistor. The drain of the NMOS transistor is the input terminal of the switch N20, the gate of the NMOS transistor is the control terminal of the switch N20, and the source of the NMOS transistor is the output terminal of the switch N20.

[0011] In one embodiment of the first or second aspect, the present invention further includes a reference unit for generating the reference voltage VREF and the bias current I2.

[0012] In one embodiment of the first or second aspect, the reference unit includes a voltage divider circuit, an operational amplifier OP, a resistor R3, a MOSFET P1, and a MOSFET P2; The input terminal of the voltage divider circuit, the source of MOSFET P1, and the source of MOSFET P2 are used to connect to the power supply voltage VDD. One voltage divider node of the voltage divider circuit is electrically connected to the positive input terminal of the operational amplifier OP. The output terminal of the operational amplifier OP is electrically connected to the gate of MOSFET P1, the drain of MOSFET P1, and the gate of MOSFET P2, respectively. The drain of MOSFET P1 is grounded through resistor R3 and electrically connected to the negative input terminal of the operational amplifier OP. The voltage across resistor R3 is the reference voltage VREF. The drain of MOSFET P2 is used to output the bias current I2.

[0013] In one embodiment of the first or second aspect, the voltage divider circuit includes resistors R1 and R2, one end of resistor R1 is used to connect to the power supply voltage VDD, the other end of resistor R1 is the voltage divider node, and is grounded through resistor R2.

[0014] In one embodiment of the first or second aspect, the resistance value of resistor R1 is the same as that of resistor R2.

[0015] The beneficial effects of this utility model compared with the prior art are as follows: The edge filtering single channel of this utility model can control the switching transistor P10 or P20 to turn on based on the signal to be filtered, so that the bias current I2 charges the capacitor. After the voltage on the capacitor is greater than the reference voltage VREF, the output of the comparator flips, thereby realizing filtering. The filtering time is the charging time of the capacitor. Since the charging time of the capacitor and the magnitude of the bias current I2 are related to the magnitude of the reference voltage VREF, the filtering time can be adjusted by adjusting the magnitude of the bias current I2 and the magnitude of the reference voltage VREF. Attached Figure Description

[0016] Figure 1 This is a circuit diagram of the edge filtering circuit in Example 1; Figure 2 for Figure 1 The circuit shown has relevant waveforms when in use. Figure 3 for Figure 1 The circuit shown presents the relevant waveforms when filtering rising edge glitches. Figure 4 This is a circuit diagram of the reference unit in the embodiment; Figure 5This is a circuit diagram of the edge filtering circuit in Example 2; Figure 6 for Figure 5 The circuit shown has relevant waveforms when in use. Figure 7 for Figure 5 The circuit shown is used for filtering rising edge glitches. Detailed Implementation

[0017] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the present invention, and therefore only show the components relevant to the present invention.

[0018] Example 1 like Figure 1 As shown, the edge filtering circuit provided in this embodiment includes an inverter INV10, a switch P10, a switch N10, a capacitor C10, a comparator CMP10, and an AND gate AND10. The input terminal of inverter INV10 is the signal input terminal, used to input the signal IN. The output terminal of inverter INV10 is electrically connected to the control terminals of switching transistors P10 and N10, respectively. The input terminal of switching transistor P10 is used to input the bias current I2. The output terminal of switching transistor P10 is electrically connected to the input terminal of switching transistor N10, one end of capacitor C10, and the positive input terminal of comparator CMP10, respectively. The other end of capacitor C10 and the output terminal of switching transistor N10 are both grounded. The negative input terminal of comparator CMP10 is used to input the reference voltage VREF. The output terminal of comparator CMP10 is electrically connected to one input terminal of AND gate AND10. The other input terminal of AND gate AND10 is electrically connected to the signal input terminal. The output terminal of AND gate AND10 outputs the first filtered signal OUT1.

[0019] In practical use, the edge filter in this embodiment can control the switch P10 to turn on based on the signal to be filtered, thereby charging the capacitor C10 with the bias current I2. When the voltage on the capacitor C10 is greater than the reference voltage VREF, the output of the comparator CMP10 flips, thus achieving filtering. The filtering time is the charging time of the capacitor C10. Since the charging time of the capacitor C10 and the magnitude of the bias current I2 are related to the magnitude of the reference voltage VREF, the filtering time can be adjusted by adjusting the magnitude of the bias current I2 and the magnitude of the reference voltage VREF.

[0020] Specifically, in this embodiment, the control terminal of the switching transistor P10 is turned on when a low-level control signal is input and turned off when a high-level control signal is input. The control terminal of the switching transistor N10 is turned on when a high-level control signal is input and turned off when a low-level control signal is input.

[0021] Specifically, in this embodiment, in Figure 1 In the diagram, switch P10 is a PMOS transistor. The source of the PMOS transistor is the input terminal of switch P10, the gate of the PMOS transistor is the control terminal of switch P10, and the drain of the PMOS transistor is the output terminal of switch P10. The switch N10 is an NMOS transistor. The drain of the NMOS transistor is the input terminal of the switch N10, the gate of the NMOS transistor is the control terminal of the switch N10, and the source of the NMOS transistor is the output terminal of the switch N10.

[0022] In this embodiment, the edge filtering circuit is used to filter the rising edge glitches. The relevant timing diagram is as follows: Figure 2 As shown, when a rising edge arrives on signal IN, signal A1 goes low. At this time, the bias current I2 charges capacitor C10, and the voltage of signal A2 begins to rise. When the voltage of signal A2 rises to the reference voltage VREF, signal A3 changes from 0 to a high level. Since signal IN is already at a high level, the first filter signal OUT1 is also at a high level. If a falling edge arrives on signal IN, the first filter signal OUT1 will be directly pulled low by signal IN without any delay.

[0023] When a glitch occurs at the IN signal, if the glitch width is less than the first preset time T1 (the filtering time), it will be directly filtered out. The relevant timing diagram is as follows: Figure 7 As shown, from Figure 2 It can be seen that the first two burrs with a width less than T1 and the last three burrs with a width less than T1 are all filtered out.

[0024] The formula for calculating T1 is as follows: T1 = C10 * VREF / I2. The value of T1 can be adjusted by changing the values ​​of capacitor C10, VREF, and I2, thereby adjusting the filtering time.

[0025] In this embodiment, the present invention also includes a reference unit, the circuit of which is as follows: Figure 4 As shown, it includes a voltage divider circuit, operational amplifier OP, resistor R3, MOSFET P1, and MOSFET P2; The input terminal of the voltage divider circuit, the source of MOSFET P1, and the source of MOSFET P2 are used to connect to the power supply voltage VDD. One voltage divider node of the voltage divider circuit is electrically connected to the positive input terminal of the operational amplifier OP. The output terminal of the operational amplifier OP is electrically connected to the gate of MOSFET P1, the drain of MOSFET P1, and the gate of MOSFET P2, respectively. The drain of MOSFET P1 is grounded through resistor R3 and electrically connected to the negative input terminal of the operational amplifier OP. The voltage across resistor R3 is the reference voltage VREF. The drain of MOSFET P2 is used to output the bias current I2.

[0026] The voltage divider circuit includes resistors R1 and R2. One end of resistor R1 is connected to the power supply voltage VDD, and the other end of resistor R1 is the voltage divider node, which is grounded through resistor R2. Furthermore, the resistance values ​​of resistors R1 and R2 can be the same.

[0027] for Figure 4 In the circuit shown, the operational amplifier OP uses a negative feedback connection. At this time, VREF and V1 are the same, and the bias current I1 is VREF / R3. MOSFETs P1 and P2 are connected as a current mirror structure. When MOSFETs P1 and P2 are the same, the bias currents I1 and I2 are also the same, which are VREF / R3 respectively. Substituting this calculation formula into the calculation formula for the first preset time T1, we can get T1=R3*C10. From this formula, we can see that the filtering time is independent of the reference voltage and only related to the two parameters R3 and C10. These three parameters are the designed resistance and capacitance values, which have a very weak correlation with the power supply and temperature, so the filtering time will be very stable.

[0028] Example 2 like Figure 5 As shown, this embodiment provides an edge filtering circuit with another structure, including a switch P20, a switch N20, a capacitor C20, a comparator CMP20, an inverter INV20, and an OR gate OR20; The control terminal of switch P20 is electrically connected to the control terminal of switch N20, serving as the signal input terminal. The input terminal of switch P20 is used to input the bias current I2. The output terminal of switch P20 is electrically connected to the input terminal of switch N20, one end of capacitor C20, and the positive input terminal of comparator CMP20. The output terminal of switch N20 and the other end of capacitor C20 are both grounded. The negative input terminal of comparator CMP20 is used to input the reference voltage VREF. The output terminal of comparator CMP20 is electrically connected to the input terminal of inverter IN20. The output terminal of inverter INV20 is electrically connected to one input terminal of OR gate OR20. The other input terminal of OR gate OR20 is electrically connected to the signal input terminal. The output terminal of OR gate OR20 outputs the second filtered signal OUT2.

[0029] In practical use, the edge filter in this embodiment can control the switch P20 to turn on based on the signal to be filtered, thereby charging the capacitor C20 with the bias current I2. When the voltage on the capacitor C20 is greater than the reference voltage VREF, the output of the comparator CMP20 flips, thus achieving filtering. The filtering time is the charging time of the capacitor C20. Since the charging time of the capacitor C20 and the magnitude of the bias current I2 are related to the magnitude of the reference voltage VREF, the filtering time can be adjusted by adjusting the magnitude of the bias current I2 and the magnitude of the reference voltage VREF.

[0030] Specifically, in this embodiment, the control terminal of the switching transistor P20 is turned on when a low-level control signal is input and turned off when a high-level control signal is input. The control terminal of the switching transistor N20 is turned on when a high-level control signal is input and turned off when a low-level control signal is input.

[0031] Specifically, in this embodiment, in Figure 5 In this circuit, switch P20 is a PMOS transistor. The source of the PMOS transistor is the input terminal of switch P20, the gate of the PMOS transistor is the control terminal of switch P20, and the drain of the PMOS transistor is the output terminal of switch P20. The switch N20 is an NMOS transistor. The drain of the NMOS transistor is the input terminal of the switch N20, the gate of the NMOS transistor is the control terminal of the switch N20, and the source of the NMOS transistor is the output terminal of the switch N20.

[0032] In this embodiment, the edge filtering circuit is used to filter the falling edge glitches. The relevant timing diagram for processing the signal IN to be filtered is as follows: Figure 6 As shown, from Figure 6 As can be seen, when a falling edge arrives with the IN signal, the voltage of signal A4 slowly rises. During this time, the bias current I2 charges capacitor C20. When signal A4 rises above the second reference voltage, signal A5 changes from a low level to a high level, and signal A6 changes from a high level to a low level. The second filter signal OUT2 also changes from a high level to a low level. When a rising edge arrives with the IN signal, the second filter signal OUT2 directly follows the IN signal to a high level, without filtering. Therefore, this circuit only filters falling edges.

[0033] When a falling edge glitch occurs at the IN signal, if the glitch width is less than the second preset time T2 (the filtering time), it will be directly filtered out. The relevant timing diagram is as follows: Figure 7 As shown, from Figure 7 It can be seen that the first two burrs with a width less than T2 and the last three burrs with a width less than T2 are all filtered out.

[0034] The formula for calculating T2 is as follows: T2 = C20 * VREF / I2. The value of T2 can be adjusted by changing the values ​​of capacitor C20, VREF, and I2.

[0035] In this embodiment, the present invention also includes a reference unit, the circuit of which is as follows: Figure 4 As shown, it includes a voltage divider circuit, operational amplifier OP, resistor R3, MOSFET P1, and MOSFET P2; The input terminal of the voltage divider circuit, the source of MOSFET P1, and the source of MOSFET P2 are used to connect to the power supply voltage VDD. One voltage divider node of the voltage divider circuit is electrically connected to the positive input terminal of the operational amplifier OP. The output terminal of the operational amplifier OP is electrically connected to the gate of MOSFET P1, the drain of MOSFET P1, and the gate of MOSFET P2, respectively. The drain of MOSFET P1 is grounded through resistor R3 and electrically connected to the negative input terminal of the operational amplifier OP. The voltage across resistor R3 is the reference voltage VREF. The drain of MOSFET P2 is used to output the bias current I2.

[0036] The voltage divider circuit includes resistors R1 and R2. One end of resistor R1 is connected to the power supply voltage VDD, and the other end of resistor R1 is the voltage divider node, which is grounded through resistor R2. Furthermore, the resistance values ​​of resistors R1 and R2 can be the same.

[0037] for Figure 4 In the circuit shown, the operational amplifier OP uses a negative feedback connection, where VREF and V1 are the same, and the bias current I1 is VREF / R3. MOSFETs P1 and P2 are connected as a current mirror structure. When MOSFETs P1 and P2 are the same, the bias currents I1 and I2 are also the same, which are VREF / R3 respectively. Substituting this formula into the formula for calculating the first preset time T1, we get T2 = R3 * C20. From this formula, we can see that the filtering time is independent of the reference voltage, and only depends on the two parameters R3 and C20. These two parameters are designed resistor and capacitor values, which have a very weak correlation with the power supply and temperature. Therefore, the filtering time will be very stable, and adjusting the size of T2 does not involve intermediate parameters such as voltage and current, making the adjustment simple and clear.

[0038] Based on the above description and inspired by this utility model, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A edge filtering circuit, characterized by, It includes inverter INV10, switching transistor P10, switching transistor N10, capacitor C10, comparator CMP10, and AND gate AND10; The input terminal of the inverter INV10 is the signal input terminal, used to input the signal. The output terminal of the inverter INV10 is electrically connected to the control terminals of the switching transistors P10 and N10, respectively. The input terminal of the switching transistor P10 is used to input the bias current I2. The output terminal of the switching transistor P10 is electrically connected to the input terminal of the switching transistor N10, one end of the capacitor C10, and the positive input terminal of the comparator CMP10, respectively. The other end of the capacitor C10 and the output terminal of the switching transistor N10 are both grounded. The negative input terminal of the comparator CMP10 is used to input the reference voltage VREF. The output terminal of the comparator CMP10 is electrically connected to one input terminal of the AND gate AND10, and the other input terminal of the AND gate AND10 is electrically connected to the signal input terminal. The output terminal of the AND gate AND10 outputs the first filtered signal.

2. A kind of edge filtering circuit according to claim 1, with, The control terminal of the switching transistor P10 is turned on when a low-level control signal is input and turned off when a high-level control signal is input. The control terminal of the switching transistor N10 is turned on when a high-level control signal is input and turned off when a low-level control signal is input.

3. A kind of edge filtering circuit according to claim 2, with, The switch P10 is a PMOS transistor. The source of the PMOS transistor is the input terminal of the switch P10, the gate of the PMOS transistor is the control terminal of the switch P10, and the drain of the PMOS transistor is the output terminal of the switch P10. The switch N10 is an NMOS transistor. The drain of the NMOS transistor is the input terminal of the switch N10, the gate of the NMOS transistor is the control terminal of the switch N10, and the source of the NMOS transistor is the output terminal of the switch N10.

4. An edge filtering circuit, characterized by, This includes switching transistor P20, switching transistor N20, capacitor C20, comparator CMP20, inverter INV20, and OR gate OR20; The control terminal of switch P20 is electrically connected to the control terminal of switch N20, serving as the signal input terminal. The input terminal of switch P20 is used to input the bias current I2. The output terminal of switch P20 is electrically connected to the input terminal of switch N20, one end of capacitor C20, and the positive input terminal of comparator CMP20. The output terminal of switch N20 and the other end of capacitor C20 are both grounded. The negative input terminal of comparator CMP20 is used to input the reference voltage VREF. The output terminal of comparator CMP20 is electrically connected to the input terminal of inverter IN20. The output terminal of inverter INV20 is electrically connected to one input terminal of OR gate OR20. The other input terminal of OR gate OR20 is electrically connected to the signal input terminal. The output terminal of OR gate OR20 outputs the second filtered signal.

5. A kind of edge filtering circuit according to claim 4, with, The control terminal of the switching transistor P20 is turned on when a low-level control signal is input and turned off when a high-level control signal is input. The control terminal of the switching transistor N20 is turned on when a high-level control signal is input and turned off when a low-level control signal is input.

6. A kind of edge filtering circuit according to claim 5, with, The switch P20 is a PMOS transistor. The source of the PMOS transistor is the input terminal of the switch P20, the gate of the PMOS transistor is the control terminal of the switch P20, and the drain of the PMOS transistor is the output terminal of the switch P20. The switch N20 is an NMOS transistor. The drain of the NMOS transistor is the input terminal of the switch N20, the gate of the NMOS transistor is the control terminal of the switch N20, and the source of the NMOS transistor is the output terminal of the switch N20.

7. An edge filter circuit according to any one of claims 1-6, characterized in that It also includes a reference unit for generating the reference voltage VREF and the bias current I2.

8. The edge filtering circuit according to claim 7, characterized in that, The reference unit includes a voltage divider circuit, an operational amplifier OP, a resistor R3, a MOSFET P1, and a MOSFET P2; The input terminal of the voltage divider circuit, the source of MOSFET P1, and the source of MOSFET P2 are used to connect to the power supply voltage VDD. One voltage divider node of the voltage divider circuit is electrically connected to the positive input terminal of the operational amplifier OP. The output terminal of the operational amplifier OP is electrically connected to the gate of MOSFET P1, the drain of MOSFET P1, and the gate of MOSFET P2, respectively. The drain of MOSFET P1 is grounded through resistor R3 and electrically connected to the negative input terminal of the operational amplifier OP. The voltage across resistor R3 is the reference voltage VREF. The drain of MOSFET P2 is used to output the bias current I2.

9. A kind of edge filtering circuit according to claim 8, with, The voltage divider circuit includes resistors R1 and R2. One end of resistor R1 is used to connect to the power supply voltage VDD, and the other end of resistor R1 is the voltage divider node, and is grounded through resistor R2.

10. A kind of edge filtering circuit according to claim 9, wherein, The resistance value of resistor R1 is the same as that of resistor R2.

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