A simple and effective PWM generation circuit

Abstract

This application relates to the field of electronic circuit technology, and provides a simple and effective PWM generation circuit. The circuit includes: a set counter, whose input terminal receives a first control signal to generate a set pulse when the count overflows; a clear counter, whose input terminal receives a second control signal to generate a clear pulse when the count overflows; a first delay module, connected to the output terminal of the set counter, for delaying the set pulse by one clock cycle; a second delay module, connected to the output terminal of the clear counter, for delaying the clear pulse by one clock cycle; and an output module, whose input terminals are respectively connected to the output terminals of the set counter, the clear counter, the first delay module, and the second delay module, for generating a PWM waveform based on the timing relationship of the four pulse signals. This application uses a configurable counter combination to replace the traditional complex architecture, reducing design complexity and maintenance difficulty.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to a simple and effective PWM generation circuit. Background Technology

[0002] Existing PWM generation technologies have the following main drawbacks: First, they consume a lot of digital circuit resources. Traditional solutions often use complex counter architectures or lookup table methods, leading to a surge in the number of gate circuits and flip-flops. Second, the circuit design is highly complex, often relying on multi-layer logic control or external microprocessor intervention, and even using multi-stage comparator cascade structures, which significantly increases the difficulty of debugging and maintenance. Third, the dynamic adjustment capability is limited. Most technologies only support fixed or discrete duty cycle adjustment and lack continuous stepless adjustment and adaptive matching functions for input signals. Utility Model Content

[0003] To help solve the above-mentioned technical problems, this application provides a simple and effective PWM generation circuit, which adopts the following technical solution: A simple and effective PWM generation circuit, comprising: A set counter is provided, and its input terminal receives a first control signal. It is used to select N-ary or N+1-ary counting according to the first control signal, and generates a set pulse when the count overflows. The reset counter receives a second control signal at its input terminal, which is used to select N-ary or N+1-ary counting according to the second control signal, and generates a reset pulse when the count overflows; The first delay module is connected to the output of the set counter and is used to delay the set pulse by one clock cycle. The second delay module is connected to the output of the reset counter and is used to delay the reset pulse by one clock cycle. The output module has its input terminals connected to the output terminals of the set counter, the clear counter, the first delay module, and the second delay module, respectively, and is used to generate a PWM waveform based on the timing relationship of the four pulse signals.

[0004] Preferably, the circuit for setting the counter includes: Multiple cascaded D flip-flops, with the output of the low-order flip-flop connected to the clock input of the high-order flip-flop, form an asynchronous counter structure. This structure receives the first control signal and selects N-ary counting when the first control signal is at the first level and N+1-ary counting when it is at the second level.

[0005] Preferably, the circuit for the reset counter includes: Multiple cascaded D flip-flops, with the output of the low-order flip-flop connected to the clock input of the high-order flip-flop, form an asynchronous counter structure. This structure receives the first control signal and selects N-ary counting when the first control signal is at the first level and N+1-ary counting when it is at the second level.

[0006] Preferably, the circuit for setting the counter includes: Multiple cascaded D flip-flops, with the output of the low-order flip-flop connected to the clock input of the high-order flip-flop, form an asynchronous counter structure. This structure receives the second control signal and selects N-ary counting when the second control signal is at the first level and N+1-ary counting when it is at the second level.

[0007] Preferably, the first delay module includes a D flip-flop, the data input terminal of which receives the corresponding set pulse, the clock terminal is connected to the system clock, and the output terminal outputs a set pulse signal delayed by one clock cycle.

[0008] Preferably, the second delay module includes a D flip-flop, the data input terminal of which receives the corresponding reset pulse, the clock terminal is connected to the system clock, and the output terminal outputs a reset pulse signal delayed by one clock cycle.

[0009] Preferably, the output module includes a first NAND gate, a second NAND gate, and an RS flip-flop; The first input terminal of the first NAND gate receives a delayed set pulse, and the second input terminal receives the clear pulse; The first input of the second NAND gate receives a delayed reset pulse, and the second input receives the set pulse; The reset terminal of the RS flip-flop is connected to the output terminal of the first NAND gate, and the reset terminal is connected to the output terminal of the second NAND gate.

[0010] In summary, this application reduces the number of gate circuits and flip-flops used by designing a dual-counter architecture and a delay module, thus solving the problem of high resource consumption; it replaces the traditional complex architecture with a configurable counter combination, reducing the number of circuit components and lowering design complexity and maintenance difficulty; the built-in automatic duty cycle matching mechanism can realize dynamic adjustment when the input signal changes, solving the rigidity problem of traditional technical adjustment mechanisms. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the structure of an embodiment of a simple and effective PWM generation circuit according to this application; Figure 2 This is a schematic diagram of the structure of the set-counter of this application; Figure 3 for Figure 2A schematic diagram of the first part in the embodiment shown; Figure 4 for Figure 2 A schematic diagram of the second part in the embodiment shown; Figure 5 for Figure 2 A schematic diagram of the third part in the embodiment shown; Figure 6 This is a schematic diagram of the structure of the reset counter in this application; Figure 7 for Figure 6 The diagram shows the structure of the first part of the embodiment shown. Figure 8 for Figure 6 The diagram shows the structure of the second part of the embodiment shown. Figure 9 for Figure 6 The diagram shows the structure of the third part of the embodiment shown. Figure 10 This is a schematic diagram of the delay module in this application; Figure 11 This is a schematic diagram of the output module of this application; Figure 12 This is a schematic diagram of the output of the PWM generation circuit when the duty cycle remains constant. Figure 13 This is a schematic diagram of the output of the PWM generation circuit when the duty cycle is increased to 100%. Figure 14 This is a schematic diagram of the output of the PWM generation circuit when the duty cycle is reduced to 0%. Detailed Implementation

[0012] The present application will be further described below with reference to the accompanying drawings. The structure and principle of the present application are very clear to those skilled in the art. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

[0013] Figure 1 This is a schematic diagram of an embodiment of a simple and effective PWM generation circuit according to this application. Figure 1 The main structure of the PWM generation circuit consists of a set counter, a clear counter, two delay modules, and an output module.

[0014] The simple and effective PWM generation circuit of this application includes: A set counter is provided, and its input terminal receives a first control signal. It is used to select N-ary or N+1-ary counting according to the first control signal, and generates a set pulse when the count overflows. The reset counter receives a second control signal at its input terminal, which is used to select N-ary or N+1-ary counting according to the second control signal, and generates a reset pulse when the count overflows; The first delay module is connected to the output of the set counter and is used to delay the set pulse by one clock cycle. The second delay module is connected to the output of the reset counter and is used to delay the reset pulse by one clock cycle. The output module has its input terminals connected to the output terminals of the set counter, the clear counter, the first delay module, and the second delay module, respectively, and is used to generate a PWM waveform based on the timing relationship of the four pulse signals.

[0015] Specifically, the set counter: when Minus (first control signal) = 0 (level), it emits a pulse every N cycles (set pulse); when Minus = 1 (level), it emits a pulse every N+1 cycles (set pulse).

[0016] Reset counter: When Plus (second control signal) = 0, a pulse (reset pulse) is emitted every N cycles; when Plus = 1, a pulse (reset pulse) is emitted every N+1 cycles.

[0017] Delay: Delay the two pulses by one cycle.

[0018] Output: Based on the two types of pulses and the two types of pulses after the delay, the current state is determined, and a PWM wave is generated.

[0019] Figure 2 This is a schematic diagram of the structure of the counter in this application. Figure 3 for Figure 2 The diagram shows the structure of the first part in the embodiment shown. Figure 4 for Figure 2 A schematic diagram of the second part in the illustrated embodiment. Figure 5 for Figure 2 A schematic diagram of the third part in the illustrated embodiment.

[0020] Combination Figures 2 to 5 It is understood that the set counter of this application includes multiple cascaded D flip-flops, with the output of the low-order flip-flop connected to the clock input of the high-order flip-flop, forming an asynchronous counter structure. This structure is used to receive the first control signal and select N-ary counting when the first control signal is at a first level and select N+1-ary counting when it is at a second level.

[0021] Except for the first D flip-flop, the D inputs of the other D flip-flops are connected to their own inverting outputs.

[0022] It should be noted that the signals "AN", "AQ", "BN", and "BQ" appearing in the diagram are names of the output signals of the internal flip-flops of the counter. The first letter (A / B) identifies the counter module.

[0023] A: Represents all signals related to the set counter.

[0024] B: Represents all signals related to the reset counter.

[0025] The second letter (Q / N) indicates the polarity of the signal.

[0026] Q: Represents the non-inverting output of the flip-flop. This is the standard output of the flip-flop; Q is high when the data stored in the flip-flop is '1'.

[0027] N: Here, it represents the inverting output of the flip-flop, often referred to as Q-NOT or Qn. Its level is always the opposite of that of the Q terminal.

[0028] <n>: Identifies the bit order of a signal. For example <0> , <1> , <2> The numbers indicate that the signal is the 0th bit (least significant bit LSB), 1st bit, 2nd bit, etc. of the binary output of the counter.

[0029] POR is an abbreviation for Power-On Reset signal, which is a global, asynchronous control signal. Typically, the SET terminal of a flip-flop is an asynchronous set terminal, meaning that as soon as this terminal is active, it will immediately force the flip-flop output Q to a high level without waiting for a clock signal.

[0030] When the POR signal is valid (active high in this embodiment), it forces all D flip-flops connected to it to output Q=1. This process occurs instantaneously upon power-on. When the circuit powers on, the voltage needs time to rise from 0V to a stable value, during which the logic circuit may be in an uncertain random state. The POR circuit detects the power supply voltage and generates a brief pulse after it reaches a reliable level, placing all flip-flops into a known, deterministic initial state (all 1s in this embodiment). This setting action occurs immediately, has the highest priority, and is independent of the clock CP_1us. In summary, the POR signal provides power-on initialization, ensuring the circuit starts operating from a unified and deterministic state (all flip-flops Q-values ​​are 1), preventing random states from causing logic errors.

[0031] CP_1us is an abbreviation for Clock Pulse signal. The suffix _1us indicates that its period is 1 microsecond (μs), meaning it is a system clock signal with a frequency of 1MHz. The clock input of the flip-flop is a synchronization signal that controls when it samples and updates data. The CP_1us signal provides a synchronization timing reference for the entire digital circuit, and all D flip-flops operate synchronously under the control of this clock signal. At each valid edge of the CP_1us clock signal (in this embodiment, the rising edge, i.e., the instant from 0 to 1), the flip-flop samples the data at its D input, latches this data, and transmits it to the output Q (and holds this value for the entire clock cycle until the next valid edge). All state changes strictly occur at the valid edge of the clock, making the operation of the entire system predictable and orderly. In summary, the role of the CP_1us signal is to synchronize and coordinate every step of the operation of all sequential logic components such as the set counter, clear counter, and delay module, ensuring that they operate in unison.

[0032] Figure 6 This is a schematic diagram of the structure of the reset counter in this application. Figure 7 for Figure 6 The diagram shows the structure of the first part of the embodiment. Figure 8 for Figure 6 The diagram shows the structure of the second part of the embodiment. Figure 9 for Figure 6 The diagram shows the structure of the third part of the embodiment.

[0033] Combination Figures 6 to 9 It is understandable that the circuit for resetting the counter includes: Multiple cascaded D flip-flops, with the output of the least significant flip-flop connected to the clock input of the most significant flip-flop, form an asynchronous counter structure. This counter receives the first control signal and selects N-ary counting when the first control signal is at a first level and N+1-ary counting when it is at a second level. Except for the first D flip-flop, the D inputs of the remaining D flip-flops are connected to their respective inverting outputs.

[0034] Figure 10 This is a schematic diagram of the delay module of this application. Figure 10 The diagram shows two delay modules with identical structures but receiving different signals. The first delay module includes a D flip-flop, whose data input receives the corresponding set pulse, whose clock input is connected to the system clock, and whose output outputs a set pulse signal delayed by one clock cycle. The second delay module also includes a D flip-flop, whose data input receives the corresponding clear pulse, whose clock input is connected to the system clock, and whose output outputs a clear pulse signal delayed by one clock cycle.

[0035] Figure 11 The diagram below shows the structure of the output module of this application. The output module includes a first NAND gate, a second NAND gate, and an RS flip-flop (composed of two NOR gates). The first input terminal of the first NAND gate receives a delayed set pulse, and the second input terminal receives the reset pulse. The first input terminal of the second NAND gate receives a delayed reset pulse, and the second input terminal receives the set pulse. The reset terminal of the RS flip-flop is connected to the output terminal of the first NAND gate, and the reset terminal is connected to the output terminal of the second NAND gate.

[0036] Figure 12 This is a schematic diagram of the output of the PWM generation circuit when the duty cycle remains constant. Figure 13 This is a schematic diagram of the PWM generation circuit output when the duty cycle is increased to 100%. Figure 14 This is a schematic diagram of the output of the PWM generation circuit when the duty cycle is reduced to 0%.

[0037] Figure 12 , Figure 13 and Figure 14 The numerical sequence in the code represents the real-time count value change trajectory of the set counter and the reset counter, for example... Figure 12 The set counter in the middle increments from N-2 to 0, triggering a set pulse (OUT high). The reset counter increments from N-11 to 0, triggering a reset pulse (OUT low). When Minus = 0, Plus = 0 or Minus = 1, Plus = 1, the periods of the two counters are the same, and the interval between the two pulses remains unchanged, so the high-level time of OUT remains unchanged, that is, the pulse width remains unchanged (e.g., ...). Figure 12 ).

[0038] When Minus = 0 and Plus = 1, the set counter is in base N and the clear counter is in base N+1. The set pulse sets OUT to 1 and the clear pulse clears OUT to 0. Because the periods of the two timers are different, the interval between the two pulses will become farther and farther, making the high level time of OUT longer and longer, that is, the pulse width will become larger and larger.

[0039] like Figure 13 When the delayed set pulse and the reset pulse arrive at the same time, it means that the interval between the two pulses has reached the limit. After that, the set counter is also adjusted to N+1 base, and the reset pulse is prevented from clearing OUT. That is, OUT will remain high, that is, the duty cycle reaches 100%.

[0040] When Minus = 1 and Plus = 0, the set counter is in base N+1 and the clear counter is in base N. The set pulse sets OUT to 1 and the clear pulse clears OUT to 0. Because the periods of the two timers are different, the interval between the two pulses will get closer and closer, making the high level time of OUT shorter and shorter, that is, the pulse width will get smaller and smaller.

[0041] like Figure 14 When the delayed reset pulse and the set pulse arrive at the same time, it means that the interval between the two pulses has reached the limit. After that, the set counter is adjusted to N-ary and the set pulse is prevented from setting OUT to 1, that is, OUT will remain low, that is, the duty cycle reaches 0%.

[0042] Thus, by properly configuring the two inputs, PWM waves of arbitrary variation can be generated.< / n>

Claims

1. A simple and effective PWM generation circuit, characterized by, include: A set counter is provided, and its input terminal receives a first control signal. It is used to select N-ary or N+1-ary counting according to the first control signal, and generates a set pulse when the count overflows. The reset counter receives a second control signal at its input terminal, which is used to select N-ary or N+1-ary counting according to the second control signal, and generates a reset pulse when the count overflows; The first delay module is connected to the output of the set counter and is used to delay the set pulse by one clock cycle. The second delay module is connected to the output of the reset counter and is used to delay the reset pulse by one clock cycle. The output module has its input terminals connected to the output terminals of the set counter, the clear counter, the first delay module, and the second delay module, respectively, and is used to generate a PWM waveform based on the timing relationship of the four pulse signals.

2. The PWM generation circuit according to claim 1, characterized by, The circuit for setting the counter includes: Multiple cascaded D flip-flops, with the output of the low-order flip-flop connected to the clock input of the high-order flip-flop, form an asynchronous counter structure. This structure receives the first control signal and selects N-ary counting when the first control signal is at the first level and N+1-ary counting when it is at the second level.

3. The PWM generation circuit of claim 1, wherein, The circuit for the reset counter includes: Multiple cascaded D flip-flops, with the output of the low-order flip-flop connected to the clock input of the high-order flip-flop, form an asynchronous counter structure. This structure receives the first control signal and selects N-ary counting when the first control signal is at the first level and N+1-ary counting when it is at the second level.

4. The PWM generation circuit of claim 1, wherein, The circuit for setting the counter includes: Multiple cascaded D flip-flops, with the output of the low-order flip-flop connected to the clock input of the high-order flip-flop, form an asynchronous counter structure. This structure receives the second control signal and selects N-ary counting when the second control signal is at the first level and N+1-ary counting when it is at the second level.

5. The PWM generation circuit of claim 1, wherein, The first delay module includes a D flip-flop. The data input terminal of the D flip-flop receives the corresponding set pulse, the clock terminal is connected to the system clock, and the output terminal outputs a set pulse signal delayed by one clock cycle.

6. The PWM generation circuit of claim 1, wherein, The second delay module includes a D flip-flop. The data input terminal of the D flip-flop receives the corresponding reset pulse, the clock terminal is connected to the system clock, and the output terminal outputs a reset pulse signal delayed by one clock cycle.

7. The PWM generation circuit of claim 1, wherein, The output module includes a first NAND gate, a second NAND gate, and an RS flip-flop; The first input terminal of the first NAND gate receives a delayed set pulse, and the second input terminal receives the clear pulse; The first input of the second NAND gate receives a delayed reset pulse, and the second input receives the set pulse; The reset terminal of the RS flip-flop is connected to the output terminal of the first NAND gate, and the reset terminal is connected to the output terminal of the second NAND gate.

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