A high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop

Abstract

This invention discloses a calibration-free, high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop (PLL). It can generate frequency-modulated continuous wave (FMCW) with a step size of 30 Hz, a sweep bandwidth covering the 76-81 GHz millimeter-wave band, support sweep slopes up to 500 MHz / μs, stable output signal power, linearity better than 0.01%, lock time less than 4 microseconds, and carrier phase noise as low as -100 dBc / Hz at a 1 MHz frequency offset at 80 GHz. Its total power consumption is lower than that of traditional millimeter-wave PLLs. Its overall performance is significantly superior to other existing solutions, making it suitable for high-performance millimeter-wave radar systems in the 76-81 GHz range.

Description

Technical Field

[0001] This utility model relates to the field of millimeter-wave radar integrated circuit technology, and in particular to a high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop. Background Technology

[0002] FMCW (Frequency Modulated Continuous Wave) radar transmits at a frequency that varies linearly in the time domain. The chirp is the FMCW frequency sweeping pattern, and common chirp sweeping methods include triangular waves, sawtooth waves, and sine waves. For example... Figure 1 This is a schematic diagram of an FMCW radar. The FMCW radar contains multiple chirp signals with identical waveforms. Its underlying principle is to transmit chirped signals and receive their reflected signals, calculating the difference between the two to detect information such as the distance, velocity, and angle of targets and obstacles. High-quality chirping is the key foundation for FMCW radar to achieve high-precision ranging, velocity measurement, and high-resolution imaging. To improve detection accuracy, FMCW radar commonly uses a multi-transmit, multi-receiver phased array architecture, with chirp slopes adjustable between tens and hundreds of MHz / μs, and idle time often needing to be as short as a few microseconds.

[0003] However, the above requirements cannot be simultaneously met by traditional phase-locked loops because their key parameters are mutually restrictive, especially linearity, phase noise, and settling time, forming an "impossible triangle." This makes high-slope FMCW chirps unable to meet stringent system requirements. The reasons are as follows: (1) Limited bandwidth of phase-locked loop: If the bandwidth is too large, it cannot effectively suppress low-frequency noise, resulting in SDM (Sigma-DeltaModulator) quantization noise leakage, the linearity of the phase-locked loop is damaged, and the spurious is too large; if the bandwidth is too small, the phase-locked loop settling time is too long, which cannot meet the idle time requirement of FMCW chirp (less than 5 microseconds).

[0004] (2) Traditional type II phase-locked loops can track step functions with zero steady-state error, but due to the small sweep time step of FMCW, which is often around 20 ns, the phase-locked loop is at risk of losing lock. Increasing the step size will reduce the chirp slope and shorten the radar detection range under the same sweep bandwidth.

[0005] (3) The traditional FMCW phase-locked loop has poor phase noise performance, partly due to bandwidth limitation and partly due to the saturation of devices such as PFD (Phase Frequency Detector) / CP (Charge Pump), which is particularly serious in the 76 to 81 GHz ultra-wideband scenario;

[0006] (4) The power and phase of the output millimeter wave signal are unstable, which will directly lead to the loss of radar resolution.

[0007] Given the aforementioned issues, FMCW millimeter-wave radar phase-locked loop systems often require complex calibration techniques, including two-point modulation, LMS algorithms, or the use of high-power, large-area LUTs. These modules significantly increase the design difficulty and potential risks. Therefore, how to improve the linearity of FMCW signals while ensuring low phase noise is an urgent problem to be solved in FMCW generation circuits. Summary of the Invention

[0008] To address the above problems, this utility model discloses a high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop, such as... Figure 2 As shown.

[0009] This phase-locked loop is an ultra-wideband, ultra-low phase noise, and high linearity fractional phase-locked loop that generates millimeter-wave high-frequency signals and performs FMCW modulation, supporting common frequency sweeping schemes for high-slope frequency-modulated continuous waves.

[0010] This utility model is achieved through the following technical solution.

[0011] A high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop includes a system clock phase-locked loop, an N-divider, a fast pull-in channel (large bandwidth), a low-noise lock-in channel (small bandwidth), a frequency and phase detector, a charge pump, a Σ∆ modulator, a phase domain low-pass filter, a loop filter, a multi-mode divider, a timing control engine, and a voltage-controlled oscillator.

[0012] The fast pull-in channel includes a PFD / CP and an LD (lock-in detection module), and the low-noise lock-in channel includes: n PFD / CPs; and one PDLPF (Phase-Domain Low-Pass Filter).

[0013] A high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop is disclosed, wherein the output of the SYSPLL is connected to the input of an N-divider, the output of the N-divider is connected to the input of a PFD / CP in a fast pull-in channel module, the output of the PFD / CP is connected to the input of an LD, and the output of the LD is connected to the input of a low-noise lock-in channel.

[0014] The other output of the N-divider is directly connected to the input of the phase domain low-pass filter in the low-noise latch-up channel. The output of the phase domain low-pass filter is connected to the input of the PFD / CP, the output of the PFD / CP is connected to the input of the LPF, the output of the LPF is connected to the input of the VCO, one output of the VCO directly forms an FMCW frequency-modulated continuous wave, and the other is connected to the input of the MMD. At the same time, the outputs of the SDM and the Time Engine are also connected to the input of the MMD. The output of the MMD is divided into two paths: one is connected to the fast pull-in channel, and the other is connected to the low-noise latch-up channel.

[0015] The SYSPLL is used to generate a stable and low-jitter system clock signal for use by subsequent modules; the voltage-controlled oscillator is used to generate a waveform output of a specific frequency from the voltage signal of the loop filter; the multimode divider (MMD) divides the output signal of the voltage-controlled oscillator to obtain a divided signal.

[0016] The high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop described herein utilizes a two-stage architecture to decouple clock signal generation and FMCW signal modulation, increasing the dimension of parameter optimization. In the second-stage phase-locked loop, the "pull-in" and "lock-in" processes are decoupled, simultaneously achieving rapid locking and low phase noise performance. Furthermore, by employing multi-channel phase detection and phase low-pass filtering techniques, the second-stage phase-locked loop can further achieve low spurious emissions and periodic slippage during high-speed frequency sweeping. Overall performance is significantly superior to traditional solutions.

[0017] like Figure 3 The diagram shown is a startup timing diagram of the fast-locking low-noise phase-locked loop of this invention, which clearly illustrates the startup process of the fast-locking mechanism of this invention.

[0018] This phase-locked loop (PLL) employs a two-stage architecture. The first stage generates a high-precision, low-noise signal, which is used as the reference clock for the second stage. Because its frequency is as high as 480 MHz, the second-stage PLL does not require a large division ratio, thus achieving even lower noise.

[0019] The second-stage phase-locked loop uses integral differential modulation (SDM) and supports 30 Hz sweep frequency steps. It can quickly configure parameters such as the chirp start frequency and slope according to chirp requirements using the Time engine.

[0020] Because of the decoupling of the "pull-in" and "lock-in" processes of the phase-locked loop, this phase-locked loop can simultaneously achieve low phase noise and fast locking, with setup time of less than 5 microseconds.

[0021] In the "Lock-in" channel, this phase-locked loop uses a phase low-pass filter to reduce the quantization noise of the SDM module, and at the same time adopts a multi-channel time-division operating scheme to suppress the noise of the frequency phase detector (PFD) and the reference clock. Therefore, it can achieve a linearity performance of one ten-thousandth in a bandwidth of 76 to 81 GHz. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the FMCW radar principle.

[0023] Figure 2 This is a schematic diagram of a high-speed, high-linearity, low-phase-noise FMCW millimeter-wave phase-locked loop structure according to this utility model.

[0024] Figure 3 This is the startup timing diagram of the fast-locking low-noise phase-locked loop of this utility model.

[0025] Figure 4 This is a block diagram of a phase-locked loop system provided in an embodiment of this utility model.

[0026] Figure 5 This is a simulation histogram of the frequency error during the establishment and sweep frequency of the phase-locked loop of this utility model.

[0027] Figure 6 This is a waveform simulation diagram of the establishment of the phase-locked loop and the frequency sweep time domain establishment process of this utility model.

[0028] Figure 7 This is a schematic diagram of the simulation results for the linearity of the FMCW chirp signal. Detailed Implementation

[0029] The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0030] Example (GF 40nm CMOS process) like Figure 4 As shown, this phase-locked loop (PLL) adopts a two-stage configuration. The first stage uses a narrowband analog PLL, multiplying the 40 MHz crystal oscillator frequency to 4.8 GHz. This serves as the clock for the entire chip and is also connected to a frequency divider to generate a 480 MHz signal, which is used as the reference clock for the second-stage fractional PLL. From a noise propagation perspective, assuming a fixed bandwidth, because the reference clock is unique, the square relationship between the in-band noise and the square of the PLL divisor (the total divisor equals the product of the two divisors N1 and N2) remains unchanged, i.e., N... 2 =N1 2 *N2 2However, by decomposing it into two stages, the adjustable parameters are decoupled to some extent, improving design flexibility and allowing for separate optimization of each stage for different frequency bands. For example, subsampling structures can be used to directly eliminate quadratic relationships; noise shaping can be used to reduce in-band noise, and appropriate bandwidth can be selected to filter out noise from the preceding stage (equivalent to mitigating N in-band noise). 2 (Laws, etc.) This lays the physical foundation for the implementation of this plan.

[0031] The second-stage fractional phase-locked loop (PLL) is split into two paths: "pull-in" and "lock-in," with different bandwidths and charge pump performance. The "pull-in" module uses a 5 MHz high-bandwidth, high-linearity charge pump, analogous to a traditional frequency-locked loop (FLL), which can pull the frequency to near the desired frequency in microseconds. Then, the "lock-in" path is switched to quickly lock in, and by dynamically narrowing the bandwidth, superior in-band noise performance is achieved without increasing spurious emissions. Through this architecture, this design simultaneously optimizes PLL setup time, in-band noise, and linearity.

[0032] This invention utilizes multi-channel PFD / CP noise reduction. By reducing the PFD sampling frequency through time-division multiplexing, its reference period (TREF=1 / fREF) is delayed. As a result, the charge pump has a larger charging and discharging time window for the loop filter in each cycle. The "noise contribution" of the charge pump is diluted (because the error signal needs a longer time to accumulate), which is equivalent to reducing the loop gain under the premise of high SDM clock, thereby reducing the noise of PFD / CP. The in-band noise of the PLL mainly comes from PFD / CP and the reference signal. Its noise power spectral density (PSD) is proportional to the loop gain. The lower the gain, the smaller the amplification factor of the in-band noise. Reducing the reference clock frequency by 4 times improves the in-band noise by 12 dB. The advantages of this method are: (1) Improved PLL stability: High loop gain may cause insufficient phase margin of PLL, especially in broadband designs; (2) Reduced LPF complexity; (3) Although the reference clock frequency decreases, the total frequency division ratio of the loop remains unchanged, so the noise of the reference clock remains unchanged after N-way summation. By separating the DSM frequency and PFD frequency, both quantization noise (higher frequency) and in-band noise (multi-channel sharing) are optimized, avoiding N 2 Side effects of amplified reference noise.

[0033] This invention utilizes a phase-domain low-pass filter (PDLPF) module to reduce transient quantization noise in SDM and prevent cycle slippage caused by loop error accumulation due to FMCW modulation. Simultaneously, adding an FIR filter module to the DSM path further reduces noise spikes and prevents side effects such as loss of lock, relock, and false lock caused by the loop momentarily exceeding the 2π limit.

[0034] This invention uses a lock detection device (LD) to trigger channel switching, which can avoid problems such as unstable locking caused by switching too early or wasted setup time caused by switching too late.

[0035] Dynamic CP current compensation solves cycle slippage: By applying weights to the current of multiple PFD / CP channels, a certain degree of circuit "memory" can be created, with an effect comparable to infinite impulse response filtering (IIR).

[0036] like Figure 5 This is a simulation histogram of the frequency error during the establishment and frequency sweep of the phase-locked loop (PLL) of this invention. The histogram reflects the steady-state performance of the PLL after locking. The mean frequency error is close to zero, indicating that the loop design eliminates systematic steady-state error and achieves accurate frequency tracking. The standard deviation of the frequency error of 52.7 kHz reflects the excellent noise immunity of the loop in the steady state. The error distribution is concentrated and symmetrical, indicating that the phase noise mainly originates from random disturbances. The design of the loop filter effectively suppresses high-frequency noise and spurious signals.

[0037] like Figure 6 This is a simulation waveform diagram of the establishment and frequency sweep time domain establishment process of the phase-locked loop of this utility model. The diagram further confirms the dynamic performance advantages of the phase-locked loop. The waveform shows that the frequency converges to a stable value quickly in a smooth and monotonic manner, without overshoot or ringing. This indicates that key parameters such as loop bandwidth and damping coefficient have been optimized, enabling it to complete frequency acquisition and phase locking in a very short establishment time, combining high-speed response and excellent stability.

[0038] like Figure 7 This is a schematic diagram illustrating the simulation results of the linearity of the FMCW chirp signal. The simulation shows that, under the current design and simulation conditions, the FMCW radar chip can generate a high-performance chirp signal: the center frequency of this chirp signal is approximately 77.5 GHz, the bandwidth reaches 5 GHz, the linearity is excellent, the frequency increases perfectly linearly with time, and the modulation slope is as high as approximately 83.33 MHz / μs. This result means that millimeter-wave radar based on this phase-locked loop design can achieve high-range resolution detection.

[0039] In summary, the simulation results of this phase-locked loop demonstrate that the design of this invention combines excellent dynamic setup speed, high stability, high linearity, and extremely low output phase noise. The overall performance meets stringent application requirements and can significantly improve the performance of radar systems.

[0040] The foregoing has shown and described the basic principles, main features, and advantages of this utility model. It will be apparent to those skilled in the art that this utility model is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or basic characteristics of this utility model. Therefore, this utility model is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop, characterized in that, include: Two-level cascaded architecture, fast pull-in channel, low-noise latch-in channel, latch-in detection module, dynamic current compensation module; The two-level cascaded architecture includes a first-level phase-locked loop and a second-level fractional phase-locked loop; The first-stage phase-locked loop is used to generate a high-frequency reference clock and is configured to multiply the crystal oscillator clock and then generate the reference clock through a frequency divider. The second-stage fractional phase-locked loop is split into two channels, "pull-in" and "latch-in," to receive the reference clock and generate a millimeter-wave FMCW signal. The fast pull-in channel employs a high bandwidth and high linearity charge pump, which can pull the frequency to near the desired frequency in microseconds. The low-noise latching channel can quickly lock in and achieve superior in-band noise performance without increasing spurious emissions by dynamically narrowing the bandwidth. The locking detection module monitors the phase error in real time and triggers the switching between the pull-in channel and the locking channel; The dynamic current compensation module applies programmable weights to multiple PFD / CP channels to suppress periodic slippage.

2. The high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop according to claim 1, characterized in that, The first-stage phase-locked loop includes: a crystal oscillator (XO) that provides a reference frequency source, a system clock phase-locked loop (SYSPLL) with a low phase noise and narrow bandwidth frequency multiplier crystal oscillator clock signal, and an N-divider, wherein the output of the crystal oscillator is connected to the input of the SYSPLL, and the output of the SYSPLL is connected to the input of the N-divider. The second-stage fractional phase-locked loop includes: a phase-domain low-pass filter (PDLPF), a low-pass filter (LPF), n parallel phase-frequency detectors / charge pumps (PFD / CP), an integral-differential modulator (SDM), a multi-mode divider (MMD), and a voltage-controlled oscillator (VCO). The output of the phase-domain low-pass filter (PDLPF) is connected to the input of the n parallel phase-frequency detectors / charge pumps; the output of the phase-frequency detectors / charge pumps is connected to the output of the lock detection module; and the outputs of the integral-differential modulator (SDM) and the timing engine are connected to the input of the multi-mode divider (MMD).

3. The high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop according to claim 2, characterized in that, The second-stage fractional phase-locked loop uses integral differential modulation and supports 30 Hz sweep frequency stepping. It can quickly configure the chirp start frequency and slope parameters using a time engine according to chirp requirements. The multimode divider (MMD) divides the output signal of the voltage-controlled oscillator to obtain the divided signal.

4. The high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop according to claim 1, characterized in that, The low-noise latching channel includes a four-channel noise reduction structure. The four PFD / CP units operate in time-division multiplexing mode, reducing the equivalent reference frequency to 120MHz. The charge pump current weight of each channel can be adjusted independently, forming an equivalent infinite impulse response filter (IIR).

5. A high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop according to claim 2, characterized in that, The parallel frequency and phase detector / charge pump unit reduces the loop gain and the noise power spectral density by lowering the equivalent reference frequency.

6. The high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop according to claim 2, characterized in that, The phase domain low-pass filter (PDLPF) directly processes the digital phase error signal and suppresses the transient quantization noise of the Σ-Δ modulator; the cascaded finite impulse response filter (FIR) limits the phase jump range.

7. The high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop according to claim 1, characterized in that, The dynamic current compensation module injects a pre-calibrated current pulse during the channel switching transition period, and the current amplitude is adaptively adjusted according to the historical locking error.

8. The high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop according to claim 1, characterized in that, A noise transmission optimization strategy is adopted: the first-stage phase-locked loop uses a subsampling structure to break the N² amplification law of in-band noise; the second stage reduces reference noise through four-channel noise reduction.

9. A high-speed, high-linearity, low-noise FMCW millimeter-wave radar phase-locked loop according to claim 1, characterized in that, The lock detection module (LD) determines the lock status based on the phase error derivative and triggers channel switching when the phase error slope is ≤5° / ns.

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