Circuit board and chip packaging structure
By setting heat dissipation pads and filling through-holes with thermally conductive filler in multi-layer wiring, a continuous heat dissipation channel is constructed, which solves the heat dissipation problem of surface mount devices, achieves efficient heat conduction, and improves the heat dissipation capacity of the circuit board and product reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WEIFANG GOERTEK ELECTRONICS CO LTD
- Filing Date
- 2025-06-27
- Publication Date
- 2026-07-31
AI Technical Summary
In existing technologies, heat dissipation is a prominent issue for surface mount devices, especially in high-power device applications. Traditional heat dissipation methods struggle to balance efficient thermal management with aesthetic consistency, leading to localized heat buildup that affects product reliability and lifespan.
By setting heat dissipation pads in multi-layer wiring and filling the overlapping areas with thermally conductive filler through-holes, a continuous heat dissipation channel is constructed that runs through multiple layers. Combined with an insulating thermally conductive layer and a heat dissipation device, a multi-level heat conduction path is formed, which enhances heat conduction efficiency and reduces thermal resistance.
It significantly improves the heat dissipation capacity of the circuit board, alleviates local heat accumulation, reduces temperature rise, and enhances the overall thermal stability and reliability of the device, making it suitable for highly integrated electronic products.
Smart Images
Figure CN224583378U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip heat dissipation technology, specifically to a circuit board and chip packaging structure. Background Technology
[0002] With the continuous development of electronic technology, electronic products are rapidly evolving towards thinner, lighter, and smaller designs, with increasingly higher levels of functional integration. This places higher demands on the packaging density and thermal management capabilities of devices on printed circuit boards (PCBs). Against this backdrop, surface mount devices (SMDs) have gradually replaced traditional through-hole technology (THTs) devices, becoming the most commonly used packaging form in electronic products.
[0003] SMD (Surface Mount Device) packages offer advantages such as small size, light weight, and high assembly efficiency, effectively increasing PCB wiring density. However, with the increasing prevalence of high-power devices in end products, the heat dissipation challenges faced by SMD devices are becoming more prominent. Since SMD devices are typically soldered directly to the PCB surface, their heat dissipation primarily relies on the thermal path between the bottom pads of the package and the PCB. If this path is not optimized within the PCB design, it often leads to localized heat buildup, causing excessive device temperature rise and potentially inducing thermal failure, thus affecting product reliability and lifespan.
[0004] To address the aforementioned issues, existing technologies primarily employ several methods to assist heat dissipation: increasing the PCB copper foil area, creating vias (such as PTH holes) below the pads to guide heat downwards, and mounting heat dissipation devices or coating with thermally conductive materials on the back. However, these solutions often suffer from discontinuous heat dissipation paths, low heat transfer efficiency, and persistently high localized temperature rises. This is particularly true for optical electronic devices with glass-encapsulated upper surfaces and limitations on appearance or structure, where traditional heat dissipation methods struggle to simultaneously meet the combined requirements of aesthetic consistency, space constraints, and efficient thermal management. Utility Model Content
[0005] The purpose of this invention is to at least solve the problem of a single heat dissipation path on a circuit board. This purpose is achieved through the following technical solution:
[0006] The first aspect of this utility model provides a circuit board, comprising:
[0007] A multi-layer wiring layer is stacked sequentially along a first direction, each of the wiring layers is provided with a heat dissipation pad, and the multiple heat dissipation pads have overlapping areas along the first direction;
[0008] At least one insulating layer is provided along the first direction, with an insulating layer between adjacent wiring layers;
[0009] Along the first direction, the overlapping area is provided with a through hole, and the through hole is filled with thermally conductive filler.
[0010] According to the circuit board of this invention, heat dissipation pads are respectively set in multiple wiring layers, and these heat dissipation pads have overlapping areas along a first direction. Through-holes filled with thermally conductive filler are then set in these overlapping areas, constructing a continuous heat dissipation channel penetrating multiple wiring layers. Compared to the prior art design where heat can only dissipate outward through a single layer of pads and surface copper foil, this invention, through the collaborative heat dissipation design of multiple pads between wiring layers, effectively increases the number and area of heat conduction paths, significantly improving the efficiency of heat conduction to deeper layers or the back of the circuit board. The thermally conductive filler filling the through-holes further reduces the thermal resistance in the heat conduction path, avoiding the problem of low heat conduction efficiency in traditional air-filled through-holes. Therefore, this invention can significantly improve the heat dissipation capacity of the circuit board, alleviate local heat accumulation, reduce the temperature rise of high heat density chips during operation, and effectively improve the thermal stability, reliability, and service life of the entire device.
[0011] In addition, the circuit board according to this utility model may also have the following additional technical features:
[0012] In some embodiments of this utility model, along the first direction, the top layer of the multi-layer wiring layer is provided with a first heat dissipation pad, and the bottom layer of the multi-layer wiring layer is provided with a second heat dissipation pad. The cross-sectional area of the first heat dissipation pad is S1, and the cross-sectional area of the second heat dissipation pad is S2, wherein S2≥1 / 2S1.
[0013] In some embodiments of this utility model, along the first direction, the second heat dissipation pad is covered with an insulating and thermally conductive layer on the side opposite to the first heat dissipation pad.
[0014] In some embodiments of this utility model, along the first direction, the insulating thermally conductive layer is provided with a heat dissipation device on the side opposite to the second heat dissipation pad.
[0015] In some embodiments of this utility model, a heat-conducting layer is formed on the inner wall of the through hole.
[0016] In some embodiments of this utility model, there are multiple through holes, and adjacent through holes are spaced apart.
[0017] In some embodiments of this utility model, the cross-sectional areas of the plurality of heat dissipation pads are the same, and the projection surfaces of the plurality of heat dissipation pads overlap each other along the first direction.
[0018] The second aspect of this utility model provides a chip packaging structure, including:
[0019] The aforementioned circuit board;
[0020] The chip, along the first direction, is attached to the heat dissipation pad on the top;
[0021] A thermal pad is attached to the side of the chip that is away from the circuit board.
[0022] In some embodiments of this utility model, the chip packaging structure further includes a shielding cover, which covers the circuit board and surrounds the circuit board to form a packaging cavity. The chip and the thermal pad are both located inside the packaging cavity, and the side of the thermal pad facing away from the chip is attached to the inner wall of the shielding cover.
[0023] In some embodiments of this utility model, heat dissipation fins are provided on the outer wall of the shield. Attached Figure Description
[0024] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:
[0025] Figure 1 A schematic diagram of the circuit board structure according to an embodiment of the present invention is shown.
[0026] Figure 2 for Figure 1 A cross-sectional view of the AA plane;
[0027] Figure 3 A schematic diagram of a chip packaging structure according to an embodiment of the present invention is shown.
[0028] The attached figures are labeled as follows:
[0029] 100. Circuit board; 10. Multilayer wiring layer; 101. Top wiring layer; 102. First internal wiring layer; 103. Second internal wiring layer; 104. Bottom wiring layer; 11. Heat dissipation pad; 12. Through-hole; 20. At least one insulating layer; 201. First insulating layer; 202. Second insulating layer; 203. Third insulating layer; 30. Insulating and thermally conductive layer; 40. Heat dissipation device;
[0030] 200, Chip; 300, Thermal pad; 400, Shielding cover; 500, Heat sink fins. Detailed Implementation
[0031] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0032] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.
[0033] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.
[0034] For ease of description, spatial relative terms may be used in the text to describe the relationship of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "over," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure is flipped, an element described as "below other elements or features" or "below other elements or features" would subsequently be oriented "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations.
[0035] like Figures 1 to 2As shown, according to an embodiment of the present invention, a circuit board 100 is provided, the circuit board 100 including components along a first direction (e.g., Figure 2 As shown by the middle arrow x, a multi-layer wiring layer 10 and at least one insulating layer 20 are stacked in sequence. Each wiring layer is provided with a heat dissipation pad 11. An insulating layer is provided between two adjacent wiring layers. Along the first direction, a through hole 12 is opened in the overlapping area. The through hole 12 is filled with thermally conductive filler.
[0036] According to the circuit board 100 of this invention, heat dissipation pads 11 are respectively provided in multiple wiring layers, and these heat dissipation pads 11 have overlapping areas along a first direction. Through-holes 12 filled with thermally conductive filler are then provided in these overlapping areas, constructing a continuous heat dissipation channel penetrating multiple wiring layers 10. Compared to the prior art design where heat can only dissipate outward through a single layer of pads and surface copper foil, this invention, through the collaborative heat dissipation design of multiple pads between wiring layers, effectively increases the number and area of vertical heat conduction paths, significantly improving the efficiency of heat conduction to deeper layers or the back of the circuit board 100. The thermally conductive filler filling inside the through-holes 12 further reduces the thermal resistance in the heat conduction path, avoiding the problem of low heat conduction efficiency in traditional air-filled through-holes 12. Therefore, this invention can significantly improve the heat dissipation capacity of the circuit board 100, alleviate local heat accumulation, reduce the temperature rise of the high heat density chip 200 during operation, and effectively improve the thermal stability, reliability, and service life of the entire device.
[0037] In some embodiments, along the first direction, the top wiring layer 101 of the multilayer wiring layers is provided with a first heat dissipation pad 11 (i.e., the top layer heat dissipation pad 11), and the bottom wiring layer of the multilayer wiring layer 10 is provided with a second heat dissipation pad 11 (i.e., the bottom layer heat dissipation pad 11). The cross-sectional area of the first heat dissipation pad 11 is S1, and the cross-sectional area of the second heat dissipation pad 11 is S2, wherein S2 ≥ 1 / 2S1. By providing the first heat dissipation pad 11 and the second heat dissipation pad 11 at the top and bottom layers of the multilayer circuit board 100 respectively, and limiting the area of the bottom second heat dissipation pad 11 to at least half the area of the top heat dissipation pad 11, it can be ensured that there is still sufficient heat dissipation contact area when heat is conducted to the bottom layer along the first direction, avoiding heat accumulation inside the circuit board 100 due to insufficient heat dissipation area at the bottom layer, thereby improving the longitudinal heat dissipation efficiency of the entire board. This embodiment enhances the vertical heat diffusion capability and provides sufficient thermal contact area for connecting external heat sinks (such as metal heat sinks or thermally conductive shells) at the bottom, effectively improving the overall heat dissipation capability of the chip 200 during operation and significantly reducing the risk of local temperature rise when the high-power chip 200 is working, thereby improving the thermal stability and reliability of the product.
[0038] Furthermore, along the first direction, the second heat dissipation pad 11 is covered with an insulating thermally conductive layer 30 on the side facing away from the first heat dissipation pad 11. The insulating thermally conductive layer 30 is used to prevent short circuits caused by electrical connections while achieving heat conduction. By providing an insulating thermally conductive layer 30 on the side of the second heat dissipation pad 11 facing away from the first heat dissipation pad 11, heat can be efficiently conducted to the outside of the circuit board 100 (such as a heat sink or housing) after being conducted to the bottom layer from the multi-layer pads and thermal vias 12, while avoiding the risk of electrical short circuits or breakdowns due to exposed bottom pads. The insulating thermally conductive layer 30 has both good thermal conductivity and electrical insulation properties, allowing heat to be quickly dissipated without affecting the electrical performance of the device, improving the heat release efficiency at the end of the heat dissipation path. It is particularly suitable for scenarios where it is used in conjunction with a metal housing or external heat sink, helping to further reduce the thermal resistance of the chip 200 and achieve a safe electrical-thermal separation structure design. Therefore, this embodiment, while ensuring electrical safety, further optimizes the overall heat dissipation capacity of the circuit board 100, and improves the operational stability and product reliability of high heat density devices in a highly integrated environment.
[0039] Specifically, the insulating and thermally conductive layer 30 is thermally conductive silicone grease. By specifically setting the insulating and thermally conductive layer 30 as thermally conductive silicone grease, its excellent thermal conductivity and flexibility enable it to form sufficient contact between the second heat dissipation pad 11 and the external heat dissipation device 40, filling tiny gaps, effectively reducing interface thermal resistance, and achieving more efficient heat conduction. Simultaneously, the thermally conductive silicone grease has excellent electrical insulation properties, preventing short circuits caused by contact between the bottom of the circuit board 100 and metal structural components. Furthermore, its flexibility and ease of application make it suitable for mass production, ensuring bonding stability and long-term reliability. Therefore, this embodiment not only enhances the thermal conduction efficiency at the end of the heat dissipation path but also improves the safety and assembly adaptability of the entire system, making it suitable for compact electronic products with high heat dissipation requirements.
[0040] Furthermore, along the first direction, a heat dissipation device 40 is attached to the side of the insulating thermally conductive layer 30 opposite to the second heat dissipation pad 11, used to further dissipate the heat conducted to the insulating thermally conductive layer 30 through the heat conduction path to the external environment. By attaching the heat dissipation device 40 to the outside of the insulating thermally conductive layer 30, the heat generated during the operation of the chip 200 and conducted to the bottom through the multilayer wiring layer 10 and the thermal via 12 can be further transferred to the heat dissipation device 40 and diffused into the ambient air, thereby significantly enhancing the overall heat release capability. This structure effectively establishes a continuous, efficient, and safe vertical heat dissipation path through a multi-stage heat conduction chain of "heat dissipation pad 11 - thermally conductive filler - insulating thermally conductive layer 30 - heat dissipation device 40", greatly reducing the risk of device performance degradation or failure caused by local heat accumulation. At the same time, the heat dissipation device 40 can be flexibly selected according to the actual application scenario, such as metal heat sink, aluminum extruded shell, water-cooled base plate, etc., with good adaptability and engineering promotion value, suitable for electronic systems with high power density and stringent heat dissipation requirements.
[0041] Specifically, the heat dissipation device 40 may include components along the second direction (e.g., Figure 2 The heat sink and the plate covered by the insulating and thermally conductive layer 30 are arranged in sequence at intervals (arrow y). The plate is bonded to the insulating and thermally conductive layer 30, and the heat sink is set on the plate. Both the plate and the heat sink can be made of copper.
[0042] In some embodiments, the via 12 is a metallized via 12 (PTH via), and a thermally conductive layer is formed on the inner wall of the via 12. The thermally conductive layer is electrically connected to the heat dissipation pads 11 in the multilayer wiring layer 10 to enhance the vertical heat conduction and electrical connection capabilities. By setting the via 12 as a PTH via and forming a continuous thermally conductive layer on its wall, reliable connection between the heat dissipation pads 11 in the multilayer wiring structure of the circuit board can be achieved, and the high thermal conductivity of the thermally conductive layer can be used to form a vertically continuous heat conduction path. The thermally conductive layer is usually a copper plating layer, which has good electrical and thermal conductivity. Compared with non-metallized vias or hollow vias 12, the metallized thermally conductive layer greatly improves the vertical heat diffusion rate, reduces the phenomenon of heat stagnation in a single layer, and provides a highly reliable connection path for bottom soldering of devices or power and ground networks. Therefore, this embodiment can effectively improve the heat conduction efficiency inside the PCB, reduce the operating temperature of devices, and take into account structural compactness and electrical integrity, thereby improving the system's thermal management capabilities and overall reliability.
[0043] In some embodiments, multiple through-holes 12 are arranged with a gap between adjacent through-holes 12 to form a uniform heat dissipation channel distribution. By setting multiple spaced through-holes 12, multiple parallel heat conduction channels can be established in the overlapping area of the heat dissipation pads 11. Compared with a single through-hole 12 or a densely stacked layout, the spaced arrangement helps to evenly distribute heat flow and prevent overheating or heat accumulation in local through-holes 12. The spaced distribution also takes into account the structural strength and heat dissipation efficiency of the circuit board 100, avoiding problems such as reduced mechanical strength of the board and increased electrical interference coupling caused by excessively dense through-holes 12. At the same time, the uniformly arranged multiple through-holes 12 can cover a larger area of heat dissipation path, improving the overall heat dissipation uniformity and system thermal stability. Therefore, this embodiment ensures heat dissipation capacity while taking into account structural reliability, electrical isolation, and manufacturability, and is suitable for reliable heat dissipation design of multilayer high-power circuit boards 100.
[0044] Specifically, the diameter of the through hole 12 and the spacing between adjacent through holes 12 can be flexibly determined according to design factors such as heat dissipation requirements, electrical wiring requirements and structural strength of the circuit board 100, and are not limited to a fixed numerical range, so as to adapt to application scenarios with different power densities and packaging structures.
[0045] In some embodiments, multiple heat dissipation pads 11 have the same cross-sectional area, and their projected surfaces overlap along a first direction, thus forming a continuous heat dissipation path. By setting multiple heat dissipation pads 11 with the same cross-sectional area and overlapping projected surfaces along the first direction, a regular and aligned heat conduction path can be constructed in the vertical direction. This structural design ensures the consistency of the thermal contact area between the via 12 and each layer of heat dissipation pads 11, which is beneficial for the vertical conduction of heat without deviation in the multilayer structure, improving the integrity and efficiency of the heat conduction channel. In addition, since the pads of each layer are of the same size and projectedly aligned in position, it not only simplifies the stack-up design and processing alignment of the circuit board 100, but also prevents heat from shifting or spreading laterally in the conduction path, reducing thermal resistance accumulation. This further improves the heat uniformity and thermal stability of the circuit board 100 in the vertical direction, making it particularly suitable for high-power device packaging applications with high requirements for heat dissipation path consistency.
[0046] In specific implementation methods, such as Figure 1 and Figure 2As shown, the circuit board 100, along a first direction (i.e., the thickness direction of the circuit board 100), sequentially includes a top wiring layer 101, a first internal wiring layer 102, a second internal wiring layer 103, and a bottom wiring layer 104. These wiring layers are used to implement functional connections and heat conduction for the chip 200. An insulating layer is provided between adjacent wiring layers to provide electrical isolation and form a laminated structure. Specifically, the circuit board 100, along the first direction, also sequentially includes a first insulating layer 201, a second insulating layer 202, and a third insulating layer 203. The first insulating layer 201 is disposed between the top wiring layer 101 and the first internal wiring layer 102, the second insulating layer 202 is disposed between the first internal wiring layer 102 and the second internal wiring layer 103, and the third insulating layer 203 is disposed between the second internal wiring layer 103 and the bottom wiring layer 104. In the above structure, each wiring layer has a heat dissipation pad 11, and multiple heat dissipation pads 11 have overlapping projection areas in the vertical direction (i.e., the first direction), forming a heat dissipation channel at the bottom of the chip 200. Along the first direction, multiple PTH vias 12 are provided in the overlapping area of multiple heat dissipation pads 11. The PTH vias 12 penetrate the top wiring layer 101, the first insulating layer 201, the first internal wiring layer 102, the second insulating layer 202, the second internal wiring layer 103, the third insulating layer 203, and the bottom wiring layer 104, and their via walls are formed with an electroplated copper thermally conductive layer to enhance the heat conduction between the heat dissipation pads 11 of each layer. Furthermore, the vias 12 are filled with thermally conductive fillers, such as thermally conductive epoxy resin, silver paste, or thermally conductive adhesive, to improve the overall thermal conductivity of the vias 12 and construct a low thermal resistance, continuous vertical heat dissipation channel. This circuit board 100, by layering multiple heat dissipation pads 11, penetrating PTH vias 12, and multi-layer insulating supports, forms a multi-layer packaging platform that has both electrical connectivity and high-efficiency heat dissipation performance, suitable for chip 200 packaging and high-speed electronic modules with strict thermal management requirements.
[0047] It is understandable that the circuits in the internal wiring layer of the circuit board 100 are not electrically connected to the heat sink 11. That is, the circuit is planned during production to avoid the heat sink 11.
[0048] like Figure 3As shown, this embodiment also proposes a chip packaging structure, including the aforementioned circuit board 100, chip 200, and thermal pad 300. Along the first direction, chip 200 is mounted on the top heat dissipation pad 11, and thermal pad 300 is mounted on the side of chip 200 facing away from the circuit board 100. In this embodiment, the chip packaging structure mounts chip 200 on the top heat dissipation pad 11 of the circuit board 100, and thermal pad 300 is mounted on the other side of chip 200, thus forming a bidirectional heat dissipation path design. On one hand, heat from the bottom of chip 200 can be conducted to the lower part of circuit board 100 through the multi-layer heat dissipation pad 11, through-hole 12, and insulating thermally conductive layer 30. On the other hand, heat from the top of chip 200 can be conducted to an external heat sink or metal casing through thermal pad 300. This design not only expands the contact area for heat dissipation of chip 200 but also constructs a bidirectional heat diffusion channel, effectively improving the heat dissipation efficiency of the high heat density chip 200, reducing the device operating temperature, and improving system thermal stability and long-term reliability. In addition, the thermal pad 300, as a flexible medium, can fill the tiny gap between the top of the chip 200 and the heat dissipation structure, reduce the interface thermal resistance, and at the same time have a certain mechanical buffering performance, which is conducive to the stable operation of the chip 200 in thermal cycling or vibration environments.
[0049] It is understood that the chip packaging structure also includes a shield 400, which covers the circuit board 100 and forms a packaging cavity with the circuit board 100. The chip 200 and the thermal pad 300 are both located inside the packaging cavity. The thermal pad 300 is attached to the side of the chip 200 away from the circuit board 100 and is in thermal contact with the inner wall of the shield 400. In this embodiment, the shield 400, as a metal conductive structure, can effectively suppress the outward diffusion of electromagnetic radiation generated by the chip 200 and surrounding circuits during operation, preventing electromagnetic interference from affecting surrounding equipment, and improving the electromagnetic compatibility of the product to meet relevant EMC standards. At the same time, the thermal pad 300 is located on top of the chip 200 and is attached to the inner wall of the shield 400, constructing an upward heat dissipation path from the chip 200 to the thermal pad 300 and then to the shield 400. The shield 400 itself can serve as an integrated heat dissipation structure or form a thermal contact interface with the external metal casing to improve heat dissipation efficiency.
[0050] Furthermore, heat dissipation fins 500 are provided on the outer wall of the shielding cover 400. The heat dissipation fins 500 are used to increase the heat dissipation surface area to accelerate the release of heat generated by the chip 200 during operation. By providing heat dissipation fins 500 on the outer wall of the shielding cover 400, the heat exchange efficiency between it and the external air can be effectively improved. After the heat is conducted to the shielding cover 400 body via the chip 200 and the thermal pad 300, it is further dissipated through convection and radiation by the heat dissipation fins 500, thereby significantly improving the overall heat dissipation capacity. The heat dissipation fin structure has the advantages of high specific surface area and high convection heat transfer capacity, which is especially suitable for application scenarios where the chip 200 operates for a long time or has a high heat power density. This embodiment organically combines electromagnetic shielding function with efficient heat dissipation function, which not only realizes the integration of EMI suppression and heat diffusion, but also avoids the structural bulkiness caused by setting up an additional external heat sink. Therefore, this solution ensures heat dissipation efficiency while taking into account space compactness, assembly convenience and thermal stability, and is particularly suitable for communication modules, processor packaging, high-frequency circuits and other systems with high requirements for both heat dissipation and electromagnetic compatibility.
[0051] Specifically, the shield 400 is connected to the circuit board 100 by locking screws to fix the shield 400 and maintain its encapsulation, sealing and thermal conductivity with the circuit board 100.
[0052] The above description is merely a preferred embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.
Claims
1. A circuit board, characterized by, include: A multi-layer wiring layer is stacked sequentially along a first direction, each of the wiring layers is provided with a heat dissipation pad, and the multiple heat dissipation pads have overlapping areas along the first direction; At least one insulating layer is provided between adjacent wiring layers along the first direction; Along the first direction, the overlapping area is provided with a through hole, and the through hole is filled with thermally conductive filler.
2. The circuit board of claim 1, wherein Along the first direction, the top layer of the multi-layer wiring layer is provided with a first heat dissipation pad, and the bottom layer of the multi-layer wiring layer is provided with a second heat dissipation pad. The cross-sectional area of the first heat dissipation pad is S1, and the cross-sectional area of the second heat dissipation pad is S2, wherein S2≥1 / 2S1.
3. The circuit board of claim 2, wherein, Along the first direction, the second heat dissipation pad is covered with an insulating and thermally conductive layer on the side opposite to the first heat dissipation pad.
4. The circuit board of claim 3, wherein Along the first direction, the insulating thermally conductive layer has a heat dissipation device attached to the side opposite to the second heat dissipation pad.
5. The circuit board according to any one of claims 1 to 4, characterized in that, A heat-conducting layer is formed on the inner wall of the through hole.
6. The circuit board according to any one of claims 1 to 4, characterized by The number of through holes is multiple, and adjacent through holes are spaced apart.
7. The circuit board according to any one of claims 1 to 4, characterized by The multiple heat dissipation pads have the same cross-sectional area, and their projected surfaces completely overlap along the first direction.
8. A chip package structure, characterized by, include: The circuit board according to any one of claims 1 to 7; The chip, along the first direction, is attached to the heat dissipation pad on the top of the circuit board; A thermal pad is attached to the side of the chip that is away from the circuit board.
9. The chip package structure of claim 8, wherein, The chip packaging structure also includes a shield, which covers the circuit board and surrounds the circuit board to form a packaging cavity. The chip and the thermal pad are both located inside the packaging cavity, and the side of the thermal pad facing away from the chip is attached to the inner wall of the shield.
10. The chip package structure of claim 9, wherein, The outer wall of the shield is provided with heat dissipation fins.