memory devices

Abstract

A memory device includes a first transistor, a second transistor, and a memory cell. The first transistor is above a substrate. The second transistor is above the first transistor. The memory cell is above the first transistor and the second transistor, wherein the memory cell includes a bottom electrode, a resistive switching layer above the bottom electrode, and a top electrode above the resistive switching layer. The resistive switching layer and the bottom electrode form a first interface. The first interface includes a first portion extending toward the substrate in a first direction and a second portion extending in a second direction different from the first direction. The first portion of the first interface is larger than the second portion of the first interface. In a cross-sectional view, the ratio of the length of the first portion of the first interface to the length of the second portion of the first interface is greater than the aspect ratio of the second transistor.

Description

Technical Field

[0001] This disclosure concerns a memory device. Background Technology

[0002] Many modern electronic devices contain electronic memory. Electronic memory can be volatile or non-volatile. Non-volatile memory retains stored data even without power, while volatile memory does not. Dynamic random-access memory (DRAM), which requires frequent re-updates, is volatile memory. Non-volatile memory includes, for example, magnetoresistive random-access memory (MRAM), resistive random-access memory (RRAM), ferroelectric random-access memory (FeRAM), and phase-change memory (PCM). Utility Model Content

[0003] In some embodiments, a memory device includes a first transistor, a second transistor, and a memory cell. The first transistor is above a substrate. The second transistor is above the first transistor. The memory cell is above the first transistor and the second transistor, wherein the memory cell includes a bottom electrode, a resistor switching layer above the bottom electrode, and a top electrode above the resistor switching layer. The resistor switching layer and the bottom electrode form a first interface, wherein the first interface includes a first portion extending toward the substrate in a first direction and a second portion extending in a second direction different from the first direction, wherein the first portion of the first interface is larger than the second portion of the first interface, and wherein in a cross-sectional view, the ratio of the length of the first portion of the first interface to the length of the second portion of the first interface is greater than the aspect ratio of the second transistor.

[0004] In some embodiments, a memory device includes a first transistor, a first interconnect structure, a second transistor, a second interconnect structure, and a memory cell. The first transistor is on a substrate. The first interconnect structure is above the first transistor. The second transistor is above the first interconnect structure, wherein the second transistor includes a gate structure and a channel layer above the gate structure. The second interconnect structure is above the second transistor. The memory cell is above the second interconnect structure and is electrically connected to the second transistor through the second interconnect structure, wherein the channel layer of the second transistor is below the memory cell and above the gate structure of the second transistor.

[0005] In some embodiments, a memory device includes a first transistor, a first interconnect structure, a second transistor, a second interconnect structure, and a memory cell. The first transistor is on a substrate. The first interconnect structure is above the first transistor. The second transistor is above the first interconnect structure, wherein the second transistor includes a gate structure and a channel layer above the gate structure. The second interconnect structure is above the second transistor. The memory cell is above the second interconnect structure and is electrically connected to the second transistor through the second interconnect structure, wherein the memory cell is vertically overlapped with the second transistor. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying items. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1 to 17A , Figure 17C ,and Figures 18 to 19 A cross-sectional view illustrating an intermediate stage in forming an example integrated circuit structure having one or more MRAM cells according to some embodiments of the present disclosure;

[0008] Figure 17B Draw Figure 17A A top view of the intermediate state;

[0009] Figure 20 A cross-sectional view of another example IC structure according to some embodiments of this disclosure is shown;

[0010] Figures 21 to 24 A cross-sectional view illustrating an intermediate stage in forming an example integrated circuit structure having one or more MRAM cells according to some embodiments of the present disclosure;

[0011] Figure 25 A cross-sectional view of another example IC structure according to some embodiments of this disclosure is shown;

[0012] Figure 26 A cross-sectional view of another example IC structure according to some embodiments of this disclosure is shown;

[0013] Figure 27 A cross-sectional view of another example IC structure according to some embodiments of the present disclosure is shown.

[0014] [Symbol Explanation]

[0015] 10B: Second Interconnect Layer

[0016] 13A~13D: Conductive vias

[0017] 14A~14D: Conductive wires

[0018] 15A~15D: IMD layer

[0019] 100: IC Structure

[0020] 100A~100E: IC Structure

[0021] 100L: Logic Area

[0022] 100M: Memory area

[0023] 101: District

[0024] 102:Substrate

[0025] 104: Transistor / FinFET

[0026] 106: Fins

[0027] 108: Source and Drain Regions

[0028] 110: STI area

[0029] 112: Gate structure

[0030] 114: Spacer

[0031] 116: First ILD

[0032] 118: Gate layer

[0033] 120: Gate layer

[0034] 122: Second ILD layer

[0035] 124: Contact element

[0036] 130: Dielectric layer

[0037] 140: Conductive layer

[0038] 142: Gate Structure

[0039] 144: Gate dielectric layer

[0040] 145: Patterned gate dielectric layer

[0041] 146: Channel Layer

[0042] 147: Patterned Channel Layer

[0043] 147E: Elevated portion

[0044] 147L: Lower part

[0045] 148: Hard mask layer

[0046] 149: Patterned mask layer

[0047] 150: BEOL transistor

[0048] 150A: BEOL transistor

[0049] 150B: BEOL transistor

[0050] 150S / D: Source / Drain Region

[0051] 160: Dielectric layer

[0052] 170: IMD layer

[0053] 180: Dielectric layer

[0054] 190: Dielectric layer

[0055] 200: IMD layer

[0056] 201: District

[0057] 202: Bottom Electrode Layer

[0058] 204:MTJ layer

[0059] 204A: Outer magnetic layer

[0060] 204B: Tunneling through the barrier layer

[0061] 204C: Inner Magnetic Layer

[0062] 206: Top electrode layer

[0063] 211: MTJ Unit

[0064] 212: Bottom electrode

[0065] 212A: First metal layer

[0066] 212B: Second metal layer

[0067] 214: MTJ Stack

[0068] 216: Top electrode

[0069] 216A: First metal layer

[0070] 216B: Second metal layer

[0071] 220: IMD layer

[0072] 310: Bottom electrode

[0073] 310A: First metal layer

[0074] 310B: Second metal layer

[0075] 312: MTJ Stack

[0076] 314: Top electrode

[0077] 314A: First metal layer

[0078] 314B: Second metal layer

[0079] 320: MTJ Unit

[0080] 330: Dielectric layer

[0081] 340: Dielectric layer

[0082] 350: IMD layer

[0083] H1~H2: Vertical dimensions

[0084] IF1: Part 1

[0085] IF2: Part Two

[0086] IF3: Part Three

[0087] IF4: Part Four

[0088] O1~O4: Opening

[0089] P1~P2: Patterned masking

[0090] W1~W2: Lateral dimensions Detailed Implementation

[0091] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0092] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature depicted in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 230 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly. As used herein, “approximately,” “about,” “roughly,” or “substantially” generally refers to within 20%, 10%, or 5% of a given value or range. The values ​​given herein are approximate, meaning that the terms “approximately,” “about,” “roughly,” or “substantially” can be inferred unless explicitly stated otherwise. However, those skilled in the art will recognize that the values ​​or ranges referenced throughout the description are merely examples and may decrease as integrated circuits shrink.

[0093] This disclosure relates to memory cells disposed within back-end-of-line (BEOL) metal interconnects of an integrated wafer. The BEOL metal interconnects include multiple vias and metal lines that provide interconnection within an inter-metal dielectric (IMD) layer. The memory cells may be of a non-volatile type. In some embodiments, the memory cells are magnetoresistive random-access memory (MRAM), resistive random-access memory (RRAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), or the like. The data storage layer may include multiple layers, the composition of which depends on the memory type.

[0094] Each magneto-resistive random-access memory (MRAM) cell comprises a magnetic tunnel junction (MTJ) cell within a back-end-of-line (BEOL) integrated process, vertically arranged between conductive electrodes. An MTJ cell includes first and second ferromagnetic layers separated by a tunneling barrier layer. One of the ferromagnetic layers (often called the "reference layer" or "fixed layer") has a fixed magnetization direction (also known as magnetization orientation), while the other ferromagnetic layer (often called the "free layer") has a variable or switchable magnetization direction. For an MTJ cell with positive tunneling magnetoresistance (TMR), if the magnetization directions of the reference layer and the free layer are parallel, electrons are more likely to tunnel through the tunneling barrier layer, resulting in a low-resistance state for the MTJ cell. Conversely, if the magnetization directions of the reference layer and the free layer are antiparallel, electrons are less likely to tunnel through the tunneling barrier layer, resulting in a high-resistance state for the MTJ cell. Therefore, the MTJ unit can switch between two states of resistance, with the first state having low resistance (R). P (The magnetization directions of the reference layer and the free layer are parallel), and the second state has high resistance (R). AP (The magnetization directions of the reference layer and the free layer are antiparallel). Due to its binary nature, MTJ cells can be used to store digital data, where the low-resistance state R... P Corresponding to the first data state (e.g., logic "0"), the high resistance state R AP This corresponds to the second data state (e.g., logic "1").

[0095] The continued demand for higher memory densities has driven significant advancements in memory technology. However, as the cell area decreases, MTJ cells become increasingly susceptible to interference from adjacent MTJ cells, leading to higher lattice failure rates. The reduction in cell area exacerbates stability issues such as magnetoresistance variations and shortened MTJ cell lifetime. To address these challenges, this disclosure provides an improved MTJ cell in various embodiments, comprising an improved MTJ layer that extends in the vertical direction beyond its lateral dimension. This vertical elongation of the MTJ layer effectively increases the MTJ junction area in the vertical direction, thereby mitigating magnetoresistance variations and improving MTJ cell lifetime without compromising cell area.

[0096] Figures 1 to 17A , Figure 17C ,and Figures 18 to 19 A cross-sectional view illustrating an intermediate stage in forming an example integrated circuit structure 100 having one or more MRAM cells according to some embodiments of the present disclosure is shown. Figure 17BDraw Figure 17A A top view of the intermediate state. Although Figures 1 to 19 The sectional and top views shown are described with reference to one method, but it should be understood that... Figures 1 to 19 The structure shown is not limited to this method, but can be used independently of it. Although Figures 1 to 19 The description is a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures.

[0097] Figure 1 A cross-sectional view of an example semiconductor structure 100 according to some embodiments is illustrated. This semiconductor structure includes a semiconductor substrate 102 in which various electronic devices can be formed, and a portion of a multi-level interconnect structure (e.g., interconnect layers 10A and 10B) formed above the substrate 102. Generally, Figure 1 A transistor 104 is illustrated on a substrate 102, with multiple interconnect layers formed above it. For example... Figure 1 As indicated by the ellipsis at the top, multiple interconnect layers can be similarly stacked in the integrated circuit manufacturing process. As shown, transistor 104 is a FinFET. In some other embodiments, transistor 104 is a planar FET, nanosheet FET, or other suitable FET. In some embodiments, transistor 104 can be used as an access transistor for a SOT-RAM cell.

[0098] Figure 1 The substrate 102 shown may comprise a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer 1 beneath a thin semiconductor layer, which is the active layer of the SOI substrate. The semiconductor of the active layer and the semiconductor of the bulk semiconductor generally comprise the crystalline semiconductor material silicon, but may include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or alloys thereof (e.g., Ga...). x Al 1-x As, Ga x Al 1-x N、In x Ga 1-x As, and the like), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, and the like), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0099] Figure 1The FinFET device 104 shown is a three-dimensional MOSFET structure formed in fin-shaped strips of semiconductor protrusions 106 called fins. Figure 1 The cross-section shown is taken along the longitudinal axis of the fin in a direction parallel to the current direction between the source and drain regions 108. The fins 106 can be formed by patterning the substrate using lithography and etching techniques. For example, spacer image transfer (SIT) patterning techniques can be used. In this method, a sacrificial layer is formed over the substrate and patterned using suitable lithography and etching processes to form a mandrel. Spacers are formed next to the mandrel using a self-aligned process. The sacrificial layer is then removed using a suitable selective etching process. The remaining spacers can then be used as hard masks to pattern individual fins 106 by etching trenches in the substrate 102, for example, using reactive ion etching (RIE). Figure 1 A single fin 106 is shown, although the substrate 102 may contain any number of fins.

[0100] Figure 1 The diagram illustrates a shallow trench isolation (STI) region 110 formed along the opposing sidewalls of fin 106. The STI region 110 can be formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trenches around the fin, followed by recessing the top surface of the dielectric material. The dielectric material of the STI region 110 can be deposited using high-density plasma chemical vapor deposition (HDP-CVD), low-pressure CVD (LPCVD), sub-atmospheric CVD (SACVD), flowable CVD (FCVD), spin-on, and / or similar methods, or combinations thereof. An annealing or curing process can be performed after deposition. In some cases, the STI region 110 may include a liner, such as, for example, a thermal oxide liner grown through a silicon oxide surface. The recessing process can use, for example, a planarization process (e.g., chemical mechanical polishing (CMP)), followed by a selective etching process (e.g., wet etching or dry etching, or a combination thereof). The selective etching process recesses the top surface of the dielectric material in the STI region 110, causing the upper portion of the fin 106 to protrude from the surrounding insulating STI region 110. In some cases, the patterned hard mask used to form the fin 106 can also be removed by the planarization process.

[0101] In some embodiments, Figure 1 The gate structure 112 of the FinFET device 104 shown is a high-k metal gate (HKMG) gate structure, which can be formed using a post-gate process. In the post-gate process, a sacrificial dummy gate structure (not shown) is formed after the STI region 110 is formed. The dummy gate structure may include a dummy gate dielectric, a dummy gate electrode, and a hard mask. First, a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, or the like) may be deposited. Next, a dummy gate material (e.g., amorphous silicon, polycrystalline silicon, or the like) may be deposited over the dummy gate dielectric, followed by planarization (e.g., by CMP). A hard mask layer (e.g., silicon nitride, silicon carbide, or the like) may be formed over the dummy gate material. The dummy gate structure is then formed by patterning the hard mask and transferring the pattern to the dummy gate dielectric and dummy gate material using suitable lithography and etching techniques. The dummy gate structure may extend along multiple sides of the protruding fins and between the fins above the surface of the STI region 110. As described in more detail below, the dummy gate structure may be replaced by the HKMG gate structure 112, such as Figure 1 As shown. The material used to form the dummy gate structure and hard mask can be deposited using any suitable method, such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or similar methods, or by thermal oxidation of the semiconductor surface, or a combination thereof.

[0102] like Figure 1 As shown, the source and drain regions 108 of the FinFET 104 and the spacer 114 are formed, for example, self-aligned with the dummy gate structure. The spacer 114 can be formed by depositing and anisotropically etching the spacer dielectric layer after the dummy gate patterning is completed. The spacer dielectric layer may include one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or combinations thereof. The anisotropic etching process removes the spacer dielectric layer from above the top of the dummy gate structure, leaving the spacer 114 along the sidewalls of the dummy gate structure.

[0103] The source and drain regions (also collectively referred to as source / drain regions or S / D regions) 108 are semiconductor regions in direct contact with the semiconductor fin 106. In some embodiments, the source and drain regions 108 may include heavily doped regions and relatively lightly doped drain extensions, or LDD regions. Generally, spacers 114 are used to separate the heavily doped regions from the dummy gate structure, and the LDD regions may be formed prior to the formation of the spacers 114, thus extending below the spacers 114, and in some embodiments, further extending into a portion of the semiconductor fin 106 below the dummy gate structure. For example, the LDD regions may be formed by implanting dopants (e.g., As, P, B, In, or the like) using an ion implantation process.

[0104] In some embodiments, the source and drain regions 108 may include epitaxially grown regions. For example, after forming the LDD regions, spacers 114 may be formed. Subsequently, by first etching the fins 106 to form grooves, and then depositing crystalline semiconductor material in the grooves using a selective epitaxial growth (SEG) process, heavily doped source and drain regions self-aligned with the spacers 114 can be formed. The SEG process can fill the grooves and typically extends beyond the original surface of the fins to form a raised source-drain structure, such as... Figure 1 As shown. Crystalline semiconductor materials can be elements (e.g., Si or Ge, or the like) or alloys (e.g., Si...). 1-x C x , or Si 1-x Ge x SEG processes can use any suitable epitaxial growth method, such as vapor / solid / liquid phase epitaxy (VPE / SPE / LPE), metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), or similar methods. High doses (e.g., from about 10...) 14 cm -2 Up to 10 18 cm -2 The dopant can be introduced into the heavily doped source and drain regions 108, either in situ during SEG, or through an ion implantation process performed after SEG, or through a combination thereof.

[0105] A first interlayer dielectric (ILD) 116 is deposited over the structure. In some embodiments, a contact etch stop layer (CESL) (not shown) of a suitable dielectric (e.g., silicon nitride, silicon carbide, or the like, or combinations thereof) may be deposited prior to the deposition of the ILD material. A planarization process (e.g., CMP) may be performed to remove excess ILD material and any remaining hard masking material over the dummy gate to form a top surface, wherein the top surface of the dummy gate material is exposed and may be substantially coplanar with the top surface of the first ILD 116. Subsequently, trenches may be formed between the individual spacers 114 by first removing the dummy gate structure using one or more etch techniques. Figure 1 The HKMG gate structure 112 is shown. Next, a replacement gate dielectric layer 118 comprising one or more dielectric materials is deposited, followed by a replacement conductive gate layer 120 comprising one or more conductive materials to completely fill the trench. Excess portions of the gate structure layers 118 and 120 can be removed from the top surface of the first ILD 116 using, for example, a CMP process. Figure 1 As shown, the resulting structure can be substantially coplanar surfaces, including the first ILD 116, spacers 114, and the exposed top surface of the remaining portions of the HKMG gate layers 118 and 120 embedded between the individual spacers 114.

[0106] The gate dielectric layer 118 comprises, for example, a high-k dielectric material, such as oxides and / or silicates of metals (e.g., Hf, Al, Zr, La, Mg, Ba, Ti, and oxides and / or silicates of other metals), silicon nitride, silicon oxide, and the like, or combinations thereof, or multiples thereof. In some embodiments, the conductive gate layer 120 may be a multilayer metal gate stack comprising a barrier layer, a work function layer, and a gate fill layer continuously formed on top of the gate dielectric layer 118. Examples of barrier layer materials include TiN, TaN, Ti, Ta, or the like, or multiple combinations thereof. The work function layer may include TiN, TaN, Ru, Mo, Al for p-type FETs and Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr for n-type FETs. Other suitable work function materials, or compositions thereof, or multiples thereof may be used. The gate fill layer for the remaining portion of the filled trench may comprise a metal, such as Cu, Al, W, Co, Ru, the like, or combinations thereof, or multiples thereof. The material used to form the gate structure can be deposited by any suitable method, such as CVD, PECVD, physical vapor deposition (PVD), ALD, PEALD, electrochemical plating (ECP), electroless plating, and / or the like.

[0107] like Figure 1 As shown, a second ILD layer 122 can be deposited over the first ILD layer 116. In some embodiments, the insulating material forming the first ILD layer 116 and the second ILD layer 122 may comprise silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), silicon-free glass (USG), low dielectric constant (low k) dielectrics such as fluorosilicone glass (FSG), silicon carbide (SiOCH), carbon-doped oxide (CDO), flowable oxides, or porous oxides (e.g., degels, aerogels), or the like, or combinations thereof. The dielectric material used to form the first ILD layer 116 and the second ILD layer 122 may be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin-on, and / or similar methods, or combinations thereof.

[0108] like Figure 1 As shown, the electrodes of the electronic device formed in the substrate 102 can be electrically connected to conductive features in the first interconnect layer 10A using conductive connectors (e.g., contact 124) formed through the intermediate dielectric layer. Figure 1In the illustrated embodiment, contact 124 is electrically connected to the source and drain regions 108 of FinFET 104. Contact 124 to the gate electrode may be formed above STI region 110, therefore... Figure 1 The cross-sectional view is not shown. The contacts can be formed using optical lithography. For example, a patterned mask can be formed over the second ILD 122 and used to etch an opening extending through the second ILD 116 to expose a portion of the gate structure 112, and to etch an opening further extending through the first ILD 116 and the CESL (if present) liner below the first ILD 116 to expose portions of the source and drain regions 108.

[0109] In some embodiments, a conductive liner may be formed in openings in the first ILD layer 116 and the second ILD layer 122. The openings are then filled with a conductive filler material. The liner includes a barrier metal to reduce the diffusion of conductive material from the contact 124 outwards into the surrounding dielectric material. In some embodiments, the liner may include two barrier metal layers. The first barrier metal contacts the semiconductor material in the source and drain regions 108 and may subsequently chemically react with the heavily doped semiconductor in the source and drain regions 108 to form a low-resistance ohmic contact, after which unreacted metal may be removed. For example, if the heavily doped semiconductor in the source and drain regions 108 is silicon or a silicon-germanium alloy semiconductor, the first barrier metal may comprise Ti, Ni, Pt, Co, other suitable metals, or alloys thereof. The second barrier metal layer of the conductive liner may additionally comprise other metals (e.g., TiN, TaN, Ta, or other suitable metals, or alloys thereof). Conductive filler material (e.g., W, Al, Cu, Ru, Ni, Co, alloys thereof, compositions thereof, and the like) can be deposited over the conductive liner layer using any acceptable deposition technique (e.g., CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, or similar, or any combination thereof) to fill the contact openings. Next, a planarization process (e.g., CMP) can be used to remove all excess conductive material from the surface of the second ILD 122. The resulting conductive socket extends into the first ILD layer 116 and the second ILD layer 122 and forms the contact 124, providing physical and electrical connection to the electrodes of the electronic device, such as... Figure 1 The three-gate FinFET 104 is shown.

[0110] like Figure 1As shown, after completing the front-end-of-line (FEOL) processing for forming transistor 104, multiple interconnect layers can be formed according to the back-end-of-line (BEOL) scheme adopted in the integrated circuit design, and vertically stacked on the contact sockets 124 formed in the first ILD layer 116 and the second ILD layer 122. Figure 1 In the BEOL scheme shown, the various interconnect layers have similar characteristics. However, it should be understood that other embodiments may utilize alternative integration schemes in which the various interconnect layers may use different characteristics. For example, the contact 124 shown as a vertical connector may extend to form conductive lines for lateral current transmission.

[0111] In this disclosure, the second interconnect layer includes conductive vias and conductive lines embedded in an inter-metal dielectric (IMD) layer. In addition to providing insulation between various conductive elements, the IMD layer may also include one or more dielectric etch-stop layers to control the etching process that forms openings in the IMD layer. Generally, vias conduct current vertically for electrically connecting two conductive features located at vertically adjacent layers, while wires conduct current laterally and are used to distribute electrical signals and power within a layer. Figure 1 In the illustrated BEOL configuration, conductive via 13A connects contact 124 to conductive wire 14A. At subsequent levels, vias connect lower wirings to upper wirings (e.g., a pair of wires 14A and 14B can be connected via via 13B). Other embodiments may employ different configurations. For example, via 13A may be omitted from the second level, and contact 124 may be configured to connect directly to wire 14A.

[0112] The first interconnect layer 10A can be formed using, for example, a dual damascene process. First, the dielectric stack for forming the IMD layer 15A can be deposited using one or more layers of dielectric materials listed in the description of the first ILD layer 116 and the second ILD layer 122. In some embodiments, the IMD layer 15A includes an etch-stop layer (not shown) located at the bottom of the dielectric stack. The etch-stop layer comprises one or more insulating layers (e.g., SiN, SiC, SiCN, SiCO, CN, combinations thereof, or the like) with an etch rate different from that of the overlying material. The technique used to deposit the dielectric stack for the IMD can be the same as the technique used to form the first ILD layer 116 and the second ILD layer 122.

[0113] The IMD layer 15A can be patterned using appropriate lithography and etching techniques (e.g., anisotropic RIE employing fluorocarbon chemistry) to form openings for vias and wiring. Openings for vias may be vertical holes extending through the IMD layer 15A to expose the top conductive surface of the contact 124, while openings for wiring may be longitudinal trenches formed in the upper portion of the IMD layer 15A. In some embodiments, the method for patterning holes and trenches in the IMD layer 15A utilizes a via-preferred approach, wherein a first lithography and etching process forms holes for vias, and a second lithography and etching process forms trenches for wiring. Other embodiments may use different methods, such as trench-preferred approaches, incomplete via-preferred approaches, or buried etch-stop layer approaches. The etching technique may utilize multiple steps. For example, a first main etching step may remove a portion of the dielectric material of the IMD layer 15A and terminate on an etch-stop dielectric layer. The etchant may then be switched to remove the etch-stop layer dielectric material. The parameters of various etching steps (e.g., gas chemical composition, flow rate, pressure, reactor power, etc.) can be adjusted to produce a tapered sidewall profile with the desired internal cone angle.

[0114] Several conductive materials can be deposited to fill the holes and trenches forming the conductive features 13A and 14A in the first interconnect layer 10A. The openings can first be lined with a conductive diffusion barrier material, and then completely filled with a conductive filler material deposited over the conductive diffusion barrier liner. In some embodiments, a thin conductive seed layer can be deposited over the conductive diffusion barrier liner to help initiate an electrochemical plating (ECP) deposition step, which completely fills the openings with the conductive filler material.

[0115] The diffusion barrier conductive liner in via 13A and wiring 14A comprises one or more layers of TaN, Ta, TiN, Ti, Co, or similar materials, or combinations thereof. The conductive filler layer in via 13A and wiring 14A may comprise metals such as Cu, Al, W, Co, Ru, or similar materials, or combinations thereof, or multiple layers thereof. The conductive material used to form conductive features 13A and 14A may be deposited by any suitable method, for example, CVD, PECVD, PVD, ALD, PEALD, ECP, electroless plating, and the like. In some embodiments, the conductive seed layer may be the same conductive material as the conductive filler layer and deposited using a suitable deposition technique (e.g., CVD, PECVD, ALD, PEALD, or PVD, or the like).

[0116] Any excess conductive material above the IMD layer 15A outside the opening can be removed by a planarization process (e.g., CMP) to form the top surface of the dielectric region containing the IMD layer 15A, which is substantially coplanar with the conductive region of the conductive line 14A. The planarization step embeds the conductive via 13A and the conductive line 14A into the IMD layer 15A, as shown below. Figure 1 As shown.

[0117] Figure 1 The interconnect layer located vertically above the first interconnect layer 10A is the second interconnect layer 10B. In some embodiments, the structures of various interconnect layers (e.g., the first interconnect layer 10A and the second interconnect layer 10B) may be similar. Figure 1 In the example shown, the second interconnect layer 10B includes conductive vias 13B and conductive lines 14B embedded in an insulating film IMD layer 15B having a flat top surface. The materials and processing techniques described above in the context of the first interconnect layer 10A can be used to form the second interconnect layer 10B and subsequent interconnect layers.

[0118] Although an example electronic device (FinFET 104) and an example interconnect structure connected to the electronic device have been described, it should be understood that those skilled in the art will appreciate that the above examples are provided for illustrative purposes only to further explain the application of this embodiment and are not intended to limit this embodiment in any way.

[0119] Figure 2 Draw Figure 1 An enlarged view of region 101 shows the upper region of interconnect layer 10B at the initial stage of manufacturing IC structure 100. Figure 2 In the diagram, conductive line 14B is shown embedded in IMD layer 15B. The top dielectric surface of IMD layer 15B is shown to be substantially coplanar with the top conductive surface of conductive line 14B within a process variation. IC structure 100 includes logic region 100L and memory region 100M. Memory devices (e.g., MRAM devices) are formed in memory region 100M, and logic devices (e.g., logic circuits) are formed in logic region 100L. Each region includes a plurality of transistors (e.g., FinFET 104) for controlling the operation of MRAM devices and / or logic circuits.

[0120] exist Figure 3In this process, a dielectric layer (also referred to as a dielectric barrier layer (SBL)) 130 is formed spanning the memory region 100M and the logic region 100L. In some embodiments, the dielectric layer 130 may include one or more dielectric materials, such as Si3N4, SiON, SiC, SiCN, or combinations thereof. The dielectric layer 130 may be formed by any suitable deposition process, such as spin-on coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), similar processes, or combinations thereof.

[0121] exist Figure 4 In this process, a patterned mask P1 is formed above the dielectric layer 130. In some embodiments, the patterned mask P1 is a patterned photoresist formed using a suitable lithography process. In an example lithography process, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. More specifically, a photomask or master photomask (not shown) may be placed on the photoresist material and then exposed to a radiation beam, which may be ultraviolet (UV) or an excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. For example, immersion lithography tools or extreme ultraviolet (EUV) tools may be used to expose the photoresist material to improve resolution and reduce the minimum achievable pitch. Baking or curing operations may be performed to harden the exposed photoresist material. Depending on whether a positive or negative resist is used, a developer can be used to remove exposed or unexposed portions of the photoresist material, leaving a patterned photoresist mask P1 above the dielectric layer 130, in which openings O1 expose a portion of the dielectric layer 130.

[0122] exist Figure 5 In this process, the dielectric layer 130 is patterned in the etching process using a patterned mask P1 as an etching mask, thereby forming an opening O2 through the dielectric layer 130 to expose the conductive line 14B. The dielectric layer 130 can be patterned using a suitable etching technique, such as wet etching, dry etching, or a combination thereof. After the opening O2 is formed in the dielectric layer 130, the patterned mask P1 can be removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist is raised until the photoresist undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, can be used.

[0123] exist Figure 6In this process, a conductive layer 140 is formed over the dielectric layer 130 using any acceptable deposition technique (e.g., CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, or similar techniques, or any combination thereof). In some embodiments, the deposition process of the conductive layer 140 continues until the openings O2 in the dielectric layer 130 are overfilled by the conductive layer 140. In some embodiments, the conductive layer 140 comprises a suitable conductive material for use as a transistor gate. For example, the conductive layer 140 comprises TaN, TiN, W, Al, polysilicon, combinations thereof, or the like.

[0124] exist Figure 7 In this process, a planarization process (e.g., CMP) can be used to remove excess portions of the conductive layer 140 outside the opening O2 in the dielectric layer 130, while leaving a portion in the opening O2 as the gate structure 142 of the BEOL transistor to be formed in subsequent processing. The gate structure 142 may be referred to as the BEOL transistor gate.

[0125] exist Figure 8 In this process, a gate dielectric layer 144, a channel layer 146, and a hard mask layer 148 are sequentially deposited over the gate 142 of the BEOL transistor using an acceptable deposition technique (e.g., CVD, ALD, PEALD, PECVD, PVD, similar, or any combination thereof). In some embodiments, the gate dielectric layer 144 comprises silicon oxide (SiO2) and / or a high-k dielectric material. As used and described herein, a high-k gate dielectric comprises a dielectric material having a high dielectric constant, for example, greater than the dielectric constant of thermally heated silicon oxide (~3.9). The high-k dielectric material of the gate dielectric layer 144 may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer 144 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), zirconium hafnium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxynitride (SiON), and combinations thereof.

[0126] In some embodiments, the channel layer 146 is a semiconductor layer formed of an oxide semiconductor, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium zinc oxide (GZO), or the like. In some other embodiments, the channel layer 146 is formed of polysilicon. In some embodiments, the masking layer 148 is formed of a dielectric material, such as silicon nitride (SiN). x Alternatively, other suitable dielectric materials may be used. In some embodiments where channel layer 146 is an n-type channel, it includes IGZO, ZnO, In2O3, SnO2, or the like. In some embodiments where channel layer 146 is a p-type channel, it includes NiO, Cu2O, CuAlO2, CuGaO2, CuInO2, SrCu2O2, SnO, or the like.

[0127] exist Figure 9 In this process, masking layer 148, channel layer 146, and gate dielectric layer 144 are patterned in one or more etching processes to form a patterned gate dielectric layer 145 above the BEOL transistor gate 142, a patterned channel layer 147 above the patterned gate dielectric layer 145, and a patterned masking layer 149. The BEOL transistor gate 142 and the patterned channel layer 147 together serve as BEOL transistor 150. In some embodiments, BEOL transistor 150 has source / drain regions electrically connected to the MTJ cell via conductive vias and wiring formed in subsequent processes. This configuration allows BEOL transistor 150 to be used as an access transistor for the MTJ cell. Compared to using FEOL transistors (e.g., FinFET 104) formed directly on substrate 102 as access transistors, BEOL transistor 150 provides a reduced distance to the MTJ cell. This shortened distance facilitates faster read and write operations, making it advantageous for high-speed memory applications. In some embodiments, such as Figure 9 As shown, one or more etching processes used to form the BEOL transistor 150 may also cause the dielectric layer 130 to extend laterally beyond a portion of the recess in the BEOL transistor 150. Therefore, the thickness of the dielectric layer 130 in the region directly below the gate dielectric layer 145 is greater than in the region not overlapping with the gate dielectric layer 145.

[0128] exist Figure 10 In this context, a dielectric layer 160 is formed above the BEOL transistor 150 and spans the memory region 100M and the logic region 100L. In some embodiments, the dielectric layer 160 includes materials such as tetraethyl orthosilicate (TEOS) oxide, silicon-free glass, or silicon-doped materials such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials having a different etch selectivity than the underlying dielectric layer 130.

[0129] exist Figure 11 In this process, an IMD layer 170 is formed above the dielectric layer 160. In some embodiments, the IMD layer 170 is made of an extremely low-k (ELK) dielectric material with a dielectric constant (k) of less than about 2.5. As technology nodes advance to 7nm and higher, and geometries shrink, ELK dielectric materials can be used to minimize device RC delay. In some embodiments, ELK dielectric materials include carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), or silicon-oxygen-carbon polymer (SiOC). In some embodiments, ELK dielectric materials include porous versions of existing dielectric materials, such as hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylene ether (PAE), porous SiLK, or porous silica (SiO2). In some embodiments, the ELK dielectric material is deposited by plasma-enhanced chemical vapor deposition (PECVD) or by spin-coating.

[0130] exist Figure 12 In the memory region 100M, a conductive via 13C and a conductive line 14C are formed in the IMD layer 170. In some embodiments, the IMD layer 170 can be patterned using appropriate lithography and etching techniques (e.g., anisotropic RIE using fluorocarbon chemistry) to form openings for vias and wiring. The opening for via 13C in the memory region 100M is a vertical hole extending through the IMD layer 170, the dielectric layer 160, and through the patterned mask 149 to the patterned channel layer 147. The opening for via 13C in the logic region 100L is a vertical hole extending through the IMD layer 170, the dielectric layers 160 and 130 to the conductive line 14B.

[0131] Several conductive materials can be deposited to fill the holes and trenches forming the conductive vias 13C and conductive lines 14C. In some embodiments, the conductive materials include, for example, TaN, TiN, W, Al, polysilicon, Ru, Co, Cu, combinations thereof, or the like. The openings may first be lined with a conductive diffusion barrier material, and then completely filled with a conductive filler material deposited over the conductive diffusion barrier liner. In some embodiments, a thin conductive seed layer may be deposited over the conductive diffusion barrier liner to help initiate an electrochemical plating (ECP) deposition step, which completely fills the openings with the conductive filler material.

[0132] The diffusion barrier conductive liner in the conductive via 13C and conductive line 14C comprises one or more layers of TaN, Ta, TiN, Ti, Co, the like, or combinations thereof. The conductive filler layer in the conductive via 13C and conductive line 14C may comprise a metal such as Cu, Al, W, Co, Ru, or the like, or combinations thereof, or multiple layers thereof. The conductive material used to form the conductive via 13C and conductive line 14C can be deposited by any suitable method, for example, CVD, PECVD, PVD, ALD, PEALD, ECP, electroless plating, and the like. In some embodiments, the conductive seed layer may be the same conductive material as the conductive filler layer and deposited using a suitable deposition technique (e.g., CVD, PECVD, ALD, PEALD, or PVD, or the like).

[0133] Any excess conductive material above the IMD layer 170 outside the opening can be removed by a planarization process (e.g., CMP) to form a top surface of a dielectric region containing the IMD layer 170 that is substantially coplanar with the conductive region of the conductive line 14C. The planarization step embeds the conductive via 13C and the conductive line 14C into the IMD layer 170, as... Figure 12 As shown.

[0134] exist Figure 13 In this process, another dielectric layer (also known as a dielectric barrier layer (SBL)) 180 is formed across the memory region 100M and the logic region 100L. In some embodiments, the dielectric layer 180 may include one or more dielectric materials, such as Si3N4, SiON, SiC, SiCN, or combinations thereof. The dielectric layer 180 may be formed by any suitable deposition process, such as spin-on coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), similar processes, or combinations thereof.

[0135] Next, another dielectric layer 190 is formed above the dielectric layer 180 and spans the memory region 100M and the logic region 100L. In some embodiments, the dielectric layer 190 includes materials such as tetraethyl orthosilicate (TEOS) oxide, silicon-free glass, or silicon-doped materials such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials having different etch selectivity than the underlying dielectric layer 180.

[0136] Next, another IMD layer 200 is formed above the dielectric layer 190. In some embodiments, the IMD layer 200 is made of an extremely low-k (ELK) dielectric material with a dielectric constant (k) of less than about 2.5. In some embodiments, the ELK dielectric material includes carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), or silicon-oxygen-carbon polymer (SiOC). In some embodiments, the ELK dielectric material includes porous versions of existing dielectric materials, such as hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane, porous polyarylene ether (PAE), porous SiLK, or porous silica (SiO2). In some embodiments, the ELK dielectric material is deposited by a plasma-enhanced chemical vapor deposition (PECVD) process or by a spin-on coating process.

[0137] exist Figure 14 In this process, a patterned mask P2 is formed above the IMD layer 120. In some embodiments, the patterned mask P2 is a patterned photoresist formed using a suitable lithography process. In an example lithography process, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. More specifically, a photomask or master photomask (not shown) may be placed on the photoresist material and then exposed to a radiation beam, which may be ultraviolet (UV) or an excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. For example, immersion lithography tools or extreme ultraviolet (EUV) tools may be used to expose the photoresist material to improve resolution and reduce the minimum achievable pitch. Baking or curing operations may be performed to harden the exposed photoresist material. Depending on whether a positive or negative resist is used, a developer can be used to remove exposed or unexposed portions of the photoresist material, leaving a patterned photoresist mask P2 above the IMD layer 200, in which openings O3 expose a portion of the IMD layer 200.

[0138] exist Figure 15In the etching process, the IMD layer 200 is patterned using a patterned mask P2 as an etching mask, thereby creating an opening O4 extending through the IMD layer 200, dielectric layers 190 and 180 to expose conductive lines 14C electrically connected to the source / drain regions of the BEOL transistor 150. The IMD layer 200 can be patterned using suitable etching techniques, such as wet etching, dry etching, or a combination thereof. After the opening O4 is formed in the dielectric IMD layer 200, the patterned mask P2 can be removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist is raised until the photoresist undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, can be used.

[0139] exist Figure 16A In this process, a bottom electrode layer 202, an MTJ layer 204, and a top electrode layer 206 are sequentially deposited into an opening O4 in an IMD layer 200. In some embodiments where the aspect ratio of the opening (i.e., the ratio of the opening depth to the opening width) is in the range of about 0.5 to about 2.5, a PVD process can be used to deposit the bottom electrode layer 202, the MTJ layer 204, and the top electrode layer 206. In some embodiments where the aspect ratio of the opening (i.e., the ratio of the opening depth to the opening width) is greater than about 2.5, an ALD process can be used to deposit the bottom electrode layer 202, the MTJ layer 204, and the top electrode layer 206. In some embodiments, the top width of the opening O4 is wider than the bottom width of the opening O4, which facilitates the deposition of the bottom electrode layer 202, the MTJ layer 204, and the top electrode layer 206 into the opening O4.

[0140] In some embodiments, a bottom electrode 202 is formed over the conductive line 14C and the IMD layer 200. The bottom electrode layer 202 is formed of a conductive material, such as titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), platinum (Pt), nickel (Ni), chromium (Cr), ruthenium (Ru), its nitrides, compositions thereof, or multilayers, or the like. The bottom electrode layer 202 can be deposited by conformal deposition processes, such as CVD, PVD, ALD, electrochemical plating, electroless plating, or the like.

[0141] In some embodiments, the MTJ layer 204 comprises MgO used as a tunneling barrier material, and Fe is mixed with Co, B, or Ni as a ferromagnetic material. In some embodiments, the MTJ layer 204 is a multilayer film stack, including, for example, an outer magnetic layer 204A, a tunneling barrier layer 204B, and an inner magnetic layer 204C sequentially formed above the bottom electrode layer 202. The outer magnetic layer 204A, the tunneling barrier layer 204B, and the inner magnetic layer 204C together form a magnetic tunnel junction (MTJ), and are therefore collectively referred to as MTJ layer 204 in some embodiments disclosed herein. Figure 16B As shown, Figure 16B yes Figure 16A Enlarged view of section 201.

[0142] In some embodiments, the outer magnetic layer 204A is a multilayer structure comprising an antiferromagnetic material (AFM) layer above the bottom electrode layer 202 and a ferromagnetic fixing layer above the AFM layer. In the antiferromagnetic material (AFM) layer, the magnetic moments of atoms (or molecules) are aligned in a regular pattern in opposite directions to the magnetic moments of adjacent atoms (or molecules). The net magnetic moment of the AFM layer is zero. In some embodiments, the AFM layer comprises platinum manganese (PtMn). In some embodiments, the AFM layer comprises iridium manganese (IrMn), rhodium manganese (RhMn), or iron manganese (FeMn). Exemplary methods for forming the AFM layer include sputtering, PVD, ALD, or similar methods.

[0143] The ferromagnetic fixing layer in the outer magnetic layer 204A forms a permanent magnet and exhibits strong interaction with the magnet. The direction of the magnetic moment of the ferromagnetic fixing layer can be pinned by an anti-ferromagnetic material (AFM) layer, and the direction of the magnetic moment does not change during operation of the resulting MTJ stack fabricated from MTJ layer 204, such as during write operations of the resulting MRAM cells. In some embodiments, the ferromagnetic fixing layer comprises cobalt iron boron (CoFeB). In some embodiments, the ferromagnetic fixing layer comprises CoFeTa, NiFe, Co, CoFe, CoPt, or an alloy of Ni, Co, and Fe. Exemplary methods for forming the ferromagnetic fixing layer include sputtering, PVD, or ALD. In some embodiments, the ferromagnetic fixing layer comprises a multilayer structure.

[0144] A tunneling barrier layer 204B is formed above the outer magnetic layer 204A. The tunneling barrier layer 204B, also referred to as a tunneling layer, is thin enough that electrons can tunnel through it when a bias voltage is applied to the resulting MTJ stack fabricated from the MTJ layer 204. In some embodiments, the tunneling barrier layer 204B comprises magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2), or zirconium oxide (ZrO2). Exemplary methods for forming the tunneling barrier layer 204B include sputtering, PVD, ALD, or similar methods.

[0145] An inner magnetic layer 204C is formed above the tunneling barrier layer 204B. In some embodiments, the inner magnetic layer 204C is a ferromagnetic free layer. More specifically, because there is no antiferromagnetic material in the inner magnetic layer 204C, the magnetic moment direction of the inner magnetic layer 204C is not pinned. Therefore, the magnetic orientation of this layer is adjustable, and thus this layer is called a free layer. In some embodiments, the magnetic moment direction of the inner magnetic layer 204C is freely rotatable, parallel or antiparallel to the pinned direction of the magnetic moment of the ferromagnetic fixed layer in the outer magnetic layer 204A. The inner magnetic layer 204C may include a ferromagnetic material similar to the material in the ferromagnetic fixed layer in the outer magnetic layer 204A. Since the inner magnetic layer 204C does not have an antiferromagnetic material, while the outer magnetic layer 204A has an antiferromagnetic material, the outer magnetic layer 204A and the inner magnetic layer 204C have different materials. In some embodiments, the inner magnetic layer 204C includes cobalt, nickel, iron, or boron. Exemplary methods for forming the inner magnetic layer 204C include sputtering, PVD, ALD, or the like. Although in the depicted embodiment, the ferromagnetic free layer 204C is the innermost layer in the MTJ layer 204, in some other embodiments, the MTJ layer 204 further includes an additional MgO layer above the free layer 204C, and a capping layer (e.g., TaN or TiN) above the additional MgO layer.

[0146] The resistance of the MTJ layer 204 varies according to the magnetic orientation of the outer magnetic layer 204A and the inner magnetic layer 204C, and this phenomenon is used to store data in the resulting MRAM cell. The outer magnetic layer 204A can be a permanent magnet with a fixed polarity, while the magnetic polarity of the inner magnetic layer 204C can be changed by applying an electric field. When the magnetization direction of the inner magnetic layer 204C matches (i.e., is parallel) to the magnetization direction of the outer magnetic layer 204A, the MRAM cell is in a low-resistance state. When the magnetization direction of the inner magnetic layer 204C is opposite to (i.e., is antiparallel) to the magnetization direction of the outer magnetic layer 204A, the MRAM cell is in a high-resistance state.

[0147] exist Figure 17A and Figure 17BIn this process, a planarization process (e.g., CMP) is used to remove excess portions of the bottom electrode layer 202, MTJ layer 204, and top electrode layer 206 outside the opening O4 in the IMD layer 200. This leaves a portion of the bottom electrode 202 in the opening O4 as the bottom electrode, a portion of the MTJ layer 204 in the opening O4 as the MTJ stack 214, and a portion of the top electrode layer 206 in the opening O4 as the top electrode. The bottom electrode 212, MTJ stack 214, and top electrode 216 together serve as the MTJ cell 211, wherein the bottom electrode 212 is electrically connected to the source / drain region in the patterned channel layer 147 of the BEOL transistor 150. In some embodiments, the MTJ cell 211 is also referred to as a memory cell, and the MTJ stack 214 serves as a resistance switching layer or element, having two resistance states depending on the magnetization direction of the free layers in the MTJ stack 214.

[0148] exist Figure 17A In some embodiments, the MTJ stack 214 has a lateral dimension W1 and a vertical dimension H1 greater than the lateral dimension W1. This vertical elongation of the MTJ stack 214 effectively increases the area of ​​the MTJ junctions in the vertical direction, thereby mitigating magnetoresistance variations and extending the lifetime of the MTJ cells 211 without compromising cell area. In some embodiments, the ratio of the vertical dimension H1 to the lateral dimension W1 of the MTJ stack 214 is greater than 2:1, 3:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1, depending on the ratio of the target MTJ junction area to the pitch of the MTJ cells 211. In some embodiments, the vertical dimension H1 of the MTJ stack 214 is higher than the vertical dimension H2 of the BEOL transistor 150, which is measured from the bottom surface of the gate structure 142 to the top surface of the patterned channel layer 147. In some embodiments, the lateral dimension W1 of the MTJ stack 214 is smaller than the lateral dimension W2 of the BEOL transistor 150, which is measured between opposite side surfaces of the patterned channel layer 147. As a result, the height-to-width ratio of the MTJ stack 214 is greater than that of the BEOL transistor 150.

[0149] In some embodiments, such as Figure 17BAs shown in the top view, the MTJ cell 211 and the BEOL transistor 150 are vertically overlapped, particularly the source / drain region 150S / D of the BEOL transistor 150, which is a portion of the patterned channel layer 147 extending beyond the gate structure 142. The MTJ cell 211 and the BEOL transistor 150 have overlapping footprints on the substrate 102. In this way, the resulting MRAM cell can have a reduced footprint on the substrate 102, thereby increasing the memory density on the IC structure 100. The memory density on the IC structure 100 refers to the amount of data storage capacity that can be packaged into a given physical area of ​​the IC structure 100. This overlapping configuration not only improves the utilization of available space but also enhances the performance characteristics of the MRAM cell. By reducing the distance between the MTJ cell 211 and the BEOL transistor 150, electrical connectivity is improved, thereby enabling faster read and write operations. In addition, this design reduces parasitic capacitance and resistance, promoting high-speed memory operation. Integrating the MTJ unit 211 with the BEOL transistor 150 in this compact manner also promotes better thermal management, as the heat generated during operation can be dissipated more effectively in a smaller footprint.

[0150] In some embodiments where the top width of opening O4 is wider than the bottom width of opening O4, such as... Figure 17C As shown, the top electrode 216 may have an inverted trapezoidal pattern with a bottom width and a top width greater than the bottom width. The MTJ stack 124 and the bottom electrode 212 have tapered sidewalls.

[0151] Next, in Figure 18 In this process, another IMD layer 220 is formed above IMD layer 200 and MTJ unit 211. In some embodiments, IMD layer 220 is made of an extremely low-k (ELK) dielectric material with a dielectric constant (k) less than about 2.5. In some embodiments, the ELK dielectric material includes carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), or silicon-oxygen-carbon polymer (SiOC). In some embodiments, the ELK dielectric material includes porous versions of existing dielectric materials, such as hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane, porous polyarylene ether (PAE), porous SiLK, or porous silica (SiO2). In some embodiments, the ELK dielectric material is deposited by plasma-enhanced chemical vapor deposition (PECVD) or by spin-coating.

[0152] exist Figure 19In the memory region 100M, conductive vias 13D and conductive lines 14D are formed in the IMD layer 220. In some embodiments, appropriate lithography and etching techniques (e.g., anisotropic RIE using fluorocarbon chemistry) can be used to pattern the IMD layers 220, 200, dielectric layers 190, and 180 to form openings for vias and wiring. The openings for vias 13D in the memory region 100M include vertical holes extending through the IMD layer 220 to the top electrode 216 of the MTJ cell 211, and vertical holes extending through the IMD layers 220, 200, and dielectric layers 190, 180 to the conductive line 14C. The openings for vias 13D in the logic region 100L are vertical holes extending through the IMD layers 220, 200, dielectric layers 190, and 130 to the conductive line 14C.

[0153] Several conductive materials can be deposited to fill the holes and trenches forming the conductive vias 13D and conductive lines 14D. The openings can first be lined with a conductive diffusion barrier material, and then completely filled with a conductive filler material deposited on top of the conductive diffusion barrier liner. In some embodiments, a thin conductive seed layer can be deposited on top of the conductive diffusion barrier liner to help initiate an electrochemical plating (ECP) deposition step, in which the openings are completely filled with conductive filler material.

[0154] The diffusion barrier conductive liner in the conductive via 13D and conductive line 14D comprises one or more layers of TaN, Ta, TiN, Ti, Co, the like, or combinations thereof. The conductive filler layer in the conductive via 13C and conductive line 14C may comprise a metal such as Cu, Al, W, Co, Ru, or the like, or combinations thereof, or multiple layers thereof. The conductive material used to form the conductive via 13D and conductive line 14D can be deposited by any suitable method, for example, CVD, PECVD, PVD, ALD, PEALD, ECP, electroless plating, and the like. In some embodiments, the conductive seed layer may be the same conductive material as the conductive filler layer and deposited using a suitable deposition technique (e.g., CVD, PECVD, ALD, PEALD, or PVD, or the like).

[0155] Any excess conductive material above the IMD layer 220 outside the opening can be removed by a planarization process (e.g., CMP) to form a top surface of a dielectric region containing the IMD layer 220 that is substantially coplanar with the conductive region of the conductive line 14D. The planarization step embeds the conductive via 13D and the conductive line 14D into the IMD layer 220, as... Figure 19 As shown.

[0156] In some embodiments, such as Figure 19As shown, the MTJ layer 214 and the bottom electrode 212 form a first interface, wherein the first interface includes a first portion IF1 extending toward the substrate in a vertical direction and a second portion IF2 extending in a lateral direction different from the vertical direction. The first portion IF1 of the first interface is larger than the second portion IF2 of the first interface. Figure 19 In the cross-sectional view shown, the ratio of the length of the first portion IF1 to the length of the second portion IF2 is greater than the aspect ratio of the BEOL transistor 150 (i.e., the ratio of the vertical dimension H2 to the lateral dimension W2 of the BEOL transistor 150). The MTJ layer 214 and the top electrode 216 form a second interface. The second interface includes a third portion IF3 extending vertically toward the substrate and a fourth portion IF4 extending laterally, wherein the third portion IF3 of the second interface is larger than the fourth portion IF4 of the second interface.

[0157] Figure 20 A cross-sectional view of another example IC structure 100A according to some embodiments of the present disclosure is shown. IC structure 100A includes... Figure 19 The IC structure 100 shown is essentially the same, except that both the bottom electrode 212 and the top electrode 216 are multilayer electrodes. Specifically, the bottom electrode 212 is a double-layer electrode, including a first metal layer 212A and a second metal layer 212B disposed above the first metal layer 212A. The first metal layer 212A and the second metal layer 212B are formed of different metal materials. For example, the first metal layer 212A may include a diffusion barrier metal, such as titanium nitride or tantalum nitride, and the second metal layer 212B may include a metal with a lower resistance than the first metal layer 212A. Similarly, the top electrode 216 includes a first metal layer 216A and a second metal layer 216B disposed above the first metal layer 216A. The first metal layer 216A and the second metal layer 216B are formed of different metal materials.

[0158] Figures 21 to 24 A cross-sectional view illustrating an intermediate stage in forming an example integrated circuit structure 100B having one or more MRAM cells according to some embodiments of the present disclosure. Figure 21 The IC structure 100B includes and Figure 12The IC structure 100A shown is substantially the same, except that the bottom electrode 310 is formed above the conductive line 14C. In some embodiments, the bottom electrode 310 is formed, for example, by depositing a metal layer over the entire memory region 100M and logic region 100L, and then patterning the metal layer into the bottom electrode 310 using suitable lithography and etching techniques. In some embodiments, the bottom electrode 310 is formed of a conductive material, such as titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), platinum (Pt), nickel (Ni), chromium (Cr), ruthenium (Ru), its nitrides, combinations thereof, or multilayers, or the like.

[0159] exist Figure 22 In this configuration, an MTJ stack 312 is formed above the bottom electrode 310, and a top electrode 314 is formed above the MTJ stack 312. In some embodiments, the MTJ stack 312 and the top electrode 314 are formed by, for example, sequentially depositing an MTJ layer and a top electrode layer across the memory region 100M and the logic region 100L, and then patterning the MTJ layer and the top electrode layer into the MTJ stack 312 and the top electrode 314 using suitable lithography and etching techniques. The bottom electrode 310, the MTJ stack 312, and the top electrode 314 are collectively referred to as MTJ cell 320. The materials of the MTJ layer and the top electrode layer may be the same as the materials of the MTJ layer 204 and the top electrode layer 206 previously described with respect to Figure 16A, and therefore will not be repeated for the sake of brevity.

[0160] exist Figure 23 In this configuration, dielectric layers 330 and 340 are sequentially formed over MTJ cell 320 and IMD layer 170. In some embodiments, dielectric layer 330 is also referred to as dielectric barrier layer (SBL) and may include one or more dielectric materials, such as Si3N4, SiON, SiC, SiCN, or combinations thereof, in various embodiments. In some embodiments, dielectric layer 340 is formed over dielectric layer 330 and spans memory region 100M and logic region 100L. In some embodiments, dielectric layer 340 includes materials such as tetraethyl orthosilicate (TEOS) oxide, silicon-free glass, or silicon-doped materials such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials having a different etch selectivity than the underlying dielectric layer 330.

[0161] exist Figure 24In this process, an IMD layer 350 is formed above the dielectric layer 340. In some embodiments, the IMD layer 350 is made of an extremely low-k (ELK) dielectric material with a dielectric constant (k) of less than about 2.5. In some embodiments, the ELK dielectric material includes carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), or silicon-oxygen-carbon polymer (SiOC). In some embodiments, the ELK dielectric material includes porous versions of existing dielectric materials, such as hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane, porous polyarylene ether (PAE), porous SiLK, or porous silica (SiO2). In some embodiments, the ELK dielectric material is deposited by a plasma-enhanced chemical vapor deposition (PECVD) process or by a spin-coating process.

[0162] Next, conductive vias 13D and conductive lines 14D are formed in the IMD layer 350. In some embodiments, suitable lithography and etching techniques (e.g., anisotropic RIE using fluorocarbon chemistry) can be used to pattern the IMD layer 350, dielectric layers 340, and 330 to form openings for vias and wiring. The openings for vias 13D in the memory region 100M include vertical holes extending through the IMD layer 350 to the top electrode 314 of the MTJ cell 320, and vertical holes extending through the IMD layer 350 and dielectric layers 340 and 330 to the conductive line 14C. The openings for vias 13D in the logic region 100L are vertical holes extending through the IMD layer 350, dielectric layers 340 and 330 to the conductive line 14C.

[0163] Figure 25 A cross-sectional view of another example IC structure 100C according to some embodiments of the present disclosure is shown. IC structure 100C includes... Figure 24 The IC structure 100B shown is essentially the same, except that both the bottom electrode 310 and the top electrode 314 are multilayer electrodes. Specifically, the bottom electrode 310 is a double-layer electrode, including a first metal layer 310A and a second metal layer 310B disposed above the first metal layer 310A. The first metal layer 310A and the second metal layer 310B are formed of different metal materials. For example, the first metal layer 310A may include a diffusion barrier metal, such as titanium nitride or tantalum nitride, and the second metal layer 310B may include a metal with a lower resistance than the first metal layer 310A. Similarly, the top electrode 314 includes a first metal layer 314A and a second metal layer 314B disposed above the first metal layer 314A. The first metal layer 314A and the second metal layer 314B are formed of different metal materials.

[0164] In some embodiments, the double-layer bottom electrode 310 is formed, for example, by forming a sacrificial dielectric layer with an opening in the memory region 100M, sequentially depositing a first metal layer 310A and a second metal layer 310B in the opening, removing portions of the first metal layer 310A and the second metal layer 310B outside the opening by a CMP process, and then removing the sacrificial dielectric layer. In some embodiments, the double-layer top electrode 314 is formed, for example, by sequentially depositing a first metal layer 314A and a second metal layer 314B above the bottom electrode 310, and then patterning the first metal layer 314A and the second metal layer 314B by a suitable lithography and etching process.

[0165] Figure 26 A cross-sectional view of another example IC structure 100D according to some embodiments of the present disclosure is shown. IC structure 100D includes... Figure 19 The IC structure 100 shown is essentially the same, except that the cross-sectional profile of the BEOL transistor 150A is the same. Figure 19 The BEOL transistor 150 shown is different. In some embodiments, in Figure 7 Following the steps shown, a selective etch-back process is used to recess the dielectric layer 130, causing the BEOL gate 142 to protrude from the top surface of the recessed dielectric layer 130. As a result, since the gate dielectric layer 145, channel layer 147, and hard mask layer 149 are deposited on the protruding portion of the BEOL gate 142, these layers can have an inverted U-shaped profile covering at least three sides of the protruding portion of the BEOL gate 142. This configuration improves the drive capability of the BEOL transistor 150A.

[0166] In some embodiments, such as Figure 26 As shown, the channel layer 147 has a lower portion 147L that laterally surrounds the sidewall of the BEOL gate 142, and a raised portion 147E that rises above the top surface of the BEOL gate 142. A conductive via 13C is disposed above the source / drain region in the lower portion 147L of the channel layer 147. This configuration reduces leakage current caused by the increased distance between the conductive via 13C and the BEOL gate 142.

[0167] Figure 27 A cross-sectional view of another example IC structure 100E according to some embodiments of the present disclosure is shown. IC structure 100E includes... Figure 26 The IC structure 100D shown is essentially the same, except that the BEOL transistor 150B has the same... Figure 26 The diagram shows different cross-sectional profiles of the BEOL transistor 150A. For example, as... Figure 27 As shown, the gate dielectric layer 145, the channel layer 147, and the masking layer 149 do not extend horizontally beyond the sidewall of the BEOL gate 142.

[0168] Based on the above discussion, it can be seen that this disclosure provides advantages in various embodiments. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor is any specific advantage required for all embodiments. One advantage is that the MTJ junction area can be increased without increasing the MTJ cell footprint. Another advantage is that magnetoresistance variation can be mitigated due to the increased MTJ junction area. Yet another advantage is that the lifetime and retention time of the MTJ cell can be improved due to the increased MTJ junction area.

[0169] In some embodiments, a method includes the following steps: Forming a metal interconnect structure (e.g., conductive vias 13C and wiring 14C) within a first dielectric layer (e.g., IMD layer 170) above a substrate. Forming a second dielectric layer (e.g., IMD layer 200) above the first metal interconnect structure. Etching an opening (e.g., opening O4) in the second dielectric layer and over a portion of the first metal interconnect structure. Depositing a bottom electrode layer (e.g., layer 202) in the opening. Depositing a magnetic tunnel junction (MTJ) layer (e.g., layer 204) in the opening and over the bottom electrode layer. Depositing a top electrode layer (e.g., layer 206) in the opening and over the MTJ layer. Removing a portion of the top electrode layer, MTJ layer, and bottom electrode layer outside the opening in the second dielectric layer to form a top electrode (e.g., top electrode 216), an MTJ stack (e.g., MTJ stack 214), and a bottom electrode (e.g., bottom electrode 212) within the opening in the second dielectric layer. In some embodiments, the top electrode layer is deposited until the opening in the second dielectric layer is overfilled by the top electrode layer. In some embodiments, the opening O4 in the second dielectric layer has a width and a depth greater than the width. In some embodiments, the top electrode 216 has a width and a height greater than the width. In some embodiments, the MTJ stack 214 forms an interface with the top electrode 216, and the interface extends further in the vertical direction than in the lateral direction. In some embodiments, the MTJ stack 214 forms an interface with the bottom electrode 212, and the interface extends further in the vertical direction than in the lateral direction. In some embodiments, portions of the top electrode layer, MTJ layer, and bottom electrode layer outside the opening in the second dielectric layer are removed in a chemical mechanical polishing (CMP) process. In some embodiments, the method further includes forming a transistor (e.g., a BEOL transistor 150, 150A, or 150B) before forming a metal interconnect, the transistor having a gate (e.g., a BEOL gate 142) above the substrate and a channel layer (e.g., a channel layer 147) above the gate. In some embodiments, the channel layer covers at least three sides of the gate.

[0170] In some embodiments, a method includes the following steps: Forming a first transistor (e.g., FinFET 104) over a substrate. Forming a first interconnect structure (e.g., conductive line 14B) over the first transistor. Forming a second transistor (e.g., BEOL transistor 150) over the first interconnect structure. The second transistor includes a gate structure and a channel layer over the gate structure. Forming a second interconnect structure (e.g., conductive line 14C) over the second transistor. Forming a memory cell (e.g., MTJ cell 211 or 320) over the second interconnect structure. The memory cell is electrically connected to the second transistor via the second interconnect structure. The channel layer of the second transistor is below the memory cell and above the gate structure of the second transistor. In some embodiments, the memory cell includes an MTJ layer (e.g., MTJ layer 214 or 312) between two electrodes, the MTJ layer extending further in the vertical direction than in the lateral direction. In some embodiments, the memory cell includes an MTJ layer (e.g., MTJ layer 214) between two electrodes (e.g., bottom electrode 212 and top electrode 216), and the MTJ layer has a U-shaped cross-sectional profile. In some embodiments, the memory cell comprises an MTJ layer (e.g., MTJ layer 312) between two electrodes (e.g., bottom electrode 310 and top electrode 314), and the MTJ layer has an inverted U-shaped cross-sectional profile. In some embodiments, forming the memory cell comprises forming a dielectric layer (e.g., IMD layer 200) over a first interconnect structure, forming an opening (e.g., opening O4) in the dielectric layer, and then forming a memory cell (e.g., MTJ cell 211) in the opening in the dielectric layer. In some embodiments, forming the memory cell comprises forming a bottom electrode (e.g., bottom electrode 310) over a first interconnect structure, forming an MTJ layer (e.g., MTJ layer 312) surrounding the bottom electrode, and forming a top electrode (e.g., top electrode 314) surrounding the MTJ layer. In some embodiments, the memory cell (e.g., MTJ cell 211 or 320) is vertically overlapped with a second transistor (e.g., BEOL transistor 150).

[0171] In some embodiments, a memory cell includes a first transistor, a second transistor above the first transistor, and a memory cell above the first transistor. The memory cell (e.g., MTJ cell 211 or 320) includes a bottom electrode (e.g., bottom electrode 212 or 310), a resistor switching layer above the bottom electrode (e.g., MTJ layer 214 or 312), and a top electrode above the resistor switching layer (e.g., top electrode 216 or 314). The resistor switching layer and the bottom electrode form a first interface. The first interface includes a first portion extending toward the substrate in a first direction and a second portion extending in a second direction different from the first direction. In a cross-sectional view, the ratio of the length of the first portion of the first interface to the length of the second portion of the first interface is greater than the aspect ratio of the second transistor. The first portion of the first interface is larger than the second portion of the first interface. In some embodiments, the resistor switching layer and the top electrode form a second interface. The second interface includes a third portion extending toward the substrate in a first direction and a fourth portion extending in a second direction different from the first direction. The third portion of the second interface is larger than the fourth portion of the second interface. In some embodiments, the memory device further includes a second transistor (e.g., BEOL transistor 150, 150A, or 150B) that is above the first transistor and electrically connected to the memory cell. In some embodiments, the second transistor has a gate (e.g., BEOL transistor 150) and a channel layer (e.g., channel layer 147) above the gate and below the memory cell.

[0172] In some embodiments, a memory device includes a first transistor on a substrate; a first interconnect structure above the first transistor; a second transistor above the first interconnect structure, wherein the second transistor includes a gate structure and a channel layer above the gate structure; a second interconnect structure above the second transistor; and a memory cell above the second interconnect structure, the memory cell being electrically connected to the second transistor via the second interconnect structure, wherein the channel layer of the second transistor is below the memory cell and above the gate structure of the second transistor. In some embodiments, the memory cell includes a magnetic tunneling junction layer between two electrodes, the magnetic tunneling junction layer extending further in a vertical direction than in a lateral direction. In some embodiments, the memory cell includes a magnetic tunneling junction layer between two electrodes, and the magnetic tunneling junction layer has a U-shaped cross-sectional profile. In some embodiments, the memory cell includes a magnetic tunneling junction layer between two electrodes, and the magnetic tunneling junction layer has an inverted U-shaped cross-sectional profile.

[0173] In some embodiments, a memory device includes a first transistor on a substrate; a first interconnect structure above the first transistor; a second transistor above the first interconnect structure, wherein the second transistor includes a gate structure and a channel layer above the gate structure; a second interconnect structure above the second transistor; and a memory cell above the second interconnect structure, the memory cell being electrically connected to the second transistor through the second interconnect structure, wherein the memory cell is perpendicularly overlapped with the second transistor. The memory cell includes a bottom electrode above the first interconnect structure, a magnetic tunneling junction layer surrounding the bottom electrode, and a top electrode surrounding the magnetic tunneling junction layer.

[0174] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, characterized in that, Include: A first transistor is located above a substrate; A second transistor, above the first transistor; and A memory cell is located above a first transistor and a second transistor. The memory cell includes a bottom electrode, a resistor switching layer above the bottom electrode, and a top electrode above the resistor switching layer. The resistor switching layer and the bottom electrode form a first interface. The first interface includes a first portion extending toward the substrate in a first direction and a second portion extending in a second direction different from the first direction. The first portion of the first interface is larger than the second portion of the first interface. In a cross-sectional view, the ratio of the length of the first portion of the first interface to the length of the second portion of the first interface is greater than the aspect ratio of the second transistor.

2. The memory device as claimed in claim 1, characterized in that, The resistor switching layer and the top electrode form a second interface. The second interface includes a third portion extending toward the substrate in the first direction and a fourth portion extending in the second direction, which is different from the first direction. The third portion of the second interface is larger than the fourth portion of the second interface.

3. The memory device as claimed in claim 1, characterized in that, The second transistor is electrically connected to the memory cell.

4. The memory device as claimed in claim 3, characterized in that, The second transistor has a gate and a channel layer above the gate and below the memory cell.

5. A memory device, characterized in that, Include: A first transistor is on a substrate; A first interconnect structure is located above the first transistor; A second transistor is disposed above the first interconnect structure, wherein the second transistor includes a gate structure and a channel layer above the gate structure; A second interconnect structure is located above the second transistor; and A memory cell is located above the second interconnect structure and is electrically connected to the second transistor via the second interconnect structure, wherein the channel layer of the second transistor is below the memory cell and above the gate structure of the second transistor.

6. The memory device as claimed in claim 5, characterized in that, The memory cell contains a magnetic tunneling junction layer between two electrodes, which extends further in a vertical direction than in a lateral direction.

7. The memory device as claimed in claim 5, characterized in that, The memory cell contains a magnetic tunneling interface layer between two electrodes, and the magnetic tunneling interface layer has a U-shaped profile.

8. The memory device as claimed in claim 5, characterized in that, The memory cell contains a magnetic tunneling interface layer between two electrodes, and the magnetic tunneling interface layer has an inverted U-shaped profile.

9. A memory device, characterized in that, Include: A first transistor is on a substrate; A first interconnect structure is located above the first transistor; A second transistor is disposed above the first interconnect structure, wherein the second transistor includes a gate structure and a channel layer above the gate structure; A second interconnect structure is located above the second transistor; and A memory cell is located above the second interconnect structure and is electrically connected to the second transistor via the second interconnect structure, wherein the memory cell and the second transistor are vertically overlapped.

10. The memory device as claimed in claim 9, characterized in that, The memory cell includes a bottom electrode above the first interconnect structure, a magnetic tunneling surface layer surrounding the bottom electrode, and a top electrode surrounding the magnetic tunneling surface layer.

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