Capacitor Structure

Abstract

A capacitor structure is configured to store charge associated with photocurrent generated by a pixel sensor in a pixel sensor array of an image sensor device. The capacitor structure may include a bottom electrode layer and a top electrode layer arranged alternately and separated by an insulating layer. The ends of the bottom electrode layer facing the top contact structure are etched to separate the ends of the bottom electrode layer from the top contact structure. Similarly, the ends of the top electrode layer facing the bottom contact structure are etched to separate the ends of the top electrode layer from the bottom contact structure.

Description

Technical Field

[0001] This disclosure pertains to a capacitor structure. Background Technology

[0002] A complementary metal-oxide-semiconductor (CMOS) image sensor may include multiple pixel sensors arranged in a pixel sensor array. Each pixel sensor in a CMOS image sensor may include a photodiode configured to convert photons of incident light into electrons of a photocurrent. The magnitude of the photocurrent depends at least in part on the intensity of the incident light. Therefore, if the pixel sensors in the pixel sensor array can sense incident light over a wide intensity range, images and / or images with high brightness and contrast can be generated in a CMOS image sensor. Utility Model Content

[0003] Some embodiments of this disclosure provide a capacitor structure. The capacitor structure includes a first electrode layer, a second electrode layer, an insulating layer, a first contact structure, and a second contact structure. The first electrode layer extends along a plurality of sidewalls and the bottom surface of a trench, wherein a first end of the first electrode layer extends laterally outward from a first side of the trench. The second electrode layer extends along the sidewalls and the bottom surface of the trench, wherein a second end of the second electrode layer extends laterally outward from a second side of the trench. An insulating layer is located between the first electrode layer and the second electrode layer. The first contact structure contacts the first end of the first electrode layer. The second contact structure contacts the second end of the second electrode layer.

[0004] Some embodiments of this disclosure provide a capacitor structure. The capacitor structure includes a first electrode layer, a second electrode layer, an insulating layer, a first contact structure, and a second contact structure. The first electrode layer extends along a first sidewall and a bottom surface of a trench. The second electrode layer extends along a second sidewall and a bottom surface of the trench. The insulating layer is located between the first electrode layer and the second electrode layer. The first contact structure is located on and contacts a first end of the first electrode layer. The second contact structure is located on and contacts a second end of the second electrode layer.

[0005] Some embodiments of this disclosure provide a capacitor structure. The capacitor structure includes a dielectric layer with trenches, a metal-insulator-metal layer stack, a first contact structure, and a second contact structure. The metal-insulator-metal layer stack is located in the trenches of the dielectric layer. The metal-insulator-metal layer stack includes a first electrode layer, an insulating layer on the first electrode layer, and a second electrode layer on the insulating layer. A first end of the first electrode layer extends laterally outward from a first side of the trench along the top surface of the dielectric layer, and a second end of the second electrode layer extends laterally outward from a second side of the trench along the top surface of the dielectric layer. The first contact structure contacts the first end of the first electrode layer. The second contact structure contacts the second end of the second electrode layer. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the detailed description below by reading in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features may not be drawn to scale. In fact, for clarity, the scale of various features may be arbitrarily increased or decreased.

[0007] Figure 1A and Figure 1B This is a schematic diagram of an exemplary circuit of the pixel sensor described in this disclosure;

[0008] Figure 2 This is a schematic diagram of an exemplary capacitor structure described in this disclosure;

[0009] Figures 3A to 3L This is a schematic diagram of an exemplary embodiment of the capacitor structure described in this disclosure;

[0010] Figure 4 This is a schematic diagram of an exemplary capacitor structure described in this disclosure;

[0011] Figures 5A to 5C This is a schematic diagram of an exemplary embodiment of the capacitor structure described in this disclosure;

[0012] Figure 6 This is a schematic diagram of an exemplary capacitor structure described in this disclosure;

[0013] Figures 7A to 7C This is a schematic diagram of an exemplary embodiment of the capacitor structure described in this disclosure;

[0014] Figure 8 This is a schematic diagram of an exemplary capacitor structure described in this disclosure;

[0015] Figures 9A to 9J This is a schematic diagram of an exemplary embodiment of the capacitor structure described in this disclosure;

[0016] Figure 10 This is a schematic diagram of an exemplary semiconductor device described in this disclosure;

[0017] Figure 11 This is a schematic diagram of an exemplary semiconductor device described in this disclosure;

[0018] Figure 12 This is a schematic diagram of an exemplary semiconductor device described in this disclosure;

[0019] Figures 13A to 13C This is a schematic top view of an exemplary layout of the overflow capacitor described in this disclosure;

[0020] Figure 14 This is a flowchart of an exemplary process related to forming the capacitor structure described in this disclosure.

[0021] [Symbol Explanation]

[0022] 100: Pixel sensor

[0023] 102: Photodiode

[0024] 102a: Photodiode

[0025] 102b: Photodiode

[0026] 104: Transfer Gate

[0027] 104a: Transfer gate

[0028] 104b: Transfer gate

[0029] 106: Floating Diffusion Node

[0030] 106a: Floating diffusion node

[0031] 106b: Floating diffusion node

[0032] 108: Reset Gate

[0033] 110: Voltage source

[0034] 112: Overflow gate

[0035] 112a: Overflow gate

[0036] 112b: Overflow gate

[0037] 114: Overflow capacitor

[0038] 114a: Overflow capacitor

[0039] 114b: Overflow capacitor

[0040] 116: Source follower gate

[0041] 118: Row Select Gate

[0042] 200: Capacitor Structure

[0043] 202: Trench

[0044] 204: Dielectric layer

[0045] 206: First electrode layer

[0046] 206a: First electrode layer

[0047] 206a-1: Section

[0048] 206a-2: Section

[0049] 206b: First electrode layer

[0050] 206b-1: Section

[0051] 206b-2: Section

[0052] 208: Second electrode layer

[0053] 208a: Second electrode layer

[0054] 208a-1: Section

[0055] 208a-2: Section

[0056] 208b: Second electrode layer

[0057] 208b-1: Section

[0058] 208b-2: Section

[0059] 210: Insulation layer

[0060] 210a: Insulation layer

[0061] 210b: Insulation layer

[0062] 210c: Insulation layer

[0063] 212: Dielectric layer

[0064] 214: First contact structure

[0065] 216: Second contact structure

[0066] 218: Air gap

[0067] 220: Air gap

[0068] 300: Implementation Method

[0069] 302: Metal-Insulator-Metal Stack

[0070] 304: Masking layer

[0071] 306: Opening

[0072] 308: Groove

[0073] 310: Shielding layer

[0074] 312: Opening

[0075] 314: Groove

[0076] 400: Capacitor Structure

[0077] 402: Barrier Layer

[0078] 404: Barrier Layer

[0079] 500: Implementation Method

[0080] 600: Capacitor Structure

[0081] 602: Insulating plug

[0082] 604: Insulating plug

[0083] 700: Implementation Method

[0084] 800: Capacitor Structure

[0085] 802: Dielectric interstitial material

[0086] 804: Dielectric interstitial material

[0087] 806: Dielectric Etching Stop Layer

[0088] 900: Implementation Method

[0089] 902: Masking layer

[0090] 904: Groove

[0091] 906: Shielding layer

[0092] 908: Groove

[0093] 1000: Semiconductor Devices

[0094] 1002: Pixel sensor array

[0095] 1004: Black level correction area

[0096] 1006: Joint Pad Area

[0097] 1008: Sealing ring area

[0098] 1010: Device Layer

[0099] 1012: Interconnection Layer

[0100] 1014: Dielectric region

[0101] 1016: Metallized Structure

[0102] 1018: Interconnection Structure

[0103] 1020: Passivation layer

[0104] 1100: Semiconductor Device

[0105] 1102: Pixel sensor array

[0106] 1104: Black level correction area

[0107] 1106: Joint Pad Area

[0108] 1108: Sealing ring area

[0109] 1110: Device Layer

[0110] 1112: Interconnection Layer

[0111] 1114: Dielectric region

[0112] 1116: Metallized Structure

[0113] 1118: Interconnection Structure

[0114] 1120a: First semiconductor die

[0115] 1120b: Second semiconductor die

[0116] 1122: Joint interface

[0117] 1124: Device Layer

[0118] 1126: Integrated Circuit Device

[0119] 1128: Interconnection Layer

[0120] 1130: Dielectric region

[0121] 1132: Metallized structure

[0122] 1134: Interconnection Structure

[0123] 1136: Joint pad

[0124] 1138: Joint pad

[0125] 1140: Connecting through hole

[0126] 1142: Connecting through hole

[0127] 1200: Semiconductor Device

[0128] 1202: Pixel sensor array

[0129] 1204: Black level correction area

[0130] 1206: Joint Pad Area

[0131] 1208: Sealing ring area

[0132] 1210: Device Layer

[0133] 1212: Interconnection Layer

[0134] 1214: Dielectric region

[0135] 1216: Metallized Structure

[0136] 1218: Interconnection Structure

[0137] 1220a: First semiconductor die

[0138] 1220b: Second semiconductor die

[0139] 1222: Joint interface

[0140] 1224: Device Layer

[0141] 1226: Integrated circuit device

[0142] 1228: Interconnection Layer

[0143] 1230: Dielectric region

[0144] 1232: Metallized Structure

[0145] 1234: Interconnection Structure

[0146] 1236: Joint pad

[0147] 1238: Joint pad

[0148] 1240: Connecting through hole

[0149] 1242: Connecting through hole

[0150] 1300: Layout

[0151] 1302: Layout

[0152] 1304: Layout

[0153] 1400: Process

[0154] 1410: Square

[0155] 1420: Square

[0156] 1430: Square

[0157] 1440: Square

[0158] 1450: Square

[0159] 1460: Square

[0160] D1: Dimensions

[0161] D2: Size

[0162] D3: Size

[0163] D4: Dimensions

[0164] D5: Size

[0165] D6: Size

[0166] x: direction

[0167] z: direction Detailed Implementation

[0168] The following disclosure provides many different implementations or examples for achieving different features of the provided object. To simplify this disclosure, specific examples of elements and configurations are described below. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, forming a first feature on or over a second feature may include implementations where the first and second features are formed through direct contact, or implementations where additional features may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various implementations and / or configurations discussed.

[0169] Furthermore, for ease of description, this disclosure may use spatially relative terms, such as "below," "below," "down," "above," "over," etc., to describe the relationship between one element or feature and another element or feature in the figure. Spatially relative terms are intended to include different orientations of the device during use or operation, other than those depicted in the figure. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0170] In some cases, the number of photons of incident light absorbed by a pixel sensor may be limited before the pixel sensor reaches saturation. "Saturation" refers to the level of photon absorption at which a pixel sensor can no longer absorb any more photons. Because it is impossible to obtain additional brightness and color information by absorbing more photons, pixel sensor saturation limits the dynamic range of the pixel sensor.

[0171] The amount of photocurrent charge that can be stored in a pixel sensor before saturation is reached is called the full-well capacity (FWC) of the pixel sensor. The full-well capacity of a pixel sensor may depend at least in part on the size (e.g., depth, width, volume) and / or shape of the photodiode in the pixel sensor. However, while increasing the size of the photodiode may increase the full-well capacity of the pixel sensor, it may reduce the pixel sensor density in the pixel sensor array at the cost of this, resulting in a decrease in the resolution of the pixel sensor array.

[0172] In some embodiments described in this disclosure, the image sensor device (e.g., a complementary metal-oxide-semiconductor (CMOS) image sensor device) includes a capacitor structure configured to store charge associated with the photocurrent generated by the pixel sensors in the pixel sensor array of the image sensor device. The photocurrent can be transferred from the pixel sensor to the capacitor structure, allowing the pixel sensor to generate more charge for the photocurrent than would be stored entirely in the photodiodes and / or floating diffusion nodes of the pixel sensor. Therefore, the capacitor structure increases the full-well capacity of the pixel sensor, thereby enabling a higher range of brightness and / or contrast in the images and / or pictures generated by the pixel sensor array.

[0173] The capacitor structure is formed using the techniques described in this disclosure to achieve a small lateral footprint. The capacitor structure may include a metal-insulator-metal (MIM) layer stack, wherein bottom and top electrode layers are alternately arranged and separated by an insulating layer. The bottom contact structure of the bottom electrode layer and the top contact structure of the top electrode layer are formed laterally adjacent to opposite ends of the MIM stack, rather than having individual contacts on the top surfaces of individual electrode layers (which would otherwise increase the lateral dimensions of the capacitor structure). To electrically isolate the bottom electrode layer from the top contact structure, the end of the bottom electrode layer facing the top contact structure is etched, thus separating the end of the bottom electrode layer from the top contact structure. Similarly, the end of the top electrode layer facing the bottom contact structure is etched, thus separating the end of the top electrode layer from the bottom contact structure. In this way, the bottom contact structure of the bottom electrode layer and the top contact structure of the top electrode layer can be formed laterally near opposite ends of the MIM stack, resulting in a more compact lateral footprint for the capacitor structure. Therefore, the image sensor device may include a higher density capacitor structure to increase the full-well capacity of the pixel sensor in the image sensor device.

[0174] Figure 1A and Figure 1B This is a schematic diagram of an exemplary circuit for a pixel sensor 100 as described in this disclosure. The pixel sensor 100 may include a front-side pixel sensor (e.g., a pixel sensor configured to receive photons from the front side of a sensor die), a rear-side pixel sensor (e.g., a pixel sensor configured to receive photons from the rear side of a sensor die), and / or other types of pixel sensors.

[0175] like Figure 1A As shown in the exemplary circuit, pixel sensor 100 includes a photodiode 102, which can be configured to sense and / or collect incident light (e.g., light directed toward pixel sensor 100) and convert photons of the incident light into a photocurrent. The magnitude of the photocurrent can be based on the number of photons collected in photodiode 102 (e.g., the intensity of the incident light). Therefore, the accumulation of photons in photodiode 102 produces an accumulation of charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a larger intensity or brightness, while a smaller amount of charge may correspond to a smaller intensity or brightness).

[0176] Photodiode 102 is electrically connected to transfer gate 104. Transfer gate 104 is configured to control the transfer of photocurrent from photodiode to floating diffusion node 106. A transfer voltage (V) can be applied to transfer gate 104. tx The transmission gate 104 is selectively switched. In some embodiments, the transmission voltage applied to the transmission gate 104 causes a leakage path (e.g., a buried channel) to be formed between the photodiode 102 and the floating diffusion node 106 across the transmission gate 104, thus causing photocurrent to travel along the leakage path to the floating diffusion node 106. In some embodiments, removing the transmission voltage from the transmission gate 104 (or in the absence of a transmission voltage) removes the leakage path and prevents photocurrent from being transmitted from the photodiode 102 to the floating diffusion node 106.

[0177] The circuitry for the pixel sensor 100 may also include a reset gate 108. The reset gate 108 is electrically connected to a voltage source 110. The reset gate 108 can be controlled to selectively apply a reset voltage (V) from the voltage source 110 to the floating diffusion node 106. rst The transfer gate 104 and the reset gate 108 may be electrically coupled to the floating diffusion node 106 such that a reset voltage may be applied to the floating diffusion node 106 to “reset” the floating diffusion node 106 (e.g., by depleting any residual charge in the floating diffusion node 106) before the transfer gate 104 is activated to transfer photocurrent from the photodiode 102 to the floating diffusion node 106.

[0178] Pixel sensor 100 may be a lateral overflow integration capacitor (LOFIC) pixel sensor, and this pixel sensor includes an overflow gate 112 and an overflow capacitor 114. The overflow capacitor 114 can be electrically coupled to the floating diffusion node 106 through the overflow gate 112, allowing photocurrent to be transferred from the floating diffusion node 106 to the overflow capacitor 114 for temporary storage. The overflow gate 112 can selectively control the photocurrent flowing into and / or out of the overflow capacitor 114. This allows additional photocurrent to be transferred from the photodiode 102 to the floating diffusion node 106 without saturating the pixel sensor 100, thereby increasing the full-well capacity and dynamic range of the pixel sensor 100.

[0179] Photocurrent can be used to convert floating diffusion voltage (V)fd The source follower gate 116 is applied to the circuitry of the pixel sensor 100. This allows the photocurrent to be observed without removing or discharging the photocurrent from the floating diffusion node 106 and / or the overflow capacitor 114. The reset gate 108 can be used to remove or discharge the photocurrent from the floating diffusion node 106 and / or the overflow capacitor 114.

[0180] To apply a floating diffusion voltage to the source follower gate 116, the transfer gate 104 can be turned off (e.g., to prevent photocurrent from flowing back to the photodiode 102) and the overflow gate 112 can be turned on. This configuration allows the photocurrent stored in the floating diffusion node 106 and the overflow capacitor 114 to be used to apply the floating diffusion voltage to the source follower gate 116.

[0181] The source follower gate 116 serves as a high-impedance amplifier for the pixel sensor 100. The source follower gate 116 provides voltage-to-current conversion for the floating diffused voltage. The output of the source follower gate 116 is electrically connected to the row select gate 118, which is configured to control the photocurrent flowing to external circuitry. The row select gate 118 selectively applies a selection voltage (V... di The photocurrent is applied to the gate of the row selection gate 118 and controlled. This allows the photocurrent to flow to the output of the pixel sensor 100.

[0182] like Figure 1B As shown in another exemplary circuit, the pixel sensor 100 may include multiple sub-circuits. The sub-circuits may include small pixel sub-circuits and large pixel sub-circuits. The small pixel sub-circuit may include a small photodiode 102a, a transmission gate 104a, a floating diffusion node 106a, an overflow gate 112a, and an overflow capacitor 114a. The large pixel sub-circuit may include a large photodiode 102b, a transmission gate 104b, a floating diffusion node 106b, an overflow gate 112b, and an overflow capacitor 114b. Both the small and large pixel sub-circuits may be connected to a reset gate 108, a voltage source 110, a source follower gate 116, and a row select gate 118. The large photodiode 102b may be physically larger than the small photodiode 102a, thereby allowing the pixel sensor 100 to have different photon sensitivity regions.

[0183] As mentioned above, Figure 1A and Figure 1B Provided as an example. Other examples may be provided. Figure 1A and Figure 1B The descriptions are different.

[0184] Figure 2 This is a schematic diagram of an exemplary capacitor structure 200 described in this disclosure. The capacitor structure 200 may include an embodiment of an exemplary structure of the overflow capacitor 114 in the pixel sensor 100 described in this disclosure.

[0185] like Figure 2 As shown, the capacitor structure 200 extends into a trench 202 formed in the dielectric layer 204. Therefore, the capacitor structure 200 can be referred to as a trench capacitor structure. The dielectric layer 204 may correspond to an interlayer dielectric (ILD) layer, an intermetallic dielectric (IMD) layer, an etch stop layer (ESL), another type of dielectric layer, or a combination thereof. The dielectric layer 204 may comprise an oxide material with a low dielectric constant (low k value), such as silicon oxide (SiO2). x The dielectric layer 204 may comprise undoped silicate glass (USG), boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or other suitable low-k dielectric materials. Additionally and / or optionally, dielectric layer 204 may comprise a dielectric material having an extremely low dielectric constant (ELK) of less than about 2.5. Examples of dielectric materials with extremely low dielectric constants include carbon-doped silicon oxide (C-SiO₂). x ), amorphous fluorinated carbon (α-C) x F y ), parylene, bis-benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbide (SiOC) polymers, porous hydrogen silsesquioxanes, porous methyl silsesquioxanes (MSQ), porous polyarylethers (PAE), and / or porous silica (SiO2).x Additionally and / or alternatively, dielectric layer 204 may comprise a dielectric material with a high dielectric constant (high k-value), such as silicon nitride (Si). x N y Silicon carbide (SiC), silicon oxynitride (SiON), hafnium oxide (HfO) x ) and / or other suitable high-k dielectric materials.

[0186] The trench 202 may have a vertical (direction z) depth (in Figure 2 The dimension D1 and the width in the horizontal direction (x) are indicated by the standard. Figure 2 (The dimension is indicated as D2). In some embodiments, the vertical depth of trench 202 ranges from approximately 0.23 micrometers to approximately 0.27 micrometers. However, other values ​​and ranges are also within the scope of this disclosure. In some embodiments, the lateral width of trench 202 ranges from approximately 0.19 micrometers to approximately 0.21 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0187] In some embodiments, trench 202 may have a high aspect ratio, i.e., the ratio of its vertical depth (dimension D1) to its lateral width (dimension D2). In these embodiments, capacitor structure 200 may be referred to as a deep trench capacitor (DTC) structure. In some embodiments, the aspect ratio of trench 202 (e.g., the ratio of dimension D1 to dimension D2) may be approximately 10:1 or greater. In some embodiments, the aspect ratio of trench 202 may include a range from approximately 20:1 to approximately 50:1. However, other values ​​and ranges are also within the scope of this disclosure.

[0188] like Figure 2As further shown, the capacitor structure includes multiple first electrode layers 206 (e.g., bottom electrode layers or capacitor bottom metal (CBM) layers), multiple second electrode layers 208 (e.g., top electrode layers or capacitor top metal (CTM) layers), and multiple insulating layers 210. The first electrode layers 206, second electrode layers 208, and insulating layers 210 are configured in a metal-insulator-metal stack within the capacitor structure 200. The metal-insulator-metal stack includes repeated arrangements of the first electrode layers 206, the insulating layers 210 on the first electrode layers 206, and the second electrode layers 208 on the insulating layers 210. For example, the first electrode layer 206a may be located on the sidewall and bottom of the trench 202, the insulating layer 210a may be located on the first electrode layer 206a, the second electrode layer 208a may be located on the insulating layer 210a, another insulating layer 210b may be located on the second electrode layer 208a, another first electrode layer 206b may be located on the insulating layer 210b, another insulating layer 210c may be located on the first electrode layer 206b, and another second electrode layer 208b may be located on the insulating layer 210c. Figure 2 The number of first electrode layers 206, the number of second electrode layers 208, and the number of insulating layers 210 shown are examples; other numbers are also within the scope of this disclosure.

[0189] The first electrode layer 206, the second electrode layer 208, and the insulating layer 210 may each include a conformal layer that conforms to the contour of the trench 202. In other words, the first electrode layer 206, the second electrode layer 208, and the insulating layer 210 may each extend along the sidewalls and bottom surface of the trench 202. The remaining area in the trench 202 may be filled by the dielectric layer 212.

[0190] The first electrode layer 206 and the second electrode layer 208 may each have a thickness ranging from approximately 200 angstroms to approximately 500 angstroms. However, other ranges of values ​​are also within the scope of this disclosure. The first electrode layer 206 and the second electrode layer 208 may include one or more conductive materials, such as molybdenum (Mo), chromium (Cr), titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), aluminum (Al), gold (Au), silver (Ag), cobalt (Co), copper (Cu), ruthenium (Ru), platinum (Pt), and / or other suitable conductive materials. The insulating layer 210 may include one or more low-k dielectric materials, one or more high-k dielectric materials, and / or another type of electrically insulating material. Examples include zirconium oxide (ZrO). x For example, ZrO2), aluminum oxide (Al) x O y For example, Al2O3), silicon nitride (Si) x Ny For example, Si3N4), yttrium oxide (Y) x O y For example, Y2O3), lanthanum oxide (La) x O y For example, La2O3) and / or hafnium oxide (HfO) x For example, HfO2). In some embodiments, each insulating layer 210 includes a multilayer stack containing multiple dielectric layers. For example, insulating layer 210 may include a ZrO2 / Al2O3 / ZrO2 (ZAZ) layer stack.

[0191] like Figure 2 As further shown, the first electrode layer 206, the second electrode layer 208, and the insulating layer 210 may extend over the trench 202 in the z-direction and laterally outward from the trench in the x-direction. A portion of the first electrode layer 206 extending laterally outward from the trench 202 along the surface of the dielectric layer 204 may be electrically connected and / or physically connected to the first contact structure 214. Specifically, the end of the portion of the first electrode layer 206 extending laterally outward from the trench 202 along the surface of the dielectric layer 204 may be electrically connected and / or physically connected to one side of the first contact structure 214. A portion of the second electrode layer 208 extending laterally outward from the trench 202 along the surface of the dielectric layer 204 may be electrically connected and / or physically connected to the second contact structure 216. Specifically, the end of the portion of the second electrode layer 208 extending laterally outward from the trench 202 along the surface of the dielectric layer 204 may be electrically connected and / or physically connected to one side of the second contact structure 216.

[0192] The first contact structure 214 and the second contact structure 216 may be laterally located on opposite sides of the trench 202. Therefore, the end of the first electrode layer 206 may be electrically connected and / or physically connected to the first contact structure 214 on the first side of the trench 202, and the end of the second electrode layer 208 may be electrically connected and / or physically connected to the second contact structure 216 on the second side of the trench 202 opposite to the first side. The first contact structure 214 and the second contact structure 216 may each have a vertical (direction z) height (in... Figure 2 The dimension is indicated as D3, and the height is within the range of approximately 0.7 micrometers to approximately 0.8 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0193] On the first side of the trench 202, an air gap 218 is included between the end of the second electrode layer 208 and the side of the first contact structure 214, so that the second electrode layer 208 and the first contact structure 214 are electrically isolated from each other at the first end. On the second side of the trench 202, an air gap 220 is included between the end of the first electrode layer 206 and the side of the second contact structure 216, so that the first electrode layer 206 and the second contact structure 216 are electrically isolated from each other at the second end.

[0194] The electrical isolation provided by the air gap 218 allows the first electrode layer 206 to couple to the side of the first contact structure 214, rather than having each contact disposed on its own first electrode layer 206. Similarly, the electrical isolation provided by the air gap 220 allows the second electrode layer 208 to couple to the side of the second contact structure 216, rather than having each contact disposed on its own second electrode layer 208. Therefore, the overall lateral dimension of the capacitor structure 200 (in Figure 2 The dimension (D4) can be smaller than that of having each contact structure disposed on its respective first electrode layer 206 and its respective second electrode layer 208, because the contact structures have minimum spacing limitations. For example, the total lateral width (dimension D4) of the capacitor structure 200 can range from about 1 micrometer to about 2 micrometers, while the total lateral width of a capacitor structure having each contact structure disposed on the electrode layers can range from about 7 micrometers to about 8 micrometers. Other values ​​and ranges of the lateral width of the capacitor structure 200 are also within the scope of this disclosure.

[0195] In some embodiments, the lateral width of the air gap 218 (in) Figure 2 The lateral width (denoted as D5) is within the range of approximately 0.2 micrometers to approximately 0.4 micrometers. If the lateral width of the air gap 218 is less than approximately 0.2 micrometers, the possibility of leakage between the second electrode layer 208 and the first contact structure 214 may increase. If the lateral width of the air gap 218 is greater than approximately 0.4 micrometers (e.g., the end of the second electrode layer 208 is further cut back to increase the lateral width of the air gap 218), the capacitance of the capacitor structure 200 may decrease, and / or if the lateral width of the air gap 218 is greater than approximately 0.4 micrometers (e.g., the first contact structure 214 is moved away from the trench 202 to increase the lateral width of the air gap 218), the total lateral width of the capacitor structure 200 may increase. If the lateral width of the air gap 218 is within the range of approximately 0.2 micrometers to approximately 0.4 micrometers, sufficient electrical isolation can be provided between the second electrode layer 208 and the first contact structure 214, and a high capacitance and a small lateral footprint can be achieved for the capacitor structure 200. However, other values ​​for the lateral width of the air gap 218, and ranges from about 0.2 micrometers to about 0.4 micrometers, are also within the scope of this disclosure.

[0196] In some embodiments, the lateral width of the air gap 220 (in Figure 2 The dimension (D6) is within the range of approximately 0.2 micrometers to approximately 0.4 micrometers. If the lateral width of the air gap 220 is less than approximately 0.2 micrometers, the possibility of leakage between the first electrode layer 206 and the second contact structure 216 may increase. If the lateral width of the air gap 220 is greater than approximately 0.4 micrometers (e.g., the end of the first electrode layer 206 is further cut back to increase the lateral width of the air gap 220), the capacitance of the capacitor structure 200 may decrease, and / or if the lateral width of the air gap 220 is greater than approximately 0.4 micrometers (e.g., the second contact structure 216 is moved away from the trench 202 to increase the lateral width of the air gap 220), the total lateral width of the capacitor structure 200 may increase. If the lateral width of the air gap 220 is within the range of approximately 0.2 micrometers to approximately 0.4 micrometers, sufficient electrical isolation can be provided between the first electrode layer 206 and the second contact structure 216, and a high capacitance and a small lateral footprint can be achieved for the capacitor structure 200. However, other values ​​for the lateral width of the air gap 220, and ranges from about 0.2 micrometers to about 0.4 micrometers, are also within the scope of this disclosure.

[0197] In some embodiments, air gaps 218 and 220 are filled with a dielectric gas, such as air. In some embodiments, air gaps 218 and 220 are filled with an electrically inert gas, such as an inert gas (e.g., argon (Ar) or helium (He)). In some embodiments, the dielectric constant of air gaps 218 and 220 may be approximately 1. In some embodiments, air gaps 218 and 220 may have a dielectric constant ranging from approximately 1 to approximately 2. However, other values ​​and ranges are also within the scope of this disclosure.

[0198] Therefore, the capacitor structure 200 may include a plurality of first electrode layers 206 and a plurality of second electrode layers 208 extending along the sidewalls and bottom surface of the trench 202, wherein the first electrode layers 206 and second electrode layers 208 are alternately disposed in the trench 202. A plurality of first ends of the first electrode layers 206 extend laterally outward from a first side of the trench 202, and a plurality of second ends of the second electrode layers 208 extend laterally outward from a second side of the trench 202 (e.g., opposite to the first side). The capacitor structure 200 may include a first contact structure 214 contacting a first end of the first electrode layer 206, and a second contact structure 216 contacting a second end of the second electrode layer 208. An air gap 218 is formed between a plurality of third ends (e.g., opposite to the second ends) of the second electrode layer 208 and the first contact structure 214, such that the second electrode layers 208 and the first contact structure 214 are spaced apart from each other. The air gap 220 is between a plurality of fourth ends (e.g., opposite to the first end) of the first electrode layer 206 and the second contact structure 216, such that the first electrode layer 206 and the second contact structure 216 are spaced apart from each other.

[0199] As mentioned above, Figure 2 Provided as an example. Other examples may be provided. Figure 2 The descriptions are different.

[0200] Figures 3A to 3L This is a schematic diagram of an exemplary embodiment 300 that forms the capacitor structure 200 described herein. In some embodiments, with Figures 3A to 3L One or more related semiconductor processing operations may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, wafer / die transfer tools and / or other types of semiconductor processing tools.

[0201] like Figure 3A As shown, trench 202 can be formed in dielectric layer 204. In some embodiments, a pattern of photoresist is used to etch dielectric layer 204 to form trench 202. In these embodiments, a photoresist layer can be formed on dielectric layer 204 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch dielectric layer 204 based on the pattern to form trench 202. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0202] Optionally, one or more hard mask layers may be formed on the dielectric layer 204, and the pattern of the photoresist layer may be transferred onto the hard mask layer(s). The dielectric layer 204 may be etched using an etching tool based on the pattern in the hard mask layer (alone or in combination with the pattern of the photoresist layer) to form the trench 202.

[0203] In some embodiments, the etching operation includes a dry etching operation. For example, trench 202 can be formed by performing a plasma-based etching operation, a gas-based etching operation, and / or other types of dry etching operations. In some embodiments, trench 202 is formed using dry etching techniques, such as reactive ion etching (RIE) or deep reactive ion etching (sometimes referred to as the "Bosch process"), to achieve high vertical sidewalls and minimal sidewall slope of trench 202. Additionally and / or alternatively, wet chemical etching operations and / or other types of etching operations can be performed to form trench 202. The angle between the sidewalls of trench 202 and the bottom surface of the trench can be approximately 90 degrees. Alternatively, the angle between the sidewalls of trench 202 and the bottom surface of the trench can be a reentrant angle (e.g., <90 degrees) or a retrograde angle (e.g., >90 degrees).

[0204] like Figure 3B As shown, a metal-insulator-metal layer stack 302 forms the capacitor structure 200. A portion of the metal-insulator-metal layer stack 302 is formed in a trench 202 such that the first electrode layer 206, the second electrode layer 208, and the insulating layer 210 of the metal-insulator-metal layer stack 302 are conformally oriented to the sidewalls and bottom surface of the trench 202. Other formed portions of the metal-insulator-metal layer stack 302 extend laterally outward from the trench 202 along the top surface of the dielectric layer 204. The metal-insulator-metal layer stack 302 may resemble an inverted Ω (omega) shape. In some embodiments, the ends of the metal-insulator-metal layer stack 302 are etched to define the lateral width (or length) of the capacitor structure 200.

[0205] In some embodiments, conformal deposition techniques such as chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) can be used to deposit the first electrode layer 206, the second electrode layer 208, and the insulating layer 210 of the metal-insulator-metal layer stack 302. One or more deposition tools can be used to deposit the first electrode layer 206a on the sidewalls and bottom of the trench 202 (and along the top surface of the dielectric layer 204), deposit the insulating layer 210a on the first electrode layer 206a, deposit the second electrode layer 208a on the insulating layer 210a, deposit the insulating layer 210b on the second electrode layer 208a, deposit the first electrode layer 206b on the insulating layer 210b, deposit the insulating layer 210c on the first electrode layer 206b, and / or deposit the second electrode layer 208b on the insulating layer 210c.

[0206] like Figure 3C As shown, the remaining area in trench 202 can be filled with dielectric layer 212. Dielectric layer 212 can also be deposited on metal-insulator-metal layer stack 302. Dielectric layer 212 can be deposited using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques via deposition tools. Dielectric layer 212 can be deposited in one or more deposition operations. In some embodiments, planarization tools can be used to perform planarization operations (e.g., chemical mechanical planarization (CMP) operations) to planarize dielectric layer 212 after deposition.

[0207] like Figure 3D and Figure 3E As shown, a mask layer 304 can be formed and patterned on the dielectric layer 212. In some embodiments, the mask layer 304 includes a photoresist layer. In these embodiments, the mask layer 304 can be formed on the dielectric layer 212 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques), the mask layer 304 can be exposed to a radiation source using an exposure tool to pattern the mask layer 304, and portions of the mask layer 304 can be developed and removed using a development tool to expose the pattern. In some embodiments, the mask layer 304 includes a hard mask layer, and its pattern is formed in the mask layer 304 using a patterned photoresist layer. The pattern in the mask layer 304 may include an opening 306 located at the end of the metal-insulator-metal layer stack 302.

[0208] like Figure 3FAs shown, an etching tool can be used to etch the ends of the first electrode layer 206, the second electrode layer 208, and the insulating layer 210 of the metal-insulator-metal layer stack 302 based on the openings 306 in the mask layer 304 to form a groove 308. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations.

[0209] like Figure 3G As shown, another etching operation is performed to etch the ends of the first electrode layer 206 exposed in the groove 308 to form an air gap 220. The etching operation may include a wet chemical etching operation, wherein the wet etchant used selectively etches the ends of the first electrode layer 206, but etches very little or nothing at the ends of the second electrode layer 208, the ends of the insulating layer 210, and the dielectric layer 212. Therefore, the etching rate of the wet etchant on the material of the first electrode layer 206 is greater than the individual etching rates of the wet etchant on the materials of the second electrode layer 208, the insulating layer 210, and the dielectric layer 212.

[0210] For example, the material of the first electrode layer 206 may include chromium (Cr), the material of the second electrode layer 208 may include molybdenum (Mo), and the material of the insulating layer 210 may include alumina (Al2O3). A chromium wet etchant comprising a mixture of perchloric acid (HClO4) and ceric ammonium nitrate ((NH4)2[Ce(NO3)6]) can be used to etch the first electrode layer 206. The etching rate of the chromium wet etchant on the chromium of the first electrode layer 206 can be about 36 times to about 16,000 times greater than the etching rate of the chromium wet etchant on the molybdenum of the second electrode layer 208 and the alumina of the insulating layer 210. However, other types of etchants and other etching rate ranges are also within the scope of this disclosure.

[0211] As another example, the material of the first electrode layer 206 may include gold (Au), the material of the second electrode layer 208 may include titanium nitride (TiN), and the material of the insulating layer 210 may include silicon nitride (Si3N4). A gold wet etchant comprising a mixture of nitric acid (HNO3) and hydrochloric acid (HCl) can be used to etch the first electrode layer 206. In some embodiments, the mixture of nitric acid and hydrochloric acid is diluted in water (H2O). The etching rate of the gold wet etchant on the gold of the first electrode layer 206 is at least about 1,300 times greater than the etching rate of the gold wet etchant on the titanium nitride of the second electrode layer 208 and the silicon nitride of the insulating layer 210. However, other types of etchants and other etching rate ranges are also within the scope of this disclosure.

[0212] After the end of the first electrode layer 206 is etched back, the remaining portion of the mask layer 304 can be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0213] like Figure 3H As shown, the groove 308 is filled by another shielding layer 310, and the shielding layer 310 is also formed on the dielectric layer 212. The shielding layer 310 can be formed in a similar manner to the shielding layer 304, and an opening 312 is formed on the opposite side of the trench 202 in a similar manner to the opening 306, passing through the shielding layer 310 and at the end of the metal-insulator-metal layer stack 302.

[0214] like Figure 3I As shown, an etching tool can be used to etch the ends of the first electrode layer 206, the second electrode layer 208, and the insulating layer 210 of the metal-insulator-metal layer stack 302 based on the openings 312 in the mask layer 310 to form a groove 314. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations.

[0215] like Figure 3J As shown, another etching operation is performed to etch the ends of the second electrode layer 208 exposed in the groove 314 to form an air gap 218. The etching operation may include a wet chemical etching operation, wherein the wet etchant used selectively etches the ends of the second electrode layer 208, but etches very little or nothing at the ends of the first electrode layer 206, the insulating layer 210, and the dielectric layer 212. Therefore, the etching rate of the wet etchant on the material of the second electrode layer 208 is greater than the individual etching rates of the wet etchant on the materials of the first electrode layer 206, the insulating layer 210, and the dielectric layer 212.

[0216] For example, the material of the first electrode layer 206 may include chromium (Cr), the material of the second electrode layer 208 may include molybdenum (Mo), and the material of the insulating layer 210 may include alumina (Al2O3). A molybdenum wet etchant including nitric acid (HNO3) can be used to etch the second electrode layer 208. In some embodiments, the molybdenum wet etchant includes a mixture of nitric acid and ammonium fluoride (NH4F) diluted in water (H2O). The etching rate of the molybdenum wet etchant on the molybdenum of the second electrode layer 208 can be about 90 to about 200 times greater than the etching rate of the molybdenum wet etchant on the chromium of the first electrode layer 206 and the alumina of the insulating layer. However, other types of etchants and other etching rate ranges are also within the scope of this disclosure.

[0217] As another example, the material of the first electrode layer 206 may include gold (Au), the material of the second electrode layer 208 may include titanium nitride (TiN), and the material of the insulating layer 210 may include silicon nitride (Si3N4). A titanium nitride wet etchant, including hydrofluoric acid (HF), can be used to etch the second electrode layer 208. The etching rate of the titanium nitride in the second electrode layer 208 by the titanium nitride wet etchant is at least about 180 times greater than the etching rate of the gold in the first electrode layer 206 and the silicon nitride in the insulating layer 210. However, other types of etchants and other etching rate ranges are also within the scope of this disclosure.

[0218] like Figure 3K As shown, after the end of the second electrode layer 208 is etched back, the remaining portion of the mask layer 310 can be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0219] like Figure 3L As shown, grooves 308 and 314 are filled with the materials of the second contact structure 216 and the first contact structure 214, respectively. After groove 308 is filled, the sidewall of the second contact structure 216 is physically coupled to the end of the second electrode layer 208 exposed through groove 308, and the air gap 220 is maintained between the sidewall of the second contact structure 216 and the end of the first electrode layer 206. After groove 314 is filled, the sidewall of the first contact structure 214 is physically coupled to the end of the first electrode layer 206 exposed through groove 314, and the air gap 218 is maintained between the sidewall of the first contact structure 214 and the end of the second electrode layer 208.

[0220] Deposition tools can be used to deposit the first contact structure 214 and the second contact structure 216. In some embodiments, physical vapor deposition (PVD) is used to deposit the first contact structure 214 and the second contact structure 216. PVD can result in lower step coverage compared to other deposition techniques (e.g., chemical vapor deposition), so little or no material of the first contact structure 214 is deposited into the air gap 218, and little or no material of the second contact structure 216 is deposited into the air gap 220. However, other deposition techniques can be used to deposit the first contact structure 214 and / or the second contact structure 216.

[0221] The first contact structure 214 and the second contact structure 216 may be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the first contact structure 214 and / or the second contact structure 216 is deposited on the seed layer. In some embodiments, a liner (e.g., an adhesive liner, a barrier liner) is deposited first, and the first contact structure 214 and / or the second contact structure 216 is deposited on the liner. The liner may include tantalum nitride (TaN) liner, titanium nitride (TiN) liner, and / or other types of liner. In some embodiments, after depositing the first contact structure 214 and the second contact structure 216, a planarization operation (e.g., a chemical mechanical planarization operation) is performed using a planarization tool to planarize the first contact structure 214 and the second contact structure 216.

[0222] As mentioned above, Figures 3A to 3L Provided as an example. Other examples may be provided. Figures 3A to 3L The descriptions differ from those in the text.

[0223] Figure 4 This is a schematic diagram of an exemplary capacitor structure 400 described in this disclosure. The capacitor structure 400 may include an embodiment of the exemplary structure of the overflow capacitor 114 in the pixel sensor 100 described in this disclosure. Figure 4 As shown, capacitor structure 400 includes a combination and arrangement of layers and / or elements similar to those in capacitor structure 200. However, capacitor structure 400 also includes a barrier layer 402 between air gap 218 and first contact structure 214, and / or a barrier layer 404 between air gap 220 and second contact structure 216.

[0224] The barrier layer 402 may be located between the ends of vertically adjacent insulating layers 210 and may provide structural support for the ends of insulating layers 210 and the first electrode layer 206. The barrier layer 402 may include conductive materials such as tantalum nitride (TaN) and / or titanium nitride (TiN) and may effectively expand the area of ​​the first contact structure 214, thereby reducing the contact resistance of the first contact structure 214.

[0225] Similarly, barrier layer 404 may be located between the ends of vertically adjacent insulating layers 210, and may provide structural support for the ends of insulating layers 210 and the second electrode layer 208, and / or provide additional electrical isolation between the end of the first electrode layer 206 and the second contact structure 216. Barrier layer 404 may include conductive materials such as tantalum nitride (TaN) and / or titanium nitride (TiN), and may effectively expand the area of ​​the second contact structure 216, thereby reducing the contact resistance of the second contact structure 216.

[0226] As mentioned above, Figure 4 Provided as an example. Other examples may be provided. Figure 4The descriptions are different.

[0227] Figures 5A to 5C This is a schematic diagram of an exemplary embodiment 500 that forms the capacitor structure 400 described herein. In some embodiments, with Figures 5A to 5C One or more related semiconductor processing operations may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, wafer / die transfer tools and / or other types of semiconductor processing tools.

[0228] like Figure 5A As shown, executable with Figures 3A to 3K Similar processing operations are performed to form trench 202, form a metal-insulator-metal layer stack 302 including a first electrode layer 206, a second electrode layer 208, and an insulating layer 210, and form a dielectric layer 212. Furthermore, it is possible to perform operations related to... Figures 3A to 3K Similar processing operations are performed to form grooves 308 and 314, to etch the end of the second electrode layer 208 to form an air gap 218, and to etch the end of the first electrode layer 206 to form an air gap 220.

[0229] like Figure 5B As shown, barrier layers 402 and 404 can be formed in grooves 314 and 308, respectively. Deposition tools can be used to deposit barrier layers 402 and 404 using conformal deposition techniques (e.g., chemical vapor deposition and / or atomic layer deposition). Thus, barrier layer 402 conforms to the sidewalls and bottom surface of groove 314 and extends into air gap 218. Similarly, barrier layer 404 conforms to the sidewalls and bottom surface of groove 308 and extends into air gap 220.

[0230] like Figure 5C As shown, the first contact structure 214 is subsequently deposited on the barrier layer 402 in the groove 314, and the second contact structure 216 is deposited on the barrier layer 404 in the groove 308. The first contact structure 214 and the second contact structure 216 can be deposited through a process similar to... Figure 3L The method of deposition and planarization is described.

[0231] As mentioned above, Figures 5A to 5C Provided as an example. Other examples may be provided. Figures 5A to 5C The descriptions differ from those in the text.

[0232] Figure 6 This is a schematic diagram of an exemplary capacitor structure 600 described in this disclosure. The capacitor structure 600 may include an embodiment of the exemplary structure of the overflow capacitor 114 in the pixel sensor 100 described in this disclosure. Figure 6As shown, capacitor structure 600 includes a combination and arrangement of layers and / or elements similar to those in capacitor structure 200. However, in capacitor structure 600, air gap 218 is filled with insulating plug 602, and air gap 220 is filled with insulating plug 604.

[0233] An insulating plug 602 is physically in contact with both the end of the second electrode layer 208 and the sidewall of the first contact structure 214. Similarly, an insulating plug 604 is physically in contact with both the end of the first electrode layer 206 and the sidewall of the second contact structure 216. The insulating plug 602 prevents material from the first contact structure 214 from depositing at the end of the second electrode layer 208 (and adheres to the upper end), and the insulating plug 604 prevents material from the second contact structure 216 from depositing at the end of the first electrode layer 206 (and adheres to the upper end).

[0234] In some embodiments, insulating plugs 602 and 604 comprise one or more dielectric materials. In some embodiments, insulating plugs 602 and 604 comprise one or more self-assembled monolayers (SAMs) formed from one or more organosilane compounds and / or one or more organosilane derivatives. For example, insulating plugs 602 and 604 may each comprise one or more self-assembled monolayers formed from organosilanes including chlorides or alkoxides.

[0235] As mentioned above, Figure 6 Provided as an example. Other examples may be provided. Figure 6 The descriptions are different.

[0236] Figures 7A to 7C This is a schematic diagram of an exemplary embodiment 700 forming the capacitor structure 600 described herein. In some embodiments, with Figures 7A to 7C One or more related semiconductor processing operations may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, wafer / die transfer tools and / or other types of semiconductor processing tools.

[0237] like Figure 7A As shown, executable with Figures 3A to 3K Similar processing operations are performed to form trench 202, form a metal-insulator-metal layer stack 302 including a first electrode layer 206, a second electrode layer 208, and an insulating layer 210, and form a dielectric layer 212. Furthermore, it is possible to perform operations related to... Figures 3A to 3KSimilar processing operations are performed to form grooves 308 and 314, to etch the end of the second electrode layer 208 to form an air gap 218, and to etch the end of the first electrode layer 206 to form an air gap 220.

[0238] like Figure 7B As shown, insulating plugs 602 and 604 can be formed in grooves 314 and 308, respectively. Insulating plugs 602 and 604 can be deposited using deposition tools via deposition techniques such as chemical vapor deposition and / or atomic layer deposition. Thus, the material of insulating plugs 602 and 604 can be deposited into air gaps 218 and 220, respectively.

[0239] like Figure 7C As shown, the first contact structure 214 is subsequently deposited in the groove 314, and the second contact structure 216 is deposited in the groove 308. The first contact structure 214 and the second contact structure 216 can be deposited in a manner similar to... Figure 3L The method of deposition and planarization is described. Insulating plug 602 prevents material of the first contact structure 214 from depositing at the end of the second electrode layer 208, and insulating plug 604 prevents material of the second contact structure 216 from depositing at the end of the first electrode layer 206.

[0240] As mentioned above, Figures 7A to 7C Provided as an example. Other examples may be provided. Figures 7A to 7C The descriptions differ from those in the text.

[0241] Figure 8 This is a schematic diagram of an exemplary capacitor structure 800 described in this disclosure. The capacitor structure 800 may include an embodiment of an exemplary structure of the overflow capacitor 114 in the pixel sensor 100 described in this disclosure.

[0242] like Figure 8 As shown, the capacitor structure 800 extends into the trench 202 in the dielectric layer 204 and includes a first electrode layer 206, a second electrode layer 208, an insulating layer 210, a dielectric layer 212, a first contact structure 214, and a second contact structure 216 similar to those in capacitor structures 200, 400, and 600.

[0243] A first segment of the first electrode layer 206 may extend along the first sidewall of the trench 202, and a second segment of the first electrode layer 206 may extend along the bottom surface of the trench 202. For example, segments 206a-1 and 206b-1 of the first electrode layers 206a and 206b may extend along the first sidewall of the trench 202, and segments 206a-2 and 206b-2 of the first electrode layers 206a and 206b may extend along the bottom surface of the trench 202.

[0244] A first segment of the second electrode layer 208 may extend along a second sidewall opposite to the first sidewall of the trench 202, and a second segment of the second electrode layer 208 may extend along the bottom surface of the trench 202. For example, segments 208a-1 and 208b-1 of the second electrode layers 208a and 208b may extend along the second sidewall of the trench 202, and segments 208a-2 and 208b-2 of the second electrode layers 208a and 208b may extend along the bottom surface of the trench 202. Therefore, the second electrode layer 208 may have an approximately L-shaped cross-sectional profile, and the first electrode layer 206 may have an approximately mirror-image L-shaped cross-sectional profile.

[0245] The ends of segments 206a-1 and 206b-1 of the first electrode layers 206a and 206b, respectively, are approximately coplanar with the top of the trench 202, and the first contact structure 214 can physically contact the ends of segments 206a-1 and 206b-1. Similarly, the ends of segments 208a-1 and 208b-1 of the second electrode layers 208a and 208b, respectively, are approximately coplanar with the top of the trench 202, and the second contact structure 216 can physically contact the ends of segments 208a-1 and 208b-1. The first contact structure 214, located above the trench 202 and directly at the top of the end of the first electrode layer 206, and the second contact structure 216, located above the trench 202 and directly at the top of the end of the second electrode layer 208, allow the lateral width of the capacitor structure 800 to be further reduced.

[0246] To electrically isolate the second electrode layer 208 from the first contact structure 214, a dielectric spacer 802 is included between the first contact structure 214 and the ends of segments 208a-2 and 208b-2 of the second electrode layers 208a and 208b. The dielectric spacer 802 may be formed as part of the process of forming the dielectric layer 212 and may include a material composed of the same material as the dielectric layer 212. To electrically isolate the first electrode layer 206 from the second contact structure 216, a dielectric spacer 804 is included between the second contact structure 216 and the ends of segments 206a-2 and 206b-2 of the first electrode layers 206a and 206b. The dielectric spacer 804 may be formed as part of the process of forming the dielectric layer 212 and may include a material composed of the same material as the dielectric layer 212.

[0247] The dielectric spacer 802 may be located between the first sidewall of the trench 202 and the ends of segments 208a-2 and 208b-2 of the second electrode layer 208a and the second electrode layer 208b. Furthermore, the dielectric spacer 802 may be laterally located between insulating layers 210a and 210b, and another dielectric spacer 802 may be laterally located between insulating layer 210c and dielectric layer 212.

[0248] The dielectric spacer 804 may be located between the second sidewall of the trench 202 and the ends of segments 206a-2 and 206b-2 of the first electrode layer 206a and the first electrode layer 206b. Furthermore, the dielectric spacer 804 may be laterally located between the insulating layer 210b and the insulating layer 210c, and another dielectric spacer 804 may be laterally located between the insulating layer 210a and the dielectric etch stop layer 806 in the trench 202.

[0249] The dielectric etch stop layer 806 may include silicon nitride (Si). x N y For example, Si3N4), aluminum oxide (Al x O y The dielectric etch stop layer 806, such as Al2O3, and / or another suitable etch stop material, allows the first electrode layer 206 and the second electrode layer 208 to be etched to form trenches in which dielectric spacers 802 and 804 can be formed, wherein the dielectric etch stop layer 806 protects the dielectric layer 204 from etching within the trench 202. The dielectric etch stop layer 806 may be included on the sidewalls and bottom surface of the trench 202. The dielectric etch stop layer 806 may be included between the metal-insulator-metal layer stack of the capacitor structure 800 and the sidewalls and bottom surface of the trench 202. Because a planarization operation can be performed to planarize the metal-insulator-metal layer stack of the capacitor structure 800, the end of the dielectric etch stop layer 806 may be approximately coplanar with the top of the trench 202.

[0250] As mentioned above, Figure 8 Provided as an example. Other examples may be provided. Figure 8 The descriptions are different.

[0251] Figures 9A to 9J This is a schematic diagram of an exemplary embodiment 900 forming the capacitor structure 800 described herein. In some embodiments, with Figures 9A to 9J One or more related semiconductor processing operations may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, wafer / die transfer tools and / or other types of semiconductor processing tools.

[0252] like Figure 9AAs shown, trench 202 can be formed in dielectric layer 204. Trench 202 can be connected to... Figure 3A It is formed in a similar manner to that described in [the text].

[0253] like Figure 9B As shown, a metal-insulator-metal layer stack 302 forms a capacitor structure 800. The metal-insulator-metal layer stack 302 can be connected to... Figure 3B Formed in a similar manner to that described herein. However, a dielectric etch stop layer 806 may be deposited first, followed by the formation of a metal-insulator-metal layer stack 302 on the dielectric etch stop layer 806. In some embodiments, conformal deposition techniques such as chemical vapor deposition and / or atomic layer deposition may be used to deposit the dielectric etch stop layer 806. The dielectric etch stop layer 806 may be conformally deposited on the sidewalls and bottom surface of the trench 202 using one or more deposition tools.

[0254] like Figure 9C As shown, a planarization operation can be performed to planarize the dielectric etch stop layer 806 and the metal-insulator-metal layer stack 302 of the capacitor structure 800. Planarization tools can be used to perform the planarization operation, including chemical mechanical planarization and / or other suitable planarization operations. The planarization operation removes portions of the dielectric etch stop layer 806 and the metal-insulator-metal layer stack 302 that extend over the trench 202 and along the top surface of the dielectric layer 204. Therefore, the ends of the dielectric etch stop layer 806, the first electrode layer 206, the second electrode layer 208, and the insulating layer 210 can be approximately coplanar with the top surface of the dielectric layer 204.

[0255] like Figure 9D As shown, a masking layer 902 may be formed at the ends of the dielectric layer 204 and the metal-insulator-metal layer stack 302. The masking layer 902 may be patterned such that the ends of the metal-insulator-metal layer stack 302 on a first side of the trench 202 are covered by the masking layer 902, and the ends of the metal-insulator-metal layer stack 302 on a second side of the trench 202 are exposed by the masking layer 902. In some embodiments, the masking layer 902 includes a photoresist layer. In some embodiments, the masking layer 902 may be formed using deposition tools (e.g., using spin coating and / or other suitable deposition techniques), the masking layer 902 may be patterned by exposing it to a radiation source using an exposure tool, and portions of the masking layer 902 may be developed and removed using a developing tool to expose the pattern. In some embodiments, the masking layer 902 includes a hard masking layer, and a pattern may be formed in the masking layer 902 using a patterned photoresist layer.

[0256] like Figure 9EAs shown, an etching operation is performed to etch the ends of the first electrode layer 206 exposed by the masking layer 902 to form a groove 904. The etching operation may include a wet chemical etching operation, and selective etching of the ends of the first electrode layer 206 using a wet etchant, but with minimal or no etching of the ends of the second electrode layer 208, the insulating layer 210, and the dielectric layer 204. Therefore, the etching rate of the wet etchant on the material of the first electrode layer 206 is greater than the individual etching rates of the wet etchant on the materials of the second electrode layer 208, the insulating layer 210, and the dielectric layer 204.

[0257] For example, the material of the first electrode layer 206 may include chromium (Cr), the material of the second electrode layer 208 may include molybdenum (Mo), and the material of the insulating layer 210 may include alumina (Al2O3). A chromium wet etchant comprising a mixture of perchloric acid (HClO4) and cerium ammonium nitrate ((NH4)2[Ce(NO3)6]) can be used to etch the first electrode layer 206. The etching rate of the chromium wet etchant on the chromium of the first electrode layer 206 is about 36 times to about 16,000 times greater than the etching rate of the chromium wet etchant on the molybdenum of the second electrode layer 208 and the alumina of the insulating layer 210. However, other types of etchants and other etching rate ranges are also within the scope of this disclosure.

[0258] As another example, the material of the first electrode layer 206 may include gold (Au), the material of the second electrode layer 208 may include titanium nitride (TiN), and the material of the insulating layer 210 may include silicon nitride (Si3N4). A gold wet etchant comprising a mixture of nitric acid (HNO3) and hydrochloric acid (HCl) can be used to etch the first electrode layer 206. In some embodiments, the mixture of nitric acid and hydrochloric acid is diluted in water (H2O). The etching rate of the gold wet etchant on the gold of the first electrode layer 206 is at least about 1,300 times greater than the etching rate of the gold wet etchant on the titanium nitride of the second electrode layer 208 and the silicon nitride of the insulating layer 210. However, other types of etchants and other etching rate ranges are also within the scope of this disclosure.

[0259] After the end of the first electrode layer 206 is etched back, the remaining portion of the mask layer 902 can be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0260] like Figure 9F As shown, the groove 904 is filled by a masking layer 906 formed at the end of another metal-insulator-metal layer stack 302 on the second side of the trench 202. The masking layer 906 may be deposited and patterned to expose the end of the metal-insulator-metal layer stack 302 on the first side of the trench 202 through the masking layer 906.

[0261] like Figure 9G As further shown, another etching operation is performed to etch the ends of the second electrode layer 208 exposed by the masking layer 906 to form a groove 908. The etching operation may include a wet chemical etching operation, and selective etching of the ends of the second electrode layer 208 using a wet etchant, with minimal or no etching of the ends of the first electrode layer 206, the insulating layer 210, and the dielectric layer 204. Therefore, the wet etchant has a greater etching rate for the material of the second electrode layer 208 than the wet etchant has for the materials of the first electrode layer 206, the insulating layer 210, and the dielectric layer 204.

[0262] For example, the material of the first electrode layer 206 may include chromium (Cr), the material of the second electrode layer 208 may include molybdenum (Mo), and the material of the insulating layer 210 may include alumina (Al2O3). A molybdenum wet etchant comprising nitric acid (HNO3) can be used to etch the second electrode layer 208. In some embodiments, the molybdenum wet etchant comprises a mixture of nitric acid and ammonium fluoride (NH4F) diluted in water (H2O). The etching rate of the molybdenum wet etchant on the molybdenum of the second electrode layer 208 is about 90 to about 200 times greater than the etching rate of the molybdenum wet etchant on the chromium of the first electrode layer 206 and the alumina of the insulating layer. However, other types of etchants and other etching rate ranges are also within the scope of this disclosure.

[0263] As another example, the material of the first electrode layer 206 may include gold (Au), the material of the second electrode layer 208 may include titanium nitride (TiN), and the material of the insulating layer 210 may include silicon nitride (Si3N4). A titanium nitride wet etchant comprising hydrofluoric acid (HF) can be used to etch the second electrode layer 208. The etching rate of the titanium nitride wet etchant on the titanium nitride of the second electrode layer 208 is at least about 180 times greater than the etching rate of the titanium nitride wet etchant on the gold of the first electrode layer 206 and the silicon nitride of the insulating layer 210. However, other types of etchants and other etching rate ranges are also within the scope of this disclosure.

[0264] like Figure 9H As shown, after etching the end of the second electrode layer 208 back into the trench 202, the remaining portion of the masking layer 906 can be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques). Removing the masking layer 906 exposes the groove 904 on the second side of the trench 202 again.

[0265] like Figure 9IAs shown, the remaining areas in trench 202, as well as grooves 904 and 908, may be filled with dielectric material to form dielectric layer 212 and dielectric spacers 802 and 804. Dielectric layer 212 may also be deposited at the ends of the metal-insulator-metal stack 302 and along the top surface of dielectric layer 204. Dielectric spacers 802 and 804 may be formed in grooves 908 and 904, respectively. Physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques may be used to deposit the dielectric layer 212 and the dielectric spacers 802 and 804 using deposition tools. In some embodiments, planarization tools may be used to perform planarization operations (e.g., chemical mechanical planarization) to planarize dielectric layer 212 after deposition.

[0266] like Figure 9J As shown, the first contact structure 214 and the second contact structure 216 can be formed in the dielectric layer 212 above the trench 202. The first contact structure 214 can be formed directly on top of the end of the first electrode layer 206 extending to the top of the trench 202. The second contact structure 216 can be formed directly on top of the end of the second electrode layer 208 extending to the top of the trench 202.

[0267] A deposition tool can be used to deposit the first contact structure 214 and the second contact structure 216 in the groove. The deposition tool can be used to deposit the first contact structure 214 and the second contact structure 216 using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques. The first contact structure 214 and the second contact structure 216 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the first contact structure 214 and / or the second contact structure 216 is deposited on the seed layer. In some embodiments, after depositing the first contact structure 214 and the second contact structure 216, a planarization operation (e.g., chemical mechanical planarization) is performed using a planarization tool to planarize the first contact structure 214 and the second contact structure 216.

[0268] As mentioned above, Figures 9A to 9J Provided as an example. Other examples may be provided. Figures 9A to 9J The descriptions differ from those in the text.

[0269] Figure 10This is a schematic diagram of an exemplary semiconductor device 1000 described in this disclosure. The semiconductor device 1000 may include examples of a three-dimensional image sensor (e.g., a three-dimensional complementary metal-oxide-semiconductor (CMOS) image sensor). The semiconductor device 1000 may be configured for use in various implementations, such as digital cameras, camcorders, night vision cameras, automotive sensors and cameras, and / or other types of light-sensing implementations.

[0270] like Figure 10 As shown, the semiconductor device 1000 may include a pixel sensor array 1002. The semiconductor device 1000 may also include a blacklevel correction (BLC) region 1004, a bonding pad region 1006, and / or a sealing ring region 1008, etc. The pixel sensor array 1002 may include a plurality of pixel sensors 100 arranged in an array. Pixel sensors 100 may be configured to sense incident light and convert photons of the incident light into photocurrent. Pixel sensors 100 may be included in the device layer 1010 of the semiconductor device 1000. Each pixel sensor 100 may include one or more photodiodes 102, and the photodiodes 102 are configured to generate photocurrent based on photons of the incident light. The pixel sensor 100 may further include a floating diffusion node 106 in the device layer 1010, wherein the floating diffusion node 106 is configured to temporarily store the photocurrent generated by the associated pixel sensor 100, and each pixel sensor 100 may include a transfer gate 104, wherein the transfer gate 104 is configured to control the photocurrent flowing from the photodiode 102 to the floating diffusion node 106. The pixel sensor 100 may be formed by one or more semiconductor processing tools using various semiconductor processing techniques, such as lithography, etching, deposition, chemical mechanical planarization, and / or ion implantation.

[0271] Black level correction region 1004 includes a metal mask layer on a portion of device layer 1010 to allow baseline measurements of the current in device layer 1010 within black level correction region 1004 to determine dark currents in pixel sensor array 1002 (e.g., currents in device layer 1010 generated from sources other than incident light, such as currents generated by heat), allowing pixel sensor array 1002 to be adjusted to compensate for dark currents. Bond pad region 1006 may include one or more conductive bonding pads (or electronic bonding pads) and / or metallization layers to establish electrical connections between semiconductor device 1000 and external devices and / or external packages. Sealing ring region 1008 may include metallization and interconnect structures to provide structural rigidity to semiconductor device 1000 and protect semiconductor device 1000 from moisture and other contaminants.

[0272] like Figure 10As further shown, the semiconductor device 1000 may include an interconnect layer 1012 below and / or at the bottom of the device layer 1010. The interconnect layer 1012 may include a dielectric region 1014, wherein the dielectric region 1014 includes one or more dielectric layers (e.g., interlayer dielectric layers, intermetallic dielectric layers, etch stop layers) and metallization structures 1016 and interconnect structures 1018 disposed within the dielectric region 1014. A passivation layer 1020 may be located below the interconnect layer 1012.

[0273] like Figure 10 As further shown, one or more overflow capacitors 114 may be included in the interconnect layer 1012. The overflow capacitor 114 may structurally implement one or more of the capacitor structures 200, 400, 600, and / or 800 illustrated and described herein. The overflow capacitor 114 may be electrically coupled to the floating diffusion node 106 of the pixel sensor 100 and may be configured to store overflow photocurrent from the floating diffusion node 106.

[0274] As mentioned above, Figure 10 Provided as an example. Other examples may be provided. Figure 10 The descriptions are different.

[0275] Figure 11 This is a schematic diagram of an exemplary semiconductor device 1100 described in this disclosure. The semiconductor device 1100 may include an example of a three-dimensional image sensor (e.g., a three-dimensional complementary metal-oxide-semiconductor image sensor). The semiconductor device 1100 may be configured for use in various implementations, such as digital cameras, camcorders, night vision cameras, automotive sensors and cameras, and / or other types of light-sensing implementations.

[0276] like Figure 11 As shown, semiconductor device 1100 includes a combination of structures and / or layers similar to those of semiconductor device 1000. For example, semiconductor device 1100 may include pixel sensor array 1002, black level correction region 1104, bonding pad region 1106, sealing ring region 1108, device layer 1010, interconnect layer 1012, dielectric region 1014, metallization structure 1016, and interconnect structure 1018 similar to those in semiconductor device 1000.

[0277] However, the semiconductor device 1100 includes a plurality of semiconductor dies, and the semiconductor dies include a first semiconductor die 1120a and a second semiconductor die 1120b. The first semiconductor die 1120a and the second semiconductor die 1120b can be directly bonded together at a bonding interface 1122, such that the first semiconductor die 1120a and the second semiconductor die 1120b are stacked in the semiconductor device 1100 and arranged perpendicularly along the z-direction. The first semiconductor die 1120a may be referred to as an image sensor die, and may include a pixel sensor array 1102 (including pixel sensor 100), a black level correction region 1104, and a bonding pad region 1106. The first semiconductor die 1120a may also include a photodiode 102, a transfer gate 104, a floating diffusion node 106, a device layer 1110, and an interconnect layer 1112 (including a dielectric region 1114, a metallization structure 1116, and an interconnect structure 1118). Figure 11 In the example, the overflow capacitor 114 is included in the interconnect layer 1112 of the first semiconductor die 1120a. The sealing ring region 1108 may extend through the first semiconductor die 1120a and the second semiconductor die 1120b.

[0278] like Figure 11 As further shown, the second semiconductor die 1120b of the semiconductor device 1100 may include a device layer 1124, one or more integrated circuit devices 1126 included in the device layer 1124, and an interconnect layer 1128 above the device layer 1124. The interconnect layer 1128 may include a dielectric region 1130, wherein the dielectric region 1130 includes one or more dielectric layers (e.g., interlayer dielectric layers, etch stop layers), and the metallization structure 1132 and the interconnect structure 1134 are disposed in the dielectric region 1130 of the interconnect layer 1128 of the second semiconductor die 1120b.

[0279] The first semiconductor die 1120a and the second semiconductor die 1120b can be joined at the bonding interface 1122 by dielectric-to-dielectric bonding between the dielectric region 1114 of the first semiconductor die 1120a and the dielectric region 1130 of the second semiconductor die 1120b. Alternatively, the first semiconductor die 1120a and the second semiconductor die 1120b can be joined at the bonding interface 1122 by metal-to-metal bonding between bonding pad 1136 included in the interconnect layer 1112 of the first semiconductor die 1120a and bonding pad 1138 included in the interconnect layer 1128 of the second semiconductor die 1120b. Bonding pad 1136 can be electrically connected to metallized structure 1116 and interconnect structure 1118 in interconnect layer 1112 through bonding via 1140, and bonding pad 1138 can be electrically connected to metallized structure 1132 and interconnect structure 1134 in interconnect layer 1128 through bonding via 1142.

[0280] As mentioned above, Figure 11 Provided as an example. Other examples may be provided. Figure 11 The descriptions are different.

[0281] Figure 12 This is a schematic diagram of an exemplary semiconductor device 1200 described in this disclosure. The semiconductor device 1200 may include an example of a three-dimensional image sensor (e.g., a three-dimensional complementary metal-oxide-semiconductor image sensor). The semiconductor device 1200 may be configured for use in various implementations, such as digital cameras, camcorders, night vision cameras, automotive sensors and cameras, and / or other types of light-sensing implementations.

[0282] like Figure 12 As shown, semiconductor device 1200 includes a combination of structures and / or layers similar to those of semiconductor device 1100. For example, semiconductor device 1200 may include a pixel sensor array 1102, a black level correction region 1104, a bonding pad region 1106, a sealing ring region 1108, a device layer 1110, an interconnect layer 1112, a dielectric region 1114, a metallization structure 1116, an interconnect structure 1118, a bonding interface 1122, a device layer 1124, an integrated circuit device 1126, an interconnect layer 1128, a dielectric region 1130, a metallization structure 1132, an interconnect structure 1134, bonding pads 1136 and 1138, and bonding vias similar to those in semiconductor device 1100. The semiconductor device 1200 includes a pixel sensor array 1202 with vias 1140 and 1142, a black level correction region 1204, a bonding pad region 1206, a sealing ring region 1208, a device layer 1210, an interconnect layer 1212, a dielectric region 1214, a metallization structure 1216, an interconnect structure 1218, a bonding interface 1222, a device layer 1224, an integrated circuit device 1226, an interconnect layer 1228, a dielectric region 1230, a metallization structure 1232, an interconnect structure 1234, bonding pads 1236 and 1238, and vias 1240 and 1242. The semiconductor device 1200 may also include a pixel sensor 100, a photodiode 102, a transfer gate 104, a floating diffusion node 106, and one or more overflow capacitors 114.

[0283] However, in semiconductor device 1200, one or more overflow capacitors 114 are included in a second semiconductor die 1220b (e.g., an application-specific integrated circuit (ASIC) die) instead of (or additionally) in a first semiconductor die 1220a (e.g., a sensor die). Including one or more overflow capacitors 114 on the second semiconductor die 1220b instead of the first semiconductor die 1220a allows a larger area in the first semiconductor die 1220a to be available for the photodiode 102 (thus providing increased full-well capacity for the photodiode 102) and / or for control circuitry for the pixel sensor 100 (e.g., for the transfer gate 104, reset gate 108, overflow gate 112), thus potentially increasing the performance of semiconductor device 1200.

[0284] As mentioned above, Figure 12 Provided as an example. Other examples may be provided. Figure 12 The descriptions are different.

[0285] Figures 13A to 13C This is a schematic top view of an exemplary layout of the overflow capacitor 114 described in this disclosure. The overflow capacitor 114 may be implemented as one or more of the capacitor structures 200, 400, 600 and / or 800 described in this disclosure.

[0286] Figure 13A An exemplary top view layout 1300 is shown, wherein the overflow capacitor 114 may include a plurality of approximately square trenches 202 arranged in a grid. The capacitance of the overflow capacitor 114 can be further increased by including a plurality of trenches 202.

[0287] Figure 13B An exemplary top view layout 1302 is shown, in which the overflow capacitor 114 may also include a plurality of trenches 202. However, the top view layout 1302 includes a plurality of trenches 202 arranged in a grid in an approximately circular pattern.

[0288] Figure 13C An exemplary top view layout 1304 is shown, in which the overflow capacitor 114 may also include a plurality of trenches 202. However, the top view layout 1304 includes a plurality of trenches 202 arranged in a grid in an approximately rectangular manner.

[0289] As mentioned above, Figures 13A to 13C Provided as an example. Other examples may be provided. Figures 13A to 13C The descriptions differ from those in the text. Figures 13A to 13CThe number, shape, and arrangement of the grooves 202 in the exemplary top-view layout are examples, and other numbers, shapes, and arrangements are also within the scope of this disclosure.

[0290] Figure 14 This is a flowchart of an exemplary process 1400 related to forming the capacitor structure described herein. In some embodiments, Figure 14 One or more process blocks in the process are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools and / or other types of semiconductor processing tools.

[0291] like Figure 14 As shown, process 1400 may include forming trenches in the dielectric layer (block 1410). For example, as described in this disclosure, trenches 202 may be formed in dielectric layer 204 using one or more semiconductor processing tools.

[0292] like Figure 14 As further shown, process 1400 may include a metal-insulator-metal layer stack (block 1420) forming a capacitor structure in a trench. For example, as described in this disclosure, a metal-insulator-metal layer stack of capacitor structures (e.g., capacitor structure 200, capacitor structure 400, capacitor structure 600, and / or capacitor structure 800) may be formed in trench 202 using one or more semiconductor processing tools. In some embodiments, the metal-insulator-metal layer stack extends along the sidewalls and bottom surface of trench 202. In some embodiments, the metal-insulator-metal layer stack includes a repeating arrangement of a first electrode layer 206, an insulating layer 210 on the first electrode layer 206, and a second electrode layer 208 on the insulating layer 210. In some embodiments, a first end of the metal-insulator-metal layer stack extends laterally outward from a first side of trench 202 along the top surface of dielectric layer 204. In some embodiments, the second end of the metal-insulator-metal layer stack extends laterally outward from the second side of the trench 202 along the top surface of the dielectric layer 204.

[0293] like Figure 14 As further shown, process 1400 may include removing a first portion of the first electrode layer from a first end of the metal-insulator-metal layer stack (block 1430). For example, as described in this disclosure, one or more semiconductor processing tools may be used to remove the first portion of the first electrode layer 206 from the first end of the metal-insulator-metal layer stack.

[0294] like Figure 14As further shown, process 1400 may include removing a second portion of the second electrode layer from the second end of the metal-insulator-metal layer stack (block 1440). For example, as described in this disclosure, one or more semiconductor processing tools may be used to remove the second portion of the second electrode layer 208 from the second end of the metal-insulator-metal layer stack.

[0295] like Figure 14 As further shown, process 1400 may include forming a first contact structure laterally adjacent to the second end of the metal-insulator-metal layer stack, such that the first contact structure contacts a first electrode layer at the second end of the metal-insulator-metal layer stack (block 1450). For example, as described in this disclosure, one or more semiconductor processing tools may be used to form a first contact structure 214 laterally adjacent to the second end of the metal-insulator-metal layer stack, such that the first contact structure 214 contacts a first electrode layer 206 at the second end of the metal-insulator-metal layer stack.

[0296] like Figure 14 As further shown, process 1400 may include forming a second contact structure 216 laterally adjacent to a first end of a metal-insulator-metal layer stack, such that the second contact structure contacts a second electrode layer at the first end of the metal-insulator-metal layer stack (block 1460). For example, as described in this disclosure, one or more semiconductor processing tools may be used to form the second contact structure 216 laterally adjacent to the first end of the metal-insulator-metal layer stack, such that the second contact structure 216 contacts a second electrode layer 208 at the first end of the metal-insulator-metal layer stack.

[0297] Process 1400 may include additional implementations, such as any single implementation or any combination of implementations described below and / or related to one or more other processes described elsewhere in this disclosure.

[0298] In the first embodiment, the first contact structure 214 is laterally spaced from the second electrode layer 208 at the second end of the metal-insulator-metal layer stack, and the second contact structure 216 is laterally spaced from the first electrode layer 206 at the first end of the metal-insulator-metal layer stack.

[0299] In the second embodiment, removing a first portion of the first electrode layer 206 from the first end of the metal-insulator-metal layer stack, either alone or in combination with the first embodiment, includes removing the first portion by etching the first electrode layer 206 with an etchant, wherein a first etch rate of the etchant for the first electrode layer 206 is greater than a second etch rate of the etchant for the second electrode layer 208.

[0300] In the third embodiment, removing a second portion of the second electrode layer 208 from the second end of the metal-insulator-metal layer stack, either alone or in combination with one or more of the first and second embodiments, includes removing the second portion by etching the second electrode layer 208 with another etchant, wherein a first etch rate of the etchant for the second electrode layer 208 is greater than a second etch rate of the etchant for the first electrode layer 206.

[0301] In the fourth embodiment, the etchant, alone or in combination with one or more of the first to third embodiments, includes perchloric acid (HClO4) and cerium ammonium nitrate ((NH4)2[Ce(NO3)6]), and another etchant includes nitric acid (HNO3).

[0302] In the fifth embodiment, the etchant includes nitric acid (HNO3) and hydrochloric acid (HCl), alone or in combination with one or more of the first to fourth embodiments, and another etchant includes hydrofluoric acid (HF).

[0303] although Figure 14 The illustration shows an exemplary block of process 1400, but in some embodiments, process 1400 may include additional blocks, fewer blocks, different blocks, or blocks similar to those in the original diagram. Figure 14 The different blocks depicted. Alternatively, two or more blocks of process 1400 can be executed in parallel.

[0304] In this manner, the image sensor device includes a capacitor structure configured to store charge associated with the photocurrent generated by the pixel sensors in the pixel sensor array of the image sensor device. The photocurrent can be transferred from the pixel sensors to the capacitor structure, enabling the pixel sensors to generate more charge for the photocurrent than the photocurrent could be entirely stored in the photodiodes and / or floating diffusion nodes of the pixel sensors. Therefore, the capacitor structure increases the full-well capacity of the pixel sensors, resulting in images and / or images generated by the pixel sensor array having a wider range of brightness and / or contrast. The capacitor structure may include a metal-insulator-metal (MIM) layer stack, wherein bottom and top electrode layers are alternately arranged and separated by an insulating layer. Bottom contact structures of the bottom electrode layers and top contact structures of the top electrode layers are formed laterally adjacent to opposite ends of the MIM stack. To electrically isolate the bottom electrode layers from the top contact structures, the ends of the bottom electrode layers facing the top contact structures are etched, such that the ends of the bottom electrode layers are separated from the top contact structures. Similarly, the ends of the top electrode layers facing the bottom contact structures are etched, such that the ends of the top electrode layers are separated from the bottom contact structures. Therefore, the bottom contact structure of the bottom electrode layer and the top contact structure of the top electrode layer can be formed laterally close to the opposite ends of the metal-insulator-metal layer stack, thereby making the lateral space occupied by the capacitor structure more compact.

[0305] As described in more detail above, some embodiments described in this disclosure provide a capacitor structure. The capacitor structure includes a first electrode layer, a second electrode layer, an insulating layer, a first contact structure, and a second contact structure. The first electrode layer extends along a plurality of sidewalls and a bottom surface of a trench, wherein a first end of the first electrode layer extends laterally outward from a first side of the trench. The second electrode layer extends along the sidewalls and a bottom surface of the trench, wherein a second end of the second electrode layer extends laterally outward from a second side of the trench. An insulating layer is located between the first electrode layer and the second electrode layer. The first contact structure contacts the first end of the first electrode layer. The second contact structure contacts the second end of the second electrode layer. In some embodiments, the first side and the second side are opposite sides of the trench. In some embodiments, a third end of the first electrode layer extends laterally outward from the second side of the trench; a fourth end of the second electrode layer extends laterally outward from the first side of the trench; the third end of the first electrode layer is spaced apart from the second contact structure; and the fourth end of the second electrode layer is spaced apart from the first contact structure. In some embodiments, the capacitor structure further includes: a first air gap between a third end of the first electrode layer and a second contact structure; and a second air gap between a fourth end of the second electrode layer and the first contact structure. In some embodiments, the first contact structure includes a first barrier layer extending from the first contact structure into the second air gap; and the second contact structure includes a second barrier layer extending from the second contact structure into the first air gap. In some embodiments, the capacitor structure further includes: a first insulating plug between the first electrode layer and the second contact structure; and a second insulating plug between the second electrode layer and the first contact structure. In some embodiments, the first insulating plug contacts the first electrode layer at a first end of the first insulating plug; and the first insulating plug contacts the second contact structure at a second end of the first insulating plug opposite to the first end of the first insulating plug.

[0306] As described in more detail above, some implementations of this disclosure provide a method for forming a capacitor structure. The method includes the following operations: Forming a trench in a dielectric layer. A metal-insulator-metal layer stack forming the capacitor structure is formed in the trench, wherein the metal-insulator-metal layer stack extends along a plurality of sidewalls and a bottom surface of the trench; the metal-insulator-metal layer stack includes a repeating arrangement of a first electrode layer, an insulating layer on the first electrode layer, and a second electrode layer on the insulating layer; a first end of the metal-insulator-metal layer stack extends laterally outward from a first side of the trench along the top surface of the dielectric layer; and a second end of the metal-insulator-metal layer stack extends laterally outward from a second side of the trench along the top surface of the dielectric layer. Removing a first portion of the first electrode layer from the first end of the metal-insulator-metal layer stack. Removing a second portion of the second electrode layer from the second end of the metal-insulator-metal layer stack. Forming a first contact structure laterally adjacent to the second end of the metal-insulator-metal layer stack, such that the first contact structure contacts the first electrode layer at the second end of the metal-insulator-metal layer stack. A second contact structure is formed laterally adjacent to the first end of the metal-insulator-metal layer stack, such that the second contact structure contacts the second electrode layer at the first end of the metal-insulator-metal layer stack. In some embodiments, the first contact structure is laterally spaced from the second electrode layer at the second end of the metal-insulator-metal layer stack; and the second contact structure is laterally spaced from the first electrode layer at the first end of the metal-insulator-metal layer stack. In some embodiments, removing a first portion of the first electrode layer from the first end of the metal-insulator-metal layer stack includes etching the first electrode layer with an etchant to remove the first portion, wherein a first etch rate of the etchant on the first electrode layer is greater than a second etch rate of the etchant on the second electrode layer. In some embodiments, removing a second portion of the second electrode layer from the second end of the metal-insulator-metal layer stack includes etching the second electrode layer with an additional etchant to remove the second portion, wherein a third etch rate of the additional etchant on the second electrode layer is greater than a fourth etch rate of the additional etchant on the first electrode layer. In some embodiments, the etchant includes perchloric acid and cerium ammonium nitrate; and another etchant includes nitric acid. In some embodiments, the etchant includes nitric acid and hydrochloric acid; and other etchants include hydrofluoric acid.

[0307] As described in more detail above, some embodiments described in this disclosure provide a capacitor structure. The capacitor structure includes a first electrode layer, a second electrode layer, an insulating layer, a first contact structure, and a second contact structure. The first electrode layer extends along a first sidewall and a bottom surface of a trench. The second electrode layer extends along a second sidewall and a bottom surface of the trench. An insulating layer is located between the first electrode layer and the second electrode layer. The first contact structure is located on and contacts a first end of the first electrode layer. The second contact structure is located on and contacts a second end of the second electrode layer. In some embodiments, the first and second sidewalls are opposing sidewalls of the trench. In some embodiments, the capacitor structure further includes: a first dielectric spacer between a third end of the first electrode layer and a second sidewall of the trench; and a second dielectric spacer between a fourth end of the second electrode layer and a first sidewall of the trench. In some embodiments, the first dielectric spacer is laterally located between the first and second electrode layers. In some embodiments, the capacitor structure further includes: a first insulating layer laterally located between a second dielectric spacer and a first electrode layer; and a second insulating layer laterally located between the first dielectric spacer and the second electrode layer. In some embodiments, a first end of the first electrode layer and a second end of the second electrode layer are approximately coplanar with the top of the trench; and a first contact structure and a second contact structure are located above the trench. In some embodiments, the capacitor structure further includes a dielectric etch stop layer on a first sidewall, a second sidewall, and a bottom surface of the trench, wherein the dielectric etch stop layer is located between the first electrode layer and the first sidewall, the second sidewall, and the bottom surface of the trench, and the dielectric etch stop layer is located between the second electrode layer and the first sidewall, the second sidewall, and the bottom surface of the trench.

[0308] Some embodiments of this disclosure provide a capacitor structure. The capacitor structure includes a dielectric layer with trenches, a metal-insulator-metal layer stack, a first contact structure, and a second contact structure. The metal-insulator-metal layer stack is located in the trenches of the dielectric layer, wherein the metal-insulator-metal layer stack includes a first electrode layer, an insulating layer on the first electrode layer, and a second electrode layer on the insulating layer. A first end of the first electrode layer extends laterally outward from a first side of the trench along the top surface of the dielectric layer, and a second end of the second electrode layer extends laterally outward from a second side of the trench along the top surface of the dielectric layer. The first contact structure contacts the first end of the first electrode layer. The second contact structure contacts the second end of the second electrode layer.

[0309] The terms “about” and “substantially” can indicate that a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to limit the scope of this disclosure. It should be understood that the terms “about” and “substantially” can refer to a percentage of a given quantity value given the scope of this disclosure. The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should recognize that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described in this disclosure. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various modifications, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A capacitor structure, characterized by include: A first electrode layer extends along a plurality of sidewalls and a bottom surface of a trench, wherein a first end of the first electrode layer extends laterally outward from a first side of the trench; A second electrode layer extends along the plurality of sidewalls and the bottom surface of the trench, wherein a second end of the second electrode layer extends laterally outward from a second side of the trench; An insulating layer is placed between the first electrode layer and the second electrode layer; A first contact structure contacts the first end of the first electrode layer; and A second contact structure contacts the second end of the second electrode layer.

2. The capacitor structure of claim 1, wherein, The first side and the second side are the two opposite sides of the trench.

3. The capacitor structure of claim 1 or claim 2, wherein, A third end of the first electrode layer extends laterally outward from the second side of the trench; a fourth end of the second electrode layer extends laterally outward from the first side of the trench; the third end of the first electrode layer is separated from the second contact structure; and the fourth end of the second electrode layer is separated from the first contact structure.

4. The capacitor structure of claim 3, wherein, Also includes: A first air gap exists between the third end of the first electrode layer and the second contact structure. as well as A second air gap is located between the fourth end of the second electrode layer and the first contact structure.

5. The capacitor structure of claim 3, wherein, Also includes: A first insulating plug is located between the first electrode layer and the second contact structure; as well as A second insulating plug is placed between the second electrode layer and the first contact structure.

6. A capacitor structure, characterized by include: A first electrode layer extends along a first sidewall and a bottom surface of a trench; A second electrode layer extends along a second sidewall and the bottom surface of the trench; An insulating layer is placed between the first electrode layer and the second electrode layer; A first contact structure is located on and in contact with a first end of the first electrode layer; and A second contact structure is located on a second end of the second electrode layer and is in contact with that second end of the second electrode layer.

7. The capacitor structure of claim 6, wherein, Also includes: A first dielectric interstitial material is located between a third end of the first electrode layer and the second sidewall of the trench; and A second dielectric interstitial material is placed between a fourth end of the second electrode layer and the first sidewall of the trench.

8. The capacitor structure of claim 6, wherein, The first end of the first electrode layer and the second end of the second electrode layer are approximately coplanar with a top of the trench; and the first contact structure and the second contact structure are located above the trench.

9. The capacitor structure of any one of claims 6 to 8, wherein, It also includes a dielectric etch stop layer on the first sidewall, the second sidewall and the bottom surface of the trench, wherein the dielectric etch stop layer is located between the first electrode layer and the first sidewall, the second sidewall and the bottom surface of the trench, and wherein the dielectric etch stop layer is located between the second electrode layer and the first sidewall, the second sidewall and the bottom surface of the trench.

10. A capacitor structure, characterized by include: A dielectric layer having a trench; A metal-insulator-metal layer is stacked in the trench of the dielectric layer, wherein the metal-insulator-metal layer stack includes a first electrode layer, an insulating layer on the first electrode layer, and a second electrode layer on the insulating layer. A first end of the first electrode layer extends laterally outward from a first side of the trench along a top surface of the dielectric layer, and a second end of the second electrode layer extends laterally outward from a second side of the trench along the top surface of the dielectric layer. a first contact structure contacts the first end of the first electrode layer; and a second contact structure contacts the second end of the second electrode layer.

Images