Asymmetric bidirectional semiconductor discharge tube chip
By designing an NPN-PNP dual transistor structure and a third-order field plate passivation layer in the semiconductor discharge tube chip, the problem that existing chips cannot meet the requirements of reverse overvoltage and high current conduction is solved, and bidirectional overvoltage protection and high reliability are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN CHANGJING MICROELECTRONICS CO LTD
- Filing Date
- 2025-07-24
- Publication Date
- 2026-07-31
AI Technical Summary
Existing semiconductor discharge tube chips cannot meet the circuit's reverse overvoltage and high current conduction requirements, and cannot effectively protect the circuit from damage caused by reverse overvoltage.
An asymmetric bidirectional semiconductor discharge tube chip was designed. By forming first and second doped regions on the upper and lower surfaces of the substrate, respectively, and setting third and fourth doped regions and multiple fifth and sixth doped regions within the doped regions, an NPN-PNP dual transistor structure was formed. Combined with the passivation layer of the third-order field plate structure, bidirectional overvoltage protection was achieved.
It achieves bidirectional overvoltage protection for the circuit, enabling high current conduction and rapid voltage reduction during reverse overvoltage, thereby improving product reliability and breakdown voltage, and reducing the probability of soft breakdown.
Smart Images
Figure CN224583589U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to semiconductor discharge tube chips, specifically to an asymmetric bidirectional semiconductor discharge tube chip. Background Technology
[0002] A semiconductor discharge tube (TSS) is a fast-switching semiconductor device capable of handling high voltage and high current. It boasts advantages such as fast response, low noise, and low power consumption, and is widely used in power electronics, communications, and optoelectronics. In power electronics, TSSs are typically used as overvoltage protection devices, protecting circuits through short-circuit discharge.
[0003] Existing semiconductor discharge tube chips typically have a symmetrical top-bottom structure, protecting circuits from transient overvoltages from both directions (positive and negative polarities). However, in practical applications, reverse overvoltage often requires a large current to ensure rapid release of abnormal voltages. Existing semiconductor discharge tube chips cannot meet this requirement. Therefore, providing a semiconductor discharge tube chip that can provide high-current conduction for reverse overvoltage protection has become a pressing problem. Utility Model Content
[0004] This invention provides an asymmetric bidirectional semiconductor discharge tube chip to solve the problem that existing semiconductor discharge tubes cannot meet the requirements of reverse overvoltage and high current conduction in circuits.
[0005] To achieve the objective of this utility model, this utility model provides an asymmetric bidirectional semiconductor discharge tube chip, characterized in that the chip comprises: The substrate includes an opposing upper surface and a lower surface; The first doped region is a groove structure extending downward from the upper surface of the substrate, and a first PN junction is connected between the first doped region and the substrate. The second doped region is a groove structure extending upward from the lower surface of the substrate, and a second PN junction is connected between the second doped region and the substrate. The third doped region is located at the end of the first PN junction. It is an annular groove structure that extends downward from the upper surface of the substrate on the outside and downward from the upper surface of the first doped region on the inside. The third doped region is connected to the first doped region by a third PN junction, and the reverse avalanche voltage of the third PN junction is less than the reverse avalanche voltage of the first PN junction. The fourth doped region is located at the end of the second PN junction. It is an annular groove structure that extends upward from the lower surface of the substrate on the outside and upward from the lower surface of the second doped region on the inside. The fourth doped region is connected to the second doped region by a fourth PN junction, and the reverse avalanche voltage of the fourth PN junction is less than that of the second PN junction. Multiple fifth doped regions are spaced apart inside the third doped region, and each fifth doped region is connected to the first doped region by a fifth PN junction. Multiple sixth doped regions are spaced apart inside the fourth doped region, and the trench width of each sixth doped region increases from both sides to the middle. Each sixth doped region is connected to the second doped region by a sixth PN junction. The first electrode is connected to the first doped region and the fifth doped region, respectively; The second electrode is connected to the second doped region and the sixth doped region, respectively.
[0006] Furthermore, the substrate is N-type doped, the first and second doped regions are P-type doped, and the third, fourth, fifth, and sixth doped regions are N-type doped, with the doping concentration of the third and fourth doped regions being higher than the doping concentration of the substrate.
[0007] Furthermore, the sixth doped regions on both sides are annular groove structures extending upward from the lower surface of the second doped region, while the sixth doped region in the middle is a groove structure extending upward from the lower surface of the second doped region.
[0008] In some embodiments, the chip further includes a first passivation layer, which is a plate-like structure. Its lower surface covers a portion of the upper surface of the substrate, the upper surface of the third doped region, the end of the third PN junction J3, and the upper surface of a portion of the first doped region. Its upper surface is a three-stage field plate structure with the thickness increasing sequentially from the center to the edge.
[0009] In some embodiments, the chip further includes a second passivation layer, which is a plate-like structure. Its upper surface covers a portion of the lower surface of the substrate, the lower surface of the fourth doped region, the end of the fourth PN junction J4, and the lower surface of a portion of the second doped region. Its lower surface is a three-stage field plate structure with the thickness increasing sequentially from the center to the edge.
[0010] In some embodiments, the chip further includes a first metal passivation layer that covers a portion of the upper surface of the first passivation layer, a side portion of the first electrode, and a portion of the upper surface of the first electrode. In some embodiments, the chip further includes a second metal passivation layer that covers a portion of the lower surface of the second passivation layer, the side portion of the second electrode, and a portion of the lower surface of the second electrode.
[0011] Furthermore, the first electrode is a metal electrode made of titanium-nickel-silver, tin-copper alloy, or nickel-gold alloy; the second electrode is a metal electrode made of titanium-nickel-silver, tin-copper alloy, or nickel-gold alloy.
[0012] Furthermore, the first passivation layer comprises SiO2, semi-insulating oxygen-doped polycrystalline silicon, phosphosilicate glass, borosilicate glass, and a low-pressure deposited silicon nitride passivation film; the second passivation layer comprises SiO2, semi-insulating oxygen-doped polycrystalline silicon, phosphosilicate glass, borosilicate glass, and a low-pressure deposited silicon nitride passivation film.
[0013] Furthermore, the first metal passivation layer is SiN, NSG, phosphosilicate glass, or a polyamide metal passivation layer; the second metal passivation layer is SiN, NSG, phosphosilicate glass, or a polyamide metal passivation layer.
[0014] The beneficial effects of this utility model are as follows: 1) By forming a first doped region and a second doped region on the upper and lower surfaces of the substrate, respectively, forming a third doped region in the first doped region, forming a fourth doped region in the second doped region, setting multiple fifth doped regions in the first doped region, setting multiple sixth doped regions in the second doped region, and setting the reverse avalanche voltage of the third PN junction less than the reverse avalanche voltage of the first PN junction and the reverse avalanche voltage of the fourth PN junction less than the reverse avalanche voltage of the second PN junction, the chip is formed into an NPN-PNP dual transistor to achieve bidirectional overvoltage protection.
[0015] 2) Since the trench width of the multiple sixth doped regions increases from both sides to the middle, when the negative electrode is over-voltage, the trench width of the sixth doped region located on the outermost side is the smallest, while the trench width of the sixth doped region located in the middle is the largest. This is conducive to achieving uniformity of current flow, thereby enabling large current discharge to quickly reduce voltage, and thus being able to withstand higher breakdown voltage, improving the reliability of the product.
[0016] 3) By setting the first passivation layer and the second passivation layer, composite high-reliability passivation protection can be provided for the third PN junction J3 and the fourth PN junction J4, respectively. In addition, by setting the first passivation layer and the second passivation layer as a third-order field plate structure, the charge of the first electrode and the second electrode is extended to the first metal passivation layer and the second metal passivation layer at the edge of the device, realizing the extension of the space charge region at the edge, thereby enabling the blocking voltage to reach the bulk breakdown voltage, reducing the probability of soft breakdown, and improving the reliability of the product. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the structure of this utility model.
[0018] Figure 2 This is the current-voltage curve of the overvoltage performance test of this utility model.
[0019] Figure 3 This is a flowchart of the manufacturing method of this utility model.
[0020] In the figure, 101 is the substrate, 102 is the first doped region, 103 is the second doped region, 104 is the third doped region, 105 is the fourth doped region, 106 is the fifth doped region, 107 is the sixth doped region, 108 is the first electrode, 109 is the second electrode, 110 is the first passivation layer, 111 is the second passivation layer, 112 is the first metal passivation layer, 113 is the second metal passivation layer, J1 is the first PN junction, J2 is the second PN junction, J3 is the third PN junction, J4 is the fourth PN junction, J5 is the fifth PN junction, and J6 is the sixth PN junction. Detailed Implementation
[0021] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0022] Please see Figure 1 The present invention provides an asymmetric bidirectional semiconductor discharge tube chip comprising a substrate 101, a first doped region 102, a second doped region 103, a third doped region 104, a fourth doped region 105, multiple fifth doped regions 106, a first electrode 107, and a second electrode 108. The single-sided bandgap low-capacitance bidirectional semiconductor discharge tube chip of this embodiment not only achieves bidirectional overvoltage protection but also meets the requirement of low-voltage rapid conduction from the positive to the negative electrode, reducing the response time of the device in practical applications, thereby making the protection more sensitive.
[0023] like Figure 1As shown, substrate 101 is a plate-like body, including an upper surface and a lower surface facing each other. Specifically, substrate 101 is N-type. <111> The single-crystal silicon substrate has a thickness of 250-350 μm and a resistivity of 1.0-10.0 Ω·cm, exhibiting high resistivity. A first doped region 102 is formed on the upper surface of the substrate 101. This first doped region 102 is a groove structure extending downward from the upper surface of the substrate 101 and is P-type doped. In this embodiment, a dense oxide layer is grown on the upper surface of the substrate 101 using hydrogen-oxygen synthesis, followed by photolithography with a negative photoresist and etching with a buffered oxide etchant (BOE) to etch out the doping window of the first doped region 102. Boron pre-expansion and boron main expansion are then performed on the doping window of the first doped region 102 to form the first doped region 102. The diffusion junction depth of the first doped region 102 is 20-40 μm. A first PN junction J1 connects the first doped region 102 and the substrate 101. A second doped region 103 is provided on the lower surface of the substrate 101. This second doped region 103 is a groove structure extending upwards from the lower surface of the substrate 101 and is P-type doped. In this embodiment, a dense oxide layer is grown on the lower surface of the substrate 101 using hydrogen-oxygen synthesis, followed by photolithography with a negative photoresist and etching with BOE etching solution to create the doping window of the second doped region 103. Boron pre-expansion and boron main expansion are then performed on the doping window of the second doped region 103 to form the second doped region 103. The diffusion junction depth of the second doped region 103 is 20-40 μm. A second PN junction J2 connects the second doped region 103 and the substrate 101. In this embodiment, the substrate 101 is selected from an N-type <1 1 1> single crystal silicon substrate with high resistivity. Then, boron diffusion is used to form a first doped region 102 and a second doped region 103, thereby achieving ultra-low capacitance and low breakdown voltage. Furthermore, the breakdown value can be effectively controlled by controlling the temperature and time of boron diffusion, and the low junction capacitance of the device can be guaranteed, thereby reducing the electromagnetic interference of the device's parasitic capacitance on the overall circuit. This method is suitable for circuit protection of communication and high-frequency devices.
[0024] like Figure 1As shown, a third doped region 104 is provided at the connection between the substrate 101 and the first doped region 102. This third doped region 104 is an annular groove structure extending downwards from the upper surface of the substrate 101 on the outer side and downwards from the upper surface of the first doped region 102 on the inner side, with a groove depth less than that of the first doped region 102. One side of the third doped region 104 is connected to the substrate 101, and the other side is connected to the first doped region 102. Its bottom is connected to a portion of the substrate 101, a portion of the first PN junction J1, and a portion of the first doped region 102. The third doped region 104 is N-type doped, and its doping concentration is greater than that of the substrate 101. A third PN junction J3 is connected between the third doped region 104 and the first doped region 102. Because the doping concentration of the third doped region 104 is greater than that of the substrate 101, the reverse avalanche voltage of the third PN junction J3 is less than that of the first PN junction J1. The volume of the third PN junction J3 is smaller than that of the first PN junction J1, so its doping concentration can be better controlled, and thus the magnitude of the reverse avalanche voltage of the third PN junction J3 can be better controlled.
[0025] A fourth doped region 105 is provided at the junction of the lower surface of the substrate 101 and the second doped region 103. The fourth doped region 105 is an annular groove structure extending upwards from the lower surface of the substrate 101 on the outer side and upwards from the lower surface of the second doped region 103 on the inner side, with a groove depth less than that of the second doped region 103. One side of the fourth doped region 105 is connected to the substrate 101, and the other side is connected to the second doped region 103. Its top is connected to a portion of the substrate 101, a portion of the second PN junction J2, and a portion of the second doped region 103. The fourth doped region 105 is N-type doped, and its doping concentration is greater than that of the substrate 101. A fourth PN junction J4 is connected between the fourth doped region 105 and the second doped region 103. Because the doping concentration of the fourth doped region 105 is greater than that of the substrate 101, the reverse avalanche voltage of the fourth PN junction J4 is less than that of the second PN junction J2. The fourth PN junction J4 has a smaller volume than the second PN junction J2, so its doping concentration can be better controlled, which in turn allows for better control of the magnitude of the reverse avalanche voltage of the fourth PN junction J4.
[0026] like Figure 1As shown, multiple fifth doped regions 106 are provided within the first doped region 102, spaced apart inside the third doped region 104. The fifth doped regions 106 on both sides are annular groove structures extending downwards from the upper surface of the first doped region 102, while the fifth doped region 106 in the middle is a recessed groove structure extending downwards from the upper surface of the first doped region 102. All fifth doped regions 106 have the same groove width and junction depth. The multiple fifth doped regions 106 are N-type doped, and each fifth doped region 106 is connected to the first doped region 102 via a fifth PN junction J5. Figure 1 In the illustrated embodiment, three fifth doped regions 106 are provided, and the three fifth doped regions 106 are spaced apart inside the third doped region 104. The two fifth doped regions 106 on both sides have annular groove structures, and the fifth doped region 106 in the middle has a groove structure. When a forward overvoltage occurs, the voltage rises rapidly, and each fifth doped region 106 is turned on, thereby achieving forward overvoltage protection.
[0027] like Figure 1 As shown, multiple sixth doped regions 107 are provided within the second doped region 103, spaced apart inside the fourth doped region 105. The sixth doped regions 107 on both sides are annular groove structures extending upward from the lower surface of the second doped region 103, while the sixth doped region 107 in the middle is a recessed groove structure extending upward from the lower surface of the second doped region 103. The multiple sixth doped regions 107 are N-type doped, and each sixth doped region 107 is connected to the second doped region 103 via a sixth PN junction J6. The junction depths of the multiple sixth doped regions 107 are the same, and their groove widths increase sequentially from the outermost to the middle, with the outermost sixth doped region 107 having the smallest groove width and the middle sixth doped region 107 having the largest groove width. Figure 1 In the illustrated embodiment, four sixth doped regions 107 are provided, and the four sixth doped regions 107 are spaced apart inside the fourth doped region 105. The three sixth doped regions 107 on both sides have annular groove structures, while the sixth doped region 107 in the middle has a groove structure. When reverse overvoltage occurs, it is usually a high-voltage, high-current overvoltage protection, which requires the large current to pass through evenly. Since the groove width of the outermost sixth doped region 107 is the smallest, while the groove width of the middle sixth doped region 107 is the largest, this not only facilitates high-current discharge for rapid voltage reduction, but also achieves uniform current flow, thereby reducing the heating of the silicon material and ultimately achieving the current carrying capacity required for application to meet the reverse overvoltage protection requirements.
[0028] like Figure 1As shown, a first electrode 108 is provided on the upper surface of the substrate 101, and the first electrode 108 is connected to the first doped region 102 and a plurality of fifth doped regions 106. In this embodiment, the first electrode 108 is a metal electrode, which is formed by depositing a layer of metallic titanium-nickel-silver, tin-copper alloy, or nickel-gold alloy by PVD, electroplating, or chemical plating. Specifically, the first electrode 108 covers part of the upper surface of the first doped region 102, the upper surface of the plurality of fifth doped regions 106, and the edge terminal of the fifth PN junction J5. A second electrode 109 is provided on the lower surface of the substrate 101, and the second electrode 109 is connected to the second doped region 103 and a plurality of sixth doped regions 107. In this embodiment, the second electrode 109 is a metal electrode, which is formed by depositing a layer of metallic titanium-nickel-silver, tin-copper alloy, or nickel-gold alloy by PVD, electroplating, or chemical plating. Specifically, the second electrode 109 covers part of the lower surface of the second doped region 103, the lower surface of the plurality of sixth doped regions 107, and the edge terminal of the sixth PN junction J6.
[0029] like Figure 1 As shown, a first passivation layer 110 is provided on the upper surface of the substrate 101 to protect the third PN junction J3. This passivation layer is a passivation film deposited by thermal growth or CVD. The first passivation layer 110 includes SiO2, semi-insulating oxygen-doped polycrystalline silicon (Sipos), silicon phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), low-pressure deposited silicon nitride (LPSiN), etc. In this embodiment, the first passivation layer 110 has a plate-like structure. Its lower surface covers part of the upper surface of the substrate 101, the upper surface of the third doped region 104, the end of the third PN junction J3, and part of the upper surface of the first doped region 102. Its upper surface has a three-stage field plate structure with thickness increasing from the center to the edge. This embodiment provides high-reliability passivation protection for the third PN junction J3 by setting a first passivation layer 110 at the edge terminal of the third PN junction J3. The semi-insulating oxygen-doped polycrystalline silicon not only reduces high-temperature leakage current in the third PN junction J3 but also reduces the stress on the silicon substrate material from the first metal passivation layer 112, further reducing the risk of chip cracking. The thermally oxidized SiO2 oxide layer effectively isolates the device from the surrounding environment, and the negative ion centers in the thermally oxidized SiO2 oxide layer can effectively capture metal ions to prevent contamination of the third PN junction J3, thereby reducing leakage current and making the high-temperature performance of the product more stable. The low-temperature SiO2 thin film effectively avoids the effect of thermal expansion and contraction on the glass during solder melting and solidification. Furthermore, this embodiment sets the first passivation layer 110 as a third-order field plate, allowing the charge of the first electrode 108 to extend to the first metal passivation layer 112 at the edge of the device, achieving the extension of the space charge region at the edge. This allows the blocking voltage to reach the bulk breakdown voltage, reducing the probability of soft breakdown and improving product reliability.
[0030] like Figure 1As shown, a second passivation layer 111 is provided on the lower surface of the substrate 101 to protect the fourth PN junction J4. This passivation layer is a passivation film grown by thermal growth or deposited by CVD. The second passivation layer 111 includes SiO2, semi-insulating oxygen-doped polycrystalline silicon (Sipos), silicon phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), low-pressure deposited silicon nitride (LPSiN), etc. In this embodiment, the second passivation layer 111 has a plate-like structure. Its upper surface covers part of the lower surface of the substrate 101, the lower surface of the fourth doped region 105, the end of the fourth PN junction J4, and part of the lower surface of the second doped region 103. Its lower surface has a three-stage field plate structure with thickness increasing from the center to the edge. This embodiment provides high-reliability passivation protection for the fourth PN junction J4 by setting a second passivation layer 111 at the edge terminal. The semi-insulating oxygen-doped polycrystalline silicon not only reduces high-temperature leakage current in the fourth PN junction J4 but also reduces the stress on the silicon substrate material from the second metal passivation layer 113, further reducing the risk of chip cracking. The thermally oxidized SiO2 oxide layer effectively isolates the device from the surrounding environment, and the negative ion centers in the thermally oxidized SiO2 oxide layer can effectively capture metal ions to prevent contamination of the fourth PN junction J4, thereby reducing leakage current and making the product's high-temperature performance more stable. The low-temperature SiO2 thin film effectively avoids the effect of thermal expansion and contraction on the glass during solder melting and solidification. Furthermore, this embodiment sets the second passivation layer 111 as a third-order field plate, allowing the charge of the second electrode 109 to extend onto the second metal passivation layer 113 at the device edge, achieving an extension of the space charge region at the edge. This allows the blocking voltage to reach the bulk breakdown voltage, reducing the probability of soft breakdown and improving product reliability.
[0031] like Figure 1As shown, a first metal passivation layer 112 is provided on the first electrode 108 to protect the first electrode 108. This passivation layer includes metal passivation layers such as SiN, NSG, PSG, and polyamide. The first metal passivation layer 112 covers a portion of the upper surface of the first passivation layer 110, the side surface of the first electrode 108, and a portion of the upper surface of the first electrode 108. A second metal passivation layer 113 is provided on the second electrode 109 to protect the second electrode 109. This passivation layer includes metal passivation layers such as SiN, NSG, PSG, and polyamide. The second metal passivation layer 113 covers a portion of the lower surface of the second passivation layer 111, the side surface of the second electrode 109, and a portion of the lower surface of the second electrode 109. In this embodiment, the first metal passivation layer 112 and the second metal passivation layer 113 contain only silicon, SiO2 and polymide. There is no glass on the dicing channel, so the blade directly contacts the silicon during subsequent dicing. The full-cut process is adopted during dicing, which can avoid the generation of dicing cracks, effectively improve the dicing speed, reduce the generation of wastewater in production, and improve the environmental friendliness of the production process.
[0032] like Figure 1 and Figure 2 As shown, the working principle of this embodiment is as follows: when the first electrode 108 is negative voltage and the second electrode 109 is positive voltage, the second PN junction J2, the fourth PN junction J4 and the fifth PN junction J5 are forward biased, and the first PN junction J1 and the third PN junction J3 are reverse biased. Since the reverse avalanche voltage of the third PN junction J3 is less than the reverse avalanche voltage of the first PN junction J1, the reverse breakdown voltage is mainly determined by the third PN junction J3. When the voltage difference between the second electrode 108 and the first electrode 107 exceeds the reverse avalanche breakdown voltage of the third PN junction J3, the current increases sharply. When the product of the current and the resistance of the first doped region 102 reaches the forward voltage drop of the fifth PN junction J5 (0.7V), the fifth PN junction J5 conducts forward, and current is injected into the fifth doped region 106. This ultimately forms an NPN structure composed of the fifth doped region 106, the first doped region 102, and the substrate 101, and a PNP structure composed of the first doped region 102, the substrate 101, and the second doped region 103, thus creating a mutual amplification effect of positive feedback between the NPN and PNP dual transistors. Figure 2 The forward blocking mode shown is the current-voltage curve of the forward overvoltage performance test, which is derived from... Figure 2 As can be seen from the forward blocking mode curve, when there is a forward overvoltage, the fifth PN junction J5 conducts, and the waveform sweeps back, thus achieving circuit protection against forward overvoltage.
[0033] like Figure 1 , Figure 2As shown, when the first electrode 108 is at a positive voltage and the second electrode 109 is at a negative voltage, the second PN junction J2, the fourth PN junction J4 and the fifth PN junction J5 are reverse biased, while the first PN junction J1, the third PN junction J3 and the sixth PN junction J6 are forward biased. Since the reverse avalanche voltage of the fourth PN junction J4 is less than the reverse avalanche voltage of the second PN junction J2, the reverse breakdown voltage is mainly determined by the fourth PN junction J4. When the voltage difference between the first electrode 108 and the second electrode 109 exceeds the reverse avalanche breakdown voltage of the fourth PN junction J4, the current increases sharply. When the product of the current and the resistance of the second doped region 103 reaches the forward voltage drop of the sixth PN junction J6 (0.7V), the sixth PN junction J6 is forward-biased, and current is injected into the sixth doped region 107. This ultimately forms an NPN structure composed of the sixth doped region 107, the second doped region 103, and the substrate 101, and a PNP structure composed of the second doped region 103, the substrate 101, and the first doped region 102, thus creating a mutual amplification effect of positive feedback between the NPN and PNP dual transistors. Figure 2 The reverse blocking mode shown is the current-voltage curve for reverse overvoltage performance testing. Figure 2 As can be seen from the reverse blocking mode curve, when there is reverse overvoltage, the current is large, and the waveform shows a sweepback after the fourth PN junction J4 is turned on, thereby realizing the circuit protection of reverse overvoltage short circuit discharge.
[0034] Furthermore, when the sixth PN junction J6 is forward-biased, since the width of the multiple sixth doped regions 109 increases sequentially from the outside to the middle, and the width of the sixth doped region 107 located in the middle is the largest, a large current can pass through evenly, realizing a large current discharge to quickly reduce voltage, and reducing the heat generation of silicon material, thereby being able to withstand a higher breakdown voltage.
[0035] like Figure 3 As shown, the fabrication method of the asymmetric bidirectional semiconductor discharge tube chip in this embodiment includes the following steps: S10, Provide a substrate 101.
[0036] In this step, the substrate 101 includes opposing upper and lower surfaces, which are N-type. <111> The crystalline substrate single crystal wafer has a thickness of 250-350 μm and a resistivity of 1.0-10.0 Ω·cm. The substrate 101 can be doped with phosphorus, i.e., P-type doping.
[0037] S20. Doping is performed on the upper surface of the substrate 101 to form a first doped region 102; doping is performed on the lower surface of the substrate 101 to form a second doped region 103.
[0038] In this step, a dense oxide layer is formed on the upper and lower surfaces of the substrate 101 through hydrogen-oxygen synthesis. The hydrogen-oxygen synthesis temperature is 1100℃, the synthesis time is 7 hours, and the thickness of the oxide layer is 13000±1000 Å. Then, the doping windows of the first doped region 102 and the second doped region 103 are prepared by photolithography. In this embodiment, negative photoresist and BOE etching solution are used to etch the doping windows of the first doped region 102 and the second doped region 103. Then, boron pre-expansion and boron main expansion are performed within the doping windows of the first doped region 102 and the second doped region 103 to form the P-type doped first doped region 102 and the second doped region 103. In the boron pre-expansion, a latex boron source is used as the dopant source. The latex boron source is uniformly covered on the upper and lower surfaces of the substrate 101 by spin coating. The maximum spin coating speed is 1600±100 r / min, and the spin coating time is: Seconds, boron pre-expansion temperature is 960℃, boron pre-expansion time is 60-90min, sheet resistance for In the boron primary expansion process, the expansion temperature is 1260℃, the expansion time is 420-480 min, and the sheet resistance is... for The diffusion junction depth is 20-40 μm, thereby forming a first doped region 102 and a second doped region 103. A first PN junction J1 is formed at the connection site between the first doped region 102 and the substrate 101. A second PN junction J2 is formed at the connection site between the second doped region 103 and the substrate 101.
[0039] S30, doping is performed on the upper surface of the first doped region 102 to form the third doped region 104 and multiple fifth doped regions 106.
[0040] In this step, photolithography is performed on the upper surface of the first doped region 102 to form the doping window of the third doped region 104 and multiple doping windows of the fifth doped regions 106. In this embodiment, negative photoresist is used for photolithography, and BOE etching solution is used for etching to form the doping windows of the third doped region 104 and multiple doping windows of the fifth doped regions 106. Phosphorus pre-expansion and main phosphorus expansion are performed on the doping windows of the third doped region 104 to form the third doped region 104, and phosphorus pre-expansion and main phosphorus expansion are performed on the doping windows of the fifth doped regions 106 to form the fifth doped region 106. The junction depth and trench width of the multiple fifth doped regions 106 are the same. In the phosphorus pre-expansion, a latex phosphorus source or phosphorus oxychloride diffusion process is used, the phosphorus pre-expansion temperature is 1030℃, and the phosphorus pre-expansion time is 180-240 min. Sheet resistance... for In the phosphorus primary expansion process, the phosphorus primary expansion temperature is 1150℃, the phosphorus pre-expansion time is 240-300 min, and the sheet resistance is... for A third PN junction J3 is connected between the third doped region 104 and the first doped region 102, and multiple fifth doped regions 106 are respectively connected to the first doped region 102 via fifth PN junctions J5.
[0041] S40, doping is performed on the lower surface of the second doped region 103 to form the fourth doped region 105 and multiple sixth doped regions 107.
[0042] In this step, photolithography is performed on the lower surface of the second doped region 103 to form the doping window of the fourth doped region 105 and multiple doping windows of the sixth doped region 107. In this embodiment, negative photoresist is used for photolithography, and BOE etching solution is used for etching to form the doping windows of the fourth doped region 105 and multiple doping windows of the sixth doped region 107. Then, phosphorus pre-expansion and main phosphorus expansion are performed on the doping windows of the fourth doped region 105 to form the fourth doped region 105, and phosphorus pre-expansion and main phosphorus expansion are performed on the doping windows of the sixth doped region 107 to form the sixth doped region 107. The junction depth of the multiple sixth doped regions 107 is the same, and their trench width increases sequentially from the outside to the middle. In the phosphorus pre-expansion, a latex phosphorus source or phosphorus oxychloride diffusion process is used, the phosphorus pre-expansion temperature is 1030℃, and the phosphorus pre-expansion time is 180-240 min. Sheet resistance... for In the phosphorus primary expansion process, the phosphorus primary expansion temperature is 1150℃, the phosphorus pre-expansion time is 240-300 min, and the sheet resistance is... for A fourth PN junction J4 is connected between the fourth doped region 105 and the second doped region 103, and a plurality of sixth doped regions 107 are connected to the second doped region 103 via sixth PN junctions J6.
[0043] S50. A first passivation layer 110 is formed at the end of the third PN junction J3, and a second passivation layer 111 is formed at the end of the fourth PN junction J4.
[0044] In this step, a first passivation layer 110 is formed at the end of the third PN junction J3. The first passivation layer 110 is a passivation film formed by thermal growth or CVD deposition, and the passivation film structure is SiO2, Sipos, PSG, BPSG, LPSiN, etc. A second passivation layer 111 is formed at the end of the fourth PN junction J4. The second passivation layer 111 is a passivation film formed by thermal growth or CVD deposition, and the passivation film structure is SiO2, Sipos, PSG, BPSG, LPSiN, etc.
[0045] S60. A first electrode 108 is formed on the upper surface of the first doped region 102, and a second electrode 109 is formed on the lower surface of the second doped region 103.
[0046] In this step, the contact hole of the first electrode 108 is exposed by photolithography on the first passivation layer 110. The contact hole of the first electrode 108 is located on the upper surface of the first doped region 102, and the end of its lower surface is located between the third doped region 104 and the outermost fifth doped region 106. A layer of metallic titanium-nickel-silver, tin-copper alloy or nickel alloy is deposited in the contact hole of the first electrode 108 by PVD, electroplating or chemical plating to form the first electrode 108. The first electrode 108 is connected to the first doped region 102 and the multiple fifth doped regions 106 respectively. The contact hole of the second electrode 109 is exposed by photolithography on the second passivation layer 111. The contact hole of the second electrode 109 is located on the lower surface of the second doped region 103, and the end of its upper surface is located between the fourth doped region 105 and the outermost sixth doped region 107. A layer of metallic titanium-nickel-silver, tin-copper alloy or nickel alloy is deposited in the contact hole of the second electrode 109 by PVD, electroplating or chemical plating to form the second electrode 109. The second electrode 109 is connected to the second doped region 102 and the multiple sixth doped regions 107 respectively.
[0047] S70. A first metal passivation layer 112 is formed on the first electrode 108, and a second metal passivation layer 113 is formed on the second electrode 109.
[0048] In this step, a first metal passivation layer 112 is prepared on the first electrode 108 using photoresist to protect the first electrode 108, and a second metal passivation layer 113 is prepared on the second electrode 109 using photoresist to protect the second electrode 109. Specifically, a negative photoresist and a metal etching solution are used to etch windows for the first metal passivation layer 112 and the second metal passivation layer 113. Then, a PVD process is used to cover SiN, NSG, PSG, etc., or a photolithography process is used to cover a metal passivation layer such as Polymide, thereby forming the first metal passivation layer 112 and the second metal passivation layer 113.
[0049] In summary, the asymmetric bidirectional semiconductor discharge transistor chip of this invention forms an NPN-PNP dual transistor by setting a highly concentrated doped third doped region 104 at the end of the first PN junction J1, a highly concentrated doped fourth doped region 105 at the end of the second PN junction J2, and multiple fifth doped regions 106 within the first doped region 102 and multiple sixth doped regions 107 within the second doped region 103, thereby achieving bidirectional overvoltage protection. Furthermore, since the trench width of the multiple sixth doped regions 107 within the second doped region 103 increases sequentially from both sides to the middle, a large current discharge can be achieved to rapidly reduce the voltage when the negative electrode is overvoltaged, thus enabling it to withstand higher breakdown voltages. It also achieves uniformity of large current flow, thereby reducing silicon material heating and ultimately achieving the required current carrying capacity for reverse overvoltage protection. In addition, by setting a first passivation layer 110 and a second passivation layer 111, composite high-reliability passivation protection can be provided for the third PN junction J3 and the fourth PN junction J4, respectively. The first passivation layer 110 and the second passivation layer 111 are configured as a third-order field plate structure, so that the charge of the first electrode 108 and the second electrode 109 extends to the first metal passivation layer 112 and the second metal passivation layer 113 at the edge of the device, thereby realizing the extension of the space charge region at the edge, so that the blocking voltage reaches the bulk breakdown voltage, reducing the probability of soft breakdown and improving the reliability of the product.
[0050] Although the present invention has been disclosed through the above embodiments, the scope of protection of the present invention is not limited thereto. Any modifications or substitutions made to the above components without departing from the concept of the present invention shall fall within the scope of the claims of the present invention.
Claims
1. An asymmetric bidirectional semiconductor discharge tube chip, characterized by, The chip includes: The substrate includes an opposing upper surface and a lower surface; The first doped region is a groove structure extending downward from the upper surface of the substrate, and a first PN junction is connected between the first doped region and the substrate. The second doped region is a groove structure extending upward from the lower surface of the substrate, and a second PN junction is connected between the second doped region and the substrate. The third doped region is located at the end of the first PN junction. It is an annular groove structure that extends downward from the upper surface of the substrate on the outside and downward from the upper surface of the first doped region on the inside. The third doped region is connected to the first doped region by a third PN junction, and the reverse avalanche voltage of the third PN junction is less than the reverse avalanche voltage of the first PN junction. The fourth doped region is located at the end of the second PN junction. It is an annular groove structure that extends upward from the lower surface of the substrate on the outside and upward from the lower surface of the second doped region on the inside. The fourth doped region is connected to the second doped region by a fourth PN junction, and the reverse avalanche voltage of the fourth PN junction is less than that of the second PN junction. Multiple fifth doped regions are spaced apart inside the third doped region, and each fifth doped region is connected to the first doped region by a fifth PN junction. Multiple sixth doped regions are spaced apart inside the fourth doped region, and the trench width of each sixth doped region increases from both sides to the middle. Each sixth doped region is connected to the second doped region by a sixth PN junction. The first electrode is connected to the first doped region and the fifth doped region, respectively; The second electrode is connected to the second doped region and the sixth doped region, respectively.
2. The asymmetric bidirectional semiconductor discharge tube chip of claim 1, wherein, The substrate is N-type doped, the first and second doped regions are P-type doped, and the third, fourth, fifth, and sixth doped regions are N-type doped, with the doping concentration of the third and fourth doped regions being higher than the doping concentration of the substrate.
3. The asymmetric bidirectional semiconductor discharge tube chip of claim 1, wherein, The sixth doped region on both sides is an annular groove structure extending upward from the lower surface of the second doped region, while the sixth doped region in the middle is a groove structure extending upward from the lower surface of the second doped region.
4. The asymmetric bidirectional semiconductor discharge tube chip of claim 1, wherein, The chip also includes a first passivation layer, which is a plate-like structure. Its lower surface covers part of the upper surface of the substrate, the upper surface of the third doped region, the end of the third PN junction J3, and part of the upper surface of the first doped region. Its upper surface is a three-stage field plate structure with the thickness increasing from the middle to the edge.
5. The asymmetric bidirectional semiconductor discharge tube chip of claim 1, wherein, The chip also includes a second passivation layer, which is a plate-like structure. Its upper surface covers part of the lower surface of the substrate, the lower surface of the fourth doped region, the end of the fourth PN junction J4, and part of the lower surface of the second doped region. Its lower surface is a three-stage field plate structure with the thickness increasing from the middle to the edge.
6. The asymmetric bidirectional semiconductor discharge tube chip of claim 4, wherein, The chip also includes a first metal passivation layer, which covers a portion of the upper surface of the first passivation layer, the side portion of the first electrode, and a portion of the upper surface of the first electrode.
7. The asymmetric bidirectional semiconductor discharge tube chip of claim 5, wherein, The chip also includes a second metal passivation layer, which covers a portion of the lower surface of the second passivation layer, the side portion of the second electrode, and a portion of the lower surface of the second electrode.
8. The asymmetric bidirectional semiconductor discharge tube of claim 1, wherein the first and second electrodes are formed of a material selected from the group consisting of: tungsten, molybdenum, tantalum, rhenium, and alloys thereof. The first electrode is a metal electrode made of titanium-nickel-silver, tin-copper alloy, or nickel-gold alloy; the second electrode is a metal electrode made of titanium-nickel-silver, tin-copper alloy, or nickel-gold alloy.
9. The asymmetric bidirectional semiconductor discharge tube chip as described in claim 6, characterized in that, The first metal passivation layer is SiN, NSG, phosphosilicate glass, or polyamide metal passivation layer.
10. The asymmetric bidirectional semiconductor discharge tube chip of claim 7, wherein, The second metal passivation layer is SiN, NSG, phosphosilicate glass, or polyamide metal passivation layer.