A semiconductor device and a transmit / receive assembly
By employing a single-step gate fabrication process with a GaAs/InGaP/AlGaAs composite barrier layer structure, the electrical and reliability issues caused by multiple gate processes in pHEMT devices have been resolved, enabling efficient fabrication of E-mode/D-mode multifunctional integrated circuit devices and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAMEN SANAN INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2025-05-16
- Publication Date
- 2026-07-31
AI Technical Summary
Existing pHEMT devices suffer from high costs due to the multiple gate metal growth processes involved in fabricating E-mode/D-mode multifunctional integrated circuit elements, which affect the device's electrical properties and reliability.
A GaAs/InGaP/AlGaAs composite barrier layer structure is adopted, and the gate is formed in the D-mode and E-mode regions respectively through a single-step gate fabrication process. The GaAs layer is used to reduce the contact resistance, the InGaP layer is used as an etch stop layer, and the AlGaAs layer is used as the E-mode gate metal contact material to achieve single-step integration of the device.
This reduces the number of gate metal growth and annealing steps, improves device performance, lowers costs, avoids electrical degradation, and enhances reliability.
Smart Images
Figure CN224583590U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor device and a transmitter-receiver assembly. Background Technology
[0002] Pseudomorphic high electron mobility transistors (pHEMTs) provide key components for high-performance radio frequency (RF) and microwave applications, particularly in wireless communications, satellite communications, radar, and space technology. With advancements in materials science and manufacturing processes, the performance of pHEMT devices continues to improve, and their application range continues to expand.
[0003] As a three-terminal device, pHEMT has higher electron mobility and less scattering effect compared to other three-terminal devices, making it more suitable for applications with high requirements for frequency and noise. For example, it is used in microwave RF chips as the core amplifying transistor in power amplifiers (PA) and low-noise amplifiers (LNA). In these circuit components, power amplifiers require the use of enhancement-mode (D-mode) pHEMTs, while LNAs more often use enhancement-mode (E-mode) pHEMTs. Integrating both types of devices on the same chip requires multiple etching and gate metal growth processes, which is currently the main fabrication method for this type of integrated circuit component.
[0004] Currently, when fabricating E-mode / D-mode multifunctional integrated circuit devices, pHEMT products first fabricate the gate process of D-mode pHEMT, and then complete the gate process of E-mode pHEMT. Because a tempering process is required after both gate metal growths, the subsequent E-mode pHEMT gate fabrication process will inevitably affect the previous D-mode pHEMT gate process, thereby causing a deterioration in the electrical performance and reliability of such E-mode and D-mode multifunctional integrated circuit devices.
[0005] Furthermore, because the gate pitch of D-mode devices is larger than that of E-mode devices, the gate fabrication process needs to be completed in two separate steps for both types of devices. The current mainstream method is to grow the gate metal in two stages. In E-mode, the thickness of the bottom platinum (Pt) gate metal is significantly greater than that of D-mode to meet the different gate pitch requirements. This technique has no significant requirements for the pHEMT epitaxial layer, typically using an AlGaAs barrier layer. It only requires two gate etching and metal growth operations; the bottom Pt metal can be changed when setting the metal growth menu. However, this fabrication process requires two gate metal growth operations and two electron beam exposures, which not only affects the reliability of the device but also increases the cost of the fabricated multifunctional integrated circuit device.
[0006] However, in GaAs pHEMT devices, key performance parameters, including transconductance, cutoff frequency, power gain, operating frequency range, power-added efficiency (PAE), linearity, and noise figure, are directly affected by gate quality. Therefore, reducing gate metal growth and annealing steps and realizing a single-step depletion-mode plus enhancement-mode gate process is urgently needed to improve chip performance. Summary of the Invention
[0007] The technical problem to be solved by this utility model is to provide a semiconductor device and a transmitter-receiver assembly that reduces process steps and avoids the impact of the two-step gate fabrication process on the electrical properties of the device.
[0008] To solve the above-mentioned technical problems, the technical solution of this utility model is:
[0009] A semiconductor device includes a substrate and an epitaxial layer formed on the substrate. The epitaxial layer includes a first semiconductor layer and a second semiconductor layer stacked sequentially from bottom to top. The first semiconductor layer includes at least a channel layer, and the second semiconductor layer includes at least a barrier layer and a cap layer. The barrier layer is composed of an AlGaAs layer, an InGaP layer and a GaAs layer stacked sequentially from bottom to top.
[0010] The epitaxial layer is divided into a D-mode region, an isolation region, and an E-mode region. The isolation region is located between the D-mode region and the E-mode region. The isolation region extends through the epitaxial layer to the substrate. The cap layer of the D-mode region forms a first groove, and the cap layer of the E-mode region and the AlGaAs layer of the barrier layer form a second groove.
[0011] The D-mode region has a first source, a first gate, and a first drain, with the first source and the first drain located on a cap layer. The first gate is disposed in the first groove and located on a GaAs layer. The E-mode region has a second source, a second gate, and a second drain, with the second source and the second drain located on a cap layer. The second gate is disposed in the second groove and located on an AlGaAs layer.
[0012] Furthermore, the thickness of the GaAs layer is 30~60 angstroms, the thickness of the InGaP layer is 15~35 angstroms, and the thickness of the AlGaAs layer is 150~210 angstroms.
[0013] Furthermore, the thickness of the InGaP layer is smaller than that of the GaAs layer.
[0014] Furthermore, the doping concentration of the GaAs layer is 5E16~4E17 cm⁻¹ -3 The doping concentration of the InGaP layer is 1E17~4E17 cm⁻¹ -3 The doping concentration of the AlGaAs layer is 1E17~5E17 cm⁻¹ -3 .
[0015] Furthermore, the cap layer has a multi-layer structure, consisting of a first etch barrier layer, a GaAs first cap layer, a second etch barrier layer, and a GaAs second cap layer stacked from bottom to top.
[0016] Furthermore, the first gate and the second gate are made of the same material, and from bottom to top they are a Pt / Ti / Pt / Au / Ti metal stack, namely the first Pt layer, the first Ti layer, the second Pt layer, the Au layer and the second Ti layer.
[0017] Furthermore, after the first and second gates are tempered, the Pt metal in the first Pt layer penetrates to a depth of 30-80 angstroms into the barrier layer.
[0018] Furthermore, the first semiconductor layer also includes a buffer layer, a lower doped layer, a lower spacer layer, an upper spacer layer, and an upper doped layer stacked sequentially from bottom to top, with the channel layer located between the lower spacer layer and the upper spacer layer.
[0019] Furthermore, the lower spacer layer and the upper spacer layer are made of the same material, AlGaAs, and the lower doped layer and the upper doped layer are made of the same material, Si planar doped AlGaAs.
[0020] This invention also provides a transmitting and receiving assembly, including the semiconductor device described above.
[0021] By adopting the above solution, since this invention changes the conventional AlGaAs barrier layer to a composite barrier layer structure of GaAs / InGaP / AlGaAs, it has the following advantages:
[0022] 1. As the semiconductor material in direct contact with the gate metal of D-mode devices, the GaAs layer has a low bandgap, which can significantly reduce the device's Rc (contact resistance) and Ron (on-resistance) and improve device performance.
[0023] 2. The InGaP layer serves as a barrier layer during the etching of the GaAs layer, and its high bandgap width also reduces gate leakage current.
[0024] 3. The AlGaAs layer serves as a barrier layer during the etching of the InGaP layer, and also as the semiconductor material in direct contact with the gate metal of the E-mode device.
[0025] 4. When forming the gate trench, only the cap layer above the barrier layer is etched, so that the GaAs layer in the barrier layer contacts the subsequent gate metal to form the first gate (D-mode gate). On this basis, additional etching steps are added to the GaAs layer and the InGaP layer, so that the subsequent gate metal contacts the AlGaAs layer to form the second gate (E-mode gate). The two types of devices control the gate trench spacing by different etching depths, thereby changing the threshold voltage to form a semiconductor device combining E-mode and D-mode. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the structure of this utility model;
[0027] Figure 2 yes Figure 1 Enlarged view at point D;
[0028] Figure 3 This is a schematic diagram of the epitaxial layer of the second embodiment of this utility model;
[0029] Figure 4 This is a schematic diagram of the process flow of this utility model.
[0030] Label Explanation
[0031] Substrate 1, Epitaxial layer 2, Buffer layer 21, Lower doped layer 22, Lower spacer layer 23
[0032] Channel layer 24, upper spacer layer 25, upper doped layer 26, barrier layer 27
[0033] AlGaAs layer 271 InGaP layer 272 GaAs layer 273 Cap layer 28
[0034] First etch barrier layer 281 GaAs first cap layer 282
[0035] Second etch barrier layer 283 GaAs second cap layer 284
[0036] First groove 31, Second groove 32, First source 41, First gate 42
[0037] First drain 43, second source 44, second gate 45, second drain 46
[0038] D-mode zone A, isolation zone B, E-mode zone C Detailed Implementation
[0039] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the terms "upper," "lower," "inner," and "outer," etc., referring to the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use, are merely for ease of description and should not be construed as limiting the present invention. The technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0040] This utility model discloses a semiconductor device, such as... Figure 1 As shown, this is a preferred embodiment of the present invention, including a substrate 1 and an epitaxial layer 2 formed on the substrate. The epitaxial layer has a multilayer structure, including a first semiconductor layer and a second semiconductor layer stacked sequentially from bottom to top. The first semiconductor layer includes at least a channel layer 24, and the second semiconductor layer includes at least a barrier layer 27 and a cap layer 28. The barrier layer 27 is composed of an AlGaAs layer 271, an InGaP layer 272, and a GaAs layer 273 stacked sequentially from bottom to top.
[0041] In this embodiment, the first semiconductor layer further includes a buffer layer 21, a lower doped layer 22, a lower spacer layer 23, an upper spacer layer 25, and an upper doped layer 26 stacked sequentially from bottom to top, and the channel layer 24 is located between the lower spacer layer 23 and the upper spacer layer 25.
[0042] The epitaxial layer is divided into D-mode region A, isolation region B, and E-mode region C.
[0043] The E / D integrated GaAs pHEMT device to be manufactured integrates an enhancement-mode GaAs pHEMT device and a depletion-mode GaAs pHEMT device. The epitaxial layer is divided according to the boundary between the two types of devices and the location of each electrode. Therefore, the epitaxial layer is divided into a D-mode region A, an isolation region B, and an E-mode region C. The enhancement-mode GaAs pHEMT device is located in the D-mode region A, and the depletion-mode GaAs pHEMT device is located in the E-mode region C.
[0044] Isolation region B is located between the D-mode region and the E-mode region; the isolation region extends through the epitaxial layer to the substrate, and the isolation region can be formed by ion implantation or by etching to form a physical isolation trench.
[0045] The cap layer 28 in the D-mode region forms a first groove 31, and the cap layer 28 in the E-mode region and the AlGaAs layer 271 of the barrier layer 27 form a second groove 32.
[0046] D-mode region A has a first source 41, a first gate 42, and a first drain 43. The first source 41 and the first drain 43 are located on the cap layer 28, and the first gate 42 is disposed in the first recess 31 and located on the GaAs layer 273. E-mode region C has a second source 44, a second gate 45, and a second drain 46. The second source 44 and the second drain 46 are located on the cap layer 28, and the second gate 45 is disposed in the second recess 32 and located on the AlGaAs layer 271. This invention realizes the gate metal fabrication of a single-step E-mode+D-mode multifunctional integrated circuit device through a GaAs / InGaP / AlGaAs composite barrier layer structure.
[0047] Furthermore, the thickness of GaAs layer 273 is 30-60 Å, the thickness of InGaP layer 272 is 15-35 Å, and the thickness of AlGaAs layer 271 is 150-210 Å. GaAs layer 273 serves as the topmost barrier layer, and its low barrier height can significantly reduce the device's Rc and Ron. InGaP layer 272 acts as a barrier layer during the etching of GaAs layer 273, and also reduces gate leakage current. AlGaAs layer 271 serves as a barrier layer for E-mode devices and a barrier layer for etching InGaP layer 272.
[0048] Furthermore, the thickness of the InGaP layer 272 is less than that of the GaAs layer 273. The InGaP layer 272, as an etch stop layer, does not need to be too thick, and the InGaP layer 272 has a large bandgap, so reducing its thickness is beneficial to Rc and Ron.
[0049] Furthermore, the doping concentration of GaAs layer 273 is 5E16~4E17 cm⁻¹. -3 The doping concentration of the InGaP layer 272 is 1E17~4E17 cm⁻¹ -3 The doping concentration of the AlGaAs layer 271 is 1E17~5E17 cm⁻¹ -3 The lightly doped barrier layer design, on the one hand, helps to reduce the Rc and Ron of the device, and on the other hand, can provide electrons to the channel layer 24, thereby increasing the channel two-dimensional electron gas concentration and saturation current density of the device. In this embodiment, the material of the channel layer 24 is InGaAs.
[0050] like Figure 3 As shown, in the second embodiment of this utility model, the cap layer 28 has a multi-layer structure, consisting of a first etch barrier layer 281, a GaAs first cap layer 282, a second etch barrier layer 283, and a GaAs second cap layer 284 stacked from bottom to top. When etching the cap layer 28 to form gate recesses (first recess 31 and second recess 32), the GaAs second cap layer 284 is etched first using citric acid or succinic acid with hydrogen peroxide. The AlAs second barrier layer 283 serves as a barrier layer in this etching step, and is subsequently removed by hydrochloric acid cleaning. The gate recess processes in D-mode and E-mode will differ. For D-mode, citric acid or succinic acid with hydrogen peroxide is used to etch the GaAs first cap layer 282, and then hydrochloric acid is used to clean and remove the AlAs first barrier layer 281. The GaAs layer 273 serves as a barrier layer when the first etch barrier layer 281 is etched by hydrochloric acid, ultimately forming the first recess 31. For E-mode, based on the D-mode gate recess, citric acid or succinic acid plus hydrogen peroxide is used to etch the GaAs layer 273 and phosphoric acid is used to etch the InGaP layer 272 to form a second groove 32.
[0051] Furthermore, the material of the first etch barrier layer 281 is AlAs or InGaP, and the material of the second etch barrier layer 283 is AlAs or InGaP.
[0052] Furthermore, the lower spacer layer 23 and the upper spacer layer 25 are made of the same material, AlGaAs. The lower spacer layer 23 serves to isolate the lower doped layer 22 and the channel layer 24. Similarly, the upper spacer layer 25 serves to isolate the upper doped layer 26 and the channel layer 24. By isolating the electrons in the channel layer 24 from the donor ions that provide electrons in the lower doped layer 22 and the upper doped layer 26, Coulomb scattering is reduced, thereby improving the channel electron mobility.
[0053] Furthermore, the first gate 42 and the second gate 45 are made of the same material, consisting of a Pt / Ti / Pt / Au / Ti (i.e., platinum / titanium / platinum / gold / titanium) metal stack from bottom to top, namely the first Pt layer, the first Ti layer, the second Pt layer, the Au layer, and the second Ti layer. The first Pt layer serves to allow the gate metal to penetrate into the barrier layer during tempering, and its thickness can be designed according to the threshold voltage requirements when designing the device. The first Ti layer, because it does not penetrate, controls the thickness of the gate metal penetration. The second Pt layer acts as a barrier layer to prevent the Au layer from contacting the semiconductor. The Au layer has the largest thickness, and its low resistivity reduces the parasitic resistance of the gate. The second Ti layer enhances the adhesion of the metal during subsequent metal interconnect processes.
[0054] Furthermore, before the tempering process of the first gate 42 and the second gate 45, the thickness of the first Pt layer is 20~40 angstroms. This thickness range facilitates the growth control of Pt metal, and the metal penetration thickness after tempering is easy to control, which is beneficial for the stable fabrication of E-mode and D-mode devices that meet the threshold voltage design requirements.
[0055] like Figure 2 As shown, after the tempering process of the first gate 42 and the second gate 45, the depth of Pt metal penetration into the barrier layer 27 is H, where 30 Å ≤ H ≤ 80 Å. This penetration depth range is beneficial for controlling that the bottom of the gate metal in the D-mode device does not exceed the contact between the InGaP layer 272 and the AlGaAs layer 271, while for the E-mode, it ensures that the gate metal penetration does not exceed the thickness of the AlGaAs layer 271.
[0056] In the second recess 32, the distance between the sidewall of the second gate 45 and the barrier layer (InGaP layer 272, GaAs layer 273) is L, 0.3 micrometers ≤ L ≤ 0.5 micrometers.
[0057] Furthermore, the lower doped layer 22 and the upper doped layer 26 are made of the same material, Si planar doped AlGaAs, and the channel layer 24 is made of InGaAs. The lower doped layer 22 and the upper doped layer 26 provide a two-dimensional electron gas for the channel layer 24. The planar doping concentration of the upper doped layer 26 is 5E12~3.5E12 cm⁻¹. -2 The planar doping concentration of the lower doped layer 22 is 1.5E12~1E12 cm⁻¹. -2 .
[0058] like Figure 4 As shown, taking the second embodiment as an example, a single-step gate fabrication process is used, requiring only one electron beam lithography development and one gate metal evaporation, which can significantly reduce the cost of E-mode+D-mode multifunctional integrated circuit devices.
[0059] Step 1: Provide an epitaxial wafer, comprising, from bottom to top, a substrate 1, a buffer layer 21, a lower doped layer 22, a lower spacer layer 23, a channel layer 24, an upper spacer layer 25, an upper doped layer 26, an AlGaAs layer 271, an InGaP layer 272, a GaAs layer 273, a first etch stop layer 281, a GaAs first cap layer 282, a second etch stop layer 283, and a GaAs second cap layer 284. The substrate 1 is a semi-insulating GaAs substrate (IS GaAs), and the first etch stop layer 281 and the second etch stop layer 283 are made of AlAs.
[0060] Step 2: Perform IS (silicon implantation) isolation on the epitaxial wafer to form D-mode region A, isolation region B and E-mode region C. At the same time, etch the second GaAs cap layer 284 and the second etch barrier layer 283 to form RE grooves in D-mode region A and E-mode region C, respectively.
[0061] Step 3: Continue etching the first GaAs cap layer 282 and the first etch barrier layer 281 in the D-mode region A to form the first groove 31.
[0062] Step four: In the E-mode region C, the first GaAs cap layer 282, the first etch barrier layer 281, the GaAs barrier layer and the InGaP barrier layer are etched to form the second groove 32.
[0063] Step 5: Metal stacks are deposited in the first groove 31 and the second groove 32 respectively, from bottom to top: Pt / Ti / Pt / Au / Ti. After the deposition is completed, a tempering process is performed, and the bottommost Pt penetrates into the barrier layer, finally forming the first gate 42 and the second gate 45.
[0064] Step 6: Deposit metal onto the second cap layer 284 of GaAs to form the first source 41, the first drain 43, the second source 44, and the second drain 46.
[0065] As can be seen from the above methods, when fabricating E-mode+D-mode multifunctional integrated circuit devices, the gate fabrication of E-mode+D-mode can be completed in one go through a single gate process. Compared with the conventional process of first D-mode and then E-mode, this avoids the impact of multiple gate processes on the device and prevents the device's electrical performance from deteriorating and its reliability from decreasing.
[0066] This invention also provides a transmitting and receiving assembly, including the semiconductor device described above. This transmitting and receiving assembly is suitable for specialized applications such as microwave transceiver communication and satellite communication.
[0067] The above description is merely a preferred embodiment of the present utility model and does not constitute any limitation on the technical scope of the present utility model. Therefore, any changes or modifications made in accordance with the claims and description of the present utility model should fall within the scope of the patent of the present utility model.
Claims
1. A semiconductor device, characterized in that: The device includes a substrate and an epitaxial layer formed on the substrate. The epitaxial layer includes a first semiconductor layer and a second semiconductor layer stacked sequentially from bottom to top. The first semiconductor layer includes at least a channel layer, and the second semiconductor layer includes at least a barrier layer and a cap layer. The barrier layer is composed of an AlGaAs layer, an InGaP layer, and a GaAs layer stacked sequentially from bottom to top. The epitaxial layer is divided into a D-mode region, an isolation region, and an E-mode region. The isolation region is located between the D-mode region and the E-mode region. The isolation region extends through the epitaxial layer to the substrate. The cap layer of the D-mode region forms a first groove, and the cap layer of the E-mode region and the AlGaAs layer of the barrier layer form a second groove. The D-mode region has a first source, a first gate, and a first drain. The first source and the first drain are located on the cap layer, and the first gate is disposed in the first groove and located on the GaAs layer. The E-mode region has a second source, a second gate, and a second drain. The second source and the second drain are located on the cap layer, and the second gate is disposed in the second groove and located on the AlGaAs layer.
2. A semiconductor device according to claim 1, characterized in that: The thickness of GaAs layers is 30–60 angstroms, the thickness of InGaP layers is 15–35 angstroms, and the thickness of AlGaAs layers is 150–210 angstroms.
3. A semiconductor device according to claim 1, characterized in that: The thickness of the InGaP layer is less than that of the GaAs layer.
4. A semiconductor device according to claim 1, characterized in that: The doping concentration of the GaAs layer is 5E16~4E17 cm -3 The doping concentration of the InGaP layer is 1E17~4E17 cm -3 The doping concentration of the AlGaAs layer is 1E17~5E17 cm -3 .
5. A semiconductor device according to claim 1, characterized in that: The cap layer has a multi-layer structure, consisting of a first etch barrier layer, a GaAs first cap layer, a second etch barrier layer, and a GaAs second cap layer stacked from bottom to top.
6. A semiconductor device according to claim 1, characterized in that: The first gate and the second gate are made of the same material, and from bottom to top they are Pt / Ti / Pt / Au / Ti metal stacks, namely the first Pt layer, the first Ti layer, the second Pt layer, the Au layer and the second Ti layer.
7. A semiconductor device according to claim 6, characterized in that: After the first and second gates are tempered, the Pt metal of the first Pt layer penetrates to a depth of 30–80 angstroms into the barrier layer.
8. A semiconductor device according to claim 1, characterized in that: The first semiconductor layer also includes a buffer layer, a lower doped layer, a lower spacer layer, an upper spacer layer, and an upper doped layer stacked sequentially from bottom to top, with the channel layer located between the lower spacer layer and the upper spacer layer.
9. A semiconductor device according to claim 8, characterized in that: The lower and upper spacer layers are made of the same material, AlGaAs, or the lower and upper doped layers are made of the same material, Si planar doped AlGaAs.
10. A transmitting and receiving assembly, characterized in that: Including the semiconductor devices as described in claims 1-9.