A sic-mosfet device with reduced parasitic capacitance

Abstract

This invention provides a SiC-MOSFET device for reducing parasitic capacitance, belonging to the technical field of SiC-MOSFET devices. The SiC-MOSFET device for reducing parasitic capacitance includes: a silicon carbide semiconductor body; a gate structure formed on the upper surface of the semiconductor body; a source region and a drain region located on both lateral sides of the gate structure; a source metal layer covering the source region and extending into the chip; and a shielding cage formed by bending the source metal layer downwards and laterally surrounding the gate structure. The shielding cage and the source metal layer are of the same conductor and maintain the same potential. The shielding cage surrounds the gate structure on at least three sides, and an insulating spacer layer is formed between the shielding cage and the gate structure. This reduces the gate-drain parasitic capacitance of the SiC-MOSFET without increasing the chip area or process complexity.

Description

Technical Field

[0001] This utility model belongs to the technical field of SiC-MOSFET devices, and more specifically, relates to a SiC-MOSFET device that reduces parasitic capacitance. Background Technology

[0002] Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC-MOSFETs) are a new generation of wide-bandgap semiconductor switching devices that emerged after silicon-based power devices. Leveraging their wide bandgap of approximately 3.2 eV, high critical breakdown electric field, and high thermal conductivity, they significantly reduce the drift region thickness at the same voltage withstand, thereby significantly lowering on-resistance and increasing the upper limit of operating temperature. Thanks to these material advantages, SiC-MOSFETs have rapidly replaced traditional silicon IGBTs and superjunction MOSFETs in fields such as new energy vehicle main inverters, photovoltaic inverters, high-speed charging piles, and industrial power supplies. However, as switching frequencies move towards hundreds of kilohertz and even megahertz, the impact of internal parasitic parameters on circuit performance becomes increasingly prominent. Among these, the gate-drain coupling capacitance (Cgd, also known as Miller capacitance) forms a displacement current path during high-speed turn-off, causing the gate voltage to be pulled up and resulting in false turn-on; simultaneously, the gate-source capacitance (Cgs) and Cgd together determine the gate charge, directly affecting drive losses. Traditional SiC-MOSFETs typically employ planar or trench gate structures to balance breakdown voltage and on-resistance, with field plates or rings added outside the gate to optimize the electric field distribution. However, these additional structures often create a large overlap area with the drain region, making it impossible to effectively compress the capacitance (Cgd). Furthermore, the high electric field concentration at the edge of the field plate introduces new reliability risks. To reduce capacitance, the industry has attempted methods such as thinning the gate oxide, shortening the gate length, and increasing doping in the drift region, but these inevitably sacrifice breakdown voltage or increase leakage current. Therefore, how to effectively reduce parasitic capacitance between the gate and drain, and between the gate and source while maintaining high breakdown voltage and low on-resistance has become a key bottleneck for the continued evolution of SiC-MOSFETs towards higher frequencies and higher efficiency. Utility Model Content

[0003] In view of this, the present invention provides a SiC-MOSFET device for reducing parasitic capacitance, which solves the problem of reducing the gate-drain parasitic capacitance of SiC-MOSFET without increasing chip area and process complexity.

[0004] This utility model is implemented as follows: This invention provides a SiC-MOSFET device for reducing parasitic capacitance, comprising: Silicon carbide semiconductor body; A gate structure formed on the upper surface of the semiconductor body; The source and drain regions are located on both sides of the gate structure laterally; A source metal layer covers the source region and extends into the chip; And a shielding cage formed by bending the source metal layer downwards and laterally surrounding the gate structure; The shielding cage and the source metal layer are the same conductor and maintain the same potential. The shielding cage surrounds the gate structure on at least three sides and forms an insulating spacer layer between the shielding cage and the gate structure.

[0005] The technical effects of this invention on reducing parasitic capacitance in a SiC-MOSFET device are as follows: By bending the source metal layer downwards integrally to form a shielding cage surrounding the gate on three sides, and setting an insulating spacer layer between the cage and the gate, the electric field lines between the gate and drain are forcibly terminated on the surface of the shielding cage at the same potential. Thus, without changing the chip area and the number of process layers, the gate-drain coupling capacitance can be significantly reduced, and the dV / dt immunity can be improved simultaneously, thereby improving the overall switching speed and reliability of the device. Here, dV / dt is the "rate of change of voltage with respect to time". In power semiconductor devices or circuits, it specifically refers to the phenomenon that the voltage of a certain node (usually the drain or collector of a MOSFET, IGBT, or other switching transistor) changes drastically in a very short time. The unit is V / μs or V / ns, and t represents time.

[0006] Based on the above technical solution, the SiC-MOSFET device for reducing parasitic capacitance of this utility model can be further improved as follows: The insulating spacer layer is a closed air gap surrounding the gate structure, which extends continuously from the upper surface of the gate structure to the sidewall and bends downward to the bottom surface.

[0007] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: after designing the insulating spacer layer as a closed air gap, the dielectric constant of the air gap is close to 1, which can further compress the capacitance between the gate and the shielding cage under the same geometric size; at the same time, the air gap can also serve as a thermal expansion buffer, reducing the mechanical stress between the metal and silicon carbide during high-temperature cycling and extending the device life.

[0008] Furthermore, the shielding cage has a U-shaped cross-section, with the U-shaped opening facing the drain region, the bottom of the U-shape located below the gate structure, and the U-shaped side arms extending upward and enclosing both sides of the gate structure.

[0009] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: by using a U-shaped shielding cage with the opening facing the drain region, the region with the highest electric field can be completely included in the shielding range, which effectively cuts off the edge electric field of the drain to the gate and avoids the introduction of additional parasitic capacitance in the source region, so that the device can still maintain low loss and low noise characteristics when operating at high frequency.

[0010] Furthermore, the upper edge of the side arm of the shielding cage is flush with the upper surface of the source metal layer, so that the shielding cage and the source metal layer form a continuous conductive shielding shell.

[0011] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: the upper edge of the shielding cage side arm is flush with the upper surface of the source metal layer to form a continuous conductive shielding shell, which eliminates the interface resistance and inductance caused by traditional multilayer metals, thereby reducing the overall impedance and improving the ability to distribute current evenly without increasing the complexity of the process.

[0012] Furthermore, the insulating spacer layer is a low dielectric constant insulating layer, which extends continuously along the outer contour of the gate structure and is sandwiched between the gate structure and the shielding cage.

[0013] In the semiconductor field, the term "low dielectric constant insulating layer" typically refers to insulating materials with a dielectric constant k < 3.9. Specifically, in this application, the following may be used, but are not limited to: Porous silica (k≈2.0–2.5); Fluorinated amorphous carbon (aC:F, k≈2.2–2.8); Polyimide, parylene, or other organic low-k polymers (k≈2.0–3.0); The above-mentioned materials are stacked or composite layers.

[0014] This layer is formed through conventional CVD, spin coating, or atomic layer deposition processes, covering the outer contour of the gate structure, thereby reducing capacitance and maintaining insulation between the shielding cage and the gate.

[0015] Furthermore, an additional spacer cavity is provided between the bottom wall of the shielding cage and the semiconductor body, and the additional spacer cavity may or may not be connected to the insulating spacer layer.

[0016] The additional spacer cavity is configured in the following ways: Before forming the shielding cage, a sacrificial layer (such as phosphosilicate glass, photoresist or low-temperature oxide) is deposited or grown on the upper surface of the semiconductor body (above the drift region). Subsequently, a source metal layer is deposited and bent downwards to form a shielding cage, at which point the sacrificial layer is located between the bottom wall of the shielding cage and the semiconductor body; Finally, the sacrificial layer is removed by wet etching or heat treatment, leaving an empty closed cavity, which is called the "additional spacer cavity".

[0017] The cavity can be a vacuum or filled with an inert gas (such as nitrogen or argon) during subsequent encapsulation to further reduce the coupling capacitance between the shielding cage and the drift zone and improve thermomechanical stress.

[0018] Furthermore, the inner surface of the side arm of the shielding cage is parallel to and equidistant from the side wall of the gate structure, so that the gate structure is symmetrically shielded in the horizontal direction.

[0019] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: keeping the inner surface of the shielding cage side arm parallel and equidistant from the gate sidewall can form a uniform electric field shield in the lateral direction, suppress local electric field spikes, avoid premature breakdown of the gate oxide layer, and thus improve the voltage margin and long-term reliability of the device.

[0020] Furthermore, the source metal layer and the shielding cage are integrally formed by the same metal deposition process, with no welding or conductive interface between them.

[0021] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: by integrally forming the source metal layer and the shielding cage through the same metal deposition process, the interface defects of traditional welding or plug connection are eliminated, which reduces contact resistance, reduces process steps and the number of metal layers, thereby improving yield and reducing manufacturing costs.

[0022] Furthermore, the U-shaped bottom of the shielding cage is located directly below the gate structure, and an additional field oxide layer is provided between the U-shaped bottom and the semiconductor body.

[0023] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: inserting an additional field oxide layer between the bottom of the U-shaped shielding cage and the semiconductor body can further reduce the vertical electric field component between the shielding cage and the drift range, thereby reducing leakage current; at the same time, the field oxide layer can also serve as a hard mask for subsequent metal alignment, simplifying the process flow.

[0024] Furthermore, the insulating spacer extends continuously in the vertical direction, so that the upper surface, sidewalls and bottom surface of the gate structure are all covered by the insulating spacer and are completely isolated from the shielding cage.

[0025] The beneficial effects of adopting the above-mentioned improved scheme are as follows: when the insulating spacer extends continuously along the upper surface, sidewall and bottom surface of the gate to form a full coverage, 360° electrical isolation is achieved between the gate and the shielding cage. This not only suppresses parasitic coupling in any direction to the greatest extent, but also provides additional mechanical protection for the gate, enabling the device to operate stably for a long time under severe vibration or temperature shock. In practical applications, the chip can be directly put into use simply by soldering it onto the substrate and leading out the gate, source and drain according to the conventional SiC-MOSFET packaging process, without the need for additional control or debugging steps.

[0026] Compared with the prior art, the beneficial effects of the SiC-MOSFET device for reducing parasitic capacitance provided by this utility model are: This invention introduces a three-dimensional shielding cage with the same potential as the source in the gate region. This cage is integrally formed by extending and bending the source metal layer into the chip, surrounding the gate on at least three sides, and retaining an insulating spacer layer between the cage and the gate. Because the cage is at the same potential as the source, the electric field lines generated by the high voltage at the drain are forcibly terminated on the cage surface and cannot penetrate to the gate. This significantly weakens the gate-drain coupling path without changing the gate oxide thickness or reducing the channel length. The insulating spacer layer uses an air gap or a low-dielectric-constant dielectric, further compressing the capacitance between the gate and the cage, reducing the overall gate charge, and consequently decreasing the transient current required by the driver, thus significantly reducing switching losses. Since the cage itself bears the main path of the source current, its cross-sectional area can be flexibly designed according to current carrying requirements, avoiding the increase of additional series resistance, and the on-state voltage drop remains unaffected. The U-shaped structure of the shielding cage completely encompasses the region with the highest electric field, while the opening faces the drain region, avoiding the increase in gate-source capacitance caused by additional overlap of the source region, maintaining gate-source charge balance, and further suppressing the risk of dv / dt-induced false conduction. The cage and source metal layer are integrally formed using the same deposition process, eliminating the welding interface between multiple metal layers, reducing contact resistance and parasitic inductance, and simultaneously reducing power circuit oscillation and EMI levels. The presence of the additional spacer cavity further increases the electrical distance between the shielding cage and the drift region. The cavity can also serve as a heat dissipation channel, rapidly introducing longitudinal heat flow into the substrate, reducing junction temperature, and extending device lifespan. From a system perspective, the reduction in gate charge and drive losses means that the drive circuit can use a smaller, lower-cost gate drive chip, while maintaining controllable temperature rise under high-frequency conditions. The shortened turn-off delay allows for a more compact dead-time setting, improving the inverter's output voltage utilization. Overall, this invention achieves simultaneous optimization of parasitic capacitance, electric field concentration, thermal resistance, and reliability in multiple dimensions without increasing chip area or introducing additional process layers, providing a practical technical path for SiC-MOSFET applications at higher frequencies and higher power densities. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 An example diagram of a SiC-MOSFET device for reducing parasitic capacitance; The attached diagram lists the components represented by each number as follows: 10. Silicon carbide semiconductor body; 20. Gate structure; 30. Source region; 40. Drain region; 50. Source metal layer; 60. Shielding cage; 61. Insulating spacer layer. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings.

[0030] like Figure 1 The diagram shown is an example of a SiC-MOSFET device for reducing parasitic capacitance provided by this invention, comprising: Silicon carbide semiconductor body 10; A gate structure 20 is formed on the upper surface of the semiconductor body; The source region 30 and drain region 40 are located on both sides of the gate structure 20 laterally; A source metal layer 50 covers the source region 30 and extends into the chip; And a shielding cage 60 formed by bending the source metal layer 50 downwards and laterally surrounding the gate structure 20; The shielding cage 60 and the source metal layer 50 are the same conductor and maintain the same potential. The shielding cage 60 surrounds the gate structure 20 on at least three sides, and an insulating spacer layer 61 is formed between the shielding cage 60 and the gate structure 20.

[0031] The shielding cage is formed by bending the vertical edge of the source metal layer laterally, creating a "U-shaped metal groove" with a cross-section resembling the letter "U" opening to the right. The three sides of the U-shaped groove are: the left vertical arm is integrated with the vertical part of the source metal layer; the bottom edge lies horizontally directly below the gate structure; and the right vertical arm folds back upwards, parallel to the right side wall of the gate. The U-shaped groove surrounds the gate structure on three sides (left, bottom, and right), but the top of the right vertical arm does not contact the drain region, leaving a gap.

[0032] In the above technical solution, the insulating spacer layer 61 is a closed air gap surrounding the gate structure 20. The air gap extends continuously from the upper surface of the gate structure 20 to the sidewall and bends downward to the bottom surface.

[0033] Furthermore, in the above technical solution, the shielding cage 60 has a U-shaped cross section, with the U-shaped opening facing the drain region 40, the bottom of the U-shape located below the gate structure 20, and the U-shaped side arms extending upward and clamping both sides of the gate structure 20.

[0034] Furthermore, in the above technical solution, the upper edge of the side arm of the shielding cage 60 is flush with the upper surface of the source metal layer 50, so that the shielding cage 60 and the source metal layer 50 form a continuous conductive shielding shell.

[0035] Furthermore, in the above technical solution, the insulating spacer layer 61 is a low dielectric constant insulating layer, which extends continuously along the outer contour of the gate structure 20 and is sandwiched between the gate structure 20 and the shielding cage 60.

[0036] Furthermore, in the above technical solution, an additional spacer cavity is left between the bottom wall of the shielding cage 60 and the semiconductor body, and the additional spacer cavity may or may not be connected to the insulating spacer layer 61.

[0037] Furthermore, in the above technical solution, the inner surface of the side arm of the shielding cage 60 is parallel to and equidistant from the side wall of the gate structure 20, so that the gate structure 20 is symmetrically shielded in the horizontal direction.

[0038] Furthermore, in the above technical solution, the source metal layer 50 and the shielding cage 60 are integrally formed by the same metal deposition process, and there is no welding or conductive interface between them.

[0039] Furthermore, in the above technical solution, the U-shaped bottom of the shielding cage 60 is located directly below the gate structure 20, and an additional field oxide layer is provided between the U-shaped bottom and the semiconductor body.

[0040] Furthermore, in the above technical solution, the insulating spacer layer 61 extends continuously in the vertical direction, so that the upper surface, sidewalls and bottom surface of the gate structure 20 are all covered by the insulating spacer layer 61 and are completely isolated from the shielding cage 60.

[0041] First embodiment: In this embodiment, after the silicon carbide epitaxial wafer undergoes standard trench gate fabrication to prepare the body region, source region, and gate oxide, a low-temperature silicon oxide layer is deposited as a sacrificial layer. A U-shaped window is defined above the gate and on the sidewalls using dual damascene lithography. Subsequently, a Ti / AlCu stacked metal is sputtered, with the metal bending downwards and extending laterally along the window to form a U-shaped shielding cage integrated with the source metal layer. The sacrificial layer is then removed using a subsequent HF wet process, leaving a completely sealed air gap between the cage and the gate. The air gap thickness is determined by the sacrificial layer thickness and controlled between 0.2–0.4 μm to ensure both mechanical strength and maintain a low dielectric constant.

[0042] This structure is particularly suitable for 650V–1.2kV automotive main inverter modules. The automotive environment demands extremely high dv / dt immunity, and space is limited, making it impossible to suppress the Miller effect through external gate resistors or buffer circuits. The air-gap shielding cage cuts off the high-voltage drain power line outside the gate, virtually eliminating the Miller plateau, shortening turn-off delay, reducing drive losses, and allowing the system to operate at higher PWM frequencies. This reduces filter size and increases power density. Simultaneously, the air gap acts as a thermal expansion buffer, alleviating shear stress at the metal-silicon carbide interface caused by temperature cycling, significantly improving lifespan in the AEC-Q101 power cycle test.

[0043] Second embodiment: In this embodiment, after gate etching, a porous SiOCH low-dielectric-constant dielectric layer (k≈2.2) with a thickness of 0.3 μm is deposited using spin coating, covering the upper surface, sidewalls, and downward-extending bottom surface of the gate. Subsequently, the dielectric surface is planarized using CMP, and then source metal (AlCu 4 wt%) is sputtered. The metal bends downward on both sides of the gate, tightly adhering to the low-k layer to form a U-shaped shielding cage. Since the low-k layer is a solid thin film, no sacrificial layer removal step is required, resulting in a wide process window and low wafer warpage risk.

[0044] This embodiment is applicable to industrial power supplies above 3.3kV or high-speed rail traction converters. These applications have higher requirements for long-term reliability, moisture protection, and mechanical strength. Solid-state low-k films provide stable dielectric isolation, avoiding potential vacuum leakage or packaging stress concentration issues that may occur in air gaps. The low-k dielectric maintains extremely low leakage current even at 150°C. With significantly reduced gate-leakage capacitance, the device can operate at higher bus voltages without additional absorption circuitry, improving overall efficiency and further reducing system size. Simultaneously, the low-k film exhibits strong adhesion to metals, eliminates cavities between the shielding cage and the gate, and provides excellent resistance to mechanical vibration, meeting the stringent IEC 61373 vibration and shock standards for rail transportation.

[0045] Specifically, the principle of this utility model is as follows: The technical principle of this invention is based on the Faraday shielding effect in electromagnetic fields. When a conductor shell completely or partially surrounds a certain area and is connected to a specific potential, the influence of the external electric field on the internal area is significantly weakened. In this structure, the source metal layer extends into the chip and is bent into a U-shaped shielding cage. This cage is at the same potential as the source, forming a continuous equipotential surface. The electric field lines generated by the high voltage at the drain are forcibly terminated upon reaching the surface of the shielding cage and cannot continue to penetrate to the gate, thereby cutting off the capacitive coupling path between the gate and drain. The insulating spacer layer serves to ensure that the gate signal is not directly affected by the shield cage potential. If a closed air gap is used, its dielectric constant is close to that of a vacuum, and the capacitance is proportional to the dielectric constant, thus maximizing the reduction of gate-cage capacitance. If a low-dielectric-constant dielectric is used, capacitance reduction comparable to that of an air gap can be achieved with a thinner layer, while also providing higher mechanical strength. The insulating spacer layer extends continuously along the top surface, sidewalls, and bottom surface of the gate, forming 360° electrical isolation to prevent leakage coupling in any direction. The U-shaped cross-section design of the shielding cage completely covers the area where the electric field is most concentrated, and the opening faces the drain region, avoiding the generation of new overlapping capacitance in the source region, thereby maintaining the gate-source charge balance. The cage itself is part of the source current path, and its cross-sectional area can be flexibly designed according to the current level, avoiding the addition of extra series resistance. The additional spacer cavity further increases the electrical distance between the shielding cage and the drift region. The cavity can also serve as a heat dissipation channel, quickly introducing longitudinal heat flow into the substrate and reducing the junction temperature.

Claims

1. A SIC-MOSFET device with reduced parasitic capacitance, characterized by, include: Silicon carbide semiconductor body; A gate structure formed on the upper surface of the semiconductor body; The source and drain regions are located on both sides of the gate structure laterally; A source metal layer covers the source region and extends into the chip; And a shielding cage formed by bending the source metal layer downwards and laterally surrounding the gate structure; The shielding cage and the source metal layer are the same conductor and maintain the same potential. The shielding cage surrounds the gate structure on at least three sides and forms an insulating spacer layer between the shielding cage and the gate structure.

2. A SIC-MOSFET device with reduced parasitic capacitance according to claim 1, characterized in that The insulating spacer layer is a closed air gap surrounding the gate structure, which extends continuously from the upper surface of the gate structure to the sidewall and bends downward to the bottom surface.

3. A SIC-MOSFET device with reduced parasitic capacitance according to claim 2, characterized in that The shielding cage has a U-shaped cross-section, with the U-shaped opening facing the drain region, the bottom of the U-shape located below the gate structure, and the U-shaped side arms extending upward and enclosing both sides of the gate structure.

4. A SIC-MOSFET device with reduced parasitic capacitance according to claim 3, wherein, The upper edge of the side arm of the shielding cage is flush with the upper surface of the source metal layer, so that the shielding cage and the source metal layer form a continuous conductive shielding shell.

5. A SIC-MOSFET device with reduced parasitic capacitance according to claim 4, characterized in that The insulating spacer layer is a low dielectric constant insulating layer, which extends continuously along the outer contour of the gate structure and is sandwiched between the gate structure and the shielding cage.

6. A SIC-MOSFET device with reduced parasitic capacitance according to claim 5, wherein, An additional spacer cavity is provided between the bottom wall of the shielding cage and the semiconductor body. The additional spacer cavity may or may not be connected to the insulating spacer layer.

7. A SIC-MOSFET device with reduced parasitic capacitance according to claim 6, characterized in that The inner surface of the side arm of the shielding cage is parallel to and equidistant from the side wall of the gate structure, so that the gate structure is symmetrically shielded in the horizontal direction.

8. A SIC-MOSFET device with reduced parasitic capacitance according to claim 7, wherein, The source metal layer and the shielding cage are integrally formed by the same metal deposition process, and there is no welding or conductive interface between them.

9. A SIC-MOSFET device with reduced parasitic capacitance according to claim 8, wherein, The U-shaped bottom of the shielding cage is located directly below the gate structure, and an additional field oxide layer is provided between the U-shaped bottom and the semiconductor body.

10. The SIC-MOSFET device of claim 9, wherein, The insulating spacer extends continuously in the vertical direction, so that the upper surface, sidewalls and bottom surface of the gate structure are all covered by the insulating spacer and are completely isolated from the shielding cage.

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