A metal oxide semiconductor field effect transistor
By adjusting the structure of the shielding oxide layer and the isolation oxide layer of the metal-oxide-semiconductor field-effect transistor and optimizing the morphology of the gate and isolation oxide layers, the problems of excessive gate-source capacitance and gate resistance are solved, resulting in faster switching speed and lower switching losses, making it suitable for high-frequency applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 捷捷微电(南通)科技有限公司
- Filing Date
- 2025-09-09
- Publication Date
- 2026-07-31
AI Technical Summary
In existing metal-oxide-semiconductor field-effect transistors (MOSFETs), the gate-source capacitance and gate resistance are relatively large, which leads to a decrease in switching speed and an increase in switching losses, making them unsuitable for high-frequency applications.
By setting a shielding oxide layer, an isolation oxide layer, and a gate in the epitaxial layer, and adjusting the thickness of the isolation oxide layer to form a flat structure in the first and second directions, the thickness of the isolation oxide layer is increased, the morphology of the gate and the isolation oxide layer is optimized, and the gate-source capacitance and gate resistance are reduced.
Smaller gate-source capacitance and gate resistance are achieved, improving the switching characteristics of the device, increasing the switching speed, and making it suitable for high-frequency applications.
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Figure CN224583592U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a metal-oxide-semiconductor field-effect transistor. Background Technology
[0002] Semiconductor power devices, specifically switching transistors, are the core of modern power converters. Commonly used power devices are fabricated from metal, oxide, and semiconductor materials. Conventional shielded-gate trench power metal-oxide-semiconductor field-effect transistors (MOSFETs) typically control the device's switching by controlling the external bias applied to the polysilicon gate. When a forward bias is applied to the gate, the gate electric field forms an inversion layer conductive channel on the oxide and semiconductor surfaces, turning the device on. Conversely, when the gate is connected to zero or a negative potential, the device is off. Current MOSFETs have large gate-source capacitances and gate resistances. Increased gate-source capacitance and gate resistance reduce the device's switching speed and increase switching losses, hindering its application in high-frequency fields. Utility Model Content
[0003] The purpose of this application is to provide a metal-oxide-semiconductor field-effect transistor with smaller gate-source capacitance and gate resistance to improve device performance.
[0004] In one aspect of this application, a metal-oxide-semiconductor field-effect transistor is provided, including an epitaxial layer. A shielding oxide layer, an isolation oxide layer, and a gate are sequentially disposed in the epitaxial layer along a first direction. A field plate is also disposed in the shielding oxide layer. The thickness of the isolation oxide layer along a second direction is greater than the thickness of the shielding oxide layer. In the plane formed by the first direction and the second direction, both the isolation oxide layer and the gate are formed with a flat structure. The first direction is perpendicular to the second direction.
[0005] Optionally, the gate is formed in a square cross-section in the plane formed by the first direction and the second direction.
[0006] Optionally, along the first direction, the field plate extends beyond the shielding oxide layer and into the isolation oxide layer.
[0007] Optionally, a gate oxide layer is further disposed between the gate and the epitaxial layer.
[0008] Optionally, along the second direction, the thickness of the isolation oxide layer is equal to the thickness of the gate electrode plus 2 * the thickness of the gate oxide layer.
[0009] Optionally, the thickness of the gate oxide layer along the second direction is greater than or equal to 50 Å.
[0010] Optionally, a trench is formed within the epitaxial layer, and the shielding oxide layer, the isolation oxide layer, and the gate are all located within the trench.
[0011] Optionally, the epitaxial layer includes an epitaxial region, a body region, and a source contact region sequentially disposed along the first direction, the shielding oxide layer and the isolation oxide layer are located in the epitaxial region, and the gate spans the epitaxial region, the body region, and the source contact region.
[0012] Optionally, along the first direction, the epitaxial layer is further provided with an interlayer dielectric layer and a source metal layer.
[0013] Optionally, the interlayer dielectric layer is further provided with a source contact hole facing the epitaxial layer, the source contact hole extending from the interlayer dielectric layer to the body region, and the source contact hole communicating with the source metal layer.
[0014] The metal-oxide-semiconductor field-effect transistor provided in this application has a shielding oxide layer, an isolation oxide layer, and a gate sequentially arranged from bottom to top along a first direction in the epitaxial layer. A field plate is also disposed in the shielding oxide layer along the first direction. In the second direction, the thickness of the isolation oxide layer is greater than that of the shielding oxide layer. In the plane formed by the first and second directions, both the isolation oxide layer and the gate have a flat surface structure, with a thicker gate and isolation oxide layer, forming a good isolation oxide layer thickness and gate morphology. This makes the metal-oxide-semiconductor field-effect transistor of this application have smaller gate-source capacitance and gate resistance, thereby improving the switching characteristics of the device. Attached Figure Description
[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a schematic diagram of an existing metal-oxide-semiconductor field-effect transistor structure;
[0017] Figure 2 This is a schematic diagram of the metal-oxide-semiconductor field-effect transistor structure provided in the embodiments of this application;
[0018] Figure 3 This is one of the process diagrams for fabricating a metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application;
[0019] Figure 4 This is the second diagram illustrating the fabrication process of the metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application;
[0020] Figure 5 This is the third diagram illustrating the fabrication process of the metal-oxide-semiconductor field-effect transistor provided in this application embodiment;
[0021] Figure 6 This is the fourth diagram illustrating the fabrication process of the metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application;
[0022] Figure 7 This is the fifth diagram illustrating the fabrication process of the metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application.
[0023] Icons: 11-Shielding oxide layer; 12-Field plate; 13-Isolation oxide layer; 14.1-Gate oxide layer; 14.2-Gate polysilicon; 100-Epiaxial region; 110-Shielding oxide layer; 112-Thin film layer; 120-Field plate; 130-Isolation oxide layer; 141-Gate oxide layer; 142-Gate; 150-Bulk region; 151-Source contact region; 201-Interlayer dielectric layer; 202-Source contact hole; 210-Source metal; F1-First direction; F2-Second direction; d1-Thickness. Detailed Implementation
[0024] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.
[0025] In the description of this application, it should be noted that the terms "inner" and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0026] It should also be noted that, unless otherwise explicitly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0027] Conventional shielded gate trench power metal-oxide-semiconductor transistor (MOSFET) structure, such as Figure 1As shown, the shielded gate MOSFET increases avalanche breakdown voltage by introducing a vertical polysilicon field plate in the bulk, transforming the triangular electric field distribution during directional breakdown into a rectangular electric field distribution. This utilizes the two-dimensional charge depletion effect, thus ensuring the device withstand voltage meets requirements while increasing the doping concentration in the drift region to reduce on-resistance. Simultaneously, because the shielded gate is located between the control gate and the drain, it shields part of the feedback capacitance, resulting in less switching failure in the shielded gate MOSFET. A common method for forming a metal-oxide-semiconductor (MOS) is to etch the shielding oxide layer 11 to a specified location and make the polysilicon field plate height higher than the shielding oxide layer 11. Oxygen is then introduced under high temperature conditions, where oxygen reacts with the protruding polysilicon field plate 12 to form an isolation oxide layer (IPO) 13. Simultaneously, oxygen reacts with the silicon epitaxial layer on the sidewall to form the gate oxide layer 14.1, and polysilicon is deposited as the gate polysilicon 14.2 for controlling the device's switching.
[0028] In the above MOSFET process, an IPO isolation oxide layer 13 is formed through oxidation. Since the thickness of the IPO after polysilicon oxidation is less than the thickness of the shielding oxide layer 11, the IPO isolation oxide layer 13 cannot fill the voids on the sidewalls. During subsequent deposition of the gate polysilicon 14.2, the gate polysilicon 14.2 will fill the voids, ultimately forming the MOSFET as described above. Figure 1 The structure;
[0029] This structure results in the thinnest part of the isolation oxide layer 13 between the gate polysilicon 14.2 and the polysilicon field plate 12 being too thin, much thinner than the shielding oxide layer 11, which will lead to an increase in gate-source capacitance. In addition, the internal part of the gate polysilicon 14.2 is occupied by the isolation oxide layer 13 between the gate polysilicon 14.2 and the polysilicon field plate 12, which leads to an increase in gate resistance. The increase in gate-source capacitance and gate resistance will reduce the device switching speed and increase switching losses, which is not conducive to the application of the device in high-frequency fields.
[0030] Please refer to Figure 2 As shown, this application provides a metal-oxide-semiconductor field-effect transistor, including: an epitaxial layer, in which a shielding oxide layer 110, an isolation oxide layer 130 and a gate 142 are sequentially disposed along a first direction F1, and a field plate 120 is also disposed in the shielding oxide layer 110. The thickness d1 of the isolation oxide layer 130 along the second direction F2 is greater than the thickness of the shielding oxide layer 110. In the plane formed by the first direction F1 and the second direction F2, both the isolation oxide layer 130 and the gate 142 form a flat structure. The first direction F1 is perpendicular to the second direction F2.
[0031] from Figure 2As can be seen, the first direction F1 is the vertical direction, and the epitaxial layer contains a shielding oxide layer 110, an isolation oxide layer 130, and a gate 142 from bottom to top. A field plate 120 is also disposed in the shielding oxide layer 110 along the first direction F1. In the second direction F2, i.e. the horizontal direction, since the field plate 120 is disposed in the shielding oxide layer 110, the thickness d1 of the isolation oxide layer 130 is greater than the thickness of the shielding oxide layer 110 (the thickness of the shielding oxide layer 110 = the thickness d1 of the isolation oxide layer 130 - the thickness of the field plate 120). In the plane formed by the first direction F1 and the second direction F2, the isolation oxide layer 130 and the gate 142 both form a flat structure with a thicker gate 142 and isolation oxide layer 130, forming a good isolation oxide layer 130 thickness d1 and gate 142 morphology. This makes the metal oxide semiconductor field-effect transistor of this application have a smaller gate-source capacitance and gate 142 resistance, thereby improving the switching characteristics of the device.
[0032] Among them, the field plate 120 is a polycrystalline silicon field plate 120, and the gate 142 is a gate 142 polycrystalline silicon.
[0033] Specifically, the side of the isolation oxide layer 130 facing the gate 142 is a plane, and the side of the gate 142 facing the isolation oxide layer 130 is also a plane. The gate 142 forms a square cross section in the plane formed by the first direction F1 and the second direction F2. Both the isolation oxide layer 130 and the gate 142 form a flat structure.
[0034] This way, it can be avoided Figure 1 The problem of the gate polysilicon 14.2 being partially occupied by the isolation oxide layer 13 between the gate polysilicon 14.2 and the polysilicon field plate 12 also increases the thickness d1 of the isolation oxide layer 130.
[0035] Along the first direction F1, the field plate 120 extends out of the shielding oxide layer 110 and into the isolation oxide layer 130.
[0036] The field plate 120 spans the shielding oxide layer 110 and the isolation oxide layer 130 along the first direction F1, that is, one end of the field plate 120 is located inside the shielding oxide layer 110 and the other end is located inside the isolation oxide layer 130.
[0037] In addition, a gate oxide layer 141 is disposed between the gate 142 and the epitaxial layer. A trench is disposed in the epitaxial layer, and the shielding oxide layer 110, the isolation oxide layer 130 and the gate 142 are all located in the trench. A thin film layer 112 is first disposed in the trench at the position corresponding to the gate 142, and then the gate 142 is formed in the thin film layer 112.
[0038] For example, the gate oxide layer 141 is formed by a thin film layer 112, which may be a thin silicon nitride layer, and the thickness of the gate oxide layer 141 along the second direction F2 is greater than or equal to 50 Å.
[0039] from Figure 2 It can be seen that along the second direction F2, the thickness of the isolation oxide layer 130 is equal to the thickness of the gate 142 plus 2 * the thickness of the gate oxide layer 141.
[0040] The gate 142 is located within the gate oxide layer 141, that is, the gate oxide layer 141 is located on both sides of the gate 142 along the second direction F2. The thickness of one side of the gate oxide layer 141 * 2 + the thickness of the gate 142 = the thickness of the isolation oxide layer 130.
[0041] In this application, the epitaxial layer can be divided into an epitaxial region 100, a body region 150 and a source contact region 151 arranged sequentially along the first direction F1. The shielding oxide layer 110 and the isolation oxide layer 130 are located in the epitaxial region 100, and the gate 142 spans the epitaxial region 100, the body region 150 and the source contact region 151.
[0042] The epitaxial region 100, body region 150 and source contact region 151 are arranged sequentially from bottom to top. The shielding oxide layer 110, isolation oxide layer 130 and field plate 120 are all located within the epitaxial region 100. The gate 142 spans the epitaxial region 100, body region 150 and source contact region 151. The top surface of the gate 142 along the first direction F1 is flush with the top surface of the source contact region 151 of the epitaxial layer.
[0043] Along the first direction F1, an interlayer dielectric layer 201 and a source metal layer 210 are also disposed on the epitaxial layer.
[0044] An interlayer dielectric layer 201 is disposed on the source contact region 151, and a source metal layer 210 is disposed on the interlayer dielectric layer 201. The interlayer dielectric layer 201 is also provided with a source contact hole 202 facing the epitaxial layer. The source contact hole 202 extends from the interlayer dielectric layer 201 to the body region 150 and communicates with the source metal layer 210.
[0045] Based on this, this application also discloses a method for fabricating a metal-oxide-semiconductor field-effect transistor, used to fabricate any of the metal-oxide-semiconductor field-effect transistors described above.
[0046] Specifically, the preparation method includes:
[0047] Step 200: After the deep trench etching of the epitaxial layer is completed, a shielding oxide layer is grown, such as... Figure 3 As shown;
[0048] Step 201: Deposit the polysilicon field plate 120 and etch it to the specified height, then etch the shielding oxide layer 110 so that the polysilicon field plate 120 extends beyond the shielding oxide layer 110, as shown below. Figure 4 As shown;
[0049] Step 202: Deposit a thin silicon nitride layer as thin film layer 112, which is used to form gate oxide layer 141, such as Figure 5 As shown;
[0050] Step 203: A window is etched into the thin film layer 112 within the trench using a photolithography plate, and the exposed polycrystalline silicon field plate 120 is oxidized at high temperature to form a dense isolation oxide layer 130, such as... Figure 6 As shown;
[0051] Step 204: Deposit a second isolation oxide layer 130 to make the surface of the isolation oxide layer 130 smooth, such as... Figure 7 As shown;
[0052] Step 205: Compatible with conventional shielded gate trench MOSFET technology, forming a shielded gate trench MOSFET structure, such as... Figure 2 As shown.
[0053] This application optimizes the thickness of the isolation oxide layer 130 and the polysilicon morphology of the gate 142 by adjusting the processes of the shielding oxide layer 110 and the isolation oxide layer 130, thereby improving the switching characteristics of the device. The process is relatively simple and effectively reduces the manufacturing cost.
[0054] The fabrication method of this metal-oxide-semiconductor field-effect transistor includes the same structure and beneficial effects as the metal-oxide-semiconductor field-effect transistor in the foregoing embodiments. The structure and beneficial effects of the metal-oxide-semiconductor field-effect transistor have been described in detail in the foregoing embodiments and will not be repeated here.
[0055] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A metal oxide semiconductor field effect transistor, characterized by, include: An epitaxial layer is provided, wherein a shielding oxide layer, an isolation oxide layer and a gate are sequentially disposed along a first direction. A field plate is also disposed within the shielding oxide layer. The thickness of the isolation oxide layer along a second direction is greater than the thickness of the shielding oxide layer. In the plane formed by the first direction and the second direction, both the isolation oxide layer and the gate are formed with a flat structure. The first direction is perpendicular to the second direction.
2. The metal oxide semiconductor field effect transistor of claim 1, wherein, The gate has a square cross-section in the plane formed by the first direction and the second direction.
3. The MOSFET of claim 1, wherein, Along the first direction, the field plate extends out of the shielding oxide layer and into the isolation oxide layer.
4. The MOSFET of claim 1, wherein: A gate oxide layer is also disposed between the gate and the epitaxial layer.
5. The MOSFET of claim 4, wherein the metal oxide is selected from the group consisting of titanium oxide, zirconium oxide, hafnium oxide, and lanthanum oxide. Along the second direction, the thickness of the isolation oxide layer = the thickness of the gate + 2 * the thickness of the gate oxide layer.
6. The MOSFET of claim 4, wherein: The thickness of the gate oxide layer along the second direction is greater than or equal to 50 Å.
7. The metal-oxide-semiconductor field-effect transistor according to any one of claims 1 to 6, characterized in that, A trench is formed within the epitaxial layer, and the shielding oxide layer, the isolation oxide layer, and the gate are all located within the trench.
8. The metal-oxide-semiconductor field-effect transistor according to any one of claims 1 to 6, characterized in that, The epitaxial layer includes an epitaxial region, a body region, and a source contact region sequentially disposed along the first direction. The shielding oxide layer and the isolation oxide layer are located in the epitaxial region, and the gate spans the epitaxial region, the body region, and the source contact region.
9. The metal-oxide-semiconductor field-effect transistor according to any one of claims 1 to 6, wherein Along the first direction, an interlayer dielectric layer and a source metal layer are also disposed on the epitaxial layer.
10. The MOSFET of claim 9, wherein, The interlayer dielectric layer is further provided with a source contact hole facing the epitaxial layer. The source contact hole extends from the interlayer dielectric layer to the body region and is connected to the source metal layer.