Semiconductor device and integrated circuit

Abstract

Various embodiments of this utility model relate to a semiconductor device. The semiconductor device includes a circuit having a first pin; a first conductor extending along a first direction, the first circuit being located between a second conductor and a first side of the first conductor; a circuit having a second pin; and a connection coupling a signal between the first pin and the second pin, the connection including: a first conductive component extending along a second direction, the first conductive component being connected to the first pin on the first side of the first conductor; a first via structure connecting the first conductive component to the back side of a substrate, including a first feedthrough via (FTV) on a second side of the first conductor; a second via structure providing a signal to the front side of the substrate, the second via structure including a second FTV; and a second conductive component connecting the second via structure and the second pin.

Description

Technical Field

[0001] This utility model relates to a semiconductor device and an integrated circuit. Background Technology

[0002] Integrated circuit (IC) devices or semiconductor devices include one or more devices represented by an IC layout (also called a "layout"). A layout is hierarchical and includes modules that perform higher-level functions according to IC design specifications. These modules are typically constructed from combinations of cells, each cell representing one or more semiconductor structures configured to perform a specific function. Cells with pre-designed layouts (sometimes called standard cells) are stored in a standard cell library (hereinafter referred to as a "library" or "cell library" for simplicity) and can be accessed through various tools (e.g., electronic design automation (EDA) tools) to generate, optimize, and verify IC designs.

[0003] Reducing signal delay (e.g., resistor-capacitor (RC) delay) in integrated circuit (IC) devices or semiconductor devices is a design consideration. Methods for reducing signal delay involve reducing the distance and / or RC characteristics of wiring connections (e.g., wiring connections on the front and back sides of a substrate). Utility Model Content

[0004] This invention provides a semiconductor device. The semiconductor device includes a first functional circuit having a first pin in a first region of a substrate. The semiconductor device also includes a first power conductor extending in a first metallization layer on the front side of the substrate along a first direction. The semiconductor device further includes a second power conductor located in the first metallization layer, with the first functional circuit located between the second power conductor and a first side of the first power conductor. The semiconductor device also includes a second functional circuit having a second pin in a second region of the substrate. The semiconductor device further includes a signal connection configured to couple a signal between the first pin and the second pin. The signal connection includes: a first conductive component extending in a second metallization layer along a second direction, the first conductive component being connected to the first pin on a first side of the first power conductor; a first via structure connecting the first conductive component to a back side of the substrate, the first via structure including a first feedthrough via (FTV) on a second side of the first power conductor; a second via structure configured to provide a signal to the front side of the substrate, the second via structure including a second FTV; and a second conductive component in the second metallization layer, the second conductive component being connected to the second via structure and the second pin.

[0005] Another aspect of this utility model provides a method for manufacturing a semiconductor device. The method includes forming a first functional circuit having a first pin in a first region of a substrate. The method also includes forming a second functional circuit having a second pin in a second region of the substrate. The method further includes forming a first power conductor extending in a first direction in a first metallization layer on the front side of the substrate, such that a first side of the first power conductor faces the first functional circuit. The method further includes forming a second power conductor in the first metallization layer, with the first functional circuit located between the second power conductor and the first side of the first power conductor. The method also includes forming a signal connection configured to couple a signal between the first pin and the second pin. Forming the signal connection includes: forming a first via structure configured to provide a signal to the back side of the substrate, forming the first via structure including forming a first feedthrough via (FTV) on a second side of the first power conductor; forming a second via structure configured to provide a signal to the front side of the substrate, forming the second via structure including forming a second FTV; forming a first conductive component extending in a second direction in a second metallization layer, the first conductive component being configured to connect the first via structure to the first pin; and forming a second conductive component in the second metallization layer, the second conductive component being configured to connect the second via structure to the second pin.

[0006] Another embodiment of this utility model provides an integrated circuit. The integrated circuit includes a first circuit and a second circuit on a first surface of a substrate, connected together by a conductive path. The conductive path includes a conductor on a second surface of the substrate, opposite to the first surface. The conductive path includes a first conductive component coupling the input or output of the first circuit to a first via structure. The input or output of the first circuit is located on the side of a first power conductor opposite to the first via structure. The first power conductor extends in a first metallization layer on the first surface of the substrate along a first direction, and the first conductive component extends in a second metallization layer above the first metallization layer along a second direction. The conductive path also includes a second conductive component in the second metallization layer, connected to a second via structure and the input or output of the second circuit. The first via structure connects the first conductive component to the conductor on the second surface of the substrate, and the first via structure includes a first feedthrough via (FTV) on one side of the first power conductor. The second via structure connects the conductor on the second surface of the substrate to the second conductive component, and the second via structure includes a second FTV.

[0007] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a block diagram of an IC device according to some embodiments.

[0009] Figures 2A to 2B It is a layout diagram of an IC device according to some embodiments, and Figure 2C It corresponds to Figures 2A to 2B A schematic cross-sectional view of the device.

[0010] Figure 2D This is a floor plan of an exemplary embodiment of the FTV unit, and Figure 2E It corresponds to Figure 2D A schematic cross-sectional view.

[0011] Figure 3 This is a flowchart of a method for designing an IC device according to some embodiments.

[0012] Figure 4 This is a schematic diagram of wiring using independent feedthrough vias according to some embodiments.

[0013] Figure 5 This is a schematic diagram of wiring using embedded feedthrough vias according to some embodiments.

[0014] Figure 6 This is a schematic diagram of wiring using a combination of embedded FTV and stand-alone FTV according to some embodiments.

[0015] Figure 7 This is a schematic diagram of wiring according to some embodiments.

[0016] Figure 8A , Figure 8B and Figure 8C This is a layout diagram of an IC device according to some embodiments.

[0017] Figure 9A and Figure 9B This is a schematic diagram of RC calculation for a signature method used in the design of a standalone FTV unit according to some embodiments.

[0018] Figure 10 This is a flowchart of a method for generating a layout and using the layout to manufacture an IC device according to some embodiments.

[0019] Figure 11 This is a flowchart of a method for generating a layout according to some embodiments.

[0020] Figure 12 This is a flowchart of a method for manufacturing one or more components of an IC device according to some embodiments.

[0021] Figure 13 This is a block diagram of an electronic design automation (EDA) system 1300 according to some embodiments.

[0022] Figure 14This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0023] This invention provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components, materials, values, steps, arrangements, or similar elements are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, or similar elements are expected. For example, the following description of a first component formed on or on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, thereby potentially preventing direct contact between the first and second components. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and does not inherently indicate a relationship between the various embodiments and / or configurations discussed.

[0024] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one component or feature and another shown in the figures. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Source / drain may refer to the source or drain individually or collectively, depending on the context.

[0025] Figure 1 This is a block diagram of an IC device 100 including a feedthrough via according to some embodiments.

[0026] A feed-through via (FTV) is an assembly that extends through a substrate and electrically connects a component in a layer on the front side of the substrate to a layer on the back side of the substrate, with the back side of the substrate opposite to the front side where the active region is formed.

[0027] exist Figure 1In this embodiment, IC device 100 includes a macro 102. In some embodiments, macro 102 includes one or more of a memory, electrical grid, one or more cells, inverters, latches, buffers, and / or any other type of circuit arrangement that can be digitally represented in a cell library. In some embodiments, macro 102 is understood in an architectural hierarchy similar to modular programming, where subroutines / programs are called by a main program (or by other subroutines) to perform a given computational function. In this context, IC device 100 uses macro 102 to perform one or more given functions. Therefore, in this context and in terms of architectural hierarchy, IC device 100 is similar to a main program and macro 102 is similar to a subroutine / program. In some embodiments, macro 102 is a soft macro. In some embodiments, macro 102 is a hard macro. In some embodiments, macro 102 is a soft macro digitally described in register-transfer level (RTL) program code. In some embodiments, macro 102 has not yet been synthesized, placed, and routed, allowing synthesis, placement, and routing of the soft macro for various process nodes. In some embodiments, macro 102 is a hard macro digitally described in a binary file format (e.g., Graphic Database System II (GDSII) stream format), wherein the binary file format represents one or more layouts of macro 102 in a hierarchical form, such as planar geometry, text labels, and other information. In some embodiments, macro 102 has been composed, placed, and routed such that the hard macro is dedicated to a specific processing node.

[0028] exist Figure 1 In the macro 102, region 104 includes independent FTV units that overlap with functional circuit units, wherein overlapping means having a row direction shared for at least a portion of the unit's width (in, for example...). Figure 2A (X-axis direction in the diagram) cell boundary. An independent FTV cell corresponds to an independent FTV in an IC device. A functional circuit cell corresponds to a functional circuit in an IC device. A functional circuit includes at least one active device, such as a transistor. In some embodiments, a functional circuit includes logic circuitry. In some embodiments, a functional circuit is or includes a buffer, inverter, etc. In some embodiments, an independent FTV cell is a separate cell in a library. In some embodiments, an independent FTV cell does not include an active device such as a transistor. In some embodiments, an independent FTV cell does not include functional circuitry components such as buffers, inverters, etc. In some embodiments, an independent FTV cell does not include logic circuitry.

[0029] In some embodiments, region 104 corresponds to a substrate on which circuitry is formed during front-end-of-line (FEOL) fabrication. In region 104, various metal layers are stacked above and / or below an insulating layer during back-end-of-line (BEOL) fabrication, above and / or below the substrate. BEOL provides power networks and / or wiring for the circuitry of IC device 100, including macro 102 and region 104.

[0030] In some embodiments, the functional circuitry includes one or more active devices, passive devices, logic circuitry, etc. Examples of active devices or active components include, but are not limited to, transistors, diodes, etc. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, resistors, etc. Examples of logic circuitry include circuits that perform AND, OR, NAND, NOR, XOR, INV, AND-OR-inverted (AOI), OR-AND-inverted (OAI), etc. Other functional circuitry includes multiplexers (MUX), flip-flops, buffers, latches, delay units, frequencies, memories, etc. Exemplary memory cells include static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM, magnetoresistive RAM (MRAM), read-only memory (ROM), etc.

[0031] In some embodiments, the IC device includes one or more feedthrough vias (FTVs) that form a signal or power connection between components in the MO layer on the front side of the substrate and components in the B_MO layer on the back side of the substrate. In some embodiments, the IC device includes one or more feedthrough vias (FTVs) that connect components in layers other than the MO layer on the front side of the substrate to components in the B_MO layer or layers other than the B_MO layer on the back side of the substrate.

[0032] In some embodiments, the FTV is formed by a vertical stack of one or more vias penetrating the substrate (where vertical means perpendicular to the main surface of the substrate). In some embodiments, the FTV includes a vertical stack of a first via formed on the front side of the substrate and a second via formed on the back side of the substrate, the second via being vertically aligned with and in contact with the first via. Details relating to methods of forming an FTV can be found, for example, in U.S. Early Publication No. 2024 / 0063093, published February 22, 2024, the entire contents of which are incorporated herein by reference.

[0033] In some embodiments, the M0 layer is a metal 0 layer, which is the bottom metal layer on the front side of the interconnect structure on the front side of the substrate (i.e., the first metal layer above the substrate).

[0034] On the front side of the substrate, below the MO layer, an active layer (e.g., a semiconductor layer, an EPI layer, etc.) is formed to provide an active region for transistors, etc. In some embodiments, the active layer is an oxide-defined (OD) layer.

[0035] On the front side of the substrate, below the MO layer, a metal-to-oxide (MD) diffusion contact layer is formed to connect the source / drain (S / D) regions of the transistor to other circuit components or layers. In some embodiments, the MD layer includes components that directly contact the S / D regions of the transistor to couple electrical signals (e.g., voltage or current) to the source and drain of the transistor. In the MO layer, the metal components may be located in the first or X-axis direction (see example...). Figure 2A Extending on the top, the first or X-axis direction intersects (e.g., substantially orthogonal) the second or Y-axis extension direction of the gate component (polysilicon component) or the MD component in the MD layer.

[0036] On the front side of the substrate, also below the M0 layer, another contact layer is formed, namely a via-on-diffusion (VD) contact layer, to electrically couple the components in the MD layer to the components in the M0 layer.

[0037] On the front side of the substrate, below the MO layer, a gate layer or polysilicon layer is formed to provide the gate of the transistor. In some embodiments, the polysilicon layer includes a component that directly covers the active region and receives an electrical signal (gate signal). In some embodiments, the gate component and the MD component are formed side-by-side on the active region. In the polysilicon layer, the gate component may extend in a direction that intersects (e.g., is substantially orthogonal) the extending direction of the metal component in the MO layer.

[0038] On the front side of the substrate, also below the MO layer, another contact layer, namely a via-on-gate (VG) contact layer, is formed to electrically couple components in the gate layer to components in the MO layer. In some embodiments, the VG components and VD components are distributed at the same level above the substrate.

[0039] On the front side of the substrate, above the M0 layer, a via 0 (VIA0) layer is formed to electrically couple components in the M0 layer to components in the M1 layer. In some embodiments, additional metal layers and via layers, such as V1, M2, V2, M3, etc., are formed on the front side of the substrate.

[0040] In some embodiments, the B_M0 layer is a back metal layer 0, which is the bottommost back metal layer (i.e., the first metal layer under the substrate) of the interconnect structure on the back side of the substrate.

[0041] On the back side of the substrate, above the B_M0 layer, a back via 0 (B_VIA0) layer is formed to electrically couple components in the B_M0 layer to components in the B_M1 layer. In some embodiments, additional metal layers and via layers, such as B_VIA1, B_M2, B_VIA2, B_M3, etc., are formed on the back side of the substrate.

[0042] Figure 2A and Figure 2B This is a layout diagram of an IC device according to some embodiments. Figure 2C It corresponds to Figures 2A to 2B A schematic cross-section of the device.

[0043] exist Figure 2A In layout 200A, an FTV 201 overlaps with or is aligned (along a second or Y-axis direction) with the driver pin 202 of the first functional circuit 206 (in some embodiments, a first buffer). In layout 200A, the FTV 201 is aligned with the driver pin 202 along a second track 240. Figure 2B In layout 200B, an FTV 203 overlaps with or is aligned (along the second or Y-axis direction) with the receiver pin 204 of the second functional circuit 208, which in some embodiments is a second buffer. In layout 200B, the FTV 203 and the receiver pin 204 are aligned along a second track 240. Each buffer is a functional circuit, i.e., the buffer has one or more transistors. Layouts 200A and 200B represent IC devices corresponding to... Figure 1 The region is region 104.

[0044] exist Figure 2A In this context, the independent FTV unit 205 overlaps with the functional circuit unit 207, where overlap means having a shared row direction (X-axis direction) unit boundary (see [reference]) with respect to at least a portion of the width of units 205 and 207. Figure 2A The common boundary 212 in the IC device. The overall layout of the IC device extends beyond the first direction (X-axis) and the second direction (Y-axis). Figure 2A The range shown.

[0045] exist Figure 2A In this embodiment, the independent FTV unit 205 and the functional circuit unit 207 are located in adjacent rows, meaning that units 205 and 207 are directly on top of each other in the second direction (Y-axis). In one embodiment, the functional circuit unit 207 is located in the first row, and the independent FTV unit 205 is located in the second row adjacent to and above the first row. In another embodiment, the functional circuit unit 207 is located in the first row, and the independent FTV unit 205 is located in the second row adjacent to and below the first row.

[0046] The independent FTV unit 205 has boundaries 210, 212, 214, and 216, wherein boundaries 210 and 212 extend parallel to a first direction (X-axis), and boundaries 214 and 216 extend parallel to a second direction (Y-axis). The functional circuit unit 207 has boundaries 212, 218, 220, and 222, wherein boundary 212 is shared with the independent FTV unit 205, boundary 218 extends parallel to the first direction (X-axis), and boundaries 220 and 222 extend parallel to the second direction (Y-axis).

[0047] Figure 2A The diagram illustrates a separate FTV unit 205 and a functional circuit unit 207 with lateral boundaries aligned along the Y-axis direction, specifically, boundary 214 and boundary 220 are aligned along the Y-axis direction, and boundary 216 and boundary 222 are aligned along the Y-axis direction. In other embodiments, the separate FTV unit 205 and the functional circuit unit 207 have different dimensions in the first direction (X-axis) and / or are offset in the first direction (X-axis), such that one or both lateral boundaries are not aligned.

[0048] In some embodiments, such as in Figure 2A In the M0 layer, the conductive components extend parallel to a first direction (parallel to the X-axis) and are arranged in units 205 and 207 with reference to the first track 238 (X-axis track or horizontal track) in layout 200A. In some embodiments, the first track 238 is spaced at a regular pitch in layout 200A (and therefore in units 205 and 207) along the vertical direction (Y-axis).

[0049] exist Figure 2A In the middle, the shared boundary 212 of adjacent cells 205, 207 corresponds to a power supply or grounding component, such as the first PG rail 230. In some embodiments, such as Figure 2A In this configuration, boundary 212 is aligned with the center of the width of the power or ground component, the width being determined in a second direction (i.e., parallel to the Y-axis). Boundary 210 of the independent FTV unit 205 corresponds to the second PG rail 232, and boundary 218 of the functional circuit unit 207 corresponds to the third PG rail 234. In some embodiments, the PG rails are used to provide power or ground to transistors, circuits, etc., formed in the cells of layout 200A. In some embodiments, the PG rails extend beyond the width of a cell, for example, extending over the entire length of a row having several or more cells. In some embodiments, the PG rails are formed in the MO layer. Figure 2AThe diagram shows that the first PG rail 230 provides VSS and the second PG rail 232 and the third PG rail 234 provide VDD, but in other embodiments VSS and VDD are interchanged and / or other voltages are provided to the first to third PG rails 230-234. In some embodiments, the lateral boundaries 214, 216, 220, 222 of units 205, 207 are defined by one or more CPODE patterns.

[0050] In some embodiments, such as Figure 2A In this layout 200A, conductive components in the M1 layer extend parallel to a second direction (parallel to the Y-axis) and are arranged in cells 205 and 207 with reference to a second track 240 (Y-axis track). In some embodiments, the second track 240 is spaced at a regular pitch along a horizontal direction (X-axis) in layout 200A (and therefore in cells 205 and 207). In some embodiments, the second track 240 is spaced along the X-axis with a contact poly pitch (CPP). In some embodiments, CPP is the minimum distance between gate patterns of gate electrodes in a semiconductor device corresponding to a process technology node associated with layout 200A. In some embodiments, CPP corresponds to the center-to-center distance of two adjacent gate regions along the X-axis (two gate regions are considered adjacent where there are no other gate regions between them). In some embodiments, CPP is a basic unit of measurement with a specific value or range of values ​​corresponding to a semiconductor process technology node. The dimensions and / or layout of many other structures (e.g., wires) in the layout and / or IC device can be normalized relative to CPP.

[0051] Figure 2A The driver pin 202 (output pin) of the functional circuit unit 207 is shown to be connected to the conductive component 242 in the M1 layer, to the via in the VIA0 layer of the independent FTV unit 205, to the conductive component 217 in the M0 layer of the independent FTV unit 205, and then to the FTV 201. Figure 2A In this configuration, conductive component 242 overlaps perpendicularly with FTV 201, that is, they overlap along the Z-axis, such that an imaginary line extending parallel to the Z-axis intersects both FTV 201 and conductive component 242. Figure 2AIn this configuration, conductive component 242 and FTV 201 share a common Y-axis centerline. In some embodiments, the FTV in the independent FTV unit 205 is located within 1 CPP of the conductive component 242 in the M1 layer and is electrically connected to the conductive component 242. In some embodiments, the FTV in the independent FTV unit 205 is located at a distance of approximately 1 / 2 CPP or less from the centerline c / l of the independent FTV unit 205. By positioning the FTV near the centerline c / l of the independent FTV unit 205, the RC calculation results can be reduced for calculations based on distance from the unit centerline.

[0052] Figure 2A The arrangement of the independent FTV unit 205 in layout 200A reduces front-side wiring due to the ability to avoid M2 layer routing compared to a layout that includes embedded FTVs in the functional circuit unit. This is because the independent FTV unit 205 is arranged to overlap with the functional circuit unit 207 (i.e., sharing the shared row direction boundary), rather than using embedded FTVs in the left or right-hand portion of the functional circuit unit. Compared to an embedded FTV unit employing a connection structure in which the connections are sequentially output pins (M1), VIA1, M2, VIA1, VIA0, and FTV (M0), the reduction in front-side wiring by using M1 instead of M2 can reduce front-side wiring resistance by approximately 50%.

[0053] exist Figure 2B In this configuration, the independent FTV unit 209 and the functional circuit unit 211 are row-adjacent, meaning that units 209 and 211 are directly on top of each other in the second direction (Y-axis). The independent FTV unit 209 has boundaries 250, 252, 254, and 256, wherein boundaries 250 and 252 extend parallel to the first direction (X-axis), and boundaries 254 and 256 extend parallel to the second direction (Y-axis). The functional circuit unit 211 has boundaries 253, 258, 260, and 262, wherein boundary 253 is aligned with boundary 252 of the independent FTV unit 209, boundary 258 extends parallel to the first direction (X-axis), and boundaries 260 and 262 extend parallel to the second direction (Y-axis).

[0054] Figure 2B The diagram shows a separate FTV unit 209 and a functional circuit unit 211 with offset lateral boundaries, namely, boundary 254 is offset from boundary 260 in the X-axis direction, and boundary 256 is offset from boundary 262 in the X-axis direction. In other embodiments, the separate FTV unit 205 and the functional circuit unit 207 have the same dimensions in the first direction (X-axis) and / or are aligned in the first direction (X-axis) such that one or both lateral boundaries are aligned in the X-axis direction.

[0055] exist Figure 2BIn the M0 layer, the conductive components extend parallel to the first direction (parallel to the X-axis) and are arranged in cells 209 and 211 in layout 200A with reference to the first track 238 (X-axis track or horizontal track).

[0056] exist Figure 2B In the middle, the boundaries 252, 253 of adjacent cells 209, 211 correspond to power supply or grounding components, such as the fourth PG rail 270. In some embodiments, such as Figure 2B In this configuration, boundaries 252 and 253 are aligned with the center of the width of the power or ground component, the width being determined in a second dimension (i.e., parallel to the Y-axis). Boundary 250 of the independent FTV unit 209 corresponds to the fifth PG rail 272, and boundary 258 of the functional circuit unit 207 corresponds to the sixth PG rail 274. In some embodiments, the PG rails are used to provide power or ground to transistors, circuits, etc., formed in the cells of layout 200B. In some embodiments, the PG rails extend beyond the width of a cell, for example, extending along the entire length of a row having several or more cells. In some embodiments, the PG rails are formed in the MO layer. Figure 2B The fourth PG rail 270 is shown to provide VDD and the fifth PG rail 272 and the sixth PG rail 274 provide VSS, but in other embodiments VDD and VSS are interchanged and / or other voltages are provided to the fourth to sixth PG rails 270-274. In some embodiments, the lateral boundaries 254, 256, 260, 262 of units 209, 211 are defined by one or more CPODE patterns.

[0057] exist Figure 2B In the M1 layer, the conductive components extend parallel to the second direction (parallel to the Y-axis) and are arranged in cells 209 and 211 in layout 200B with reference to the second track 240 (Y-axis track).

[0058] Figure 2B The diagram shows the wiring from the conductive component 255 in the M0 layer of the independent FTV unit 209 through the via in the VIA0 layer, the conductive component 282 in the M1 layer, and the via in the VIA0 layer to the receiver pin 204, where the receiver pin 204 is the input pin of the functional circuit unit 211 in the M0 layer.

[0059] Figure 2BThe arrangement of the independent FTV unit 209 in layout 200B results in reduced front-side wiring due to the shorter conductive components in the M0 layer of the independent FTV unit 209 relative to the layout of the functional circuit unit including the embedded FTV. This is because the independent FTV unit 209 is arranged to overlap with the functional circuit unit 211 (i.e., sharing the X-axis boundary with the functional circuit unit 211), rather than using the embedded FTV in the left or right-hand portion of the functional circuit unit. Compared to an embedded FTV unit employing a connection structure in which the connections are sequentially FTV (M0), VIA0, M1, VIA0, M0, and input pin (M0), the reduced front-side wiring reduces the front-side wiring resistance by approximately 60%.

[0060] Figure 2C It corresponds to Figures 2A to 2B A schematic cross-sectional view of the device 200C.

[0061] exist Figure 2C In the first through-hole structure, FTV 201 and the first through-hole V0_01 in the through-hole 0 layer (VIA0) are included, and the second through-hole structure includes FTV 203 and the second through-hole V0_02 in the through-hole 0 layer (VIA0). Figure 2C In this embodiment, the first and second via structures also include vias in the back via layers B_VIA0 and B_VIA1, and conductors in the back metallization layers B_M0 and B_M1. The connection between the first and second via structures is made in the back metallization layer B_M2. In other embodiments, depending on the wiring resources on the back side of the substrate, one or more back vias and / or back conductors are omitted from the via structure, and the connection between the first and second via structures in B_M2 is made in different back metallization layers (e.g., B_M1 or B_M0).

[0062] Figure 2C Show Figure 2A The reduced front-side wiring (i.e., output pin (or driver pin) (M1) to M1 to VIA0 to FTV (M0)) uses M1 instead of M2. Figure 2C Also shown Figure 2B Reduced front-side wiring (i.e., FTV(M0) to VIA0 to M1 to VIA0 (via V0_03) to the input pin (or receiver pin) (M0)). In Figure 2C In this context, the B_FCC layer corresponds to a simplified layer for EDA tools to model FTV-related layers during the design process, and is used, for example, for RC extraction engines and routers to identify via stacks during back-side routing in EDA tools, so that the RC engine and router can treat this cell as a via for a mesh structure.

[0063] As mentioned above Figures 2A to 2C The semiconductor device according to the embodiment includes a first functional circuit 206, such as a buffer, in the functional circuit unit 207. The first functional circuit 206 includes driver pins 202. A first PG rail 230 extends along a first direction (parallel to the X-axis) in a MO layer (first metallization layer) on the front side of the semiconductor substrate. A third PG rail 234 extends along the first direction in the MO layer. The third PG rail 234 is spaced apart from the first PG rail 230 in a second direction (parallel to the Y-axis). The first functional circuit 206 is located on a first side of the third PG rail 234 and the first PG rail 230. Figure 2A Between the lower side of the first PG rail 230. A second functional circuit 208 (e.g., a buffer) is located in the functional circuit unit 211 and includes a receiver pin 204. A signal connection including back-side wiring couples a signal from the driver pin 202 to the receiver pin 204. The signal connection includes a conductive component 242 extending in the M1 layer (second metallization layer) along a second direction (Y-axis). The conductive component 242 is connected to the driver pin 202 and from the first side of the first PG rail 230. Figure 2A The lower side of the middle) spans across to the second side of the first PG guide rail 230 ( Figure 2A The upper side of the first PG rail 230 is also included in the signal connection. Figure 2A A first via structure (on the upper side of the first PG rail 230) is configured to provide signals from the conductive component 242 to the back side of the semiconductor substrate. The first via structure includes a second via structure located on the second side of the first PG rail 230. Figure 2A The signal connection also includes an FTV 201 (located on the upper side of the substrate). The signal connection further includes a second via structure configured to provide a signal to the front side of the semiconductor substrate. The second via structure includes an FTV 203. The signal connection also includes a conductive component 282 extending in the M1 layer along a second direction (Y-axis). The conductive component 282 is connected to the second via structure and the receiver pin 204.

[0064] Figure 2D This is a plan view of an exemplary embodiment of an FTV unit 200D having two pins (FTV_F 294 in layer M0 (front) and FTV_B292 in layer B_M0 (back)). Figure 2E It corresponds to Figure 2D A schematic cross-sectional view.

[0065] exist Figures 2D to 2E In this model, the RC model uses a simplified model of the signal FTV connection between M0 and B_M0. Figures 2D to 2E In the example shown, B_FCC combines an intermediate layer that includes MD, VD, and FTV related process layers.

[0066] refer to Figure 2DThe FTV unit 200D has a placement and routing boundary 290b_b for the back side and a placement and routing boundary 290b_f for the front side. Pin FTV_B 292 in the back side metal layer B_M0 is located within the back side placement and routing boundary 290b_b. Pin FTV_F 294 in the front side metal layer M0 is located within the front side placement and routing boundary 290b_f. Layer B_FCC 296 overlaps with pin FTV_F 294 along at least one of the X-axis and Y-axis directions. Pin FTV_F 294 and layer B_FCC 296 are located between M0 layer barriers 298 relative to the Y-axis direction. Figure 2E The cross-section of layer B_FCC 296 is shown, representing the intermediate layer between metal layer M0 and B_M0.

[0067] Corresponding to Figures 2D to 2E Examples of macros include the following:

[0068] MACRO FTV_CELL

[0069] PIN FTV_B

[0070] DIRECTION INOUT;

[0071] USE SIGNAL;

[0072] PORT

[0073] LAYER BFCC_B_M0_TAP;

[0074] RECT …;

[0075] LAYER B_M0 ;

[0076] RECT …;

[0077] END

[0078] END FTV_B

[0079] PIN FTV_F

[0080] DIRECTION INOUT;

[0081] USE SIGNAL;

[0082] PORT

[0083] LAYER B_FCC;

[0084] RECT …;

[0085] LAYER M0 ;

[0086] RECT …;

[0087] LAYER M0_BFCC_TAP;

[0088] RECT …;

[0089] END

[0090] END FTV_CELL

[0091] Figure 3 This is a flowchart of a method 300 for designing an IC device according to some embodiments. In some embodiments, Figure 3 Method 300 is incorporated into the method for manufacturing IC devices.

[0092] In method 300, the operation 302 of preparing the library includes preparing a standard unit library, which includes at least one standard unit as an independent FTV unit, for example... Figure 2A A separate FTV unit 205. In some embodiments, the library includes components such as... Figure 2A The standard units correspond to functional circuits such as functional circuit unit 207. In some embodiments, one or more standard units correspond to functional circuits with embedded FTV, such that the library includes both standalone FTV units and embedded FTV units.

[0093] Operation 304 includes establishing a layout plan for the IC device, such as setting cell sizes, arranging and allocating space for functional blocks (logic, memory, I / O, power, etc.). In some embodiments, operation 302 includes setting on the die... Figure 1 The position of macro 102.

[0094] In operation 306, various circuit components are configured. Operation 306 includes defining at least one region having independent FTV units that overlap with functional circuit units (see [link to relevant documentation]). Figure 1 (Region 104).

[0095] After operation 306, the following operations are performed: circuit optimization operation 308, clock tree synthesis (CTS) operation 310, signal routing (including back-side routing) operation 312, and post-routing optimization operation 314.

[0096] Following operation 314, operation 316 is performed to generate a Design Exchange Format (DEF) file representing the physical layout of the IC device. In other embodiments, data structures other than DEF files are used. Operation 316 includes outputting a net structure with subnets for FTVs. In some embodiments, a net structure represents a circuit structure connecting two functional circuits and including at least one FTV, as well as both front and back wiring (hereinafter combined). Figure 9A (Example describing a network structure). As discussed below, in some embodiments, the FTV unit is considered in the same way as a via; that is, the FTV unit is not considered a device. In other embodiments, the FTV unit is considered a device.

[0097] The result of operation 316 is used in operation 318 to extract the RC (resistance-capacitance) characteristics of the IC device. In some embodiments, operation 316 includes generating a Standard Parasitic Exchange Format (SPEF) file.

[0098] Similarly, after operation 314, operation 320 is performed to generate a netlist that includes a net structure for individual FTV units.

[0099] Finally, in operation 322, a statistical timing analysis (STA) is performed to evaluate the timing of the IC design, such as timing-critical routing (including timing-critical back-end routing). Depending on the results of operation 322, one or more of the previous operations of method 300 may be repeated.

[0100] The above description of method 300 is based on each of operations 302-322 being performed. However, in some embodiments, one or more of operations 302-322 are omitted, performed in a different order, and / or repeated.

[0101] Method 300 employs a standard cell library using independent FTV cells. As described in detail below, a standard cell library using independent FTV cells allows for optimized cell placement for layout by using a single cell for each independent FTV, and reduces the size and complexity of the standard cell library. This enables faster placement generation and reduces the consumption of system resources (e.g., memory, communication bandwidth, processor cycles, etc.) when designing IC devices. Furthermore, as mentioned above, Method 300 also reduces front-side wiring resistance compared to IC devices that only use embedded FTV functional circuit cells. Therefore, both the IC design flow and the resulting IC device are improved.

[0102] Figure 4This is a schematic diagram of the wiring using a standalone FTV according to some embodiments. Figure 5 This is a schematic diagram of wiring using an embedded FTV according to some embodiments.

[0103] In some embodiments, the IC device includes functional circuitry electrically connected via front and rear wiring connected by FTVs (at least some of which are implemented using separate FTV units). Figure 4 This is an example of using a separate FTV unit to connect the front and back wiring. According to some embodiments, the IC device uses, for example... Figure 4 The layout can be based on independent FTV units, and can also include layouts based on the use of, for example Figure 5 Wiring of the embedded FTV unit in the system.

[0104] exist Figure 4 In some embodiments, the first two-pin device 410 is a buffer. In some embodiments, the second two-pin device 420 is also a buffer. It should be understood that the first device 410 and the second device 420 may be the same or different, may have the same or different numbers of pins, and may be functional circuits other than buffering.

[0105] exist Figure 4 In this configuration, the first device 410 includes a first pin 412 and a second pin 414, and the second device 420 includes a third pin 422 and a fourth pin 424. For clarity, although connections to the first pin 412 or the fourth pin 424 exist, these connections are not shown. The first to fourth pins 412, 414, 422, and 424 are located on the front side of the substrate. The connection between the second pin 414 and the third pin 422 includes back-side routing using a first independent FTV 430 and a second independent FTV 440, whereby the first independent FTV 430 routes signals from the second pin 414 on the front side of the substrate to the back side of the substrate, and the second independent FTV 440 routes signals from the back side of the substrate to the third pin 422 on the front side of the substrate. The layout of the first device 410, the second device 420, the first feedthrough via (FTV) 430, and the second feedthrough via (FTV) 440 is fabricated using independent FTV cells for the first FTV 430 and the second FTV 440.

[0106] exist Figure 5 In some embodiments, the first device 510 is a buffer. In some embodiments, the second device 520 is also a buffer. It should be understood that the first device 510 and the second device 520 may be the same or different, may have the same or different numbers of pins, and may be functional circuits other than buffering.

[0107] The first device 510 includes a first pin 512, and the second device 520 includes a second pin 522. The first pin 512 and the second pin 522 are located on the front side of the substrate. The connection between the first pin 512 and the second pin 522 includes back-side wiring using a first embedded FTV 530 (embedded together with the first device 510) and a second embedded FTV 540 (embedded together with the second device 520). The layout of the first device 510 and the second device 520 is fabricated using embedded FTV cells, wherein cells for functional circuitry (i.e., buffers) include corresponding FTVs 430 and 440.

[0108] Although Figure 5 In principle, it seems there is no Figure 4 It's that complicated, but actually, due to the additional front wiring, Figure 5 The embedded FTV unit relative to Figure 4 The independent FTV unit exhibits wiring RC costs. In other words, as mentioned above... Figure 2A The subject of discussion Figure 4 The layout of the independent FTV units of the first FTV 430 and the second FTV 440 in the middle results in a layout relative to the functional circuit units therein, including embedded FTVs (such as...). Figure 5 As shown, this reduces the front-side routing. Furthermore, as discussed in detail below, such as... Figure 5 Using embedded FTV cells to implement devices involves a trade-off between area loss (due to the larger cell area of ​​embedded FTV cells) and library complexity (due to the large number of area-optimized standard cells used for embedded FTV cells if area loss is to be avoided). However, despite the limitations imposed by embedded FTV cells, in some cases it may be desirable to combine embedded FTV cells with standalone FTV cells in an IC device. This will now be discussed in conjunction with... Figure 6 This will be described.

[0109] Figure 6 This is a schematic diagram of wiring using a combination of embedded FTV and stand-alone FTV according to some embodiments.

[0110] exist Figure 6 In some embodiments, the first device 610 is a large drive buffer. The second device 620 is generally represented as a receiver that receives signals from the first device 610. The first device 610 is implemented using an embedded FTV unit, and the wiring to the second device 620 is implemented using a separate FTV unit. More specifically, the first device 610 is shown as including embedded FTVs 630, 632, and 634 (the number of embedded FTVs may be less than three or more), and the wiring to the second device 620 is shown as using a separate FTV 640. Figure 6The hybrid unit implementation allows for flexibility and ease of wiring, such as wider and less complex wiring for higher current circuit paths, while retaining at least some of the advantages offered by the layout using individual FTV units, such as reduced front wiring.

[0111] Figure 7 This is a schematic diagram of wiring according to some embodiments.

[0112] exist Figure 7 In this context, the independent FTV unit is used to implement the front and back wiring of the first series of three-pin units.

[0113] exist Figure 7 In this circuit, the first functional circuit unit 710_1 is connected to the second functional circuit unit 710_2, the third functional circuit unit 710_3, and the fourth functional circuit unit 710_4 using wiring that includes an independent FTV unit. The first to fourth functional circuit units 701_1 to 710_4 are identical.

[0114] Compared to a standard unit library that uses standard units with embedded FTVs, the standard unit library, according to some embodiments, is simplified by using independent FTV units. Figure 7 In this context, all first to fourth functional circuit units 710_1 to 710_4 can be identical; for example, all pins are on the front side. In the embedded FTV unit library, to save layout area, standard units with embedded FTV and multiple input pins should be included in the library with all combinations of front and rear input pins.

[0115] More in detail, Figure 7 Using a combination of a functional circuit unit with only front-side pins and a standalone FTV unit, while embedded FTV units have various combinations for front-to-back, back-to-back, and back-to-front connections, leads to greater library complexity. For example, for an embedded FTV unit with 2 input pins and 1 output pin (3 pins in total), the library of 3-input pin units should include 2... 3 =8 units. Furthermore, the unit library immediately becomes more complex when including embedded FTV units with more pins and providing standard units for all combinations of front and rear input pins. For example, each embedded FTV 4-pin unit should be provided as 2 4 =16 units, each embedded FTV 5-pin unit should be provided as 2 5 =32 units, each embedded FTV 6-pin unit should be provided as 2 6 =64 units, stacked in this way, so that for each embedded FTV 10-pin unit, the unit library should provide 2 10=1024 units.

[0116] According to some embodiments, the standard cell library using independent FTV cells allows for optimized layout using single-function circuit cells and single cells for independent FTVs, thereby reducing the size and complexity of the standard cell library. This enables faster layout generation and reduces the consumption of system resources (e.g., memory, communication bandwidth, processor cycles, etc.). According to some embodiments, IC designs using independent FTV cells allow only front-side pin cells (i.e., cells with only front-side pins) to be routed using a back-side routing layer with a relatively simple cell library, i.e., without the need for the larger and more complex libraries that would be used when routing the back-side pins of multi-input pin cells.

[0117] Figure 8A , Figure 8B and Figure 8C This is a layout diagram of an IC device according to some embodiments.

[0118] Figures 8A to 8C The embodiments use various layouts and wiring of independent FTV units connected to functional circuit units.

[0119] refer to Figure 8A Layout 800A includes a separate FTV unit 805A connected to functional circuit unit 807A. In some embodiments, functional circuit unit 807A is a large drive unit (a buffer with multiple output pins). Larger drive units are used in some embodiments to drive correspondingly wider networks.

[0120] Layout 800A includes a single M1 wiring connection between the standalone FTV unit 805A and the functional circuit unit 807A. In some embodiments, using wiring in M1 instead of M0 allows for a lower resistance connection because the wiring in M1 can be wider than the wiring in M0. In layout 800A, a conductive component 842 in the M1 layer extends parallel to the Y-axis between the standalone FTV unit 805A and the functional circuit unit 807A. The conductive component 842 is generally centered relative to the X-axis along the centerline CL of the output pin of the functional circuit unit 807A.

[0121] refer to Figure 8B Layout 800B includes a separate FTV unit 805B connected to functional circuit unit 807B. In some embodiments, functional circuit unit 807B is a large drive unit. Layout 800B includes multiple M1 wiring connections to reduce resistance. In layout 800B, a first conductive component 842_1 and a second conductive component 842_2 on the M1 layer extend parallel to the Y-axis between the separate FTV unit 805B and the functional circuit unit 807B.

[0122] refer to Figure 8CLayout 800C includes a first independent FTV unit 805C and a second independent FTV unit 805D, each connected to a functional circuit unit 807C. In some embodiments, the functional circuit unit 807C is a large drive unit. Using multiple independent FTV units can further reduce the front wiring resistance of the rear wiring network. Layout 800C includes a single M1 wiring connection (conductive components 842_1, 842_2 shown in solid lines) to the independent FTV units 805C, 805D or multiple M1 wiring connections (conductive components 842_1, 842_2 shown in solid lines and conductive components 842_3, 842_4 shown in dashed lines).

[0123] Figure 9A and Figure 9B This is a schematic diagram of the network structure of a signature method designed according to some embodiments of an independent FTV unit.

[0124] exist Figure 9A In this method, the sign-off method treats the FTV network in the netlist as a network structure (denoted as network N2). This method supports the use of traditional sign-off operations (e.g., Automated Place-and-Route (APR) processes, Statistical Timing Analysis (STA), RC verification calculations for calculating the resistance and capacitance of the wiring interconnects, and / or formal verification).

[0125] use Figure 9A The network-based sign-off method allows FTV RC components to be treated as part of the cabling RC, thus simplifying RC calculations. This approach avoids latency and variations in STA calculations. However, the APR process becomes more complex because the database structure is modified to divide the network into front and back sections for entity implementation.

[0126] exist Figure 9A In this configuration, the first buffer 910 and the second buffer 920 are connected using a first independent FTV 930 and a second independent FTV 940, wherein the first independent FTV 930 routes the signal from the front side of the substrate to the back side of the substrate, and the second independent FTV 940 routes the signal from the back side of the substrate to the front side of the substrate. According to some embodiments, the first FTV 930 and the second FTV 940 are fabricated using independent FTV units. The wiring on the front side of the substrate includes front wiring components (e.g., conductive components in the wiring layer), which include a first front wiring component 913 and a second front wiring component 917. The wiring on the back side of the substrate includes a back wiring component 915. The first front wiring component 913, the second front wiring component 917, the back wiring component 915, the first FTV 930, and the second FTV 940 are collectively considered as a network, denoted as a first network N2. This is in Figure 9AThe diagram schematically shows a series of RC components combined into a network between the first buffer 910 and the second buffer 920.

[0127] exist Figure 9B In this method, the approval process considers the FTV network as a network structure consisting of at least three networks (first and second front cabling assemblies 913, 917 and rear cabling assembly 915; N1 to N3). This method can use a more... Figure 9A The method uses a less complex database structure because it uses separate networks for the front and back sides. However, this leads to increased RC and / or STA computational complexity when the RC components of the FTV 930 and 940 are absent, unknown, or of insufficient accuracy, because the STA timing path is disrupted by the FTV cells. Therefore, Figure 9B The approval methodology should model characteristics such as FTV unit timing and crosstalk to provide more accurate STA. Furthermore, data structures such as SDF (Standard Delay Format) or SPEF (Standard Parasitic Exchange Format) files should be updated to evaluate FTV unit RC contributions, and corresponding enhancements should be made to delay and STA calculations.

[0128] Refer again Figure 9A Layout versus schematic (LVS) verification is performed according to the embodiment to treat the FTV as a via rather than a separate device. In one example, Figure 9A One network structure is omitted from the netlist of Verilog or the Simulation Program with Integrated Circuit Emphasis (SPICE):

[0129] BUFF buf1(.Z(N2), .I(N0)); BUFF buf2(.Z(N4), .I(N2));

[0130] In the example above, buf1 is the first buffer 910, and buf2 is the second buffer 920. N0 represents the input of the first buffer 910, N2 represents the network connecting the first buffer 910 to the second buffer 920 and including FTVs 930 and 940, and N4 represents the output of the second buffer 920. In some embodiments, the above example is used in the place and route (PNR) operation of digital circuits.

[0131] In another example, Figure 9A One network architecture treats the FTV as a device included in a Verilog or SPICE netlist:

[0132] BUFF buf1(.I(N0), .Z(N2)); FTV ftv1(.I(N2), .Z(N2)); FTV ftv2(.I(N2), .Z(N2)); BUFF buf2(.I(N2), .Z(N4));

[0133] In the example above, buf1 is the first buffer 910, ftv1 is the first FTV 930, ftv2 is the second FTV 940, and buf2 is the second buffer 920. N0 represents the input to the first buffer 910, N2 represents the wiring from the first buffer 910 to the second buffer 920 (including the first FTV 930, the second FTV 940, and the front and back wiring connected thereto), and N4 represents the output of the second buffer 920. In some embodiments, the above device-based example is used for evaluating analog circuits.

[0134] Refer again Figure 9B ,and Figure 9A In contrast, LVS verification is not implemented to treat the FTV as a via. More precisely, LVS verification uses a device-based approach, employing three networks from a Verilog or SPICE netlist, to describe the FTV connection:

[0135] BUFF buf1(.I(N0), .Z(N1)); FTV ftv1(.I(N1), .Z(N2)); FTV ftv2(.I(N2), .Z(N3)); BUFF buf2(.I(N3), .Z(N4));

[0136] In the example above, buf1 is the first buffer 910, ftv1 is the first FTV 930, ftv2 is the second FTV 940, and buf2 is the second buffer 920. N0 represents the input to the first buffer 910, N1 represents the front-side routing from the first buffer 910 to the first FTV 930, N2 represents the back-side routing from the first FTV 930 to the second FTV 940, N3 represents the front-side routing from the second FTV 940 to the second buffer 920, and N4 represents the output of the second buffer 920. In some embodiments, the above device-based example is used for evaluating analog circuits.

[0137] Figure 10 This is a flowchart of a method 1000 for generating a layout and using the layout to manufacture an IC device according to some embodiments.

[0138] According to some embodiments, method 1000 may, for example, use electronic design automation system 1300 (see...). Figure 13 The EDA system 1300 (described below) and the integrated circuit (IC) manufacturing system 1400 ( Figure 14 The following discussion describes how this method is implemented. Examples of layouts related to method 1000 include those disclosed herein. Examples of IC devices manufactured according to method 1000 include those disclosed herein. Figure 10 In this context, method 1000 includes operations 1002 and 1004.

[0139] At operation 1002, a layout is generated. In some embodiments, operation 1002 for generating the layout includes selecting standard cells from a standard cell library, the standard cell library including one or more standard cells representing an FTV. In some embodiments, operation 1002 includes selecting functional circuit standard cells and standard cells representing independent FTVs from the library, and placing the functional circuit standard cells and independent FTV cells in the layout. In some embodiments, an independent FTV cell is a separate cell in the library. In some embodiments, an independent FTV cell does not include active devices such as transistors. In some embodiments, an independent FTV cell does not include functional circuit components such as buffers, inverters, etc. In some embodiments, an independent FTV cell does not include logic. The process proceeds from operation 1002 to operation 1004.

[0140] At operation 1004, based on the layout, at least one of the following is true: (A) performing one or more photolithographic exposures, or (B) fabricating one or more semiconductor masks, or (C) fabricating one or more components in a layer of an IC device.

[0141] Figure 11 This is a flowchart of a method 1100 for generating a layout according to some embodiments. More specifically, Figure 11 The flowchart illustrates additional operations according to one or more embodiments, demonstrating that they can be performed... Figure 10 An example of the procedure implemented in operation 1002. Figure 11 In this context, operation 1002 includes operations 1102 to 1104.

[0142] At operation 1102, the method includes placing a first unit in a first row of the layout and placing a first independent FTV unit in a second row of the layout adjacent to the first row.

[0143] At operation 1104, the method includes generating wiring connections to a first cell and a first independent FTV cell, the wiring connections including a first wiring connection on the front side of the substrate and a second wiring connection on the back side of the substrate, the first wiring connection connecting the first cell to the first independent FTV cell and extending from the first cell to the first independent FTV cell in a second direction orthogonal to the first direction, the second wiring connection being connected to the first independent FTV cell.

[0144] Figure 12 This is a flowchart of a method 1200 for manufacturing one or more components of an IC device according to some embodiments. More specifically, Figure 12 The flowchart illustrates additional operations according to one or more embodiments, demonstrating that... Figure 10 An example of the procedure implemented in operation 1004. Figure 12In the middle, operation 1004 includes operations 1202~1210.

[0145] At operation 1202, a first functional circuit is formed having a first pin in a first region of the semiconductor substrate, and a second functional circuit is formed having a second pin in a second region of the semiconductor substrate.

[0146] At operation 1204, a first power conductor is formed extending in a first direction in a first metallization layer (e.g., MO metallization layer) on the front side of a semiconductor substrate, such that a first side of the first power conductor faces the first functional circuit, and a second power conductor is formed extending in the first metallization layer in the first direction, and the first functional circuit is arranged between the second power conductor and the first side of the first power conductor.

[0147] At operation 1206, a signal connection is formed to couple the signal between the first pin and the second pin. Operation 1206 includes operations 1208 to 1210.

[0148] At operation 1208, a first via structure is formed to provide a signal to the back side of the semiconductor substrate. Forming the first via structure includes forming a first feed-through via (FTV) on the second side of the first power conductor. Operation 1208 also includes forming a second via structure configured to provide a signal to the front side of the semiconductor substrate. Forming the second via structure includes forming a second FTV.

[0149] At operation 1210, a first conductive component is formed extending along a second direction in a second metallization layer. In some embodiments, the second direction is perpendicular to the first direction. The second metallization layer is, for example, an M1 metallization layer, which is a first metallization layer above an M0 metallization layer. The first conductive component is formed to connect a first via structure to a first pin. Operation 1210 also includes forming a second conductive component extending along the second direction in the second metallization layer. The second conductive component is formed to connect a second via structure to a second pin.

[0150] The described methods include exemplary operations, but they do not necessarily need to be performed in the order shown. Operations may be appropriately added, substituted, rearranged, and / or eliminated according to the spirit and scope of the embodiments disclosed herein. Embodiments combining different components and / or different embodiments are still within the scope of this disclosure and will be apparent to those skilled in the art upon reading this disclosure.

[0151] In some embodiments, at least one of the above methods is performed, in whole or in part, by at least one EDA system. In some embodiments, the EDA system may be used as part of the design organization of the IC manufacturing system discussed below.

[0152] Figure 13 This is a block diagram of an electronic design automation (EDA) system 1300 according to some embodiments.

[0153] In some embodiments, EDA system 1300 includes an APR system. According to one or more embodiments, the design layout methods described herein indicate that wiring arrangements can be implemented, for example, using EDA system 1300 according to some embodiments.

[0154] In some embodiments, the EDA system 1300 is a general-purpose computing device including a hardware processor 1302 and a non-transitory computer-readable storage medium 1304. Among other forms, the computer-readable storage medium 1304 is encoded with (i.e., stores) computer program code 1306 (i.e., an executable instruction set). Execution of the instructions 1306 by the processor 1302 represents (at least partially) an EDA tool for implementing some or all of the methods described herein (hereinafter referred to as the mentioned process and / or method) according to one or more embodiments.

[0155] Processor 1302 is electrically coupled to computer-readable storage medium 1304 via bus 1308. Processor 1302 is also electrically coupled to input / output (I / O) interface 1310 via bus 1308. Network interface 1312 is also electrically connected to processor 1302 via bus 1308. Network interface 1312 is connected to network 1314 so that processor 1302 and computer-readable storage medium 1304 can be connected to external components via network 1314. Processor 1302 is configured to execute computer program code 1306 encoded in computer-readable storage medium 1304 so that EDA system 1300 can be used to implement some or all of the mentioned processes and / or methods. In one or more embodiments, processor 1302 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0156] In one or more embodiments, the computer-readable storage medium 1304 is an electronic system, magnetic system, optical system, electromagnetic system, infrared system, and / or semiconductor system (or device or apparatus). Examples of the computer-readable storage medium 1304 include semiconductor or solid-state memory, magnetic tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1304 includes compact disk-readonly memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0157] In one or more embodiments, the computer-readable storage medium 1304 stores computer program code 1306 configured to enable the EDA system 1300 to perform some or all of the mentioned processes and / or methods (where such execution (at least partially) represents an EDA tool). In one or more embodiments, the computer-readable storage medium 1304 also stores information that facilitates the performance of some or all of the mentioned processes and / or methods. In one or more embodiments, the computer-readable storage medium 1304 stores a library 1307 of standard cells, including such standard cells as disclosed herein.

[0158] EDA system 1300 includes I / O interface 1310. I / O interface 1310 is coupled to an external circuit system. In one or more embodiments, I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1302.

[0159] EDA system 1300 also includes a network interface 1312 coupled to processor 1302. Network interface 1312 enables EDA system 1300 to communicate with a network 1314 connected to one or more other computer systems. Network interface 1312 includes: a wireless network interface, such as Bluetooth, Wireless Fidelity (WIFI), Worldwide Interoperability of Microwave Access (WIMAX), General Packet Radio Service (GPRS), or Wideband Code Division Multiple Access (WCDMA); or a wired network interface, such as Ethernet, Universal Serial Bus (USB), or Institute of Electrical and Electronics Engineers (IEEE)-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more EDA systems 1300.

[0160] EDA system 1300 is configured to receive information via I / O interface 1310. The information received via I / O interface 1310 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1302. This information is transferred to processor 1302 via bus 1308. EDA system 1300 is also configured to receive information related to the user interface (UI) via I / O interface 1310. This information is stored as user interface (UI) 1342 in computer-readable storage medium 1304.

[0161] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by EDA system 1300. In some embodiments, a layout including standard cells is generated using tools such as VIRTUOSO®, available from Cadence Design Systems, Inc., or another suitable layout generation tool.

[0162] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in memory or memory cells, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, memory cards), and one or more of similar media.

[0163] Figure 14 This is a block diagram of an integrated circuit (IC) manufacturing system 1400 and associated IC manufacturing processes according to some embodiments. In some embodiments, the IC manufacturing system 1400 is used to fabricate at least one of the following based on layout: (A) one or more semiconductor masks; or (B) at least one component in a layer of a semiconductor integrated circuit.

[0164] exist Figure 14In this IC manufacturing system 1400, entities such as a design house 1420, a mask house 1430, and an IC manufacturer / fab 1450 interact with each other in design, development, and manufacturing cycles and / or services related to the manufacture of IC devices 1460. These entities in the IC manufacturing system 1400 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 1420, mask house 1430, and IC foundry 1450 are owned by a single, larger company. In some embodiments, two or more of the design facility 1420, mask facility 1430, and IC foundry 1450 coexist in a shared facility and use shared resources.

[0165] Design organization (or design team) 1420 generates IC design layout 1422. IC design layout 1422 includes various geometric patterns designed for IC device 1460. The geometric patterns correspond to patterns of metal layers, oxide layers, or semiconductor layers constituting various components of the IC device 1460 to be manufactured. The various layers are combined to form various IC features. For example, a portion of IC design layout 1422 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer), such as active regions, gate electrodes, source and drain electrodes, interlayer interconnecting metal lines or vias, and openings in bonding pads, as well as various material layers disposed on the semiconductor substrate. Design organization 1420 performs a formal design process to form IC design layout 1422. The design process includes one or more of logic design, physical design, or placement and routing. IC design layout 1422 exists in one or more data files containing information of the geometric patterns. For example, IC design layout 1422 can be expressed as a GDSII file format or a Design Framework II (DFII) file format.

[0166] Masking mechanism 1430 includes data preparation 1432 and mask fabrication 1444. Masking mechanism 1430 uses IC design layout 1422 to fabricate one or more masks 1445 for the various layers to be used in fabricating IC device 1460, based on IC design layout 1422. Masking mechanism 1430 performs mask data preparation 1432, in which IC design layout 1422 is translated into a representative data file (RDF). Mask data preparation 1432 provides the RDF to mask fabrication 1444. Mask fabrication 1444 includes a mask writer. The mask writer converts the RDF into an image on a substrate (e.g., a mask (reticle) 1445 or a semiconductor wafer 1453). IC design layout 1422 is adjusted by mask data preparation 1432 to comply with the specific characteristics of the mask writer and / or the requirements of IC foundry 1450. exist Figure 14 In this embodiment, mask data preparation 1432 and mask fabrication 1444 are shown as separate components. In some embodiments, mask data preparation 1432 and mask fabrication 1444 may be collectively referred to as mask data preparation.

[0167] In some embodiments, mask data preparation 1432 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, and similar factors. OPC adjusts the IC design layout 1422. In some embodiments, mask data preparation 1432 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and similar techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT), which treats OPC as a reverse imaging problem, is also used.

[0168] In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that uses a set of mask creation rules, containing certain geometric and / or connectivity constraints, to check the IC design layout 1422 that has undergone various processes in the OPC to ensure that there is sufficient margin to account for variability in semiconductor manufacturing processes and achieve similar effects. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for constraints during mask fabrication 1444, which may undo some of the modifications implemented by the OPC to satisfy the mask creation rules.

[0169] In some embodiments, mask data preparation 1432 includes lithography process checking (LPC), which simulates a process to be performed by IC foundry 1450 to fabricate IC device 1460. LPC simulates this process based on IC design layout 1422 to create a simulated fabricated device (e.g., IC device 1460). Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar factors, or combinations thereof. In some embodiments, after a simulated fabricated device has been created using LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1422.

[0170] It should be understood that, for clarity, the above description of mask data preparation 1432 has been simplified. In some embodiments, data preparation 1432 includes additional features such as logic operations (LOPs) to modify the IC design layout 1422 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1422 during data preparation 1432 can be performed in various different sequences.

[0171] Following mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or a group of masks 1445 is fabricated based on a modified IC design layout 1422. In some embodiments, mask fabrication 1444 includes performing one or more lithographic exposures based on the IC design layout 1422. In some embodiments, a pattern is formed on the mask (photomask or stencil) 1445 based on the modified IC design layout 1422 using an electron beam (e-beam) or multiple electron beam mechanism. The mask 1445 can be formed using various techniques. In some embodiments, the mask 1445 is formed using binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary mask version of mask 1445 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in opaque areas of the binary mask. In another example, mask 1445 is formed using a phase-shifting technique. In the phase-shift mask (PSM) version of mask 1445, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase difference to enhance resolution and image quality. In various examples, the phase-shift mask may be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 1444 is used in various processes. For example, this mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1453, in etching processes to form various etched regions in semiconductor wafer 1453, and / or other suitable processes.

[0172] IC foundry 1450 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC foundry 1450 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end fabrication (front-end-of-line (FEOL) fabrication) of multiple IC products, a second manufacturing facility that provides back-end fabrication (back-end-of-line (BEOL) fabrication) for interconnection and packaging of IC products, and a third manufacturing facility that provides other services to the foundry company.

[0173] IC foundry 1450 includes fabrication tooling 1452 configured to perform various manufacturing operations on semiconductor wafer 1453, thereby enabling the fabrication of IC device 1460 based on a mask (e.g., mask 1445). In various embodiments, fabrication tooling 1452 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, process chamber (e.g., CVD chamber or low-pressure chemical vapor deposition (LPCVD) furnace), chemical mechanical polishing (CMP) system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes discussed herein.

[0174] IC foundry 1450 uses mask 1445, fabricated by mask assembly 1430, to fabricate IC device 1460. Therefore, IC foundry 1450 uses IC design layout 1422 at least indirectly to fabricate IC device 1460. In some embodiments, semiconductor wafer 1453 is fabricated by IC foundry 1450 using mask 1445 to form IC device 1460. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1422. Semiconductor wafer 1453 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1453 further includes one or more of various doped regions, dielectric features, multilevel interconnects, and similar components (formed at subsequent manufacturing steps).

[0175] Involving integrated circuit (IC) manufacturing systems (e.g., Figure 14 Details of the IC manufacturing system 1400 and its associated IC manufacturing processes can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Early Publication No. 2015 / 0278429, published October 1, 2015; U.S. Early Publication No. 2014 / 0040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of which are incorporated herein by reference.

[0176] In some embodiments, standard cells from a cell library are used to generate a layout. The standard cells include at least a first cell and a first independent feedthrough via (FTV) cell. The first cell includes a transistor, and the first independent FTV cell includes a first FTV but does not include a transistor. The first cell is placed in a first row of the layout, the first row extending along a first direction. The first independent FTV cell is placed in a second row of the layout, the second row extending along the first direction and adjacent to the first row. Wiring connections to the first cell and the first independent FTV cell are generated, the wiring connections including: a first wiring connection on a first side of the substrate, the first wiring connection connecting the first cell and the first independent FTV cell, and extending from the first cell to the first independent FTV cell in a second direction orthogonal to the first direction; and a second wiring connection on a second side of the substrate, the second side opposite to the first side, the second wiring connection connecting to the first independent FTV cell; and an IC design is generated based on the layout.

[0177] In some embodiments, a method of manufacturing an integrated circuit (IC) device includes: generating a layout using standard cells from a cell library, the standard cells including at least a first cell, a second cell, and an independent feedthrough via (FTV) cell, the first cell including a transistor, the second cell including a transistor and being the same as or different from the first cell, and the independent FTV cell including an FTV but not including a transistor; placing the first cell in a first row of the layout; placing a first instance of the independent FTV cell in a second row of the layout, the second row being adjacent to the first row; placing the second cell in a row of the layout that is the same as or different from the first row and the second row; placing a second instance of the independent FTV cell in a row of the layout that is the same as or different from the first row and the second row; generating the first cell, the second cell, and the first and second instances of the independent FTV cell. The wiring connection includes: a first wiring connection on a first side of a substrate, the first wiring connection connecting a first cell and a first instance of an independent FTV cell; a second wiring connection on a second side of the substrate, the second side being opposite to the first side, the second wiring connection connecting the first instance of the independent FTV cell to a second instance of the independent FTV cell; and a third wiring connection on the first side of the substrate, the third wiring connection connecting the second instance of the independent FTV cell to a second cell; evaluating the timing characteristics of a first circuit portion of the layout by treating a first circuit portion as a single network, the first circuit portion including: the first wiring connection, a first FTV in the first instance of the independent FTV cell, the second wiring connection, a second FTV in the second instance of the independent FTV cell, and the third wiring connection; and generating a layout-based IC design.

[0178] In some embodiments, a system for manufacturing an integrated circuit (IC) device includes: at least one memory configured to store device layout data, the memory including a non-transitory computer-readable storage medium; and at least one processor configured to: access the at least one memory and retrieve the device layout data; generate a device layout from the device layout data; and generate an IC design based on the layout, the device layout generation comprising: selecting standard cells from a cell library, the standard cells including at least a first cell and a first independent feedthrough via (FTV) cell, the first cell including a transistor, and the first independent FTV cell including an FTV but not including a transistor; placing the first cell in a first row of the layout, the first row extending along a first direction; placing the first independent FTV cell in a second row of the layout, the second row extending along the first direction and adjacent to the first row; and generating wiring connections to the first cell and the first independent FTV cell, the wiring connections including: a first wiring connection on a first side of a substrate, the first wiring connection connecting the first cell and the first independent FTV cell, and extending from the first cell to the first independent FTV cell in a second direction orthogonal to the first direction; and a second wiring connection on a second side of a substrate, the second side opposite to the first side, the second wiring connection connecting to the first independent FTV cell.

[0179] In some embodiments, a semiconductor device includes: a first functional circuit having a first pin in a first region of a substrate; a first power conductor extending in a first direction in a first metallization layer on the front side of the substrate; a second power conductor located in the first metallization layer, the first functional circuit being located between the second power conductor and a first side of the first power conductor; a second functional circuit having a second pin in a second region of the substrate; and a signal connection configured to couple a signal between the first pin and the second pin. The signal connection includes: a first conductive component extending in a second metallization layer in a second direction, the first conductive component being connected to the first pin on a first side of the first power conductor; a first via structure connecting the first conductive component to a back side of the substrate, the first via structure including a first feedthrough via (FTV) on a second side of the first power conductor; a second via structure configured to provide a signal to the front side of the substrate, the second via structure including a second FTV; and a second conductive component in a second metallization layer, the second conductive component being connected to the second via structure and the second pin.

[0180] In some embodiments, the first conductive component overlaps perpendicularly with the first FTV. In some embodiments, the first conductive component is located near the centerline of the first FTV. In some embodiments, the distance between the centerline of the first conductive component along the second direction and the centerline of the first FTV is about one contact polysilicon pitch (CPP) or less. In some embodiments, the first conductive component overlaps perpendicularly with a first pin. In some embodiments, the second conductive component extends in the second direction and overlaps perpendicularly with the second FTV. In some embodiments, the second conductive component overlaps perpendicularly with a second pin. In some embodiments, at least one of the first pin or the second pin corresponds to a metal-to-oxide diffusion (MD) contact. In some embodiments, the first functional circuit and the second functional circuit are each multi-pin circuits with all pins on the front side of the substrate.

[0181] In some embodiments, a method of manufacturing a semiconductor device includes: forming a first functional circuit having a first pin in a first region of a substrate; forming a second functional circuit having a second pin in a second region of the substrate; forming a first power conductor extending in a first direction in a first metallization layer on the front side of the substrate, such that a first side of the first power conductor faces the first functional circuit; forming a second power conductor in the first metallization layer, the first functional circuit being located between the second power conductor and the first side of the first power conductor; forming a signal connection configured to couple a signal between the first pin and the second pin, the signal connection including: forming a first via structure configured to provide a signal to the back side of the substrate, the first via structure including forming a first feedthrough via (FTV) on a second side of the first power conductor; forming a second via structure configured to provide a signal to the front side of the substrate, the second via structure including forming a second FTV; forming a first conductive component extending in a second direction in a second metallization layer, the first conductive component being configured to connect the first via structure to the first pin; and forming a second conductive component in the second metallization layer, the second conductive component being configured to connect the second via structure to the second pin.

[0182] In some embodiments, forming a first conductive component includes: forming a first conductive component perpendicularly overlapping a first FTV. In some embodiments, forming a first conductive component includes: forming a first conductive component such that the first conductive component perpendicularly overlaps a first pin. In some embodiments, forming a second conductive component includes: forming a second conductive component extending along a second direction and perpendicularly overlapping a second FTV. In some embodiments, forming a first functional circuit and a second functional circuit includes: forming the first functional circuit and the second functional circuit as multi-pin circuits with all pins on the front side of the substrate.

[0183] In some embodiments, an integrated circuit includes: a first circuit and a second circuit on a first surface of a substrate, the first circuit and the second circuit being connected together by a conductive path, the conductive path including a conductor on a second surface of the substrate, the second surface being opposite to the first surface, the conductive path including: a first conductive component coupling an input or output of the first circuit to a first via structure, the input or output of the first circuit being located on a side of a first power conductor opposite to the first via structure, the first power conductor extending in a first metallization layer on the first surface of the substrate along a first direction, and the first conductive component extending in a second metallization layer above the first metallization layer along a second direction; and a second conductive component in the second metallization layer, the second conductive component being connected to a second via structure and the input or output of the second circuit. The first via structure connects the first conductive component to the conductor on the second surface of the substrate, the first via structure including a first feedthrough via (FTV) on one side of the first power conductor. The second via structure connects the conductor on the second surface of the substrate to the second conductive component, the second via structure including a second FTV.

[0184] In some embodiments, the first conductive component overlaps perpendicularly with the first FTV. In some embodiments, the distance between the centerline of the first conductive component along the second direction and the centerline of the first FTV is about one contact polysilicon pitch (CPP) or less. In some embodiments, the first conductive component overlaps perpendicularly with the input or output of the first circuit. In some embodiments, the second conductive component overlaps perpendicularly with the input or output of the second circuit. In some embodiments, the first circuit and the second circuit are each multi-pin circuits with all pins on the first surface of the substrate.

[0185] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor device, characterized by comprising: include: A first functional circuit having a first pin in a first region of a substrate; A first power conductor extends in a first direction in a first metallization layer on the front side of the substrate; The second power conductor is located in the first metallization layer, and the first functional circuit is located between the second power conductor and the first side of the first power conductor. The second functional circuit has a second pin in the second region of the substrate; as well as A signal connection, configured to couple a signal between the first pin and the second pin, the signal connection comprising: A first conductive component extends in a second direction in a second metallization layer, and the first conductive component is connected to the first pin on the first side of the first power conductor. A first via structure connects the first conductive component to the back side of the substrate, the first via structure including a first feedthrough via on the second side of the first power conductor; A second via structure, configured to provide the signal to the front side of the substrate, the second via structure including a second feedthrough via; and The second conductive component is located in the second metallization layer and is connected to the second via structure and the second pin.

2. The semiconductor device according to claim 1, wherein The first conductive component overlaps perpendicularly with the first feedthrough hole.

3. The semiconductor device according to claim 1, wherein The distance between the centerline of the first conductive component along the second direction and the centerline of the first feedthrough via is approximately one contact polysilicon pitch or less.

4. The semiconductor device according to claim 1, wherein The first conductive component overlaps perpendicularly with the first pin.

5. The semiconductor device according to claim 1, wherein The second conductive component overlaps perpendicularly with the second pin.

6. The semiconductor device according to claim 1, wherein At least one of the first pin or the second pin corresponds to a metal-to-oxide diffusion contact.

7. An integrated circuit, characterized by include: A first circuit and a second circuit are located on a first surface of a substrate and are connected together via a conductive path. The conductive path includes a conductor on a second surface of the substrate, opposite to the first surface. The conductive path includes: A first conductive component couples the input or output of the first circuit to a first via structure, wherein the input or output of the first circuit is located on the side of a first power conductor opposite to the first via structure, and the first power conductor extends along a first direction in a first metallization layer on the first surface of the substrate. The first conductive component extends along a second direction in a second metallization layer above the first metallization layer; and The second conductive component, within the second metallization layer, is connected to the second via structure and the input or output of the second circuit, wherein: The first via structure connects the first conductive component to the conductor on the second surface of the substrate, and the first via structure includes a first feedthrough via on one side of the first power conductor. The second via structure connects the conductor on the second side of the substrate to the second conductive component, and the second via structure includes a second feedthrough via.

8. The integrated circuit of claim 7, wherein, The first conductive component overlaps vertically with the input or output of the first circuit.

9. The integrated circuit of claim 7, wherein, The second conductive component vertically overlaps the input or the output of the second circuit.

10. The integrated circuit of claim 7, wherein, The first circuit and the second circuit are each a multi-pin circuit having all pins on the first side of the substrate.

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