A back contact cell

Abstract

This invention provides a back contact battery. By setting a dielectric layer between two doped layers of different conductivity types, and during the preparation of the doped layer, the dopant diffuses to form the doped layer while penetrating the dielectric layer to form nano-sized, uniformly distributed pores in the dielectric layer for carrier transport, serving as a leakage channel between the two doped layers, the risk of hot spots is reduced, and the preparation process is simple and does not require additional process steps.

Description

Technical Field

[0001] This utility model relates to the field of photovoltaic technology, and more specifically, to a back contact battery. Background Technology

[0002] Back-contact solar cells are solar cells where the light-facing side of the cell has no electrodes, and both the positive and negative electrodes are located on the back side of the cell. This reduces electrode shading of the cell, increases the short-circuit current, and improves the cell's energy conversion efficiency. In this type of back-contact cell, to improve efficiency, the doped layer and dielectric layer on the back side consist of a contact passivation structure. This passivation structure often consists of a passivation dielectric layer and doped polycrystalline silicon / doped amorphous silicon / microcrystalline silicon. Existing back-contact cells are shown in the attached manual. Figure 1 As shown, a first dielectric layer 202 and a second dielectric layer 203 are respectively disposed on the substrate 201. A first conductivity type doped layer 204 and a second conductivity type doped layer 205 are respectively disposed on the first dielectric layer 202 and the second dielectric layer 203. The two doped layers 204 and 205 are insulated from each other by an isolation region 212 to reduce the reverse leakage current of the back contact cell, thereby reducing the risk of hot spots at the module end. During manufacturing, it is necessary to control the reverse leakage current of the cell to a low value. During the fabrication process, various defects exist, leading to the generation of local leakage points, including local contact between the two doped layers 204 and 205 with opposite conductivity types. This makes the back contact cell very prone to exceeding the control value of the reverse leakage current, resulting in low cell manufacturing efficiency. Therefore, how to improve the structure and manufacturing process of the back contact cell to reduce the risk of hot spots at the module end has become an important aspect affecting its reliability. Utility Model Content

[0003] This invention provides a back-contact battery that forms nanoscale, uniformly distributed leakage channels in a dielectric layer between two doped layers with opposite conductivity types. This allows for localized and uniform contact between the two doped layers, improving the battery's leakage capability and reducing the voltage across the battery when shaded. Consequently, it reduces the heat generation at the leakage point and lowers the risk of hot spots. Furthermore, by introducing leakage channels at predetermined locations, this invention protects against hot spots caused by defects, reducing the requirements for defect control and improving the manufacturing capability of solar cells while mitigating the risk of hot spots. Moreover, this invention can form uniformly distributed pores as leakage channels in the dielectric layer through the diffusion formation step of the doped layers, based on existing back-contact battery fabrication processes. The process is simple and does not require additional processes to form the leakage channels.

[0004] The back contact battery structure provided by this utility model is as follows.

[0005] A back-contact battery includes multiple back-contact battery cells, each back-contact battery cell comprising: a semiconductor substrate, a first conductivity type structure, a second conductivity type structure, and at least one leakage region.

[0006] The first conductivity type structure includes a first dielectric layer and a first doped layer, and the second conductivity type structure includes a second dielectric layer and a second doped layer;

[0007] There is at least one leakage region between the first conductivity type structure and the second conductivity type structure.

[0008] On a plane parallel to the semiconductor substrate, the first conductivity type structure and the second conductivity type structure are arranged at intervals along a first direction on one side of the backlight surface of the semiconductor substrate, and the first conductivity type structure and the second conductivity type structure extend along a second direction, with the first direction being perpendicular to the second direction.

[0009] The first dielectric layer and the second dielectric layer are formed on the back side of the semiconductor substrate. The first doped layer is located on the first dielectric layer, and the second doped layer is located on the second dielectric layer. The first doped layer and the second doped layer have opposite conductivity types.

[0010] The leakage region includes a third dielectric layer and a third doped layer formed along the thickness direction of the semiconductor substrate. The third doped layer has the same conductivity type as the second doped layer. Along the thickness direction of the semiconductor substrate, the third doped layer is adjacent to the side of the first doped layer through the third dielectric layer. The first dopant of the first doped layer or the second dopant of the second doped layer diffuses through the third dielectric layer, forming a carrier transport hole in a local area of ​​the third dielectric layer, thus locally connecting the second doped layer and the first doped layer.

[0011] Furthermore, the pores are nanoscale.

[0012] Furthermore, the holes are evenly distributed.

[0013] Furthermore, the first dielectric layer and the second dielectric layer are flush with each other or have a height difference along the thickness direction of the semiconductor substrate, and the height difference is less than or equal to 4 μm.

[0014] Furthermore, the first dielectric layer and the second dielectric layer are flush along the thickness direction of the semiconductor substrate;

[0015] The first conductivity type structure further includes a first doped region, wherein the first dopant of the first doped layer penetrates the first dielectric layer to form a first doped region inside the semiconductor substrate;

[0016] The second conductivity type structure further includes a second doped region, wherein the second dopant of the second doped layer penetrates the second dielectric layer to form a second doped region inside the semiconductor substrate;

[0017] The leakage region also includes a third doped region, which is formed by the diffusion of a first dopant through the third dielectric layer within the third doped layer, or by the diffusion of a second dopant through the third dielectric layer within the first doped layer.

[0018] Furthermore, the first dielectric layer and the second dielectric layer have a height difference along the thickness direction of the semiconductor substrate.

[0019] The first conductivity type structure further includes a first doped region, wherein the first dopant of the first doped layer penetrates the first dielectric layer to form a first doped region inside the semiconductor substrate;

[0020] The second conductivity type structure further includes a second doped region, wherein the second dopant of the second doped layer penetrates the second dielectric layer to form a second doped region inside the semiconductor substrate;

[0021] The leakage region further includes a third doped region and a fourth doped region. The third doped region and the fourth doped region are formed in the third doped layer by the diffusion of the first dopant through the third dielectric layer, or the third doped region and the fourth doped region are formed in the first doped layer and the first doped region by the diffusion of the second dopant through the third dielectric layer.

[0022] Furthermore, in the leakage region, the first dopant diffuses through the third dielectric layer, and the contact resistance between the third doped region and the first doped layer is 0.01-100 mol / cm². 2 The contact resistance between the fourth doped region and the first doped layer is 0.01-100 mol / cm². 2 ;

[0023] Alternatively, the second dopant diffuses through the third dielectric layer, and the contact resistance between the third doped region and the third doped layer is 0.01-100 mol / cm². 2 The contact resistance between the fourth doped region and the third doped layer is 0.01-100 mol / cm². 2 .

[0024] Furthermore, the third doped region is formed within the third doped layer by the diffusion of the first dopant through the third dielectric layer. The highest doping concentration of the third doped region is less than the doping concentration of the first doped layer, and the lowest doping concentration is equal to the concentration of the third doped layer.

[0025] Alternatively, the third doped region may be formed within the first doped layer by the diffusion of the second dopant through the third dielectric layer, wherein the highest doping concentration of the third doped region is less than the doping concentration of the third doped layer, and the lowest doping concentration is equal to the doping concentration of the first doped layer.

[0026] Furthermore, the third and fourth doped regions are formed within the third doped layer by the diffusion of the first dopant through the third dielectric layer. The highest doping concentration of the third and fourth doped regions is less than the doping concentration of the first doped layer, and the lowest doping concentration of the third and fourth doped regions is equal to the concentration of the third doped layer.

[0027] Alternatively, the third and fourth doped regions may be formed by the diffusion of the second dopant through the third dielectric layer within the first doped layer and the first doped region, respectively. The highest doping concentration of the third and fourth doped regions is less than the doping concentration of the third doped layer, the lowest doping concentration of the third doped region is equal to the concentration of the first doped layer, and the lowest doping concentration of the fourth doped region is equal to the doping concentration at the same depth within the first doped region.

[0028] Furthermore, the third doped layer is the same as the second doped layer and is integrally formed in the same process, and the doping concentration of the third doped layer is equal to the doping concentration of the second doped layer.

[0029] Furthermore, the doping concentration of the first doped region, the second doped region, the third doped region, and the fourth doped region gradually decreases in the semiconductor substrate along the direction away from the back surface of the substrate.

[0030] Furthermore, the highest doping concentration of the higher concentration region in the first and second doped regions is 1E20-1E21 atm / cm³. 3 The highest doping concentration of the one with the lower concentration is 1E19-1E20 atm / cm³. 3 .

[0031] Furthermore, along the thickness direction of the semiconductor substrate, the depth of the first doped region is 0.01μm-0.6μm, and the depth of the second doped region is 0.01μm-0.6μm.

[0032] Furthermore, along the first direction, the depths of the third doped region and the fourth doped region are both 0.001 μm to 0.3 μm.

[0033] Furthermore, the thickness of the first dielectric layer is 1.0 nm-2.5 nm, and the thickness of the second dielectric layer is 1.0 nm-2.5 nm.

[0034] Furthermore, the leakage region also includes: a first sub-doped layer and a first sub-dielectric layer.

[0035] The first sub-dielectric layer is located on the semiconductor substrate. Along the first direction, one side of the first sub-dielectric layer is connected to the third dielectric layer, and the other side is connected to the second dielectric layer.

[0036] The first sub-doped layer is located on the first sub-dielectric layer. Along the first direction, one side is connected to the third doped layer and the other side is connected to the second doped layer. The first sub-doped layer has the same conductivity type as the third doped layer and the second doped layer.

[0037] Furthermore, the first sub-doped layer, the third doped layer, and the second doped layer are integrally formed in the same process, and the first sub-dielectric layer, the second dielectric layer, and the third dielectric layer are integrally formed in the same process.

[0038] Furthermore, the leakage region includes: a second sub-doped layer and a second sub-dielectric layer.

[0039] The second sub-dielectric layer is located on the first doped layer, and in the first direction, one side of the second sub-dielectric layer is connected to the third dielectric layer.

[0040] The second sub-doped layer is located on the second sub-dielectric layer. In the first direction, one side of the second sub-doped layer is connected to the third doped layer. The second sub-doped layer and the third doped layer have the same conductivity type.

[0041] Furthermore, the second sub-doped layer, the third doped layer, and the second doped layer are integrally formed in the same process.

[0042] Furthermore, the thickness of the second sub-dielectric layer is 5nm-100nm.

[0043] Furthermore, in each of the back contact battery cells, the first conductive type structure and the second conductive type structure are strip-shaped regions extending along the second direction, and the first conductive type structure and the conductive type structure are parallel and spaced apart.

[0044] Furthermore, in each of the back contact battery cells, at least one insulating region is included between the first conductive type structure and the second conductive type structure.

[0045] Furthermore, in each back-contact battery cell, along the first direction, the width of the insulating region is D1, the width of the first doped layer is D2, and the width of the second doped layer is D3, where 20μm≤D1≤500μm, 100μm≤D2≤800μm, and 100μm≤D3≤800μm.

[0046] Furthermore, along the first direction, the width of the second sub-doped layer on the first doped layer is X1, X1 < (1 / 2)D2, and along the second direction, the length of the second sub-doped layer on the first doped layer is W, 5μm ≤ W ≤ 600μm.

[0047] Furthermore, when the back contact battery is a whole back contact battery, the number of the third doped region and the fourth doped region of the back contact battery is N1, where 20≤N1≤8000; when the back contact battery is a 1 / N segment back contact battery, the number of the third doped region and the fourth doped region of the back contact battery is N2, where 30 / N≤N2≤8000 / N, and N is a positive integer greater than or equal to 2. Attached Figure Description

[0048] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments of this utility model will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a three-dimensional structural diagram of a back-contact battery in the prior art;

[0050] Figures 2(a) to 2(i) These are structural diagrams illustrating each step in the fabrication process of the back contact battery of this invention.

[0051] Figure 3 This is a three-dimensional view of the back contact battery unit of this utility model;

[0052] Figure 4 This is a top view of the back contact battery of this utility model;

[0053] Figure 5 This is a cross-sectional view of the back contact battery cell of Embodiment 1 of the present invention, including the leakage area.

[0054] Figure 6 This is a cross-sectional view of the back contact battery unit of Embodiment 2 of the present invention, including the leakage area;

[0055] Figure 7 This is a cross-sectional view of the back contact battery unit of Embodiment 3 of the present invention, including the leakage area.

[0056] Figure 8 This is a cross-sectional view of the back contact battery unit of Embodiment 4 of the present invention, including the leakage area.

[0057] Figure 9Electron micrographs of the pores formed in the third dielectric layer in embodiments 1-4 of this utility model.

[0058] In the figure, 101. Semiconductor substrate, 102. First dielectric layer, 103. Second dielectric layer, 1031. First sub-dielectric layer, 1032. Second sub-dielectric layer, 1033. Third dielectric layer, 104. First doped layer, 105. Second doped layer, 1051. First sub-doped layer, 1052. Second sub-doped layer, 1053. Third doped layer, 106. First doped region, 107. Second doped region, 109. Third doped region, 110. Hole, 111. Fourth doped region, 112. Insulating region, 113. Leakage region, 114. Removal region, 201. Semiconductor substrate, 202. First dielectric layer, 203. Second dielectric layer, 204. First doped layer, 205. Second doped layer, 212. Isolation region. Detailed Implementation

[0059] The technical solutions of the present invention will now be described with reference to the accompanying drawings in the embodiments of the present invention.

[0060] The back contact battery provided by this invention can be prepared by the following process.

[0061] Step (1): A first dielectric layer 102 is formed on the backlight side of the semiconductor substrate 101;

[0062] Step (2), as shown in Figure 2(a), a first intrinsic polysilicon layer is grown on the first dielectric layer 102, and a first dopant is diffused into the first intrinsic polysilicon layer to form a first doped layer 104. The dopant partially penetrates the first dielectric layer 102 along the thickness direction of the semiconductor substrate 101, forming a hole 110 in the first dielectric layer 102 for carrier transport, and the dopant diffuses into the substrate 101 to form a first doped region 106.

[0063] Step (3), as shown in Figure 2(b), forms a second sub-dielectric layer 1032 on the first doped layer 104;

[0064] Step (4), as shown in Figure 2(c), remove a portion of the formed second sub-dielectric layer 1032, first doped layer 104, first dielectric layer 102 and first doped region 106 on the backlight side of the semiconductor substrate 101, exposing the surface of the silicon substrate 101 after the removal of part of the first doped region 106.

[0065] In step (5), as shown in Figure 2(d), a first sub-dielectric layer 1031 and a second dielectric layer 103 are grown on the surface of the exposed silicon substrate 101. A third dielectric layer 1033 is grown along the thickness direction of the semiconductor substrate 101 on the sides of the remaining first doped region 106, first dielectric layer 102, first doped layer 104, and second sub-dielectric layer 1032. The first sub-dielectric layer 1031, the second dielectric layer 103, and the third dielectric layer 1033 are integrally formed in this step. There is a height difference between the first sub-dielectric layer 1031, the second dielectric layer 103, and the first dielectric layer 102.

[0066] Step (6), as shown in FIG2(e), a second intrinsic polysilicon layer is grown on the upper surface of the first sub-dielectric layer 1031 and the second dielectric layer 103, the side surface of the third dielectric layer 1033, and the upper surface of the second sub-dielectric layer 1032. A portion of the second intrinsic polysilicon layer is adjacent to the surface of the semiconductor substrate 101 through the first sub-dielectric layer 1031 and the second dielectric layer 103. A portion of the second intrinsic polysilicon layer is adjacent to the side surface of the remaining first doped region 106, the first dielectric layer 102, the first doped layer 104, and the second sub-dielectric layer 1032 through the third dielectric layer 1033. A portion of the second intrinsic polysilicon layer is adjacent to the first doped layer 104 through the second sub-dielectric layer 1032.

[0067] Step (7) involves diffusing the second dopant into the second intrinsic polysilicon layer, including: forming a first sub-doped layer 1051 by doping the second intrinsic polysilicon portion adjacent to the surface of the semiconductor substrate through the first sub-dielectric layer 1031; forming a second doped layer 105 by doping the second intrinsic polysilicon portion adjacent to the surface of the semiconductor substrate through the second dielectric layer 103; forming a third doped layer 1053 by doping the second intrinsic polysilicon portion adjacent to the side of the remaining first doped region 106, first dielectric layer 102, first doped layer 104, and second sub-dielectric layer 1032 through the third dielectric layer 1033; and forming a second sub-doped layer 1052 by doping the second intrinsic polysilicon portion adjacent to the first doped layer 104 through the second sub-dielectric layer 1032.

[0068] The second dopant also partially penetrates the first sub-dielectric layer 1031 and the second dielectric layer 103 along the thickness direction of the substrate 101, forming carrier transport holes 110 in the local area of ​​the first sub-dielectric layer 1031 and the second dielectric layer 103, and the second dopant diffuses into the substrate 101 to form a second doped region 107.

[0069] If the first dopant is a P-type dopant and the second dopant is an N-type dopant, in step (7), while the second dopant diffuses to form the second doped layer 105 and the second doped region 107, the second dopant also partially penetrates the third dielectric layer 1033 and diffuses into the first doped layer 104 and the first doped region 106, forming a carrier transport hole 110 in the local part of the third dielectric layer 1033, forming the third doped region 109 in the first doped layer 104, and forming the fourth doped region 111 in the first doped region 106, as shown in Figure 2(f).

[0070] If the first dopant is an N-type dopant and the second dopant is a P-type dopant, in step (7), while the second dopant diffuses to form the second doped layer 105 and the second doped region 107, the first dopant partially penetrates the third dielectric layer 1033 and diffuses into the third doped layer 1053, forming a carrier transport hole 110 in the local part of the third dielectric layer 1033, and forming the third doped region 109 and the fourth doped region 111 in the third doped layer 1053, as shown in Figure 2(g).

[0071] Step (8) is illustrated using Figure 2(f) as an example. On the plane of the parallel semiconductor substrate 101, a portion of the second sub-dielectric layer 1032 located above the first doped layer 104 and the second sub-doped layer 1052 located on the second sub-dielectric layer 1032 are removed, as shown in Figure 2(h).

[0072] Step (9): On the plane of the parallel semiconductor substrate 101, the first doped layer 104 and the second doped layer 105 are arranged at intervals along the first direction and extend along the second direction, which is perpendicular to the first direction, as shown below. Figure 3 As shown in Figure 2(i), along the second direction, the following first structure, second structure, and third structure are removed at intervals, and the first structure, second structure, and third structure constitute the removed region 114 as shown in Figure 2(i):

[0073] (a) Interval removal of the first structure: Interval removal of a portion of the second sub-dielectric layer 1032 and a portion of the second sub-doped layer 1052 located above the first doped layer 104;

[0074] (b) Spaced removal of the second structure: spaced removal of a portion of the third doped region 109, a portion of the fourth doped region 111, a portion of the third dielectric 1033, a portion of the third doped layer 1053, a portion of the first sub-doped layer 1051, and a portion of the first sub-dielectric layer 1031;

[0075] (c) Interval removal of the third structure: Interval removal of the third structure located below the second structure until the surface of the semiconductor substrate is exposed;

[0076] After the spacer removal region 114, at least one or more spaced exposed semiconductor substrate surface regions are formed, which are the insulating regions 112, and a leakage region 113 is formed between two adjacent insulating regions.

[0077] Since the third doped region 109 and the fourth doped region 111 formed in step (7) can cause the carriers generated during battery operation to recombine, reducing the battery operating efficiency, in step (9), by retaining a small number of leakage regions 113 along the second direction and removing regions 114 in segments to form spaced insulating regions 112, the efficiency loss caused by recombination can be reduced, and sufficient leakage regions 113 can be retained to reduce the risk of hot spots.

[0078] Preferably, in steps (1) and (5), the first dielectric layer 102 and the second dielectric layer 103 are formed by thermal growth at a temperature of 550℃-650℃ and a thickness of 1.0nm-2.5nm.

[0079] Preferably, in steps (2) and (6), the first intrinsic polysilicon layer and the second intrinsic polysilicon layer are prepared by LPCVD process at a temperature of 550℃-650℃, respectively. The thickness of the first intrinsic polysilicon layer is 20nm-400nm, and the thickness of the second intrinsic polysilicon layer is 20nm-400nm.

[0080] Preferably, in steps (2) and (7), the P-type dopant is BCl3 or BBr3, which is diffused at a temperature of 850℃-1000℃. During the diffusion process, BCl3 or BBr3 decomposes, and the B element diffuses into the intrinsic polysilicon layer to form a doped layer and partially penetrates the dielectric layer below it, forming a hole 110 in the dielectric layer and forming a doped region in the substrate 101 below the dielectric layer. The N-type dopant is POCl3, which is diffused at a temperature of 800℃-1000℃. During the diffusion process, POCl3 decomposes, and the P element diffuses into the intrinsic polysilicon to form a doped layer and partially penetrates the dielectric layer below it, forming a hole 110 in the dielectric layer and forming a doped region in the substrate 101 below the dielectric layer. The P element can also pass through the third dielectric layer 1033 and form a hole 110 therein. At the same time, the P element diffuses to form the third doped region 109 and the fourth doped region 111.

[0081] Alternatively, in step (4), a portion of the already formed second sub-dielectric layer 1032, first doped layer 104, and first dielectric layer 102 can be removed on the backlight side of the semiconductor substrate 101. In step (5), the first sub-dielectric layer 1031 and second dielectric layer 103 can be grown at a position flush with the first dielectric layer 102, and the third dielectric layer 1033 can be grown along the thickness direction of the substrate 101 on the side of the first dielectric layer 102, first doped layer 104, and second sub-dielectric layer 1032, and then the subsequent steps (5)-(9) can continue. Since the first dielectric layer 102 and the first sub-dielectric layer 1031 and second dielectric layer 103 are flush in step (4), the third doped region 109 is only formed in the first or third doped layer in step (7).

[0082] The back contact battery manufacturing process provided by this utility model has the following advantages:

[0083] (1) This invention forms a spaced leakage region between the first doped layer 104 and the second doped layer 105. The leakage region is formed by forming a dielectric layer 1033 between two adjacent first doped layers 104 and second doped layers 105 of different conductivity types. Nanoscale, uniformly distributed holes 110 for carriers to pass through are formed in the dielectric layer 1033, i.e., leakage channels. Compared with the randomly distributed leakage region formed by the inability to achieve complete insulation between the two doped layers in the prior art, the leakage region is less and unevenly distributed. The spaced leakage region formed by this invention can improve the leakage capability of the battery, reduce the reverse bias voltage at both ends of the battery when it is shaded, thereby reducing the heat generation power when shaded, and thus reducing the risk of hot spots in the battery. At the same time, it eliminates the control requirements for low leakage current in the prior art, improving the productivity of the battery.

[0084] (2) The hole 110 formed in the third dielectric layer 1033 between the two doped layers in this invention allows charge carriers to pass through directly. Compared with the use of direct tunneling to realize the leakage channel, the transmission resistance of charge carriers passing through the third dielectric layer 1033 is greatly reduced. Therefore, the leakage channel formed by the hole 110 has a significant conduction effect.

[0085] (3) This utility model can achieve precise control over the size of the hole 110, such as Figure 9The diagram shows two locations of textural discontinuity in the third dielectric layer 1033, forming nanoscale pores 110. The pores 110 formed in this invention are at the nanometer scale, thus reducing damage to the third dielectric layer 1033. Even after the formation of the pores 110, the third dielectric layer 1033 retains good passivation, avoiding a decrease in the efficiency of the back-contact battery. In contrast, chemically etching the third dielectric layer 1033 to form pores at the micrometer scale or larger not only fails to create uniformly distributed leakage channels and has an insignificant effect on reducing hot spots, but also severely damages the dielectric layer, leading to a significant decrease in its passivation effect and a reduction in battery efficiency.

[0086] (4) Based on the existing back contact battery manufacturing process, the present invention first forms a dielectric layer 1033 on the side of a doped layer. Then, during the process of forming another doped layer, the dopant diffuses through the dielectric layer 1033 between the two doped layers to form uniformly distributed holes 110 as leakage channels. The process is simple and does not require additional processes to form leakage channels.

[0087] The back contact batteries in Examples 1-4 were prepared using the back contact battery fabrication process described above.

[0088] Example 1

[0089] Example 1 provides a back contact battery, including multiple back contact battery cells arranged along a first direction, such as... Figure 4 As shown.

[0090] Each back-contact battery cell, such as Figure 3 As shown, the system includes a semiconductor substrate 101, a first conductivity type structure, a second conductivity type structure, and at least one leakage region 113. The first conductivity type structure includes a first dielectric layer 102 and a first doped layer 104, and the second conductivity type structure includes a second dielectric layer 103 and a second doped layer 105. On a plane parallel to the semiconductor substrate 101, the first conductivity type structure and the second conductivity type structure are arranged at intervals along a first direction on one side of the backlight surface of the semiconductor substrate 101, and extend along a second direction, with the first direction perpendicular to the second direction. Figure 4 As shown, at least one leakage region 113 is included between the first conductivity type structure and the second conductivity type structure.

[0091] Figure 5 This is a cross-sectional view of each back-contact battery cell in this embodiment, including a leakage region 113.

[0092] In this configuration, a first doped layer 104 and a second doped layer 105 are arranged at intervals on the back surface of the semiconductor substrate, and the first doped layer 104 and the second doped layer 105 have opposite conductivity types. The first doped layer 104 is located on the first dielectric layer 102, and the second doped layer 105 is located on the second dielectric layer 103, as shown below. Figure 5 As shown, there is a height difference h between the surfaces of the two dielectric layers 102 and 103. <h≤4μm。

[0093] The leakage region 113 includes a third dielectric layer 1033 and a third doped layer 1053 formed along the thickness direction of the semiconductor substrate. The third doped layer 1053 has the same conductivity type as the second doped layer 105. Along the thickness direction of the semiconductor substrate 101, the third doped layer 1053 is adjacent to the side of the first doped layer 104 through the third dielectric layer 1033. Additionally, the leakage region 113 may also include a first sub-dielectric layer 1031 and a first sub-doped layer 1051, as well as a second sub-dielectric layer 1032 and a second sub-doped layer 1052. The first sub-dielectric layer 1031, the third dielectric layer 1033, and the second dielectric layer 103 are integrally formed in the same step, and the first sub-doped layer 1051, the second sub-doped layer 1052, the third doped layer 1053, and the second doped layer 105 are integrally formed in the same step.

[0094] In this embodiment, the second doped layer 105 is an N-type doped layer and the first doped layer 104 is a P-type doped layer. In the steps of forming the second doped layer 105, the first sub-doped layer 1051, the second sub-doped layer 1052, and the third doped layer 1053, the following are also included: (1) the N-type dopant diffuses through the third dielectric layer 1033 to form nano-sized, uniformly distributed carrier transport holes 110 in the third dielectric layer 1033, which locally connects the second doped layer 105 and the first doped layer 104; and the N-type dopant penetrates the third dielectric layer 1033 to form a third doped region 109 in the first doped layer 104 and a fourth doped region 111 in the first doped region 106; (2) the N-type dopant diffuses through the second dielectric layer 103 to form holes 110 therein, and a second doped region 107 is formed below the second dielectric layer 103 in the substrate.

[0095] The first doped region 106 and the second doped region 107 are formed by P-type dopant and N-type dopant penetrating the first dielectric layer 102 and the second dielectric layer 103, respectively. Therefore, the doping concentration of the first doped region 106 and the second doped region 107 gradually decreases in the direction away from the back surface of the semiconductor substrate 101. The third doped region 109 and the fourth doped region 111 are formed by N-type dopant penetrating the third dielectric layer 1033 in the first doped layer 104 and the first doped region 106, respectively. Therefore, the highest doping concentration of the third doped region 109 is less than the doping concentration of the second doped layer 105, and the lowest doping concentration is equal to the doping concentration of the first doped layer 104. The highest doping concentration of the fourth doped region 111 is less than the doping concentration of the second doped layer 105, and the lowest doping concentration is equal to the doping concentration of the first doped region 106 at the same depth as the fourth doped region 111.

[0096] Specifically, the first doped layer 104 is a boron-doped polycrystalline silicon layer with a thickness of 300 nm and a doping concentration of 6.5E19 atm / cm. 3 .

[0097] The second doped layer 105 is a phosphorus-doped polycrystalline silicon layer with a thickness of 200 nm and a doping concentration of 7E20 atm / cm. 3 .

[0098] The depth of the first doped region 106 is 0.4 μm, and the highest doping concentration is 6.5E19 atm / cm. 3 .

[0099] The second doped region 107 has a depth of 0.35 μm and a maximum doping concentration of 7E20 atm / cm. 3 .

[0100] The third doped region 109 and the fourth doped region 111 are phosphorus-doped polycrystalline silicon layers. The higher the doping concentration and the deeper the doping depth, the better the leakage current effect between the first and second doped layers 104 and 105. Therefore, in this embodiment, along the first direction, the depth of the third doped region 109 and the fourth doped region 111 is 0.06 μm, and the maximum doping concentration is 6.35E20 atm / cm. 3 .

[0101] In this example, the contact resistance between the formed third doped region 109, the fourth doped region 111, and the third doped layer 1053 is 1.7 mol / cm². 2The lower the contact resistance, the stronger the conduction of charge carriers between the first doped layer 104 and the second doped layer 105, and the higher the leakage current capability. Therefore, in addition to controlling the concentration of the dopant and the diffusion temperature, the thickness of the third dielectric layer 1033 between the first doped layer 104 and the second doped layer 105 is controlled. This reduces the contact resistance by decreasing the thickness of the dielectric layer and increasing the density of the pores 110 therein.

[0102] Specifically, the thickness of the second dielectric layer 103, the first sub-dielectric layer 1031, and the third dielectric layer 1033 is 1.6 nm. Additionally, the thickness of the first dielectric layer 102 is 1.9 nm. In the fabrication process, to protect the underlying first doped layer 104, the thickness of the second sub-dielectric layer 1032 is relatively large, often set to the tens to hundreds of nanometers, much greater than the thickness of the first dielectric layer 102 and the second dielectric layer 103. In this embodiment, the thickness of the second sub-dielectric layer 1032 is 28 nm.

[0103] like Figure 4 As shown, the back contact battery of this embodiment includes multiple back contact battery cells arranged along a first direction. In each back contact battery cell, one or more spaced insulating regions 112 are included between the first conductivity type structure and the second conductivity type structure. In the first direction, the width D2 of the first doped layer 104 is 400 μm, the width D3 of the second doped layer 105 is 400 μm, and the width X1 of the second sub-doped layer 1052 in the leakage region 113 on the first doped layer 104 is 150 μm. Along the second direction, the length W of the second sub-doped layer 1052 on the first doped layer 104 is 500 μm.

[0104] In this embodiment, the number of the third doped region 109 and the fourth doped region 111 are 300 each.

[0105] Example 2

[0106] Example 2 provides a back contact battery, such as Figure 6 The diagram shows a cross-sectional view of the back contact battery cell in Embodiment 2, including the leakage region 113. Unlike Embodiment 1, the back contact battery cell in Embodiment 2 first grows an N-type doped layer as the first doped layer 104 and then grows a P-type doped layer as the second doped layer 105. Therefore, the N-type dopant penetrates the third dielectric layer 1033 and forms the third doped region 109 and the fourth doped region 111 in the third doped layer 1053.

[0107] The thickness of the first dielectric layer 102 is 1.8 nm, and the thickness of the second dielectric layer 103 is 1.4 nm.

[0108] The first doped layer 104 is a phosphorus-doped polycrystalline silicon layer with a thickness of 220 nm and a doping concentration of 6E20 atm / cm². 3 .

[0109] The first doped region, 106, has a depth of 0.4 μm and a maximum doping concentration of 6E20 atm / cm². 3 .

[0110] The second doped layer 105 is a boron-doped polycrystalline silicon layer with a thickness of 250 nm and a doping concentration of 7E19 atm / cm². 3 .

[0111] The second doped region, 107, has a depth of 0.35 μm and a maximum doping concentration of 7E19 atm / cm². 3 .

[0112] The third doped region 109 and the fourth doped region 111 are phosphorus-doped polycrystalline silicon layers with a depth of 0.08 μm and a maximum doping concentration of 5.3E20 atm / cm². 3 It is located within the third doped layer 1053.

[0113] The thickness of the second sub-dielectric layer 1032 is 30 nm.

[0114] The contact resistance between the third doped region 109 and the first doped layer 104 is 1.5 mol / cm². 2 .

[0115] The contact resistance between the fourth doped region 111 and the first doped region 106 is 1.5 mol / cm². 2 .

[0116] like Figure 4 As shown, along the first direction, the width D2 of the first doped layer is 450 μm, the width D3 of the second doped layer is 400 μm, and the width X1 of the second sub-doped layer 1052 on the first doped layer 104 is 160 μm. Along the second direction, the length W of the second sub-doped layer 1052 on the first doped layer 104 is 450 μm.

[0117] The number of third doped regions 109 is 200, and the number of fourth doped regions 111 is 200.

[0118] Example 3

[0119] Example 3 provides a back contact battery, such as Figure 7The diagram shows a cross-sectional view of the back contact battery cell in Embodiment 3, including the leakage region 113. Unlike Embodiments 1 and 2, in step (4), a portion of the already formed second sub-dielectric layer 1032, first doped layer 104, and first dielectric layer 102 are removed on the back side of the semiconductor substrate 101. In step (5), a second dielectric layer 103 and a first sub-dielectric layer 1031 are grown at a position flush with the first dielectric layer 102. The first doped layer 104 is a P-type doped layer, and the second doped layer 105 is an N-type doped layer. Therefore, in step (7), a third doped region 109 is formed only in the first doped layer 105.

[0120] The thickness of the first dielectric layer 102 is 1.7 nm, and the thickness of the second dielectric layer 103 is 1.5 nm.

[0121] The first doped layer 104 is a boron-doped polycrystalline silicon layer with a thickness of 250 nm and a doping concentration of 6E19 atm / cm². 3 .

[0122] The first doped region, 106, has a depth of 0.4 μm and a maximum doping concentration of 6E19 atm / cm². 3 .

[0123] The second doped layer 105 is a phosphorus-doped polycrystalline silicon layer with a thickness of 200 nm and a doping concentration of 5E20 atm / cm². 3 .

[0124] The second doped region, 107, has a depth of 0.35 μm and a maximum doping concentration of 5E20 atm / cm. 3 .

[0125] The third doped region 109 is a phosphorus-doped polycrystalline silicon layer with a depth of 0.1 μm and a maximum doping concentration of 4.4E20 atm / cm². 3 It is located within the first doped layer 104.

[0126] The contact resistance between the third doped region 109 and the third doped layer 1053 is 1 mol / cm². 2 .

[0127] like Figure 4 As shown, along the first direction, the width D2 of the first doped layer is 400 μm, the width D3 of the second doped layer is 350 μm, and the width X1 of the second sub-doped layer 1052 on the first doped layer 104 is 150 μm. Along the second direction, the length W of the second sub-doped layer 1052 on the first doped layer 104 is 400 μm.

[0128] The number of third doped regions 109 is 100.

[0129] Example 4

[0130] Example 4 provides a back contact battery, such as Figure 8 The diagram shows a cross-sectional view of the back contact battery cell in Embodiment 4, including the leakage region 113. Unlike Embodiments 1 and 2, in step (4), a portion of the already formed second sub-dielectric layer 1032, first doped layer 104, and first dielectric layer 102 are removed on the back surface side of the semiconductor substrate 101. In step (5), the second dielectric layer 103 and the first sub-dielectric layer 1031 are grown at a position flush with the first dielectric layer 102. The first doped layer 104 is an N-type doped layer, and the second doped layer 105 is a P-type doped layer. Therefore, in step (7), only the third doped region 109 is formed in the third doped layer 1053.

[0131] The thickness of the first dielectric layer 102 is 1.8 nm, and the thickness of the second dielectric layer 103 is 1.4 nm.

[0132] The first doped layer 104 is a phosphorus-doped polycrystalline silicon layer with a thickness of 220 nm and a doping concentration of 6E20 atm / cm². 3 .

[0133] The depth of the first doped region 106 is 0.4 μm, and the highest doping concentration is 6E20 atm / cm. 3 .

[0134] The second doped layer 105 is a boron-doped polycrystalline silicon layer with a thickness of 250 nm and a doping concentration of 7E19 atm / cm². 3 .

[0135] The second doped region 107 has a depth of 0.35 μm and a maximum doping concentration of 7E19 atm / cm. 3 .

[0136] The third doped region 109 is a phosphorus-doped polycrystalline silicon layer with a depth of 0.08 μm and a maximum doping concentration of 5.3E20 atm / cm². 3 It is located within the third doped layer 1053.

[0137] The thickness of the second sub-dielectric layer 1032 is 30 nm.

[0138] The contact resistance between the third doped region 109 and the first doped layer 104 is 1.5 mol / cm². 2 .

[0139] like Figure 4As shown, along the first direction, the width D2 of the first doped layer 104 is 450 μm, the width D3 of the second doped layer 105 is 400 μm, and the width X1 of the second sub-doped layer 1052 on the first doped layer 104 is 160 μm. Along the second direction, the length W of the second sub-doped layer 1052 on the first doped layer 104 is 350 μm.

[0140] The number of third doped regions 109 is 200.

[0141] The back contact battery structure provided in Embodiment 1 of this utility model is, according to... Figure 3 The number of leakage regions 113 retained between the first conductivity type structure and the second conductivity type structure varies. As in Test Examples 1-4, the number of leakage regions 113 gradually increases from Test Example 1 to Test Example 4. Figure 1 The existing back-contact battery was used as Comparative Example 1 for testing and comparison. The test results are shown in Table 1. Table 1 shows that in the Comparative Example, due to the limited and unevenly distributed leakage conduction structures randomly present between the two doped layers, the reverse saturation current is small, the maximum reverse voltage is too high, and the maximum hot spot temperature reaches 160℃, easily burning out the battery backsheet. In contrast, in Examples 1-4, multiple nano-sized, uniformly distributed leakage conduction structures were set between the first and second doped layers. Furthermore, as the number of leakage regions 113 increases, the reverse protection current increases, the maximum reverse voltage decreases, and the maximum hot spot temperature can decrease to 140℃ or even 100℃, significantly reducing the risk of hot spots.

[0142] Table 1. Test results of Experimental Examples 1-4 and Comparative Example 1

[0143] Comparative Example 1 0.2A 17V 160℃ / Experimental Example 1 5A 15V 140℃ -0.05％ Experimental Example 2 10A 12V 130℃ -0.08％ Experimental Example 3 20A 7V 120℃ -0.1％ Test Example 4 20A 4V 100℃ -0.12％

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A back contact cell comprising a plurality of back contact cell units, each back contact cell unit comprising: A semiconductor substrate, a first conductivity type structure, a second conductivity type structure, and at least one leakage region. The first conductivity type structure includes a first dielectric layer and a first doped layer, and the second conductivity type structure includes a second dielectric layer and a second doped layer; There is at least one leakage region between the first conductivity type structure and the second conductivity type structure. On a plane parallel to the semiconductor substrate, the first conductivity type structure and the second conductivity type structure are arranged at intervals along a first direction on one side of the backlight surface of the semiconductor substrate, and the first conductivity type structure and the second conductivity type structure extend along a second direction, with the first direction being perpendicular to the second direction. The first dielectric layer and the second dielectric layer are formed on the back side of the semiconductor substrate. The first doped layer is located on the first dielectric layer, and the second doped layer is located on the second dielectric layer. The first doped layer and the second doped layer have opposite conductivity types. The feature is that the leakage region includes: a third dielectric layer and a third doped layer formed along the thickness direction of the semiconductor substrate, wherein the third doped layer has the same conductivity type as the second doped layer, and along the thickness direction of the semiconductor substrate, the third doped layer is adjacent to the side of the first doped layer through the third dielectric layer, wherein the first dopant of the first doped layer or the second dopant of the second doped layer diffuses through the third dielectric layer, forming a hole for carrier transport in a local area of ​​the third dielectric layer, thereby locally connecting the second doped layer and the first doped layer.

2. A back contact cell according to claim 1, wherein, In the third dielectric layer, the pores are nanoscale.

3. A back contact cell according to claim 1, wherein, In the third dielectric layer, the pores are evenly distributed.

4. A back contact cell according to one of claims 1-3, wherein The first dielectric layer and the second dielectric layer are flush with each other or have a height difference along the thickness direction of the semiconductor substrate, and the height difference is less than or equal to 4 μm.

5. A back contact battery according to claim 4, characterized in that, The first dielectric layer and the second dielectric layer are flush along the thickness direction of the semiconductor substrate; The first conductivity type structure further includes a first doped region, wherein the first dopant of the first doped layer penetrates the first dielectric layer to form a first doped region inside the semiconductor substrate; The second conductivity type structure further includes a second doped region, wherein the second dopant of the second doped layer penetrates the second dielectric layer to form a second doped region inside the semiconductor substrate; The leakage region also includes a third doped region, which is formed by the diffusion of a first dopant through the third dielectric layer within the third doped layer, or by the diffusion of a second dopant through the third dielectric layer within the first doped layer.

6. A back contact battery according to claim 4, characterized in that, The first dielectric layer and the second dielectric layer have a height difference along the thickness direction of the semiconductor substrate. The first conductivity type structure further includes a first doped region, wherein the first dopant of the first doped layer penetrates the first dielectric layer to form a first doped region inside the semiconductor substrate; The second conductivity type structure further includes a second doped region, wherein the second dopant of the second doped layer penetrates the second dielectric layer to form a second doped region inside the semiconductor substrate; The leakage region further includes a third doped region and a fourth doped region. The third doped region and the fourth doped region are formed in the third doped layer by the diffusion of the first dopant through the third dielectric layer, or the third doped region and the fourth doped region are formed in the first doped layer and the first doped region by the diffusion of the second dopant through the third dielectric layer.

7. A back contact cell according to claim 5, wherein, In the leakage region, the first dopant diffuses through the third dielectric layer, and the contact resistance between the third doped region and the first doped layer is 0.01-100 mohm cm 2 ; or the second dopant diffuses through the third dielectric layer, the contact resistance between the third doped region and the third doped layer is 0.01-100 mohm cm 2 .

8. A back contact cell according to claim 6, wherein, In the leakage region, the first dopant diffuses through the third dielectric layer, and the contact resistance between the third doped region and the first doped layer is 0.01-100 mohmcm 2 , and the contact resistance between the fourth doped region and the first doped layer is 0.01-100 mohmcm 2 . Alternatively, the second dopant diffuses through the third dielectric layer, and the contact resistance between the third doped region and the third doped layer is 0.01-100 mol / cm². 2 The contact resistance between the fourth doped region and the third doped layer is 0.01-100 mol / cm². 2 .

9. A back contact battery according to claim 5, characterized in that, The third doped region is formed within the third doped layer by the diffusion of the first dopant through the third dielectric layer. The highest doping concentration of the third doped region is less than the doping concentration of the first doped layer, and the lowest doping concentration is equal to the concentration of the third doped layer. Alternatively, the third doped region may be formed within the first doped layer by the diffusion of the second dopant through the third dielectric layer, wherein the highest doping concentration of the third doped region is less than the doping concentration of the third doped layer, and the lowest doping concentration is equal to the doping concentration of the first doped layer.

10. A back contact battery according to claim 6, characterized in that, The third and fourth doped regions are formed within the third doped layer by the diffusion of the first dopant through the third dielectric layer. The highest doping concentration of the third and fourth doped regions is less than the doping concentration of the first doped layer, and the lowest doping concentration of the third and fourth doped regions is equal to the concentration of the third doped layer. Alternatively, the third and fourth doped regions may be formed by the diffusion of the second dopant through the third dielectric layer within the first doped layer and the first doped region, respectively. The highest doping concentration of the third and fourth doped regions is less than the doping concentration of the third doped layer, the lowest doping concentration of the third doped region is equal to the concentration of the first doped layer, and the lowest doping concentration of the fourth doped region is equal to the doping concentration at the same depth within the first doped region.

11. A back contact cell according to claim 9 or 10, wherein, The third doped layer is the same as the second doped layer and is integrally formed in the same process. The doping concentration of the third doped layer is equal to the doping concentration of the second doped layer.

12. A back contact cell according to claim 5, wherein, The doping concentration of the first doped region, the second doped region, and the third doped region gradually decreases in the semiconductor substrate along the direction away from the back surface of the substrate.

13. A back contact cell according to claim 6, wherein, The doping concentration of the first doped region, the second doped region, the third doped region, and the fourth doped region gradually decreases in the semiconductor substrate along the direction away from the back surface of the substrate.

14. A back contact cell according to claim 5 or 6, wherein, The highest doping concentration of the higher doping region among the first and second doping regions is 1E20-1E21 atm / cm³. 3 The highest doping concentration of the one with the lower concentration is 1E19-1E20 atm / cm³. 3 .

15. A back contact cell according to claim 5 or 6, wherein, Along the thickness direction of the semiconductor substrate, the depth of the first doped region is 0.01μm-0.6μm, and the depth of the second doped region is 0.01μm-0.6μm.

16. A back contact cell according to claim 5, wherein, Along the first direction, the depth of the third doped region is 0.001 μm-0.3 μm.

17. A back contact cell according to claim 6, wherein, Along the first direction, the depths of the third doped region and the fourth doped region are both 0.001 μm to 0.3 μm.

18. A back contact cell as claimed in any one of claims 1 to 3, wherein, The thickness of the first dielectric layer is 1.0 nm-2.5 nm, and the thickness of the second dielectric layer is 1.0 nm-2.5 nm.

19. A back contact cell as claimed in any one of claims 1 to 3, wherein, The leakage region further includes: a first sub-doped layer and a first sub-dielectric layer. The first sub-dielectric layer is located on the semiconductor substrate. Along the first direction, one side of the first sub-dielectric layer is connected to the third dielectric layer, and the other side is connected to the second dielectric layer. The first sub-doped layer is located on the first sub-dielectric layer. Along the first direction, one side is connected to the third doped layer and the other side is connected to the second doped layer. The first sub-doped layer has the same conductivity type as the third doped layer and the second doped layer.

20. A back contact cell according to claim 19, wherein, The first sub-doped layer, the third doped layer, and the second doped layer are integrally formed in the same process, and the first sub-dielectric layer, the second dielectric layer, and the third dielectric layer are integrally formed in the same process.

21. A back contact cell as claimed in any one of claims 1 to 3, wherein, The leakage region includes: a second sub-doped layer and a second sub-dielectric layer. The second sub-dielectric layer is located on the first doped layer, and in the first direction, one side of the second sub-dielectric layer is connected to the third dielectric layer. The second sub-doped layer is located on the second sub-dielectric layer. In the first direction, one side of the second sub-doped layer is connected to the third doped layer. The second sub-doped layer and the third doped layer have the same conductivity type.

22. A back contact cell according to claim 21, wherein, The second sub-doped layer, the third doped layer, and the second doped layer are integrally formed in the same process.

23. A back contact cell according to claim 21, wherein, The thickness of the second sub-dielectric layer is 5nm-100nm.

24. The back contact cell of claim 21, wherein, In each of the back contact battery cells, the first conductive type structure and the second conductive type structure are strip-shaped regions extending along the second direction, and the first conductive type structure and the conductive type structure are parallel and spaced apart.

25. A back contact cell according to claim 24, wherein, In each of the back contact battery cells, at least one insulating region is included between the first conductive type structure and the second conductive type structure.

26. A back contact cell according to claim 25, wherein, In each back-contact battery cell, along the first direction, the width of the insulating region is D1, the width of the first doped layer is D2, and the width of the second doped layer is D3, where 20μm≤D1≤500μm, 100μm≤D2≤800μm, and 100μm≤D3≤800μm.

27. A back contact cell according to claim 26, wherein, Along the first direction, the width of the second sub-doped layer on the first doped layer is X1, X1 < (1 / 2)D2, and along the second direction, the length of the second sub-doped layer on the first doped layer is W, 5μm ≤ W ≤ 600μm.

28. A back contact battery according to claim 5, characterized in that, When the back contact battery is a whole back contact battery, the number of third doped regions in the back contact battery is N1, 20≤N1≤8000; when the back contact battery is a 1 / N segment back contact battery, the number of third doped regions in the back contact battery is N2, 30 / N≤N2≤8000 / N, where N is a positive integer greater than or equal to 2.

29. A back contact battery according to claim 6, characterized in that, When the back contact battery is a whole back contact battery, the number of the third doped region and the fourth doped region of the back contact battery is N1, and 20≤N1≤8000; when the back contact battery is a 1 / N segment back contact battery, the number of the third doped region and the fourth doped region of the back contact battery is N2, and 30 / N≤N2≤8000 / N, where N is a positive integer greater than or equal to 2.

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