Display device

Abstract

This disclosure relates to a display device with improved image quality. The display device may include: a substrate; a light-emitting element above the substrate; a transistor connected to the light-emitting element; a first node connected to the gate electrode of the transistor; a second node connected to the source electrode of the transistor; and a capacitor connected between the first node and the second node, wherein the capacitor includes a first capacitor electrode connected to the first node and including a first sub-capacitor electrode, and a second capacitor electrode connected to the second node and including a second sub-capacitor electrode located in the same layer as the first sub-capacitor electrode, wherein one of the first sub-capacitor electrodes is located between adjacent second sub-capacitor electrodes. The display device has improved display quality.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0073165, filed on June 4, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device with improved image quality. Background Technology

[0003] A head-mounted display (HMD) is an image display device worn on a user's head in the form of glasses or a helmet, and focuses in front of the user's eyes at a distance close to their eyes. Head-mounted displays can enable virtual reality (VR) or augmented reality (AR).

[0004] Head-mounted displays use multiple lenses to magnify and display images from small display devices. Therefore, display devices used in head-mounted displays need to provide high-resolution images, for example, images with a resolution of approximately 3000 pixels per inch (PPI) or higher. For this purpose, silicon-based organic light-emitting diodes (OLEDoS), as small organic light-emitting display devices with relatively high resolution, have been used in head-mounted displays. OLEDoS is a device that displays images by placing organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (CMOS) is disposed. Utility Model Content

[0005] This disclosure provides a display device with improved image quality.

[0006] According to an aspect of this disclosure, a display device is provided, the display device comprising: a substrate; a light-emitting element above the substrate; a transistor connected to the light-emitting element; a first node connected to the gate electrode of the transistor; a second node connected to the source electrode of the transistor; and a capacitor connected between the first node and the second node, wherein the capacitor includes a first capacitor electrode connected to the first node and including a first sub-capacitor electrode and a second capacitor electrode connected to the second node and including a second sub-capacitor electrode located in the same layer as the first sub-capacitor electrode, wherein one of the first sub-capacitor electrodes is located between adjacent second sub-capacitor electrodes.

[0007] The first sub-capacitor electrode may include a first outermost sub-capacitor electrode and a second outermost sub-capacitor electrode located on the corresponding side of the first sub-capacitor electrode, wherein the second sub-capacitor electrode includes a third outermost sub-capacitor electrode and a fourth outermost sub-capacitor electrode located on the corresponding side of the second sub-capacitor electrode.

[0008] The first sub-capacitor electrode can be located between the third outermost sub-capacitor electrode and the fourth outermost sub-capacitor electrode.

[0009] The first outermost subcapacitor electrode can be located between the third outermost subcapacitor electrode and the fourth outermost subcapacitor electrode.

[0010] The second outermost subcapacitor electrode can be located between the third outermost subcapacitor electrode and the fourth outermost subcapacitor electrode.

[0011] The first outermost subcapacitor electrode and the third outermost subcapacitor electrode can be adjacent to each other.

[0012] The second outermost subcapacitor electrode and the fourth outermost subcapacitor electrode can be adjacent to each other.

[0013] The display device may also include a first data line adjacent to the third outermost subcapacitor electrode.

[0014] The third outermost sub-capacitor electrode can be located between the first data line and the first outermost sub-capacitor electrode.

[0015] The display device may also include a second data line adjacent to the fourth outermost subcapacitor electrode.

[0016] The third outermost sub-capacitor electrode can be located between the second outermost sub-capacitor electrode and the second data line.

[0017] The first capacitor electrode may further include: a third sub-capacitor electrode, above the first sub-capacitor electrode and connected to the first sub-capacitor electrode; and a fourth sub-capacitor electrode, below the first sub-capacitor electrode and connected to the first sub-capacitor electrode.

[0018] The first data line may include: a first sub-data line located on the same layer as the first sub-capacitor electrode; and a second sub-data line located on the same layer as the third sub-capacitor electrode and connected to the first sub-data line.

[0019] The second capacitor electrode may further include: a fifth sub-capacitor electrode, above the second sub-capacitor electrode and connected to the second sub-capacitor electrode; and a sixth sub-capacitor electrode, below the second sub-capacitor electrode and connected to the second sub-capacitor electrode.

[0020] The third sub-capacitor electrode and the fifth sub-capacitor electrode can be located in the same layer.

[0021] The fourth sub-capacitor electrode and the sixth sub-capacitor electrode can be located in the same layer.

[0022] The first capacitor electrode may further include a seventh sub-capacitor electrode, located above the third sub-capacitor electrode and connected to the third sub-capacitor electrode.

[0023] The first data line may include: a first sub-data line located on the same layer as the first sub-capacitor electrode; and a second sub-data line located on the same layer as the third sub-capacitor electrode and connected to the first sub-data line.

[0024] In the plan view, one end of the connection portion where the first sub-capacitor electrodes are connected to each other can be above the same straight line as one end of the outermost sub-capacitor electrode in the second sub-capacitor electrodes.

[0025] The extension direction of the first sub-capacitor electrode can be parallel to the extension direction of the second sub-capacitor electrode.

[0026] According to an aspect of this disclosure, an electronic device including a display apparatus is provided, the display apparatus comprising: a substrate; a light-emitting element above the substrate; a transistor connected to the light-emitting element; a first node connected to the gate electrode of the transistor; a second node connected to the source electrode of the transistor; and a capacitor connected between the first node and the second node, wherein the capacitor includes a first capacitor electrode connected to the first node and including a first sub-capacitor electrode and a second capacitor electrode connected to the second node and including a second sub-capacitor electrode located in the same layer as the first sub-capacitor electrode, wherein one of the first sub-capacitor electrodes is located between adjacent second sub-capacitor electrodes in the second sub-capacitor electrode.

[0027] Electronic devices may include smartphones, televisions, monitors, tablets, electric vehicles, mobile phones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, ultra-mobile PCs (UMPCs), laptops, billboards, Internet of Things (IoT) devices, smartwatches, watch phones, or head-mounted displays (HMDs).

[0028] Image quality can be improved by using a display device according to one or more embodiments.

[0029] The effects described herein are not limited to those described above, and other aspects not described herein will become more apparent to those skilled in the art from the following description. Attached Figure Description

[0030] The above and other aspects of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0031] Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments;

[0032] Figure 2 This is a block diagram illustrating a display device according to one or more embodiments;

[0033] Figure 3 It is an equivalent circuit diagram of the first pixel according to one or more embodiments;

[0034] Figure 4 This is a layout diagram illustrating examples of display panels according to one or more embodiments;

[0035] Figure 5 and Figure 6 It is shown Figure 4 A layout diagram of an embodiment of the display area;

[0036] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel, taken by line I1-I1';

[0037] Figure 8 It is a plan view of the first first sub-capacitor electrode of the first capacitor electrode, the second first sub-capacitor electrode of the second capacitor electrode, the third first sub-capacitor electrode of the third capacitor electrode, the fourth first sub-capacitor electrode of the fourth capacitor electrode, and the third connecting electrode.

[0038] Figure 9 It is a plan view of the first and second sub-capacitor electrodes of the first capacitor electrode, the second and second sub-capacitor electrodes of the second capacitor electrode, the third and second sub-capacitor electrodes of the third capacitor electrode, the fourth and second sub-capacitor electrodes of the fourth capacitor electrode, and the first sub-data line.

[0039] Figure 10 It is a plan view of the first and third sub-capacitor electrodes of the first capacitor electrode, the second and third sub-capacitor electrodes of the second capacitor electrode, the third and third sub-capacitor electrodes of the third capacitor electrode, the fourth and third sub-capacitor electrodes of the fourth capacitor electrode, and the second sub-data line.

[0040] Figure 11 It is a plan view of the first fourth sub-capacitor electrode of the first capacitor electrode, the second fourth sub-capacitor electrode of the second capacitor electrode, the third fourth sub-capacitor electrode of the third capacitor electrode, and the fourth fourth sub-capacitor electrode of the fourth capacitor electrode.

[0041] Figure 12 It shows along Figures 8 to 11 A cross-sectional view of an example display panel, taken by line I2-I2';

[0042] Figure 13 yes Figure 9 A magnified view of region A;

[0043] Figure 14 It is a view used to describe the arrangement of sub-capacitor electrodes between multiple data lines that are adjacent to each other;

[0044] Figure 15 It is a cross-sectional view of a display panel according to one or more other embodiments;

[0045] Figure 16 It is a cross-sectional view of a display panel according to another or one other embodiment;

[0046] Figure 17 It is a cross-sectional view of a display panel according to another or one other embodiment;

[0047] Figure 18 This is a view illustrating one or more other embodiments of the sub-capacitor electrodes in a display device according to one or more embodiments;

[0048] Figure 19 This is a perspective view showing a head-mounted display device according to one or more embodiments;

[0049] Figure 20 It is shown Figure 19 An exploded perspective view of an example of a head-mounted display device; and

[0050] Figure 21 This is a perspective view illustrating a head-mounted display according to one or more other embodiments. Detailed Implementation

[0051] Some aspects of this disclosure and methods for implementing some embodiments of this disclosure can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey all aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or that are not essential for a person of ordinary skill in the art to fully understand all aspects of this disclosure, may be omitted. Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description; therefore, their repeated description may be omitted.

[0052] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown herein. The terms "can," "may," or "may not" are used in the described embodiments to correspond to one or more embodiments of this disclosure.

[0053] It will be appreciated by those skilled in the art that, in view of the whole of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or in part or in whole with each other, and may be technically interlocked and operated in a variety of suitable ways unless otherwise stated or implied, and each embodiment may also be implemented independently or in combination with each other in any suitable way.

[0054] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, the disclosure is not limited thereto because the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of description. Additionally, crosshairs and / or shading are typically used in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, scale, commonalities between the elements shown, and / or any other characteristics, properties, or characteristics of the elements.

[0055] Various embodiments are described herein with reference to cross-sectional views that serve as schematic diagrams of examples and / or intermediate structures. Thus, variations in the shapes shown in the illustrations due to, for example, manufacturing techniques and / or tolerances will be expected. Furthermore, for the purpose of describing embodiments according to the concept of this disclosure, the descriptions of specific structures or functions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes shown for elements, layers, or regions, but will include deviations in shape due to, for example, manufacturing processes.

[0056] For example, an injection region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of injection concentration, rather than a binary variation from the injection region to the non-injection region. Similarly, a buried region formed by injection can induce some injection in the region between the buried region and the surface through which the injection occurs.

[0057] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “above,” “higher,” “upper side,” “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element or feature to another, as shown in the accompanying drawings. It will be understood that spatial relative terms are intended to include not only the orientations depicted in the drawings but also different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged above or below the second part based on the direction of gravity, and is not limited to the upper side of the second part.

[0058] Furthermore, the phrase "in a plan view" refers to the view of the target portion from above, and the phrase "in a schematic sectional view" refers to the view of a schematic section taken by vertically cutting the target portion from the side. The terms "overlapping with" or "overlapping" mean that the first object may be above, below, or to the side of the second object, or vice versa. Additionally, the term "overlapping with" can include stacking, facing or oriented, extending over, covering or partially covering, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include meanings such as "separated," "offset," or "deviated," and any other suitable equivalents that will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented" can indicate that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, although the first and second objects still face each other, they can be understood as being indirectly opposite each other.

[0059] It will be understood that when a component, layer, region, or assembly (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed on," "on," "connected to," or "(operably, functionally, or communicatively) incorporated into" another component, layer, region, or assembly, that component, layer, region, or assembly may be directly formed on, directly on, directly connected to, or directly incorporated into, the other component, layer, region, or assembly, or indirectly formed on, indirectly on, indirectly connected to, or indirectly incorporated into, the other component, layer, region, or assembly, such that one or more intermediary components, intermediary layers, intermediary regions, or intermediary assemblies may exist. Furthermore, this may collectively mean direct or indirect incorporation or direct connection or indirect connection, as well as integral or non-integral incorporation or integral connection or non-integral connection. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically coupled" to another layer, region, or component, that layer, region, or component may be directly electrically connected or directly electrically coupled to said other layer, region, and / or component, or one or more intermediary layers, intermediary regions, or intermediary components may be present. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Therefore, connections are not limited to those shown in the accompanying drawings or detailed descriptions, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression for connection indicates an electrical connection, and "direct connection / direct coupling" or "directly on..." means that one component is directly connected or coupled to another component, or on another component, without any intermediate components.

[0060] Furthermore, in this specification, when a portion of a layer, film, region, plate, etc., is formed on another portion, the forming direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, plate, etc., is formed "below" another portion, this includes not only the case where the portion is "directly below" the other portion, but also the case where another portion exists between the portion and the other portion. Similarly, other expressions describing relationships between components, such as "between," "directly between," or "adjacent to," and "directly adjacent to," can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0061] For the purposes of this disclosure, expressions such as “at least one of…” or “any one of…” or “one or more of…” following a list of elements modify the entire list of elements without modifying any individual elements within the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XYY, YZ, and ZZ), or any variations thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, expressions such as “at least one of…”, “multiple…”, “one of…”, and other prepositional phrases, when placed before or after a column of elements, modify the entire column of elements without modifying any individual elements within that column. In the case of the statement “C to D”, it means C or more and D or fewer, unless otherwise stated.

[0062] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position, or priority, and are used only to distinguish one element, component, assembly, region, area, layer, section, or part from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, first assembly, first region, first layer, or first section described below may be referred to as a second element, second assembly, second region, second layer, or second part. Describing an element as a “first” element may not require or imply the presence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0063] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0064] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular form “a” is intended to include the plural form, and the plural form is intended to include the singular form. It will also be understood that when the terms “comprising,” “including,” “having,” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0065] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than as terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. For example, “substantially” can include a range of + / - 5% for the corresponding value. As used herein, “about” or “approximately” includes the stated value and means: within an acceptable deviation range for the specific value as determined by one of ordinary skill in the art, taking into account the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range acceptable to one of ordinary skill in the art. Other expressions may also omit the word “substantially.”

[0066] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and / or in the context of this specification, and shall not be interpreted in an idealized or overly formalized sense, unless expressly defined herein.

[0067] Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments. Figure 2 This is a block diagram illustrating a display device according to one or more embodiments.

[0068] Reference Figure 1 and Figure 2The display device 10 according to one or more embodiments is a device for displaying moving or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 according to one or more embodiments can be applied as a display unit in a television, laptop computer, monitor, billboard, or Internet of Things (IoT) device. Optionally, the display device 10 according to one or more embodiments can be applied to smartwatches, watch phones, or head-mounted displays (HMDs) for implementing virtual reality and augmented reality.

[0069] The display device 10 according to one or more embodiments includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing controller 400, and a power supply unit 500.

[0070] In a plan view, the display panel 100 may have a shape similar to a rectangle. For example, in a plan view, the display panel 100 may have a shape similar to a rectangle having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may have a rounded or right angle with a curvature (e.g., a predetermined curvature). The shape of the display panel 100 in a plan view is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, circular shapes, or elliptical shapes. The shape of the display device 10 in a plan view may follow the shape of the display panel 100 in a plan view, but one or more embodiments of this disclosure are not limited thereto.

[0071] like Figure 2 As shown, the display panel 100 may include a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0072] The display area DAA includes multiple pixels PX1, PX2 and PX3, multiple scan lines GWL and EBL, multiple emission control lines EL and multiple data lines DL.

[0073] Multiple pixels PX1, PX2, and PX3 can be arranged in a matrix on the first direction DR1 and the second direction DR2. Multiple scan lines GWL and EBL, as well as multiple emission control lines EL, can extend on the first direction DR1 and can be arranged on the second direction DR2. Multiple data lines DL can extend on the second direction DR2 and can be arranged on the first direction DR1.

[0074] Multiple scan lines GWL and EBL include multiple write scan lines GWL and multiple bias scan lines EBL.

[0075] Multiple unit pixels (UPX) include multiple pixels PX1, PX2, and PX3. Multiple pixels PX1, PX2, and PX3 can include, for example... Figure 3 The diagram shows multiple pixel transistors, which can be formed using semiconductor processes and can be located on a semiconductor substrate SSUB (see...). Figure 7 As used here, "located on" can mean "above". For example, the multiple pixel transistors of the data driver 700 can be formed as complementary metal-oxide-semiconductor (CMOS).

[0076] Each of the multiple pixels PX1, PX2, and PX3 can be connected to any one of the multiple write scan lines GWL, any one of the multiple bias scan lines EBL, any one of the multiple emitt control lines EL, and any one of the multiple data lines DL. Each of the multiple pixels PX1, PX2, and PX3 can receive the data voltage of the data line DL according to the write scan signal of the write scan line GWL, and allow the light-emitting element to emit light according to the data voltage.

[0077] The non-display area NDA includes a scan driver 610, a transmit driver 620, and a data driver 700.

[0078] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed using semiconductor processes and are formed on a semiconductor substrate SSUB (see [link to SSUB]). Figure 7 On the CMOS, for example, multiple scanning transistors and multiple light-emitting transistors can be formed. This has already been implemented. Figure 2 The diagram shows a scan driver 610 located on the left side of the display area DAA and a transmit driver 620 located on the right side of the display area DAA, but one or more embodiments of this disclosure are not limited thereto. For example, the scan driver 610 and the transmit driver 620 may be located on both the left and right sides of the display area DAA.

[0079] The scan driver 610 may include a write scan signal output unit 611 and a bias scan signal output unit 612. Each of the write scan signal output unit 611 and the bias scan signal output unit 612 may receive a scan timing control signal SCS from the timing controller 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS from the timing controller 400, and sequentially output the write scan signal to the write scan line GWL. The bias scan signal output unit 612 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line EBL.

[0080] The transmit driver 620 can generate transmit control signals according to the transmit timing control signal ECS, and output the transmit control signals sequentially to the transmit control line EL.

[0081] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed by semiconductor processes and formed on a semiconductor substrate SSUB (see Figure 7 For example, multiple data transistors can be formed as CMOS.

[0082] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing controller 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, pixels PX1, PX2, and PX3 can be selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected pixels PX1, PX2, and PX3.

[0083] The heat dissipation layer 200 may be stacked on the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be located on one surface (e.g., the rear surface) of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a layer made of graphite or a metal with high thermal conductivity, such as silver (Ag), copper (Cu), or aluminum (Al).

[0084] Circuit board 300 can be electrically connected to the first pad (also referred to as "soldering pad" or "soldering pad") unit PDA1 of display panel 100 using conductive adhesive components such as anisotropic conductive film (see...). Figure 4 Multiple first pads PD1 (see) Figure 4 The circuit board 300 can be a flexible printed circuit board or a flexible film with a flexible material. Figure 1The circuit board 300 is shown to be unbent, but it can be bent. In this case, one end of the circuit board 300 can be located on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 can be the first pad unit PDA1 (see [reference]) connected to the display panel 100 using conductive adhesive members. Figure 4 Multiple first pads PD1 (see) Figure 4 The other end opposite to the other end of the ).

[0085] The timing controller 400 can receive digital video data and timing signals from an external source. Based on the timing signals, the timing controller 400 can generate scan timing control signals (SCS), transmit timing control signals (ECS), and data timing control signals (DCS) for controlling the display panel 100. The timing controller 400 can output the scan timing control signal (SCS) to the scan driver 610 and the transmit timing control signal (ECS) to the transmit driver 620. The timing controller 400 can also output digital video data and the data timing control signal (DCS) to the data driver 700.

[0086] The power supply unit 500 can generate multiple panel driving voltages based on an external source voltage. For example, the power supply unit 500 can generate a common voltage VSS, a driving voltage VDD, and an initialization voltage VINT, and can supply the common voltage VSS, the driving voltage VDD, and the initialization voltage VINT to the display panel 100. (See below for further details.) Figure 3 Describe the common voltage VSS, drive voltage VDD, and initialization voltage VINT.

[0087] Each of the timing controller 400 and the power supply unit 500 can be formed as an integrated circuit (IC) and can be attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing controller 400 can be supplied to the display panel 100 through the circuit board 300. In addition, the common voltage VSS, drive voltage VDD, and initialization voltage VINT of the power supply unit 500 can be supplied to the display panel 100 through the circuit board 300.

[0088] Optionally, each of the timing controller 400 and power supply unit 500 may be located in the non-display area NDA of the display panel 100, similar to the scan driver 610, transmit driver 620, and data driver 700. In this case, the timing controller 400 may include multiple timing transistors, and the power supply unit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors can be formed by semiconductor processes and are formed on a semiconductor substrate SSUB (see [link to semiconductor data]). Figure 7On the CMOS, for example, multiple timing transistors and multiple power transistors can be formed as CMOS. Each of the timing controller 400 and the power supply unit 500 can be located in the data driver 700 and the first pad unit PDA1 (see Figure 4 )between.

[0089] Figure 3 It is an equivalent circuit diagram of the first pixel according to one or more embodiments.

[0090] Reference Figure 3 The first pixel PX1 can be connected to the write scan line GWL, the bias scan line EBL, the transmit control line EL, and the data line DL. Additionally, the first pixel PX1 can be connected to the common voltage line VSL, the drive voltage line VDL, the initialization voltage line VIL, and the reference voltage line VRL. The common voltage line VSL is applied with a common voltage VSS corresponding to a low potential voltage; the drive voltage line VDL is applied with a drive voltage VDD corresponding to a high potential voltage; the initialization voltage line VIL is applied with an initialization voltage VINT; and the reference voltage line VRL is applied with a reference voltage VREF. In this case, the common voltage VSS can be a voltage lower than the initialization voltage VINT, and the drive voltage VDD can be a voltage higher than the initialization voltage VINT.

[0091] The first pixel PX1 includes multiple transistors T1 to T4, a light-emitting element LE, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0092] The light-emitting element LE emits light according to the driving current flowing through the channel of the first transistor T1. The amount of light emitted from the light-emitting element LE can be proportional to the driving current. The light-emitting element LE can be connected between the first transistor T1 and the common voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the first transistor T1, and the second electrode of the light-emitting element LE can be connected to the common voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer located between the first electrode and the second electrode, but one or more embodiments of this disclosure are not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor located between the first electrode and the second electrode; in this case, the light-emitting element LE can be a miniature light-emitting diode.

[0093] The first transistor T1 may be a driving transistor that controls the source-drain current (hereinafter referred to as the "driving current") flowing between the source and drain electrodes according to the voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a second node N2, a drain electrode connected to a third node N3, and a body electrode connected to a driving voltage line VDL.

[0094] A second transistor T2 can be connected between the data line DL and the first node N1. The second transistor T2 is turned on by the write scan signal GW of the write scan line GWL to electrically connect the data line DL and the first node N1. For this purpose, the data voltage of the data line DL can be applied to an electrode of the first capacitor C1 connected to the first node. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, a drain electrode connected to the first node N1, and a body electrode connected to the drive voltage line VDL.

[0095] The data line may include multiple sub-data lines SDL1 and SDL2 positioned to overlap each other in a vertical direction (e.g., third direction DR3) (see Figure 9 , Figure 10 and Figure 12 Multiple sub-data lines SDL1 and SDL2 can be connected to each other through vias in the insulating film.

[0096] The third transistor T3 can be connected between the drive voltage line and the second node N2. The third transistor T3 can be turned on by the emit control signal EM of the emit control line EL to electrically connect the drive voltage line VDL and the second node N2 to each other. The third transistor T3 includes a gate electrode connected to the emit control line EL, a source electrode connected to the drive voltage line VDL, a drain electrode connected to the second node N2, and a body electrode connected to the drive voltage line VDL.

[0097] A fourth transistor T4 can be connected between the third node N3 and the initialization voltage line VIL. The fourth transistor T4 is turned on by the bias scan signal EB of the bias scan line EBL to connect the third node N3 and the initialization voltage line VIL to each other. The fourth transistor T4 includes a gate electrode connected to the bias scan line EBL, a drain electrode connected to the third node N3, a source electrode connected to the initialization voltage line VIL, and a body electrode connected to the initialization voltage line VIL.

[0098] A first capacitor C1 is connected between a first node N1 and a second node N2. The first capacitor C1 may include a first capacitor electrode CPE1 connected to the first node N1 (see...). Figure 12 ), and the second capacitor electrode CPE2 connected to the second node N2 (see Figure 12).

[0099] According to one or more embodiments, the first capacitor electrode CPE1 may include a first first sub-capacitor electrode SUE1-1 positioned to be stacked on top of each other in a vertical direction (e.g., third direction DR3) (see Figure 8 and Figure 12 ), first and second sub-capacitor electrodes SUE1-2 (see Figure 9 and Figure 12 ), first and third sub-capacitor electrodes SUE1-3 (see Figure 10 and Figure 12 ) and the first and fourth sub-capacitor electrodes SUE1-4 (see Figure 11 and Figure 12 The first sub-capacitor electrode SUE1-1, the first second sub-capacitor electrode SUE1-2, the first third sub-capacitor electrode SUE1-3, and the first fourth sub-capacitor electrode SUE1-4 mentioned above can be connected to the first node N1.

[0100] According to one or more embodiments, the second capacitor electrode CPE2 may include a second first sub-capacitor electrode SUE2-1 positioned to overlap each other in a vertical direction (e.g., third direction DR3) (see Figure 8 and Figure 12 ), second sub-capacitor electrode SUE2-2 (see Figure 9 and Figure 12 ), second and third sub-capacitor electrodes SUE2-3 (see Figure 10 and Figure 12 ) and the second and fourth sub-capacitor electrodes SUE2-4 (see Figure 11 and Figure 12 The aforementioned second first sub-capacitor electrode SUE2-1, second second sub-capacitor electrode SUE2-2, second third sub-capacitor electrode SUE2-3, and second fourth sub-capacitor electrode SUE2-4 can be connected to the second node N2.

[0101] The second capacitor C2 is connected between the first node N1 and the reference voltage line VRL. The second capacitor C2 includes a third capacitor electrode connected to the first node N1 and a fourth capacitor electrode connected to the reference voltage line VRL.

[0102] According to one or more embodiments, the third capacitor electrode may include a third first sub-capacitor electrode SUE3-1 positioned to be stacked on top of each other in a vertical direction (e.g., third direction DR3) (see Figure 8 ), the third and second sub-capacitor electrodes SUE3-2 (see Figure 9 ), the third sub-capacitor electrode SUE3-3 (see Figure 10 ) and the third and fourth sub-capacitor electrodes SUE3-4 (see Figure 11 The aforementioned third sub-capacitor electrode SUE3-1, third second sub-capacitor electrode SUE3-2, third third sub-capacitor electrode SUE3-3, and third fourth sub-capacitor electrode SUE3-4 can be connected to the first node N1.

[0103] According to one or more embodiments, the fourth capacitor electrode may include a fourth first sub-capacitor electrode SUE4-1 positioned to be stacked on top of each other in a vertical direction (e.g., third direction DR3) (see Figure 8 ), the fourth and second sub-capacitor electrodes SUE4-2 (see Figure 9 ), fourth and third sub-capacitor electrodes SUE4-3 (see Figure 10 ) and the fourth sub-capacitor electrode SUE4-4 (see Figure 11 The aforementioned fourth sub-capacitor electrode SUE4-1, fourth second sub-capacitor electrode SUE4-2, fourth third sub-capacitor electrode SUE4-3, and fourth fourth sub-capacitor electrode SUE4-4 can be connected to the reference voltage line VRL.

[0104] The third capacitor C3 is connected between the first node N1 and the third node N3. The third capacitor C3 includes a fifth capacitor electrode connected to the first node N1 and a sixth capacitor electrode connected to the third node N3.

[0105] Each of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistor T1, the second transistor T2, and the third transistor T3 can be a P-type MOSFET, and the fourth transistor T4 can be an N-type MOSFET.

[0106] exist Figure 3 The diagram already shows that the first pixel PX1 includes four transistors T1 to T4 and three capacitors C1, C2 and C3, but the equivalent circuit diagram of the first pixel PX1 is not limited to... Figure 3 The equivalent circuit diagram is shown below. For example, the number of transistors and capacitors in the first pixel PX1 is not limited to... Figure 3 The quantities shown in the figure.

[0107] Furthermore, the equivalent circuit diagrams of the second pixel PX2 and the third pixel PX3 can be compared with the reference. Figure 3 The equivalent circuit diagram of the first pixel PX1 is substantially the same. Therefore, the substantially similar descriptions of the equivalent circuit diagrams of the second pixel PX2 and the third pixel PX3 are omitted in this disclosure.

[0108] Figure 4This is a layout diagram illustrating an example of a display panel according to one or more embodiments.

[0109] Reference Figure 4 The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX1, PX2 and PX3 arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad unit PDA1 and a second pad unit PDA2.

[0110] The scan driver 610 may be located on a first side of the display area DAA, and the transmit driver 620 may be located on a second side of the display area DAA. For example, the scan driver 610 may be located on one side of the display area DAA in the first direction DR1, and the transmit driver 620 may be located on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 may be located on the left side of the display area DAA, and the transmit driver 620 may be located on the right side of the display area DAA. However, one or more embodiments of this disclosure are not limited thereto, and the scan driver 610 and the transmit driver 620 may be located on both the first and second sides of the display area DAA.

[0111] The first pad unit PDA1 may include a plurality of first pads PD1 connected to the circuit board 300 by a conductive adhesive member. The first pad unit PDA1 may be located on the third side of the display area DAA. For example, the first pad unit PDA1 may be located on one side of the display area DAA in the second direction DR2.

[0112] The first pad unit PDA1 can be located outside the data driver 700 on the second direction DR2. That is, the first pad unit PDA1 can be closer to the edge of the display panel 100 than the data driver 700.

[0113] The second pad unit PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to check whether the display panel 100 is operating normally. The multiple second pads PD2 may be connected to a fixture or probe pins or to a circuit board for inspection during the inspection process. The circuit board used for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0114] The first distribution circuit 710 distributes the data voltage applied through the first pad unit PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad unit PDA1 to P data lines DL (P is a positive integer of 2 or greater), thus reducing the number of first pads PD1. The first distribution circuit 710 can be located on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be located on one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can be located on the lower side of the display area DAA.

[0115] The second distribution circuit 720 distributes the signal applied through the second pad unit PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad unit PDA2 and the second distribution circuit 720 can be components for checking the operation of each of the pixels PX1, PX2, and PX3 in the display area DAA. The second distribution circuit 720 can be located on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be located on the other side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be located on the upper side of the display area DAA.

[0116] Figure 5 and Figure 6 It is shown Figure 4 A layout diagram of an embodiment of the display area.

[0117] Reference Figure 5 and Figure 6 Each of the multiple unit pixels UPX includes a first emission region EA1 as the emission region of a first pixel PX1, a second emission region EA2 as the emission region of a second pixel PX2, and a third emission region EA3 as the emission region of a third pixel PX3. In other words, a unit pixel UPX may include a unit emission region UEA, and the unit emission region UEA includes the aforementioned first emission region EA1, second emission region EA2, and third emission region EA3.

[0118] In the plan view, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape.

[0119] The maximum length of the third transmission region EA3 in the first direction DR1 can be less than the maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1. The maximum lengths of the first transmission region EA1 and the second transmission region EA2 in the first direction DR1 can be substantially the same as each other.

[0120] The maximum length of the third transmission region EA3 in the second direction DR2 can be greater than the maximum length of the first transmission region EA1 in the second direction DR2 and the maximum length of the second transmission region EA2 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 can be greater than the maximum length of the second transmission region EA2 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 can be less than the maximum length of the third transmission region EA3 in the second direction DR2.

[0121] like Figure 6 As shown, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a hexagonal shape comprising six straight lines in the plan view, but one or more embodiments of this disclosure are not limited thereto. In the plan view, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape other than a hexagonal shape.

[0122] like Figure 5 As shown, in each of the plurality of unit pixels UPX, the second emission region EA2 and the third emission region EA3 can be adjacent to each other in the first direction DR1. Furthermore, the first emission region EA1 and the third emission region EA3 can be adjacent to each other in the first direction DR1. Additionally, the first emission region EA1 and the second emission region EA2 can be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be different from each other.

[0123] Optionally, such as Figure 6As shown, the first transmission region EA1 and the second transmission region EA2 can be adjacent to each other in the first direction DR1, but the second transmission region EA2 and the third transmission region EA3 can be adjacent to each other in the first diagonal direction DD1, and the first transmission region EA1 and the third transmission region EA3 can be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 is the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45° relative to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction orthogonal to the first diagonal direction DD1.

[0124] The first emission region EA1 can emit light of the first color, the second emission region EA2 can emit light of the second color, and the third emission region EA3 can emit light of the third color. Here, the first color of light can be light in the blue band, the second color of light can be light in the green band, and the third color of light can be light in the red band. For example, the blue band can represent the main peak wavelength of light included in the band of approximately 370 nm to approximately 460 nm, the green band can represent the main peak wavelength of light included in the band of approximately 480 nm to approximately 560 nm, and the red band can represent the main peak wavelength of light included in the band of approximately 600 nm to approximately 750 nm.

[0125] exist Figure 5 and Figure 6 The present disclosure has shown that each of the plurality of unit pixel UPXs includes three emission regions EA1, EA2, and EA3, but one or more embodiments of the present disclosure are not limited thereto. That is, each of the plurality of unit pixel UPXs may also include four emission regions.

[0126] Furthermore, the arrangement of the emission regions of multiple unit pixel UPXs is not limited to Figure 5 and Figure 6 The arrangement shown in the image. For example, as... Figure 6 As shown in the diagram, in the planar view, the emission regions of multiple unit pixels UPX can be located in a stripe structure in which the emission regions are arranged in the first direction DR1, wherein the emission regions have diamond-shaped PenTile arrangements. ® Structure (PenTile) ® (It is a registered trademark of Samsung Display Co., Ltd. of South Korea), or a hexagonal structure in which a hexagonal emission area is arranged.

[0127] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line I1-I1'.

[0128] Reference Figure 7The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0129] A semiconductor backplane (SBP) may include a semiconductor substrate (SSUB) comprising a plurality of pixel transistors (PTRs), a plurality of semiconductor insulating films covering the plurality of pixel transistors (PTRs), and a plurality of contact terminals (CTEs) electrically connected to the plurality of pixel transistors (PTRs). The plurality of pixel transistors (PTRs) may be referenced. Figure 3 The first transistor T1 to the fourth transistor T4 are described.

[0130] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be located on the upper surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the first type of impurity described above. For example, when the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. Optionally, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0131] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH located between the source region SA and the drain region DA.

[0132] The bottom insulating film (BINS) can be located between the gate electrode GE and the well region WA. The side surface insulating film (SINS) can be located on the side surface of the gate electrode GE. The side surface insulating film (SINS) can be located on the bottom insulating film (BINS).

[0133] Each of the source region SA and drain region DA can be a region doped with type I impurities. The gate electrode GE of the pixel transistor PTR can be stacked with the well region WA on the third-direction DR3. The channel region CH can be stacked with the gate electrode GE on the third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0134] Each of the multiple well regions WA also includes a first low-concentration impurity region LDD1 located between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 located between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region with a lower impurity concentration than the source region SA due to the bottom insulating film BINS. The second low-concentration impurity region LDD2 may be a region with a lower impurity concentration than the drain region DA due to the bottom insulating film BINS. The distance between the source region SA and the drain region DA can be increased by the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH in each of the pixel transistors PTR can be increased, thereby reducing or preventing punch-through and hot carrier phenomena caused by short channels.

[0135] The first semiconductor insulating film SINS1 can be located on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be formed based on silicon carbonitride (SiCN) or silicon oxide (SiO2). x The inorganic membrane is described, but one or more embodiments of this disclosure are not limited thereto.

[0136] The second semiconductor insulating film SINS2 can be located on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be formed based on silicon oxide (SiO2). x The inorganic membrane is described, but one or more embodiments of this disclosure are not limited thereto.

[0137] Multiple contact terminals (CTEs) may be located on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) may be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and their alloys.

[0138] A third semiconductor insulating film (SINS3) can be located on the side surface of each of the plurality of contact terminals (CTEs). The upper surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3). The third semiconductor insulating film (SINS3) can be formed based on silicon oxide (SiO2). x The inorganic membrane is described, but one or more embodiments of this disclosure are not limited thereto.

[0139] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as a polyimide substrate. In this case, the thin-film transistor can be located on either the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, or the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0140] The backplane (EBP) of the light-emitting element includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9. Additionally, the backplane (EBP) includes multiple insulating films INS1 to INS9 located between the first conductive layer ML1 to the eighth conductive layer ML8.

[0141] The first conductive layers ML1 to the eighth conductive layers ML8 are used to achieve [the desired effect] by connecting multiple contact terminals CTE exposed from the semiconductor backplane SBP to each other. Figure 3 The circuitry for the first pixel PX1 is shown. For example, only the first transistor T1 to the fourth transistor T4 are formed in the semiconductor backplane SBP, and the connections between the first transistor T1 to the fourth transistor T4, as well as the formation of the first capacitor C1, the second capacitor C2, and the third capacitor C3, are performed through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connections between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE are also performed through the first conductive layer ML1 to the eighth conductive layer ML8.

[0142] The first insulating film INS1 may be located on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating film INS1 to connect to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be located on the first insulating film INS1 and may be connected to the first via VA1.

[0143] The second insulating film INS2 may be located on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 may penetrate the second insulating film INS2 to connect to the exposed first conductive layer ML1. Each of the second conductive layers ML2 may be located on the second insulating film INS2 and may be connected to the second via VA2.

[0144] The third insulating film INS3 may be located on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 may penetrate the third insulating film INS3 to connect to the exposed second conductive layer ML2. Each of the third conductive layers ML3 may be located on the third insulating film INS3 and may be connected to the third via VA3.

[0145] A fourth insulating film INS4 may be located on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 may penetrate the fourth insulating film INS4 to connect to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 may be located on the fourth insulating film INS4 and may be connected to the fourth via VA4.

[0146] The fifth insulating film INS5 may be located on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 may penetrate the fifth insulating film INS5 to connect to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 may be located on the fifth insulating film INS5 and may be connected to the fifth via VA5.

[0147] The sixth insulating film INS6 may be located on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 may penetrate the sixth insulating film INS6 to connect to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 may be located on the sixth insulating film INS6 and may be connected to the sixth via VA6.

[0148] The seventh insulating film INS7 may be located on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 may penetrate the seventh insulating film INS7 to connect to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 may be located on the seventh insulating film INS7 and may be connected to the seventh via VA7.

[0149] The eighth insulating film INS8 may be located on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 may penetrate the eighth insulating film INS8 to connect to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 may be located on the eighth insulating film INS8 and may be connected to the eighth via VA8.

[0150] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be made of substantially the same material. Each of the first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and their alloys. The first vias VA1 to VA8 can be made of substantially the same material. The first insulating film INS1 to INS8 can be formed based on silicon oxide (SiO2). x The inorganic membrane is described, but one or more embodiments of this disclosure are not limited thereto.

[0151] The thickness of each of the following conductive layers can be greater than the thickness of each of the following: the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of each of the following: the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thicknesses of the following: the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same as each other. For example, the thickness of the first conductive layer ML1 can be approximately 1360 Å, the thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately 1440 Å, and the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be approximately 1150 Å.

[0152] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of each of the seventh via VA7 and the eighth via VA8. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same as each other. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately 9000 Å. The thickness of the seventh via VA7 and the thickness of the eighth via VA8 can each be approximately 6000 Å.

[0153] The ninth insulating film INS9 can be located on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be formed based on silicon oxide (SiO2). x The inorganic membrane is described, but one or more embodiments of this disclosure are not limited thereto.

[0154] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 to connect to the exposed eighth conductive layer ML8. Each of the ninth vias VA9 can be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and their alloys. The thickness of the ninth via VA9 can be approximately 16500 Å.

[0155] The display element layer (EML) can be located on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include a reflective electrode layer (RL), a tenth insulating film (INS10) and an eleventh insulating film (INS11), a tenth via (VA10), a light-emitting element (LE) including a first electrode (AND), a light-emitting stack (ES) and a second electrode (CAT), a pixel defining film (PDL), and multiple trenches (TRC).

[0156] The reflective electrode layer RL can be located on the ninth insulating film INS9. The reflective electrode layer RL can include one or more reflective electrodes RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL can include... Figure 7 The first to fourth reflective electrodes RL1, RL2, RL3 and RL4 are shown in the figure.

[0157] Each of the first reflective electrodes RL1 may be located on the ninth insulating film INS9 and may be connected to the ninth via VA9. Each of the first reflective electrodes RL1 may be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and their alloys. For example, each of the first reflective electrodes RL1 may include titanium nitride (TiN).

[0158] Each of the second reflective electrodes RL2 may be located on the first reflective electrode RL1. Each of the second reflective electrodes RL2 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and their alloys. For example, each of the second reflective electrodes RL2 may include aluminum (Al).

[0159] Each of the third reflective electrodes RL3 may be located on the second reflective electrode RL2. Each of the third reflective electrodes RL3 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and their alloys. For example, each of the third reflective electrodes RL3 may include titanium nitride (TiN).

[0160] Each of the fourth reflective electrodes RL4 may be located on the third reflective electrode RL3. Each of the fourth reflective electrodes RL4 may be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and their alloys. For example, each of the fourth reflective electrodes RL4 may include titanium (Ti).

[0161] Because the second reflective electrode RL2 is the electrode that essentially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately 100 Å, and the thickness of the second reflective electrode RL2 can be approximately 850 Å.

[0162] The tenth insulating film INS10 can be located on the ninth insulating film INS9. The tenth insulating film INS10 can be located between horizontally adjacent reflective electrode layers RL. The tenth insulating film INS10 can be located on the reflective electrode layer RL in the third pixel PX3. The tenth insulating film INS10 can be formed based on silicon oxide (SiO2). x The inorganic membrane is described, but one or more embodiments of this disclosure are not limited thereto.

[0163] The eleventh insulating film INS11 can be located on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 can be formed based on silicon oxide (SiO2). x The inorganic film is not limited to this, but one or more embodiments of the present disclosure are not limited thereto. The tenth insulating film INS10 and the eleventh insulating film INS11 may be optical auxiliary layers through which light emitted from the light-emitting element LE and reflected by the reflective electrode layer RL passes.

[0164] To adjust the resonant distance of light emitted from the light-emitting element LE in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the tenth insulating film INS10 and the eleventh insulating film INS11 may not be located below the first electrode AND of the first pixel PX1. The first electrode AND of the first pixel PX1 may be located directly on the reflective electrode layer RL. The eleventh insulating film INS11 may be located below the first electrode AND of the second pixel PX2. The tenth insulating film INS10 and the eleventh insulating film INS11 may be located below the first electrode AND of the third pixel PX3.

[0165] In summary, the corresponding distance between the first electrode AND and the reflective electrode layer RL can be different in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. That is, in order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the dominant wavelength of light emitted from each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the presence or absence of the tenth insulating film INS10 and the eleventh insulating film INS11 can be provided in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, in Figure 7 It has been shown that the distance between the first electrode AND and the reflective electrode layer RL in the third pixel PX3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2, and greater than the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1. The distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1. However, one or more embodiments of this disclosure are not limited thereto.

[0166] Additionally, while a tenth insulating film INS10 and an eleventh insulating film INS11 have been shown in one or more embodiments of this disclosure, a twelfth insulating film may be added below the first electrode AND of the first pixel PX1. In this case, the eleventh insulating film INS11 and the twelfth insulating film may be located below the first electrode AND of the second pixel PX2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be located below the first electrode AND of the third pixel PX3.

[0167] Each of the tenth vias VA10 can penetrate the tenth insulating film INS10 and / or the eleventh insulating film INS11 in the second pixel PX2 and the third pixel PX3 to connect to the exposed fourth reflective electrode RL4. Each of the tenth vias VA10 can be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and their alloys. The thickness of the tenth via VA10 in the second pixel PX2 can be less than the thickness of the tenth via VA10 in the third pixel PX3.

[0168] The first electrode AND of each of the light-emitting elements LE can be located on the tenth insulating film INS10 and can be connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR via the tenth via VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be made of any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and their alloys. For example, the first electrode AND of each of the light-emitting elements LE can be made of titanium nitride (TiN).

[0169] The pixel-defining film (PDL) may be located in a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL may cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL is used to separate the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0170] The first emitting region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked in the first pixel PX1 to emit light. The second emitting region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked in the second pixel PX2 to emit light. The third emitting region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked in the third pixel PX3 to emit light.

[0171] The pixel-defining film (PDL) may include first pixel-defining films to third pixel-defining films PDL1, PDL2, and PDL3. The first pixel-defining film PDL1 may be located on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel-defining film PDL2 may be located on the first pixel-defining film PDL1, and the third pixel-defining film PDL3 may be located on the second pixel-defining film PDL2. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may be formed based on silicon oxide (SiO2). x The inorganic film is described, but one or more embodiments of this disclosure are not limited thereto. The thickness of the first pixel defining film PDL1, the thickness of the second pixel defining film PDL2, and the thickness of the third pixel defining film PDL3 may each be approximately 500 Å.

[0172] When the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 form a single pixel-defining film, the height of this single pixel-defining film increases, making the first encapsulating inorganic film TFE1 potentially break due to step coverage. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the easier it is for the film to break at the inclined portion.

[0173] Therefore, to reduce or prevent the possibility of the first encapsulated inorganic film TFE1 breaking due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can have a cross-sectional structure with steps in a step shape. For example, the width of the first pixel defining film PDL1 can be greater than the width of the second pixel defining film PDL2, and can also be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to its length in the horizontal direction defined by the first direction DR1 and the second direction DR2.

[0174] Each of the plurality of trench TRCs can penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Additionally, each of the plurality of trench TRCs can penetrate the eleventh insulating film INS11. In each of the plurality of trench TRCs, the tenth insulating film INS10 can have a portion thereof slotted.

[0175] At least one trench TRC can be located between adjacent pixels PX1, PX2, and PX3. (This is already in place.) Figure 7 The illustration shows two trench TRCs located between adjacent pixels PX1, PX2, and PX3, but one or more embodiments of this disclosure are not limited thereto.

[0176] Light-emitting stacks (ES) can include multiple layers. [This is already in use.] Figure 7 The image shows a light-emitting stack ES having a triple-tandem structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but one or more embodiments of this disclosure are not limited thereto. For example, the light-emitting stack ES may have a double-tandem structure including two intermediate layers.

[0177] In a three-tiered structure, the light-emitting stack ES can have a series structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different colors of light. For example, the light-emitting stack ES may include a first stacked layer IL1 for emitting light of a first color, a second stacked layer IL2 for emitting light of a third color, and a third stacked layer IL3 for emitting light of a second color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0178] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0179] A first charge-generating layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be located between the first stacked layer IL1 and the second stacked layer IL2. The first charge-generating layer may include an N-type charge-generating layer that supplies electrons to the first stacked layer IL1 and a P-type charge-generating layer that supplies holes to the second stacked layer IL2. The N-type charge-generating layer may include a dopant of a metallic material.

[0180] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be located between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second stacked layer IL2 and a P-type charge generation layer that supplies holes to the third stacked layer IL3.

[0181] A first stacked layer IL1 may be located on the first electrode AND and the pixel defining film PDL, and may be located on the bottom surface of each of the trench TRCs. Due to the trench TRCs, the first stacked layer IL1 may be disconnected between adjacent pixels PX1, PX2, and PX3. A second stacked layer IL2 may be located on the first stacked layer IL1. Due to the trench TRCs, the second stacked layer IL2 may be disconnected between adjacent pixels PX1, PX2, and PX3. A cavity ESS or empty space may be located between the first stacked layer IL1 and the second stacked layer IL2. A third stacked layer IL3 may be located on the second stacked layer IL2. The third stacked layer IL3 may not be disconnected by the trench TRCs and may be positioned to cover the second stacked layer IL2 in each of the trench TRCs. That is, in a three-in-line structure, each of the plurality of trench TRCs may be a structure for disconnecting the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer and the second charge generation layer of the display element layer EML between adjacent pixels PX1, PX2, and PX3. In addition, in the two-series structure, each of the multiple trench TRCs can be a structure used to disconnect the charge generation layer located between the lower intermediate layer and the upper intermediate layer from the lower intermediate layer.

[0182] To stably disconnect the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2, and PX3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. To disconnect the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2, and PX3, other structures other than trench TRCs may exist. For example, a separator wall with an inverted conical shape can be positioned on the pixel defining film PDL instead of a trench TRC.

[0183] The number of stacked layers IL1, IL2, and IL3 that emit different light is not limited to Figure 7 The quantities shown are as follows. For example, the light-emitting stack ES may include two intermediate layers. In this case, either of the two intermediate layers may be substantially the same as the first stack layer IL1, and the other of the two intermediate layers may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge-generating layer for supplying electrons to either intermediate layer and holes to the other intermediate layer may be located between the two intermediate layers.

[0184] exist Figure 7The first to third stacked layers IL1, IL2, and IL3 have been shown to be located entirely within the first emission region EA1, the second emission region EA2, and the third emission region EA3, but one or more embodiments of this disclosure are not limited thereto. For example, the first stacked layer IL1 may be located within the first emission region EA1, but may not be located within the second emission region EA2 or the third emission region EA3. Similarly, the second stacked layer IL2 may be located within the second emission region EA2, but may not be located within the first emission region EA1 or the third emission region EA3. Furthermore, the third stacked layer IL3 may be located within the third emission region EA3, but may not be located within the first emission region EA1 or the second emission region EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0185] The second electrode CAT can be located on the third stacked layer IL3. The second electrode CAT can be located on the third stacked layer IL3 in each of the multiple trenches of the TRC. The second electrode CAT can be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO) capable of allowing light to pass through it, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is made of a semi-transmissive conductive material, the luminous efficiency of each of the first to third pixels PX1, PX2, and PX3 can be increased through the microcavity.

[0186] The encapsulation layer TFE can be located on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 or TFE2 to reduce or prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0187] The first encapsulating inorganic film TFE1 can be located on the second electrode CAT. The first encapsulating inorganic film TFE1 can be formed in which silicon nitride (SiN) is alternately stacked. x ) layer, silicon oxynitride (SiON) layer and silicon oxide (SiO) layer x Multiple films consisting of one or more inorganic films in a layer. The first encapsulated inorganic film TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0188] The second encapsulation inorganic film TFE2 can be located on the first encapsulation inorganic film TFE1. The second encapsulation inorganic film TFE2 can be formed as titanium oxide (TiO2). x ) layer or aluminum oxide (AlO) xThe second encapsulation inorganic film TFE2 may be formed by atomic layer deposition (ALD). The thickness of the second encapsulation inorganic film TFE2 may be less than the thickness of the first encapsulation inorganic film TFE1.

[0189] Organic film APL can be a layer used to increase the interfacial adhesion strength between the encapsulation layer TFE and the optical layer OPL. Organic film APL can be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0190] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be located on the organic film APL.

[0191] A first color filter CF1 can be superimposed on a first emission region EA1 of a first pixel PX1. The first color filter CF1 allows light of a first color (i.e., light in the blue band) to pass through it. The blue band can be approximately 370 nm to approximately 460 nm. Therefore, the first color filter CF1 allows light of the first color emitted from the first emission region EA1 to pass through it.

[0192] The second color filter CF2 can be superimposed on the second emission region EA2 of the second pixel PX2. The second color filter CF2 allows light of the second color (that is, light in the green band) to pass through it. The green band can be approximately 480nm to approximately 560nm. Therefore, the second color filter CF2 allows light of the second color emitted from the second emission region EA2 to pass through it.

[0193] The third color filter CF3 can be superimposed on the third emission region EA3 of the third pixel PX3. The third color filter CF3 allows light of the third color (i.e., light in the red band) to pass through it. The blue band can be approximately 600nm to approximately 750nm. Therefore, the third color filter CF3 allows light of the third color emitted from the third emission region EA3 to pass through it.

[0194] Each of the plurality of lenses LNS may be located on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light directed to the front surface of the display device 10. Each of the plurality of lenses LNS may have a profile shape that convexes in the upward direction.

[0195] The filler layer (FIL) can be located on multiple lens lenses (LNS). The filler layer (FIL) can have a refractive index (e.g., a predetermined refractive index) such that light travels in the third direction (DR3) at the interface between the multiple lens lenses (LNS) and the filler layer (FIL). Alternatively, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0196] The cover layer CVL can be located on the filler layer FIL. The cover layer CVL can be a glass substrate or a polymeric resin such as a resin. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to adhere the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymeric resin such as a resin, it can be applied directly to the filler layer FIL.

[0197] The polarizer POL can be located on one surface of the CVL cover layer. The polarizer POL can be a structure used to reduce or prevent visibility degradation due to external light reflection. The polarizer POL can include a linear polarizer and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but one or more embodiments of this disclosure are not limited thereto. However, the polarizer POL can be omitted when visibility due to external light reflection is sufficiently improved by the first to third color filters CF1, CF2, and CF3.

[0198] Figure 8 It is a plan view of the first sub-capacitor electrode SUE1-1 of the first capacitor electrode CPE1, the second sub-capacitor electrode SUE2-1 of the second capacitor electrode CPE2, the third sub-capacitor electrode SUE3-1 of the third capacitor electrode, the fourth sub-capacitor electrode SUE4-1 of the fourth capacitor electrode, and the third connecting electrode CNE3. Figure 9 This is a plan view of the first and second sub-capacitor electrodes SUE1-2 of the first capacitor electrode CPE1, the second and second sub-capacitor electrodes SUE2-2 of the second capacitor electrode CPE2, the third and second sub-capacitor electrodes SUE3-2 of the third capacitor electrode, the fourth and second sub-capacitor electrodes SUE4-2 of the fourth capacitor electrode, and the first sub-data line SDL1. Figure 10This is a plan view of the first and third sub-capacitor electrodes SUE1-3 of the first capacitor electrode CPE1, the second and third sub-capacitor electrodes SUE2-3 of the second capacitor electrode CPE2, the third and third sub-capacitor electrodes SUE3-3 of the third capacitor electrode, the fourth and third sub-capacitor electrodes SUE4-3 of the fourth capacitor electrode, and the second sub-data line SDL2. Figure 11 This is a plan view of the first fourth sub-capacitor electrode SUE1-4 of the first capacitor electrode CPE1, the second fourth sub-capacitor electrode SUE2-4 of the second capacitor electrode CPE2, the third fourth sub-capacitor electrode SUE3-4 of the third capacitor electrode, and the fourth fourth sub-capacitor electrode SUE4-4 of the fourth capacitor electrode. Figure 12 It shows along Figures 8 to 11 A cross-sectional view of an example display panel, taken by line I2-I2'.

[0199] like Figures 8 to 10 As shown, the first node N1 may include a plurality of node electrodes NE1-1, NE1-2, and NE1-3 positioned adjacent to each other in the vertical direction (e.g., on the third direction DR3). For example, the first node N1 may include a first node electrode NE1-1, a first second node electrode NE1-2 located on the first node electrode NE1-1, and a first third node electrode NE1-3 located on the first second node electrode NE1-2. The first node electrode NE1-1, the first second node electrode NE1-2, and the first third node electrode NE1-3 may be connected to each other.

[0200] The first capacitor C1 may include a first capacitor electrode CPE1 and a second capacitor electrode CPE2 positioned adjacent to each other in a horizontal direction (e.g., in the first direction DR1 and / or the second direction DR2).

[0201] The second capacitor C2 may include a third capacitor electrode and a fourth capacitor electrode positioned adjacent to each other in the horizontal direction (e.g., in the first direction DR1 and / or the second direction DR2).

[0202] like Figures 8 to 11As shown, the first capacitor electrode CPE1 may include a plurality of sub-capacitor electrodes positioned adjacent to each other in a vertical direction (e.g., third direction DR3). For example, the first capacitor electrode CPE1 may include a plurality of first first sub-capacitor electrodes SUE1-1, a plurality of first second sub-capacitor electrodes SUE1-2 located on the plurality of first first sub-capacitor electrodes SUE1-1, a plurality of first third sub-capacitor electrodes SUE1-3 located on the plurality of first second sub-capacitor electrodes SUE1-2, and a plurality of first fourth sub-capacitor electrodes SUE1-4 located on the plurality of first third sub-capacitor electrodes SUE1-3. The first first sub-capacitor electrodes SUE1-1, first second sub-capacitor electrodes SUE1-2, first third sub-capacitor electrodes SUE1-3, and first fourth sub-capacitor electrodes SUE1-4 may be connected to each other.

[0203] like Figures 8 to 11 As shown, the second capacitor electrode CPE2 may include a plurality of sub-capacitor electrodes positioned adjacent to each other in a vertical direction (e.g., third direction DR3). For example, the second capacitor electrode CPE2 may include a plurality of second first sub-capacitor electrodes SUE2-1, a plurality of second second sub-capacitor electrodes SUE2-2 located on the plurality of second first sub-capacitor electrodes SUE2-1, a plurality of second third sub-capacitor electrodes SUE2-3 located on the plurality of second second sub-capacitor electrodes SUE2-2, and a plurality of second fourth sub-capacitor electrodes SUE2-4 located on the plurality of second third sub-capacitor electrodes SUE2-3. The second first sub-capacitor electrodes SUE2-1, second second sub-capacitor electrodes SUE2-2, second third sub-capacitor electrodes SUE2-3, and second fourth sub-capacitor electrodes SUE2-4 may be connected to each other.

[0204] like Figures 8 to 11 As shown, the third capacitor electrode may include a plurality of sub-capacitor electrodes positioned adjacent to each other in a vertical direction (e.g., third direction DR3). For example, the third capacitor electrode may include a plurality of third first sub-capacitor electrodes SUE3-1, a plurality of third second sub-capacitor electrodes SUE3-2 located on the plurality of third first sub-capacitor electrodes SUE3-1, a plurality of third third sub-capacitor electrodes SUE3-3 located on the plurality of third second sub-capacitor electrodes SUE3-2, and a plurality of third fourth sub-capacitor electrodes SUE3-4 located on the plurality of third third sub-capacitor electrodes SUE3-3. The third first sub-capacitor electrodes SUE3-1, third second sub-capacitor electrodes SUE3-2, third third sub-capacitor electrodes SUE3-3, and third fourth sub-capacitor electrodes SUE3-4 may be connected to each other.

[0205] like Figures 8 to 11As shown, the fourth capacitor electrode may include a plurality of sub-capacitor electrodes positioned adjacent to each other in a vertical direction (e.g., third direction DR3). For example, the fourth capacitor electrode may include a plurality of fourth first sub-capacitor electrodes SUE4-1, a plurality of fourth second sub-capacitor electrodes SUE4-2 located on the plurality of fourth first sub-capacitor electrodes SUE4-1, a plurality of fourth third sub-capacitor electrodes SUE4-3 located on the plurality of fourth second sub-capacitor electrodes SUE4-2, and a plurality of fourth fourth sub-capacitor electrodes SUE4-4 located on the plurality of fourth third sub-capacitor electrodes SUE4-3. The fourth first sub-capacitor electrodes SUE4-1, fourth second sub-capacitor electrodes SUE4-2, fourth third sub-capacitor electrodes SUE4-3, and fourth fourth sub-capacitor electrodes SUE4-4 may be connected to each other.

[0206] like Figure 8 As shown, each of the first sub-capacitor electrodes SUE1-1 can extend along the second direction DR2. The first sub-capacitor electrodes SUE1-1 can be arranged along the first direction DR1. Corresponding sides of the first sub-capacitor electrodes SUE1-1 can be connected to each other. For example, corresponding sides of multiple first sub-capacitor electrodes SUE1-1 can be connected to the first node N1. For example, corresponding sides of multiple first sub-capacitor electrodes SUE1-1 can be connected to the first node electrode NE1-1 of the first node N1. The first node electrode NE1-1 and the multiple first sub-capacitor electrodes SUE1-1 can be integrally formed together.

[0207] like Figure 8 As shown, each of the second first sub-capacitor electrodes SUE2-1 can extend along the second direction DR2. The second first sub-capacitor electrodes SUE2-1 can be arranged along the first direction DR1. Corresponding sides of the second first sub-capacitor electrodes SUE2-1 can be connected to each other. For example, corresponding sides of multiple second first sub-capacitor electrodes SUE2-1 can be connected to the second node N2.

[0208] According to one or more embodiments, such as Figure 8 As shown, the first sub-capacitor electrode SUE1-1 can be located between two second sub-capacitor electrodes SUE2-1 that are adjacent to each other in the first direction DR1.

[0209] According to one or more embodiments, when a first first sub-capacitor electrode SUE1-1 and a second first sub-capacitor electrode SUE2-1 positioned along a first direction DR1 are defined as a first sub-capacitor electrode group, a second first sub-capacitor electrode SUE2-1 may be located at the outermost portion of the first sub-capacitor electrode group. For example, any second first sub-capacitor electrode SUE2-1 located at the outermost portion on one side and any second first sub-capacitor electrode SUE2-1 located at the outermost portion on the other side may be located at the outermost portions on both sides of the first sub-capacitor electrode group, respectively. In other words, the second first sub-capacitor electrodes SUE2-1 located at the outermost portions on both sides may be located at the outermost portions on both sides of the first sub-capacitor electrode group, respectively.

[0210] In addition, such as Figure 8 As shown, each of the third first sub-capacitor electrodes SUE3-1 can extend along the second direction DR2. The third first sub-capacitor electrodes SUE3-1 can be arranged along the first direction DR1. Corresponding sides of the third first sub-capacitor electrodes SUE3-1 can be connected to each other. For example, corresponding sides of multiple third first sub-capacitor electrodes SUE3-1 can be connected to the first node N1. For example, corresponding sides of the third first sub-capacitor electrodes SUE3-1 can be connected to the first node electrode NE1-1 of the first node N1. The first node electrode NE1-1 and the multiple third first sub-capacitor electrodes SUE3-1 can be integrally formed together.

[0211] like Figure 8 As shown, each of the fourth first sub-capacitor electrodes SUE4-1 can extend along the second direction DR2. The fourth first sub-capacitor electrodes SUE4-1 can be arranged along the first direction DR1. Corresponding sides of the fourth first sub-capacitor electrodes SUE4-1 can be connected to each other. For example, corresponding sides of multiple fourth first sub-capacitor electrodes SUE4-1 can be connected to the reference voltage line VRL.

[0212] According to one or more embodiments, such as Figure 8 As shown, the third first sub-capacitor electrode SUE3-1 can be located between two fourth first sub-capacitor electrodes SUE4-1 that are adjacent to each other in the first direction DR1.

[0213] According to one or more embodiments, when the third first sub-capacitor electrode SUE3-1 and the fourth first sub-capacitor electrode SUE4-1 positioned along the first direction DR1 are defined as the second sub-capacitor electrode group, the fourth first sub-capacitor electrode SUE4-1 can be located at the outermost portion of the second sub-capacitor electrode group. For example, any fourth first sub-capacitor electrode SUE4-1 located at the outermost portion on one side and any fourth first sub-capacitor electrode SUE4-1 located at the outermost portion on the other side can be located at the outermost portions on both sides of the second sub-capacitor electrode group, respectively. In other words, the fourth first sub-capacitor electrodes SUE4-1 located at the outermost portions on both sides can be located at the outermost portions on both sides of the second sub-capacitor electrode group, respectively.

[0214] The third connecting electrode CNE3 can be positioned close to the second first sub-capacitor electrode SUE2-1. For example, the third connecting electrode CNE3 can be positioned adjacent to the second first sub-capacitor electrode SUE2-1 located on the outermost part of one side of the second first sub-capacitor electrode SUE2-1 in the first direction DR1.

[0215] like Figure 9 As shown, both the first and second sub-capacitor electrodes SUE1-2 can extend along the second direction DR2. The first and second sub-capacitor electrodes SUE1-2 can be arranged along the first direction DR1. Corresponding sides of the first and second sub-capacitor electrodes SUE1-2 can be connected to each other. For example, corresponding sides of multiple first and second sub-capacitor electrodes SUE1-2 can be connected to the first node N1. For example, corresponding sides of multiple first and second sub-capacitor electrodes SUE1-2 can be connected to the first and second node electrodes NE1-2 of the first node N1. The first and second node electrodes NE1-2 and the multiple first and second sub-capacitor electrodes SUE1-2 can be integrally formed together.

[0216] like Figure 9 As shown, each of the second sub-capacitor electrodes SUE2-2 can extend along the second direction DR2. The second sub-capacitor electrodes SUE2-2 can be arranged along the first direction DR1. Corresponding sides of the second sub-capacitor electrodes SUE2-2 can be connected to each other. For example, corresponding sides of multiple second sub-capacitor electrodes SUE2-2 can be connected to the second node N2.

[0217] According to one or more embodiments, such as Figure 9 As shown, the first and second sub-capacitor electrodes SUE1-2 can be located between two second sub-capacitor electrodes SUE2-2 that are adjacent to each other in the first direction DR1.

[0218] According to one or more embodiments, when the first second sub-capacitor electrode SUE1-2 and the second second sub-capacitor electrode SUE2-2 positioned along the first direction DR1 are defined as a third sub-capacitor electrode group, the second second sub-capacitor electrode SUE2-2 can be located at the outermost portion of the third sub-capacitor electrode group. For example, any second second sub-capacitor electrode SUE2-2 located at the outermost portion on one side and any second second sub-capacitor electrode SUE2-2 located at the outermost portion on the other side can be located at the outermost portions on both sides of the third sub-capacitor electrode group, respectively. In other words, the second second sub-capacitor electrodes SUE2-2 located at the outermost portions on both sides can be located at the outermost portions on both sides of the third sub-capacitor electrode group, respectively.

[0219] In addition, such as Figure 9 As shown, the third and second sub-capacitor electrodes SUE3-2 can all extend along the second direction DR2. The third and second sub-capacitor electrodes SUE3-2 can be arranged along the first direction DR1. Corresponding sides of the third and second sub-capacitor electrodes SUE3-2 can be connected to each other. For example, corresponding sides of multiple third and second sub-capacitor electrodes SUE3-2 can be connected to the first node N1. For example, corresponding sides of the third and second sub-capacitor electrodes SUE3-2 can be connected to the first and second node electrodes NE1-2 of the first node N1. The first and second node electrodes NE1-2 and multiple third and second sub-capacitor electrodes SUE3-2 can be integrally formed together.

[0220] like Figure 9 As shown, the fourth second sub-capacitor electrodes SUE4-2 can all extend along the second direction DR2. The fourth second sub-capacitor electrodes SUE4-2 can be arranged along the first direction DR1. The corresponding sides of the fourth second sub-capacitor electrodes SUE4-2 can be connected to each other. For example, the corresponding sides of a plurality of fourth second sub-capacitor electrodes SUE4-2 can be connected to the reference voltage line VRL.

[0221] According to one or more embodiments, such as Figure 9 As shown, the third second sub-capacitor electrode SUE3-2 can be located between two fourth second sub-capacitor electrodes SUE4-2 that are adjacent to each other in the first direction DR1.

[0222] According to one or more embodiments, when the third second sub-capacitor electrode SUE3-2 and the fourth second sub-capacitor electrode SUE4-2 positioned along the first direction DR1 are defined as a fourth sub-capacitor electrode group, the fourth second sub-capacitor electrode SUE4-2 can be located at the outermost portion of the fourth sub-capacitor electrode group. For example, any fourth second sub-capacitor electrode SUE4-2 located at the outermost portion on one side and any fourth second sub-capacitor electrode SUE4-2 located at the outermost portion on the other side can be located at the outermost portions on both sides of the fourth sub-capacitor electrode group, respectively. In other words, the fourth second sub-capacitor electrodes SUE4-2 located at the outermost portions on both sides can be located at the outermost portions on both sides of the fourth sub-capacitor electrode group, respectively.

[0223] The first sub-data line SDL1 can be positioned close to the second sub-capacitor electrode SUE2-2 and the fourth sub-capacitor electrode SUE4-2. For example, in the first direction DR1, the first sub-data line SDL1 can be positioned adjacent to the second sub-capacitor electrode SUE2-2 located at the outermost portion on one side of the second sub-capacitor electrode SUE2-2, and adjacent to the fourth sub-capacitor electrode SUE4-2 located at the outermost portion on one side of the fourth sub-capacitor electrode SUE4-2.

[0224] like Figure 10 As shown, the first and third sub-capacitor electrodes SUE1-3 can all extend along the second direction DR2. The first and third sub-capacitor electrodes SUE1-3 can be arranged along the first direction DR1. Corresponding sides of the first and third sub-capacitor electrodes SUE1-3 can be connected to each other. For example, corresponding sides of multiple first and third sub-capacitor electrodes SUE1-3 can be connected to the first node N1. For example, corresponding sides of multiple first and third sub-capacitor electrodes SUE1-3 can be connected to the first and third node electrode NE1-3 of the first node N1. The first and third node electrode NE1-3 and the multiple first and third sub-capacitor electrodes SUE1-3 can be integrally formed together.

[0225] like Figure 10 As shown, both the second and third sub-capacitor electrodes SUE2-3 can extend along the second direction DR2. The second and third sub-capacitor electrodes SUE2-3 can be arranged along the first direction DR1. Corresponding sides of the second and third sub-capacitor electrodes SUE2-3 can be connected to each other. For example, corresponding sides of multiple second and third sub-capacitor electrodes SUE2-3 can be connected to the second node N2.

[0226] According to one or more embodiments, such as Figure 10 As shown, the first and third sub-capacitor electrodes SUE1-3 can be located between two second and third sub-capacitor electrodes SUE2-3 that are adjacent to each other in the first direction DR1.

[0227] According to one or more embodiments, when the first third sub-capacitor electrode SUE1-3 and the second third sub-capacitor electrode SUE2-3 positioned along the first direction DR1 are defined as the fifth sub-capacitor electrode group, the second third sub-capacitor electrode SUE2-3 can be located at the outermost portion of the fifth sub-capacitor electrode group. For example, any second third sub-capacitor electrode SUE2-3 located at the outermost portion on one side and any second third sub-capacitor electrode SUE2-3 located at the outermost portion on the other side can be located at the outermost portions on both sides of the fifth sub-capacitor electrode group, respectively. In other words, the second third sub-capacitor electrodes SUE2-3 located at the outermost portions on both sides can be located at the outermost portions on both sides of the fifth sub-capacitor electrode group, respectively.

[0228] In addition, such as Figure 10 As shown, the third sub-capacitor electrodes SUE3-3 can all extend along the second direction DR2. The third sub-capacitor electrodes SUE3-3 can be arranged along the first direction DR1. Corresponding sides of the third sub-capacitor electrodes SUE3-3 can be connected to each other. For example, corresponding sides of multiple third sub-capacitor electrodes SUE3-3 can be connected to the first node N1. For example, corresponding sides of the third sub-capacitor electrodes SUE3-3 can be connected to the first third node electrode NE1-3 of the first node N1. The first third node electrode NE1-3 and the multiple third sub-capacitor electrodes SUE3-3 can be integrally formed together.

[0229] like Figure 10 As shown, the fourth and third sub-capacitor electrodes SUE4-3 can all extend along the second direction DR2. The fourth and third sub-capacitor electrodes SUE4-3 can be arranged along the first direction DR1. The corresponding sides of the fourth and third sub-capacitor electrodes SUE4-3 can be connected to each other. For example, the corresponding sides of a plurality of fourth and third sub-capacitor electrodes SUE4-3 can be connected to the reference voltage line VRL.

[0230] According to one or more embodiments, such as Figure 10 As shown, the third sub-capacitor electrode SUE3-3 can be located between two fourth sub-capacitor electrodes SUE4-3 that are adjacent to each other in the first direction DR1.

[0231] According to one or more embodiments, when the third sub-capacitor electrode SUE3-3 and the fourth sub-capacitor electrode SUE4-3 positioned along the first direction DR1 are defined as the sixth sub-capacitor electrode group, the fourth sub-capacitor electrode SUE4-3 can be located at the outermost portion of the sixth sub-capacitor electrode group. For example, any fourth sub-capacitor electrode SUE4-3 located at the outermost portion on one side and any fourth sub-capacitor electrode SUE4-3 located at the outermost portion on the other side can be located at the outermost portions on both sides of the sixth sub-capacitor electrode group, respectively. In other words, the fourth sub-capacitor electrodes SUE4-3 located at the outermost portions on both sides can be located at the outermost portions on both sides of the sixth sub-capacitor electrode group, respectively.

[0232] The second sub-data line SDL2 can be positioned close to the second and third sub-capacitor electrodes SUE2-3 and SUE4-3. For example, in the first direction DR1, the second sub-data line SDL2 can be positioned adjacent to the second and third sub-capacitor electrode SUE2-3 located at the outermost portion on one side of the second and third sub-capacitor electrodes SUE2-3, and adjacent to the fourth and third sub-capacitor electrode SUE4-3 located at the outermost portion on one side of the fourth and third sub-capacitor electrodes SUE4-3.

[0233] like Figure 11 As shown, the first and fourth sub-capacitor electrodes SUE1-4 can all extend along the second direction DR2. The first and fourth sub-capacitor electrodes SUE1-4 can be arranged along the first direction DR1. Corresponding sides of the first and fourth sub-capacitor electrodes SUE1-4 can be connected to each other. For example, corresponding sides of multiple first and fourth sub-capacitor electrodes SUE1-4 can be connected to the first node N1. For example, corresponding sides of multiple first and fourth sub-capacitor electrodes SUE1-4 can be connected to the first and third node electrodes NE1-3 of the first node N1.

[0234] like Figure 11 As shown, both the second and fourth sub-capacitor electrodes SUE2-4 can extend along the second direction DR2. The second and fourth sub-capacitor electrodes SUE2-4 can be arranged along the first direction DR1. Corresponding sides of the second and fourth sub-capacitor electrodes SUE2-4 can be connected to each other. For example, corresponding sides of multiple second and fourth sub-capacitor electrodes SUE2-4 can be connected to the second node N2.

[0235] According to one or more embodiments, such as Figure 11As shown, the first fourth sub-capacitor electrode SUE1-4 can be located between two second fourth sub-capacitor electrodes SUE2-4 that are adjacent to each other in the first direction DR1.

[0236] According to one or more embodiments, when the first fourth sub-capacitor electrode SUE1-4 and the second fourth sub-capacitor electrode SUE2-4 positioned along the first direction DR1 are defined as the seventh sub-capacitor electrode group, the second fourth sub-capacitor electrode SUE2-4 can be located at the outermost portion of the seventh sub-capacitor electrode group. For example, any second fourth sub-capacitor electrode SUE2-4 located at the outermost portion on one side and any second fourth sub-capacitor electrode SUE2-4 located at the outermost portion on the other side can be located at the outermost portions on both sides of the seventh sub-capacitor electrode group, respectively. In other words, the second fourth sub-capacitor electrodes SUE2-4 located at the outermost portions on both sides can be located at the outermost portions on both sides of the seventh sub-capacitor electrode group, respectively.

[0237] In addition, such as Figure 11 As shown, the third and fourth sub-capacitor electrodes SUE3-4 can both extend along the second direction DR2. The third and fourth sub-capacitor electrodes SUE3-4 can be arranged along the first direction DR1. Corresponding sides of the third and fourth sub-capacitor electrodes SUE3-4 can be connected to each other. For example, corresponding sides of multiple third and fourth sub-capacitor electrodes SUE3-4 can be connected to the first node N1. For example, corresponding sides of the third and fourth sub-capacitor electrodes SUE3-4 can be connected to the first third node electrode NE1-3 of the first node N1.

[0238] like Figure 11 As shown, the fourth sub-capacitor electrodes SUE4-4 can all extend along the second direction DR2. The fourth sub-capacitor electrodes SUE4-4 can be arranged along the first direction DR1. The corresponding sides of the fourth sub-capacitor electrodes SUE4-4 can be connected to each other. For example, the corresponding sides of multiple fourth sub-capacitor electrodes SUE4-4 can be connected to the reference voltage line VRL.

[0239] According to one or more embodiments, such as Figure 11 As shown, the third and fourth sub-capacitor electrodes SUE3-4 can be located between two fourth sub-capacitor electrodes SUE4-4 that are adjacent to each other in the first direction DR1.

[0240] According to one or more embodiments, when the third and fourth sub-capacitor electrodes SUE3-4 and the fourth sub-capacitor electrode SUE4-4 positioned along the first direction DR1 are defined as the eighth sub-capacitor electrode group, the fourth sub-capacitor electrode SUE4-4 can be located at the outermost portion of the eighth sub-capacitor electrode group. For example, any fourth sub-capacitor electrode SUE4-4 located at the outermost portion on one side and any fourth sub-capacitor electrode SUE4-4 located at the outermost portion on the other side can be located at the outermost portions on both sides of the eighth sub-capacitor electrode group, respectively. In other words, the fourth sub-capacitor electrodes SUE4-4 located at the outermost portions on both sides can be located at the outermost portions on both sides of the eighth sub-capacitor electrode group, respectively.

[0241] like Figure 12 As shown, the first insulating film INS1' may be located on the semiconductor backplane SBP. Here, the semiconductor backplane SBP may include a transistor region TRA in which the pixel transistor PTR as described above is positioned.

[0242] A first conductive layer, including a first connection electrode CNE1, a write scan line GWL, and an emit control line EL, may be located on a first insulating film INS1'. Simultaneously, the aforementioned bias scan line EBL may be further located at the first conductive layer. At least one of the components of the first conductive layer can be connected to at least one of the pixel transistors in the transistor region TRA via a first via VA1'. For example, the first connection electrode CNE1, which is any one of the components of the first conductive layer, can be connected to the source electrode of the second transistor T2 via the first via VA1'.

[0243] The second insulating film INS2' can be located on the first conductive layer.

[0244] A second conductive layer, including the initialization voltage line VIL and the drive voltage line VDL, may be located on the second insulating film INS2'. At least one component of the second conductive layer may be connected to the first conductive layer via a second via VA2'. For example, a second connection electrode CNE2, which is any component of the second conductive layer, may be connected to a first connection electrode CNE1 via the second via VA2'.

[0245] The third insulating film INS3' can be located on the second conductive layer.

[0246] A third conductive layer comprising a third connecting electrode CNE3, a plurality of second first sub-capacitor electrodes SUE2-1, and a plurality of first first sub-capacitor electrodes SUE1-1 may be located on a third insulating film INS3'. According to one or more embodiments, the second first sub-capacitor electrodes SUE2-1 and the first first sub-capacitor electrodes SUE1-1 on the third insulating film INS3' may be alternately positioned along a first direction DR1. In this case, the second first sub-capacitor electrode SUE2-1 among the sub-capacitor electrodes on the third insulating film INS3' may be located at the outermost portion. For example, when the second first sub-capacitor electrodes SUE2-1 and the first first sub-capacitor electrodes SUE1-1 are defined as a first sub-capacitor electrode group as described above, the second first sub-capacitor electrode SUE2-1 may be located at the outermost portion of the first sub-capacitor electrode group. At least one of the components of the third conductive layer may be connected to the second conductive layer via a third via VA3'. For example, the third connecting electrode CNE3, which is any one of the components of the third conductive layer, may be connected to the second connecting electrode CNE2 via the third via VA3'.

[0247] The fourth insulating film INS4' can be located on the third conductive layer.

[0248] A fourth conductive layer, comprising a first sub-data line SDL1, a plurality of second sub-capacitor electrodes SUE2-2, and a plurality of first sub-capacitor electrodes SUE1-2, may be located on a fourth insulating film INS4'. According to one or more embodiments, the second sub-capacitor electrodes SUE2-2 and the first sub-capacitor electrodes SUE1-2 on the fourth insulating film INS4' may be alternately positioned along a first direction DR1. In this case, the second sub-capacitor electrode SUE2-2 among the sub-capacitor electrodes on the fourth insulating film INS4' may be located at the outermost portion. For example, when the second sub-capacitor electrode SUE2-2 and the first sub-capacitor electrode SUE1-2 are defined as a third sub-capacitor electrode group as described above, the second sub-capacitor electrode SUE2-2 may be located at the outermost portion of the third sub-capacitor electrode group. At least one of the components of the fourth conductive layer may be connected to the third conductive layer via a fourth via VA4'. For example, the first sub-data line SDL1, which is any one of the components of the fourth conductive layer, may be connected to the third connection electrode CNE3 via the fourth via VA4'.

[0249] The fifth insulating film INS5' can be located on the fourth conductive layer.

[0250] A fifth conductive layer comprising a second sub-data line SDL2, a plurality of second and third sub-capacitor electrodes SUE2-3, and a plurality of first and third sub-capacitor electrodes SUE1-3 may be located on a fifth insulating film INS5'. According to one or more embodiments, the second and third sub-capacitor electrodes SUE2-3 and the first and third sub-capacitor electrodes SUE1-3 on the fifth insulating film INS5' may be alternately positioned along a first direction DR1. In this case, the second and third sub-capacitor electrodes SUE2-3 among the sub-capacitor electrodes on the fifth insulating film INS5' may be located at the outermost portion. For example, when the second and third sub-capacitor electrodes SUE2-3 and the first and third sub-capacitor electrodes SUE1-3 are defined as a fifth sub-capacitor electrode group as described above, the second and third sub-capacitor electrodes SUE2-3 may be located at the outermost portion of the fifth sub-capacitor electrode group. At least one of the components of the fifth conductive layer may be connected to a fourth conductive layer via a fifth via VA5'. For example, the second sub-data line SDL2, which is any one of the components of the fifth conductive layer, may be connected to the first sub-data line SDL1 via the fifth via VA5'.

[0251] The sixth insulating film INS6' can be located on the fifth conductive layer.

[0252] A sixth conductive layer comprising a plurality of second and fourth sub-capacitor electrodes SUE2-4 and a plurality of first and fourth sub-capacitor electrodes SUE1-4 may be located on a sixth insulating film INS6'. According to one or more embodiments, the second and fourth sub-capacitor electrodes SUE2-4 and the first and fourth sub-capacitor electrodes SUE1-4 on the sixth insulating film INS6' may be alternately positioned along a first direction DR1. In this case, the second and fourth sub-capacitor electrodes SUE2-4 among the sub-capacitor electrodes on the sixth insulating film INS6' may be located at the outermost portion. For example, when the second and fourth sub-capacitor electrodes SUE2-4 and the first and fourth sub-capacitor electrodes SUE1-4 are defined as a seventh sub-capacitor electrode group as described above, the second and fourth sub-capacitor electrodes SUE2-4 may be located at the outermost portion of the seventh sub-capacitor electrode group.

[0253] The sub-capacitor electrodes of the first capacitor C1 that are stacked on the third-direction DR3 can be electrically connected to each other. For example, the second first sub-capacitor electrode SUE2-1, the second second sub-capacitor electrode SUE2-2, the second third sub-capacitor electrode SUE2-3, and the second fourth sub-capacitor electrode SUE2-4 that are stacked on the third-direction DR3 can be connected to each other. In addition, the first first sub-capacitor electrode SUE1-1, the first second sub-capacitor electrode SUE1-2, the first third sub-capacitor electrode SUE1-3, and the first fourth sub-capacitor electrode SUE1-4 that are stacked on the third-direction DR3 can be connected to each other.

[0254] The sub-capacitor electrodes of the second capacitor C2, which are stacked on the third direction DR3, can be electrically connected to each other. For example, the third first sub-capacitor electrode SUE3-1, the third second sub-capacitor electrode SUE3-2, the third third sub-capacitor electrode SUE3-3, and the third fourth sub-capacitor electrode SUE3-4, which are stacked on the third direction DR3, can be connected to each other. In addition, the fourth first sub-capacitor electrode SUE4-1, the fourth second sub-capacitor electrode SUE4-2, the fourth third sub-capacitor electrode SUE4-3, and the fourth fourth sub-capacitor electrode SUE4-4, which are stacked on the third direction DR3, can be connected to each other.

[0255] According to one or more embodiments, for example, the first capacitor electrode CPE1 connected to the gate node (e.g., first node N1) of the driving transistor (e.g., T1) can be shielded by the second capacitor electrode CPE2. In other words, the outermost sub-capacitor electrode of the second capacitor electrode CPE2 is located outside the outermost sub-capacitor electrode of the first capacitor electrode CPE1. Therefore, the outermost sub-capacitor electrode of the second capacitor electrode CPE2 can be located between the outermost sub-capacitor electrode of the first capacitor C1 and the data line (e.g., the first sub-data line SDL1 or the second sub-data line SDL2). Therefore, the second capacitor electrode CPE2 can reduce or prevent the possibility of coupling between the first capacitor electrode CPE1 connected to the gate node and the data line (e.g., coupling between the first capacitor electrode CPE1 and the data line DL caused by the parasitic capacitance between the first capacitor electrode CPE1 and the data line DL). Therefore, the voltage of the first capacitor electrode CPE1 can be stably maintained even if the voltage of the data line DL changes. Ultimately, regardless of changes in the voltage of the data line DL, the voltage of the gate node (e.g., the first node N1) can be maintained stably. Therefore, fluctuations in the drive current flowing through the drive transistor connected to the gate node can be reduced or minimized. Consequently, the image quality of the display device can be improved.

[0256] As an example, such as Figure 12As shown, when the first sub-capacitor electrode SUE1-2, among the four first and second sub-capacitor electrodes SUE1-2, closest to the first sub-data line SDL1 in the first direction DR1, is defined as the first outermost sub-capacitor electrode, and when the second sub-capacitor electrode SUE2-2, among the five second sub-capacitor electrodes SUE2-2, closest to the first sub-data line SDL1, is defined as the second outermost sub-capacitor electrode, the second outermost sub-capacitor electrode can be located between the first sub-data line SDL1 and the first outermost sub-capacitor electrode. In other words, when the first sub-capacitor electrode SUE1-2, located at the outermost portion on one side, among the four first and second sub-capacitor electrodes SUE1-2, is defined as the aforementioned first outermost sub-capacitor electrode, and when the second sub-capacitor electrode SUE2-2, located at the outermost portion on one side, among the five second sub-capacitor electrodes SUE2-2, is defined as the aforementioned second outermost sub-capacitor electrode, the second outermost sub-capacitor electrode can be located between the first sub-data line SDL1 and the first outermost sub-capacitor electrode. Therefore, the possibility of coupling between the first outermost sub-capacitor electrode and the first sub-data line SDL1 can be reduced or prevented by using the second outermost sub-capacitor electrode. Thus, even if the voltage of the first sub-data line SDL1 changes, the voltages of the first and second sub-capacitor electrodes SUE1-2 and the gate nodes connected to the first and second sub-capacitor electrodes SUE1-2 can be stably maintained.

[0257] As another example, such as Figure 12As shown, when the first or third sub-capacitor electrode SUE1-3, among the four first or third sub-capacitor electrodes SUE1-3, that is closest to the second sub-data line SDL2 in the first direction DR1, is defined as the third outermost sub-capacitor electrode, and when the second or third sub-capacitor electrode SUE2-3, among the five second or third sub-capacitor electrodes SUE2-3, that is closest to the second sub-data line SDL2, is defined as the fourth outermost sub-capacitor electrode, the fourth outermost sub-capacitor electrode can be located between the second sub-data line SDL2 and the third outermost sub-capacitor electrode. In other words, when the first or third sub-capacitor electrode SUE1-3, among the four first or third sub-capacitor electrodes SUE1-3, that is located at the outermost portion on one side, is defined as the aforementioned third outermost sub-capacitor electrode, and when the second or third sub-capacitor electrode SUE2-3, among the five second or third sub-capacitor electrodes SUE2-3, that is located at the outermost portion on one side, is defined as the aforementioned fourth outermost sub-capacitor electrode, the fourth outermost sub-capacitor electrode can be located between the second sub-data line SDL2 and the third outermost sub-capacitor electrode. Therefore, the coupling between the third outermost sub-capacitor electrode and the second sub-data line SDL2 can be reduced or prevented by the fourth outermost sub-capacitor electrode. Thus, although the voltage of the second sub-data line SDL2 changes, the voltage of the first and third sub-capacitor electrodes SUE1-3 and the gate node connected to the first and third sub-capacitor electrodes SUE1-3 can be stably maintained.

[0258] Meanwhile, when one of the four first and second sub-capacitor electrodes SUE1-2 located at the outermost part on the other side is defined as the fifth outermost sub-capacitor electrode, and when one of the five second sub-capacitor electrodes SUE2-2 located at the outermost part on the other side is defined as the sixth outermost sub-capacitor electrode, the aforementioned four first and second sub-capacitor electrodes SUE1-2 can be located between the aforementioned second outermost sub-capacitor electrode and the sixth outermost sub-capacitor electrode.

[0259] Meanwhile, when one of the four first and third sub-capacitor electrodes SUE1-3 located at the outermost part on the other side is defined as the seventh outermost sub-capacitor electrode, and when one of the five second and third sub-capacitor electrodes SUE2-3 located at the outermost part on the other side is defined as the eighth outermost sub-capacitor electrode, the aforementioned four first and third sub-capacitor electrodes SUE1-3 can be located between the aforementioned fourth outermost sub-capacitor electrode and the eighth outermost sub-capacitor electrode.

[0260] In addition, such as Figure 12As shown, a power line (e.g., the initialization voltage line VIL) is connected between a data line (e.g., the first sub-data line SDL1) and a scan line (e.g., the write scan line GWL). The possibility of coupling between the data line DL and the scan line can be reduced or prevented via the power line. Therefore, the RC delay of the data signal (e.g., the data signal on the data line DL) caused by such coupling can be reduced or minimized.

[0261] At the same time, such as Figure 12 As shown, the data line DL may also include a third sub-data line SDL3. For example, the data line DL may include a first sub-data line SDL1, a second sub-data line SDL2, and a third sub-data line SDL3 connected to each other through vias VA5' and VA6'.

[0262] The third sub-data line SDL3 can be located on the same layer as the second and fourth sub-capacitor electrodes SUE2-4. For example, the third sub-data line SDL3 can be located on the sixth insulating film INS6'.

[0263] According to one or more embodiments, the data lines may include multiple sub-data lines interconnected on a third-direction DR3. In this case, the resistance of the data lines can be reduced, thereby further reducing or minimizing the RC delay of the data signal.

[0264] Figure 13 yes Figure 9 A magnified view of region A.

[0265] like Figure 13 As shown, the end 11 of the second sub-capacitor electrode SUE2-2 located at the outermost portion among the plurality of second sub-capacitor electrodes SUE2-2 and the end 12 of the first connection portion 131 between the plurality of first sub-capacitor electrodes SUE1-2 can be aligned with each other. For example, the end 11 of the second sub-capacitor electrode SUE2-2 located at the outermost portion and the end 12 of the first connection portion 131 can be located on the virtual first line VL1. Therefore, the first connection portion 131 between the first sub-capacitor electrodes SUE1-2 can be shielded by the outermost second sub-capacitor electrode SUE2-2.

[0266] In addition, such as Figure 13As shown, the end 21 of the fourth second sub-capacitor electrode SUE4-2 located at the outermost portion among the plurality of fourth second sub-capacitor electrodes SUE4-2 and the end 22 of the second connection portion 132 between the plurality of third second sub-capacitor electrodes SUE3-2 can be aligned with each other. For example, the end 21 of the fourth second sub-capacitor electrode SUE4-2 located at the outermost portion and the end 22 of the second connection portion 132 can be located on the virtual second line VL2. Therefore, the second connection portion 132 between the third second sub-capacitor electrodes SUE3-2 can be shielded by the outermost fourth second sub-capacitor electrode SUE4-2.

[0267] Meanwhile, the first connecting portion 131 and the second connecting portion 132 can be connected to the first and third sub-capacitor electrodes SUE1-3 and the third sub-capacitor electrode SUE3-3 through the contact hole CT of the insulating film.

[0268] at the same time, Figure 10 Each of the first and third sub-capacitor electrodes SUE1-3, the second and third sub-capacitor electrodes SUE2-3, the third and third sub-capacitor electrodes SUE3-3, and the fourth and third sub-capacitor electrodes SUE4-3 may also have the same characteristics as described above. Figure 13 The constructed described are the same as the constructed.

[0269] Figure 14 It is a view used to describe the arrangement of sub-capacitor electrodes between multiple data lines that are adjacent to each other.

[0270] like Figure 14 As shown, among the plurality of second sub-capacitor electrodes SUE2-2, the second sub-capacitor electrode SUE2-2 located at the outermost portion on one side can be positioned adjacent to the first sub-data line SDL1 of the first data line, and another second sub-capacitor electrode SUE2-2 located at the outermost portion on the other side can be positioned adjacent to the first sub-data line SDL1' of the second data line.

[0271] like Figure 14 As shown, the fourth second sub-capacitor electrode SUE4-2 located at the outermost portion on one side of the plurality of fourth second sub-capacitor electrodes SUE4-2 can be positioned adjacent to the first sub-data line SDL1 of the first data line, and another fourth second sub-capacitor electrode SUE4-2 located at the outermost portion on the other side of the plurality of fourth second sub-capacitor electrodes SUE4-2 can be positioned adjacent to the first sub-data line SDL1' of the second data line.

[0272] Figure 15 It is a cross-sectional view of a display panel according to one or more other embodiments.

[0273] Figure 15 The display panel 100 and the reference above Figure 12 The difference in the described display panel 100 lies in the arrangement of the sub-data cables, and this difference will be mainly described below.

[0274] like Figure 15 As shown, the data line DL may include a first sub-data line SDL1 and a second sub-data line SDL2. Additionally, the data line DL may also include at least one of a third sub-data line SDL3 and a fourth sub-data line SDL4. For example, the data line DL may include the first sub-data line SDL1, the second sub-data line SDL2, the third sub-data line SDL3, and the fourth sub-data line SDL4 connected to each other via vias VA4', VA5', and VA6'.

[0275] The third sub-data line SDL3 can be located on the same layer as the second first sub-capacitor electrode SUE2-1. For example, the third sub-data line SDL3 can be located on the third insulating film INS3'.

[0276] The fourth sub-data line SDL4 can be located on the same layer as the second and fourth sub-capacitor electrodes SUE2-4. For example, the fourth sub-data line SDL4 can be located on the sixth insulating film INS6'.

[0277] According to one or more embodiments, the data line DL may include multiple sub-data lines connected to each other on the third-direction DR3. In this case, the resistance of the data line DL can be reduced, thereby further reducing or minimizing the RC delay of the data signal.

[0278] Figure 16 It is a cross-sectional view of a display panel according to yet another or one other embodiment.

[0279] Figure 16 The display panel 100 and the reference above Figure 12 The difference in the described display panel 100 lies in the arrangement of the sub-data cables, and this difference will be mainly described below.

[0280] like Figure 16 As shown, the data line DL may include a first sub-data line SDL1 as a single sub-data line. Simultaneously, the data line DL may also include at least one of a second sub-data line SDL2 and a third sub-data line SDL3. For example, the data line DL may include a first sub-data line SDL1, a second sub-data line SDL2, and a third sub-data line SDL3 connected to each other via vias VA4' and VA5'.

[0281] The second sub-data line SDL2 can be located on the same layer as the second first sub-capacitor electrode SUE2-1. For example, the second sub-data line SDL2 can be located on the third insulating film INS3'.

[0282] The third sub-data line SDL3 can be located on the same layer as the second and third sub-capacitor electrodes SUE2-3. For example, the third sub-data line SDL3 can be located on the fifth insulating film INS5'.

[0283] According to one or more embodiments, the data line DL may include multiple sub-data lines connected to each other on the third-direction DR3. In this case, the resistance of the data line DL can be reduced, thereby further reducing or minimizing the RC delay of the data signal.

[0284] Figure 17 It is a cross-sectional view of a display panel according to yet another or one other embodiment.

[0285] Figure 17 The display panel 100 and the reference above Figure 12 The difference in the described display panel 100 lies in the arrangement of the sub-data lines and the arrangement of some conductive layers, which will be mainly described below.

[0286] like Figure 17 As shown, the data line DL may include a first sub-data line SDL1 and a second sub-data line SDL2. Additionally, the data line may also include at least one of a third sub-data line SDL3 and a fourth sub-data line SDL4. For example, the data line may include the first sub-data line SDL1, the second sub-data line SDL2, the third sub-data line SDL3, and the fourth sub-data line SDL4 connected to each other via vias VA3', VA4', and VA5'.

[0287] The third sub-data line SDL3 can be located on the same layer as the second first sub-capacitor electrode SUE2-1. For example, the third sub-data line SDL3 can be located on the second insulating film INS2'.

[0288] The fourth sub-data line SDL4 can be located on the same layer as the second and fourth sub-capacitor electrodes SUE2-4. For example, the fourth sub-data line SDL4 can be located on the fifth insulating film INS5'.

[0289] According to one or more embodiments, the data line DL may include multiple sub-data lines connected to each other on the third-direction DR3. In this case, the resistance of the data line DL can be reduced, thereby further reducing or minimizing the RC delay of the data signal.

[0290] In addition, such as Figure 17As shown, the initialization voltage line VIL and the drive voltage line VDL can be located on the first capacitor C1.

[0291] At the same time, such as in Figure 12 , Figure 15 and Figure 17 In the example shown, in the cross-sectional view, the data line DL may be located on the same layer as the intermediate sub-capacitor electrode of the first capacitor C1. The intermediate sub-capacitor electrode may refer to the sub-capacitor electrode positioned in the middle of a plurality of sub-capacitor electrodes stacked on top of each other in the vertical direction (e.g., the third direction DR3) in the cross-sectional view. Figure 12 , Figure 15 and Figure 17 The intermediate sub-capacitor electrodes may include, for example, multiple first and second sub-capacitor electrodes SUE1-2, multiple second sub-capacitor electrodes SUE2-2, multiple first and third sub-capacitor electrodes SUE1-3, and multiple second and third sub-capacitor electrodes SUE2-3. The first sub-data line SDL1 of the data line DL may be located on the same layer as the multiple first and second capacitor electrodes SUE1-2 and the multiple second sub-capacitor electrodes SUE2-2. Additionally, the second sub-data line SDL2 of the data line DL may be located on the same layer as the multiple first and third capacitor electrodes SUE1-3 and the multiple second and third sub-capacitor electrodes SUE2-3.

[0292] Additionally, as in Figure 16 In the example shown, in the cross-sectional view, the data line DL can be located on the same layer as the intermediate sub-capacitor electrode of the first capacitor C1. Here, Figure 16 The intermediate sub-capacitor electrodes may include, for example, multiple first and second sub-capacitor electrodes SUE1-2. The data line DL or the first sub-data line SDL1 may be located on the same layer as the multiple first and second sub-capacitor electrodes SUE1-2.

[0293] Figure 18 This is a view illustrating one or more other embodiments of a sub-capacitor electrode in a display device according to one or more embodiments. For example, Figure 18 It can be Figure 9 Enlarged views of one or more other embodiments of region A.

[0294] The second sub-capacitor electrode SUE2-2 and the fourth sub-capacitor electrode SUE4-2, located on the same layer and at the outermost portion, can have an embossed pattern. For example, the facing ends of the second sub-capacitor electrode SUE2-2 and the fourth sub-capacitor electrode SUE4-2 can both have embossed patterns. In this case, the concave portion of the end of the second sub-capacitor electrode SUE2-2 can be positioned to correspond to the convex portion of the end of the fourth sub-capacitor electrode SUE4-2, and the convex portion of the end of the second sub-capacitor electrode SUE2-2 can be positioned to correspond to the concave portion of the end of the fourth sub-capacitor electrode SUE4-2.

[0295] Therefore, according to one or more embodiments, such as Figure 18 As shown, the end of the second sub-capacitor electrode SUE2-2 may include a first extension portion EX1 extending toward the end of the fourth sub-capacitor electrode SUE4-2, and the end of the fourth sub-capacitor electrode SUE4-2 may include a second extension portion EX2 extending toward the end of the second sub-capacitor electrode SUE2-2. In this case, the first extension portion EX1 and the second extension portion EX2 may extend from different regions of their respective ends in a direction opposite to the second direction DR2, so as not to face each other. In other words, the first extension portion EX1 may be located outside the second extension portion EX2, closer to the data line DL than the second extension portion EX2. At the same time, the first extension portion EX1 and the second extension portion EX2 may face each other along the first direction DR1.

[0296] like Figure 18 As shown, when the second sub-capacitor electrode SUE2-2 and the fourth sub-capacitor electrode SUE4-2 respectively include the first extension portion EX1 and the second extension portion EX2, the coupling between the connection portions 131 and 132 and the adjacent data line DL can be further reduced or minimized, thereby further improving the image quality of the display device 10.

[0297] Figure 19 This is a perspective view showing a head-mounted display device according to one or more embodiments. Figure 20 It is shown Figure 19 An exploded perspective view of an example of a head-mounted display device.

[0298] Reference Figure 19 and Figure 20The head-mounted display device 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing portion 1100, a housing portion cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0299] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. Each of the first display device 10_1 and the second display device 10_2 is associated with a reference... Figures 1 to 18 The display devices 10 described are substantially the same, therefore the description of the first display device 10_1 and the second display device 10_2 is omitted.

[0300] The first optical component 1510 may be located between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be located between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0301] The intermediate frame 1400 can be located between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0302] The control circuit board 1600 can be located between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert an externally input image source into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via connectors.

[0303] The control circuit board 1600 can send digital video data DATA corresponding to a left-eye image optimized for the user's left eye to a first display device 10_1, and digital video data DATA corresponding to a right-eye image optimized for the user's right eye to a second display device 10_2. Optionally, the control circuit board 1600 can send the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0304] The display device housing 1100 is used to house a first display device 10_1, a second display device 10_2, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is positioned to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 19 and Figure 20 The first eyepiece 1210 and the second eyepiece 1220 have been shown to be positioned separately, but one or more embodiments of this disclosure are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into a single eyepiece.

[0305] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0306] The headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 can be held in a position where they are respectively positioned over the user's left and right eyes. When the display device housing 1100 is implemented to have a relatively light weight and a relatively small size, the head-mounted display device 1000 may include, for example... Figure 21 The eyeglasses frame shown is not the headband 1300.

[0307] Additionally, the head-mounted display device 1000 may also include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, or a Wi-Fi wireless communication module. ® Module or Bluetooth ® Module (Wi-Fi) ® Bluetooth is a registered trademark of the non-profit Wi-Fi Alliance. ® Bluetooth is a registered trademark of BluetoothSig, Inc., Kirkland, Washington.

[0308] Figure 21This is a perspective view illustrating a head-mounted display according to one or more other embodiments.

[0309] Reference Figure 21 The head-mounted display device 1000_1 according to one or more other embodiments may be an eyeglass-type display device in which the display device housing portion 1200_1 is implemented as lightweight and small in size. The head-mounted display device 1000_1 according to one or more other embodiments may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, eyeglass frame temples 1040 and 1050, an optical component 1060, an optical path conversion component 1070, and a display device housing portion 1200_1.

[0310] The display device housing 1200_1 may include a display device 10_3, an optical component 1060, and a light path conversion component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060, converted into the light path by the light path conversion component 1070, and provided to the user's right eye through the right eye lens 1020. Therefore, the user can view an augmented reality image in which a virtual image displayed on the display device 10_3 through his / her right eye and a real image seen through the right eye lens 1020 are combined.

[0311] Although already Figure 21 The diagram shows the display device housing 1200_1 located at the right end of the support frame 1030, but one or more embodiments of this disclosure are not limited thereto. For example, the display device housing 1200_1 may be located at the left end of the support frame 1030, in which case the image on the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be located at both the left and right ends of the support frame 1030, in which case the user can view the image displayed on the display device 10_3 through both his / her left and right eyes.

[0312] It will be understood by those skilled in the art to which this disclosure pertains that this disclosure may be implemented in other specific forms without altering the technical spirit or essential features of this disclosure. Therefore, it will be understood that the above embodiments are illustrative in all respects and not restrictive. It will be understood that the scope of this disclosure is defined by the claims rather than the foregoing detailed description, and that all modifications and alterations derived from the claims and their equivalents fall within the scope of this disclosure.

Claims

1. A display device, characterized by comprising: The display device includes: Base; The light-emitting element is located above the substrate; A transistor is connected to the light-emitting element; The first node is connected to the gate electrode of the transistor; The second node is connected to the source electrode of the transistor; and A capacitor is connected between the first node and the second node, and the capacitor includes: a first capacitor electrode connected to the first node and including a first sub-capacitor electrode; and a second capacitor electrode connected to the second node and including a second sub-capacitor electrode located on the same layer as the first sub-capacitor electrode. Wherein, one of the first sub-capacitor electrodes is located between adjacent second sub-capacitor electrodes in the second sub-capacitor electrode.

2. The display device according to claim 1, wherein The first sub-capacitor electrode includes a first outermost sub-capacitor electrode and a second outermost sub-capacitor electrode located on corresponding sides of the first sub-capacitor electrode, and The second sub-capacitor electrode includes a third outermost sub-capacitor electrode and a fourth outermost sub-capacitor electrode located on the corresponding side of the second sub-capacitor electrode.

3. The display device according to claim 2, wherein The first sub-capacitor electrode is located between the third outermost sub-capacitor electrode and the fourth outermost sub-capacitor electrode.

4. The display device according to claim 2, wherein The first outermost subcapacitor electrode is located between the third outermost subcapacitor electrode and the fourth outermost subcapacitor electrode.

5. The display device according to claim 2, wherein The second outermost sub-capacitor electrode is located between the third outermost sub-capacitor electrode and the fourth outermost sub-capacitor electrode.

6. The display device according to claim 2, wherein The first outermost sub-capacitor electrode and the third outermost sub-capacitor electrode are adjacent to each other.

7. The display device according to claim 2, wherein The second outermost sub-capacitor electrode and the fourth outermost sub-capacitor electrode are adjacent to each other.

8. The display device according to claim 2, wherein The display device also includes a first data line adjacent to the third outermost sub-capacitor electrode.

9. The display device according to claim 8, wherein The third outermost sub-capacitor electrode is located between the first data line and the first outermost sub-capacitor electrode.

10. The display device according to claim 8, wherein The display device also includes a second data line adjacent to the fourth outermost sub-capacitor electrode.

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