Display device

Abstract

A display device according to one embodiment includes: a substrate; a first thin-film transistor and a second thin-film transistor; a protective layer; a connection electrode; a sacrificial layer; a first pixel defining film disposed on the protective layer and the sacrificial layer, and including a first opening; a first pixel electrode and a second pixel electrode, the first pixel electrode being disposed on the connection electrode and the second pixel electrode being disposed on the first pixel defining film and connected to the second thin-film transistor; a second pixel defining film disposed on the first pixel defining film and the second pixel electrode, and including a second opening overlapping the first opening; a light-emitting layer including a first organic layer disposed on the first pixel electrode and a second organic layer disposed on the second pixel electrode; a common layer disposed on the light-emitting layer and the second pixel defining film; a common electrode disposed on the common layer; an encapsulation layer disposed on the common electrode; and a light-shielding layer disposed on the encapsulation layer, and including a hole overlapping the first opening and the second opening.

Description

Technical Field

[0001] This utility model relates to a display device. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being used in various electronic devices, such as smartphones, digital cameras, laptops, navigation devices, and smart TVs.

[0003] Display devices can be flat panel display devices, such as liquid crystal display devices, field emission display devices, and light-emitting display devices. Light-emitting display devices include organic light-emitting display devices with organic light-emitting elements, inorganic light-emitting display devices with inorganic light-emitting elements (e.g., inorganic semiconductors), and ultra-miniature light-emitting display devices with ultra-miniature light-emitting elements.

[0004] Since organic light-emitting display devices, which include organic light-emitting elements, do not require light sources such as backlight units, they can be configured as thin, lightweight, and low-power devices. They also have high-quality characteristics such as wide viewing angle, high brightness, high contrast and fast response time. Therefore, organic light-emitting display devices are attracting much attention as the next generation of display devices. Utility Model Content

[0005] Technical issues

[0006] The problem to be solved by this utility model is to provide a display device that can provide a privacy protection mode.

[0007] The subject matter of this utility model is not limited to the subject matter mentioned above, and those skilled in the art will clearly understand other objectives not mentioned from the following description.

[0008] Solution

[0009] A display device according to one embodiment for solving the above-mentioned problems may include: a substrate; a first thin-film transistor and a second thin-film transistor disposed on the substrate; a protective layer disposed on the first thin-film transistor and the second thin-film transistor; a connecting electrode disposed on the protective layer and connected to the first thin-film transistor; a sacrificial layer covering the edge of the connecting electrode; a first pixel defining film disposed on the protective layer and the sacrificial layer and including a first opening; a first pixel electrode and a second pixel electrode, the first pixel electrode being disposed on the connecting electrode, the second pixel electrode being disposed on the first pixel defining film and connected to the second thin-film transistor; a second pixel defining film disposed on the first pixel defining film and the second pixel electrode and including a second opening overlapping the first opening; a light-emitting layer including a first organic layer disposed on the first pixel electrode and a second organic layer disposed on the second pixel electrode; a common layer disposed on the light-emitting layer and the second pixel defining film; a common electrode disposed on the common layer; an encapsulation layer disposed on the common electrode; and a light-shielding layer disposed on the encapsulation layer and including a hole overlapping the first opening and the second opening.

[0010] The side surface of the first pixel defining film may include a tip protruding from the side surface of the sacrificial layer, the first pixel electrode and the second pixel electrode being separated from each other by the tip of the first pixel defining film, and the first organic layer and the second organic layer being separated from each other by the tip of the first pixel defining film.

[0011] The display device may include: a first light-emitting element, including a first pixel electrode, a first organic layer, a common layer, and a common electrode; and a second light-emitting element, including a second pixel electrode, a second organic layer, the common layer, and a common electrode. The first light-emitting element includes a main light-emitting region that overlaps with the first opening and corresponds to the inner peripheral surface of the second pixel electrode. The second light-emitting element includes a peripheral light-emitting region that overlaps with the second pixel electrode, the second organic layer, the common layer, and the common electrode in the thickness direction. The main light-emitting region overlaps with the first opening, the second opening, and the hole. The peripheral light-emitting region does not overlap with the first opening and the hole but overlaps with the second opening.

[0012] In the first light-emitting mode, the same driving voltage can be applied to the first pixel electrode and the second pixel electrode through the first thin-film transistor and the second thin-film transistor to emit light in the light-emitting layer.

[0013] In the second light-emitting mode, a driving voltage can be applied to the first pixel electrode through the first thin-film transistor to emit light in the first organic layer of the light-emitting layer, and the second thin-film transistor is turned off and the driving voltage is not applied to the second pixel electrode to prevent light emission in the second organic layer of the light-emitting layer.

[0014] The light-shielding layer may include: a first light-shielding layer including the hole; a second light-shielding layer spaced apart from the first light-shielding layer and surrounding the first light-shielding layer in a plane; and a surrounding hole disposed between the first light-shielding layer and the second light-shielding layer, wherein the surrounding hole does not overlap with the first opening and overlaps with the second opening.

[0015] The corner where the lower surface and side surface of the first light-shielding layer intersect can intersect with the virtual line. The virtual line passes through the bend of the second pixel electrode from the upper surface of the first pixel electrode, which intersects with the end of the second pixel electrode in the thickness direction. The bend of the second pixel electrode corresponds to the part where the upper surface and side surface of the first pixel electrode intersect.

[0016] Furthermore, a display device according to one embodiment includes a plurality of pixels, each of which includes a plurality of sub-pixels, wherein each of the plurality of sub-pixels includes: a substrate; a first thin-film transistor and a second thin-film transistor disposed on the substrate; a protective layer disposed on the first thin-film transistor and the second thin-film transistor; a first pixel electrode and a second pixel electrode disposed on the protective layer, the first pixel electrode being connected to the first thin-film transistor and the second pixel electrode being connected to the second thin-film transistor; a pixel defining film covering the edge of each of the first pixel electrode and the second pixel electrode, and including a first opening overlapping the first pixel electrode and a second opening overlapping the second pixel electrode; a light-emitting layer including a first organic layer disposed on the first pixel electrode and a second organic layer disposed on the second pixel electrode; a common electrode disposed on the light-emitting layer and the pixel defining film; an encapsulation layer disposed on the common electrode; and a first light-shielding layer and a second light-shielding layer disposed on the encapsulation layer, the first light-shielding layer including a hole overlapping the first opening, and the second light-shielding layer surrounding the first light-shielding layer and including a main hole overlapping the first light-shielding layer.

[0017] The display device may include: a first light-emitting element, including a first pixel electrode, a first organic layer and a common electrode; and a second light-emitting element, including a second pixel electrode, a second organic layer and the common electrode, wherein the second pixel electrode is arranged to be spaced apart from the first pixel electrode and surrounds the first pixel electrode in a plane, the first light-emitting element includes a main light-emitting region that overlaps with the first opening and the hole, and the second light-emitting element includes a surrounding light-emitting region that overlaps with the main hole and does not overlap with the main light-emitting region.

[0018] The display device may further include a peripheral hole disposed between the first light-shielding layer and the second light-shielding layer, wherein the peripheral hole does not overlap with the main light-emitting area but overlaps with the peripheral light-emitting area.

[0019] Specific details of other implementation methods are included in the detailed description and accompanying drawings.

[0020] Beneficial effects

[0021] According to one embodiment, a display device includes multiple light-emitting elements in a sub-pixel, thereby providing a privacy-protected mode where only the user can see the light. Furthermore, by utilizing the tip structure of the pixel-defining film to separately arrange the light-emitting layer and the pixel electrode, the structure can be simplified and the manufacturing process made easier.

[0022] The effects of the embodiments are not limited to those illustrated above, and many more effects are included in this specification. Attached Figure Description

[0023] Figure 1 This is a schematic perspective view of an electronic device according to one embodiment.

[0024] Figure 2 This is a perspective view showing a display device included in an electronic device according to one embodiment.

[0025] Figure 3 Observed from the side surface Figure 2 A cross-sectional view of the display device.

[0026] Figure 4 This is a schematic circuit diagram illustrating a sub-pixel of a pixel in a display device according to one embodiment.

[0027] Figure 5 This is a top view showing a pixel of a display device according to one embodiment.

[0028] Figure 6 It is along Figure 5 A sectional view taken by line X1-X1'.

[0029] Figure 7This is a schematic diagram showing a display device emitting light in a first light-emitting mode according to an embodiment.

[0030] Figure 8 This is a schematic diagram showing a display device emitting light in a second light-emitting mode according to one embodiment.

[0031] Figures 9 to 15 This is a cross-sectional view showing the manufacturing method of a display device according to one embodiment, in accordance with the process.

[0032] Figure 16 This is a top view showing one pixel of a display device according to another embodiment.

[0033] Figure 17 It is along Figure 16 The sectional view taken by line X2-X2'.

[0034] Figure 18 This is a schematic diagram showing a display device emitting light in a first light-emitting mode according to another embodiment.

[0035] Figure 19 This is a schematic diagram illustrating a display device emitting light in a second light-emitting mode according to another embodiment.

[0036] Figure 20 This is a cross-sectional view showing a display device according to yet another embodiment.

[0037] Figure 21 This is a schematic diagram showing a display device emitting light in a first light-emitting mode according to yet another embodiment.

[0038] Figure 22 This is a schematic diagram showing a display device emitting light in a second light-emitting mode according to yet another embodiment.

[0039] Explanation of reference numerals in the attached figures

[0040] 10: Display device SUB: substrate

[0041] TFT1: First thin-film transistor; TFT2: Second thin-film transistor

[0042] PAS1: Protective layer; CNE1: First connecting electrode

[0043] AE1: First pixel electrode; AE2: Second pixel electrode

[0044] EL1: First organic layer; EL2: Second organic layer

[0045] CEL: Public Layer

[0046] PDL1: First pixel limiting film; PDL2: Second pixel limiting film

[0047] CE: Common electrode; TFEL: Encapsulation layer

[0048] BM: Light-shielding layer; SCR: Sacrificial layer Detailed Implementation

[0049] The advantages and features of this invention, as well as the methods of implementing them, will become clear from the accompanying drawings and the embodiments described in detail below. However, this invention is not limited to the embodiments disclosed below, but is implemented in various different ways. These embodiments are provided merely to complete the disclosure of this invention and to fully inform those skilled in the art of its scope, which is defined only by the scope of the claims.

[0050] When an element or layer is referred to as "on" another element or layer, it includes cases where it is directly on top of another element or where other layers or other elements are interposed in between. Similarly, when referred to as "below," "left," and "right," it includes cases where it is directly adjacent to another element or where other layers or other elements are interposed in between. Throughout this specification, the same reference numerals refer to the same constituent elements.

[0051] Although terms such as "first," "second," etc., are used to describe various constituent elements, these constituent elements are not limited by these terms. These terms are only used to distinguish one constituent element from another. Therefore, it is obvious that without departing from the technical concept of this utility model, the first constituent element mentioned below can also be a second constituent element.

[0052] The embodiments will now be described with reference to the accompanying drawings.

[0053] Figure 1 This is a schematic perspective view of an electronic device according to one embodiment.

[0054] Reference Figure 1 Electronic device 1 displays moving or still images. Electronic device 1 can refer to any electronic device that provides a display screen. For example, televisions, laptops, monitors, billboards, IoT devices, mobile phones, smartphones, tablet PCs (Personal Computers), electronic clocks, smartwatches, watch phones, head-mounted displays, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigators, game consoles, digital cameras, camcorders, etc., that provide a display screen can be included in electronic device 1.

[0055] Electronic device 1 may include a display device that provides a display screen ( Figure 2 (10). Examples of display devices include inorganic light-emitting diode (LED) display devices, organic light-emitting diode (OLED) display devices, quantum dot (QD) light-emitting diode (LED) display devices, plasma display devices, field emission display devices, etc. The following example illustrates the application of an organic light-emitting diode (OLED) display device, but it is not limited to this; other display devices can also be applied as long as the same technical concept is applicable.

[0056] The shape of electronic device 1 can be varied. For example, electronic device 1 can be a rectangle with a long horizontal axis, a rectangle with a long vertical axis, a square, a rectangle with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area DA of electronic device 1 can also be similar to the overall shape of electronic device 1. Figure 1 In the example shown, an electronic device 1 with a long rectangular shape on the second direction DR2 is shown.

[0057] Electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is the area where an image can be displayed, and the non-display area NDA is the area where no image is displayed. The display area DA may be referred to as the active area, and the non-display area NDA may be referred to as the inactive area. The display area DA may occupy the center of electronic device 1.

[0058] Figure 2 This is a perspective view showing a display device included in an electronic device according to one embodiment.

[0059] Reference Figure 2 An electronic device 1 according to one embodiment may include a display device 10. The display device 10 can provide an image displayed on the electronic device 1. The display device 10 may have a planar shape similar to that of the electronic device 1. For example, the display device 10 may have a shape similar to a rectangle having a short side in a first direction DR1 and a long side in a second direction DR2. The angle where the short side in the first direction DR1 intersects the long side in the second direction DR2 may be rounded to have curvature, but is not limited thereto, and may also be right angled. The planar shape of the display device 10 is not limited to a rectangle, and may be formed similarly to other polygons, circles, or ellipses.

[0060] The display device 10 may include a display panel 100, a display driver unit 200, and a circuit board 300.

[0061] The display panel 100 may include a main area MA and a sub-area SBA.

[0062] The main region MA may include the display region DA and the non-display region NDA, where the display region DA includes pixels used to display the image. Figure 5 The display panel 100 may include: a pixel circuit including switching elements; a pixel defining film defining the light-emitting area or the opening area; and a self-light-emitting element. The display panel 100 may also include: a pixel circuit including switching elements; a pixel defining film defining the light-emitting area or the opening area; and a self-light-emitting element.

[0063] For example, a self-emissive element may include at least one of the following: an organic light-emitting diode (OLED) with an organic light-emitting layer, a quantum dot LED with a quantum dot light-emitting layer, an inorganic light-emitting diode with an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0064] The non-display area NDA can be the peripheral area of ​​the display area DA. The non-display area NDA can be defined as the edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) that provides gate signals to the gate lines and a fan-out line (not shown) that connects the display driving unit 200 and the display area DA.

[0065] A sub-region SBA can be a region extending from one side of a main region MA. The sub-region SBA can include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-region SBA is bent, it can overlap with the main region MA in the thickness direction (third direction DR3). The sub-region SBA can include a display driver unit 200 and pads connected to the circuit board 300. In another embodiment, the sub-region SBA can be omitted, and the display driver unit 200 and pads can be arranged in a non-display area NDA.

[0066] The display driver unit 200 can output signals and voltages for driving the display panel 100. The display driver unit 200 can supply data voltage to data lines. The display driver unit 200 can supply power voltage to power lines and gate control signals to the gate driver unit. The display driver unit 200 can be formed as an integrated circuit (IC) and mounted on the display panel 100 using a chip-on-glass (COG), chip-on-plastic (COP), or ultrasonic bonding method. For example, the display driver unit 200 can be arranged in a sub-region SBA and can overlap with the main region MA in the thickness direction by bending the sub-region SBA. As another example, the display driver unit 200 can be mounted on a circuit board 300.

[0067] The circuit board 300 can be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 can be electrically connected to the pad portion of the display panel 100. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0068] Figure 3 Observed from the side surface Figure 2 A cross-sectional view of the display device. Figure 3 It shows in Figure 2 The display device 10 shows that the sub-region SBA of the display panel 100 is in a folded state.

[0069] Reference Figure 3 The display panel 100 may include a substrate SUB, a thin film transistor layer (TFTL), a light-emitting element layer (EML), and a packaging layer (TFEL).

[0070] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate SUB can include, but is not limited to, a polymer resin such as polyimide (PI). In another embodiment, the substrate SUB can include a glass material or a metal material.

[0071] A thin-film transistor layer (TFTL) can be disposed on a substrate SUB. The TFTL may include multiple thin-film transistors constituting pixel circuitry. The TFTL may also include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driving unit 200 and the data lines, and leads connecting the display driving unit 200 and the pad units. Each of the thin-film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driving unit is formed on one side of the non-display area NDA of the display panel 100, the gate driving unit may include a thin-film transistor.

[0072] Thin-film transistor (TFTL) layers can be arranged in the display area (DA), the non-display area (NDA), and the sub-area (SBA). The thin-film transistors, gate lines, data lines, and power lines of each pixel in the TFTL can be arranged in the display area (DA). The gate control lines and fan-out lines of the TFTL can be arranged in the non-display area (NDA). The leads of the TFTL can be arranged in the sub-area (SBA).

[0073] The light-emitting element layer (EML) can be disposed on the thin-film transistor layer (TFTL). The EML may include: multiple light-emitting elements, including a first electrode, a second electrode, and a light-emitting layer to emit light; and a pixel defining film to define pixels. The multiple light-emitting elements of the EML can be disposed in the display area (DA).

[0074] In one embodiment, the light-emitting layer may be an organic light-emitting layer comprising organic materials. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin-film transistor of the thin-film transistor layer (TFTL) and the second electrode receives a cathode voltage, holes and electrons can move to the organic light-emitting layer through the hole transport layer and electron transport layer, respectively, and can recombine with each other in the organic light-emitting layer to emit light.

[0075] In another embodiment, the light-emitting element may include a quantum dot light-emitting diode having a quantum dot light-emitting layer, an inorganic light-emitting diode having an inorganic semiconductor, or a micro light-emitting diode.

[0076] The encapsulation layer TFEL can cover the top and side surfaces of the light-emitting element layer EML and can protect the light-emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light-emitting element layer EML.

[0077] In another embodiment, the touch sensing layer may be disposed on the encapsulation layer TFEL. The touch sensing layer may include a plurality of touch electrodes for capacitively sensing the user's touch and touch lines connected to the plurality of touch electrodes. For example, the touch sensing layer may sense the user's touch in a mutual capacitance or self-capacitance manner.

[0078] In another embodiment, the color filter layer may be disposed on the touch sensing layer or the encapsulation layer TFEL. The color filter layer may include multiple color filters corresponding to multiple light-emitting areas. Each of the color filters selectively transmits light of a specific wavelength and blocks or absorbs light of other wavelengths. The color filter layer may absorb a portion of the light incident from the outside of the display device 10 to reduce reflected light caused by external light. Therefore, the color filter layer can prevent color distortion caused by the reflection of external light.

[0079] Figure 4 This is a schematic circuit diagram illustrating a sub-pixel of a pixel in a display device according to one embodiment.

[0080] Reference Figure 4 The sub-pixel SPX may include light-emitting elements LE1 and LE2, a driving transistor DTR, and first transistors STR1 to seventh transistors STR7. Light-emitting elements LE1 and LE2 may include first light-emitting element LE1 and second light-emitting element LE2.

[0081] The first electrode of the driving transistor DTR can be electrically connected to the light-emitting elements LE1 and LE2 via the sixth transistor STR6. The driving transistor DTR receives data signals according to the switching operation of the second transistor STR2 and supplies driving current to the light-emitting elements LE1 and LE2.

[0082] The gate electrode of the first transistor STR1 can be connected to the scan write line GWL. The first electrode of the first transistor STR1 can be connected to the first electrode of the driving transistor DTR, and connected to the pixel electrodes of the light-emitting elements LE1 and LE2 via the sixth transistor STR6. The second electrode of the first transistor STR1 can be connected together with the first electrode of the capacitor CST, the first electrode of the third transistor STR3, and the gate electrode of the driving transistor DTR. The first transistor STR1 may include a first-1 transistor ST1-1 and a first-2 transistor ST1-2. However, it is not limited to this and may be formed by a single transistor. The first transistor STR1 is turned on according to the scan signal received through the scan write line GWL to connect the gate electrode and drain electrode of the driving transistor DTR to each other, thereby connecting the driving transistor DTR diode.

[0083] The gate electrode of the second transistor STR2 is connected to the scan write line GWL, and its first electrode is connected to the data line DTL. The second electrode of the second transistor STR2 can be connected to the second electrode of the drive transistor DTR, and is connected to the first power line ELVDL via the fifth transistor STR5. The second transistor STR2 is turned on according to the scan signal received through the scan write line GWL to perform a switching operation that transmits the data signal transmitted to the data line DTL to the second electrode of the drive transistor DTR.

[0084] The gate electrode of the third transistor STR3 can be connected to the scan initialization line GIL. The second electrode of the third transistor STR3 can be connected to the initialization voltage line VIL. The first electrode of the third transistor STR3 can be connected together with the first electrode of the capacitor CST, the second electrode of the first transistor STR1, and the gate electrode of the driving transistor DTR. The third transistor STR3 may include the third-first transistor ST3-1 and the third-second transistor ST3-2. However, it is not limited to this and may also be formed by a single transistor. The third transistor STR3 can be turned on according to the scan initialization signal received through the scan initialization line GIL to perform an initialization operation that initializes the voltage of the gate electrode of the driving transistor DTR by transmitting the initialization voltage to the gate electrode of the driving transistor DTR.

[0085] The gate electrode of the fourth transistor STR4 can be connected to the scan initialization line GIL. The first electrode of the fourth transistor STR4 can be connected to the pixel electrodes of the light-emitting elements LE1 and LE2. The second electrode of the fourth transistor STR4 can be connected to the initialization voltage line VIL. The fourth transistor STR4 can be turned on according to the scan signal received through the scan initialization line GIL to initialize the pixel electrodes of the light-emitting elements LE1 and LE2.

[0086] The gate electrode of the fifth transistor STR5 can be connected to the light-emitting control line EL. The first electrode of the fifth transistor STR5 can be connected to the first power supply line ELVDL. The second electrode of the fifth transistor STR5 is connected to the second electrode of the driving transistor DTR and the second electrode of the second transistor STR2.

[0087] The gate electrode of the sixth transistor STR6 can be connected to the light emission control line EL. The first electrode of the sixth transistor STR6 can be connected to the first electrode of the driving transistor DTR and the first electrode of the first transistor STR1. The second electrode of the sixth transistor STR6 can be electrically connected to the pixel electrodes of the light-emitting elements LE1 and LE2. The fifth transistor STR5 and the sixth transistor STR6 are simultaneously turned on according to the light emission control signal received through the light emission control line EL, so that the first power supply voltage of the first power supply line ELVDL is transmitted to the light-emitting elements LE1 and LE2, and the driving current flows through the light-emitting elements LE1 and LE2.

[0088] The gate electrode of the seventh transistor STR7 can be connected to the light-emitting switch line MSL. The first electrode of the seventh transistor STR7 can be connected to the second electrode of the sixth transistor STR6. The second electrode of the seventh transistor STR7 can be electrically connected to the pixel electrode of the second light-emitting element LE2. The seventh transistor STR7 is turned on according to the switching signal received through the light-emitting switch line MSL, so that the first power supply voltage of the first power supply line ELVDL is transmitted to the second light-emitting element LE2, and driving current flows through the second light-emitting element LE2.

[0089] The first electrode of capacitor CST can be connected together with the gate electrode of driving transistor DTR, the second electrode of first transistor STR1, and the first electrode of third transistor STR3.

[0090] The common electrode of light-emitting elements LE1 and LE2 receives a second power supply voltage through the second power supply line ELVSS. Light-emitting elements LE1 and LE2 emit light by receiving drive current from the drive transistor DTR.

[0091] The light-emitting elements LE1 and LE2 of the aforementioned sub-pixel SPX can emit light differently depending on the emission mode. For example, in the first emission mode (normal mode), the seventh transistor STR7 can be turned on, causing the first light-emitting element LE1 and the second light-emitting element LE2 to emit light simultaneously. In the second emission mode (privacy protection mode), the seventh transistor STR7 can be turned off, causing only the first light-emitting element LE1 to emit light.

[0092] Figure 5 This is a top view showing a pixel of a display device according to one embodiment. Figure 6 It is along Figure 5 A sectional view taken by line X1-X1'. Figure 7 This is a schematic diagram showing a display device emitting light in a first light-emitting mode according to an embodiment. Figure 8 This is a schematic diagram showing a display device emitting light in a second light-emitting mode according to one embodiment.

[0093] Reference Figure 5The display device 10 may include pixels PX arranged in the display area DA. Pixel PX may include multiple light-emitting areas LA1, LA2, LA3, and LA4. For example, pixel PX may include a first light-emitting area LA1, a second light-emitting area LA2, a third light-emitting area LA3, and a fourth light-emitting area LA4. However, it is not limited to this. The number of light-emitting areas LA1, LA2, LA3, and LA4 arranged in pixel PX can be varied.

[0094] A pixel PX may include more than one light-emitting element, which may emit light of different colors. For example, a light-emitting element including a first light-emitting region LA1 may emit red light. A light-emitting element including a second light-emitting region LA2 may emit blue light, and a light-emitting element including a third light-emitting region LA3 may emit green light. Furthermore, a light-emitting element including a fourth light-emitting region LA4 may emit the blue light. However, it is not limited to this.

[0095] Each light-emitting region LA1, LA2, LA3, and LA4 can emit light of various colors. For example, the first light-emitting region LA1 can emit red light, the second light-emitting region LA2 can emit blue light, the third light-emitting region LA3 can emit green light, and the fourth light-emitting region LA4 can emit blue light. In an exemplary embodiment, each light-emitting region LA1, LA2, LA3, and LA4 of the display device 10 can be a region overlapping with a pixel electrode, for example, Figure 6 The pixel-defining film shown in the figure ( Figure 6 The openings of “PDL1” and “PDL2” can correspond to the light-emitting regions LA1, LA2, LA3, and LA4.

[0096] Each of the light-emitting regions LA1, LA2, LA3, and LA4 can be defined by a pixel-defined film formed on the light-emitting element layer EML. Figure 6 The first light-emitting region LA1 may be defined by a plurality of openings OPA1 and OPA2 in the pixel defining film ("PDL1" and "PDL2"). For example, the first light-emitting region LA1 may be defined by a first opening OPA1 and a second opening OPA2 that overlap with the first pixel electrode AE1 and the second pixel electrode AE2 in the pixel defining film.

[0097] Each of the luminescent regions LA1, LA2, LA3, and LA4 may include main luminescent regions MLA1, MLA2, MLA3, and MLA4 and surrounding luminescent regions SLA1, SLA2, SLA3, and SLA4. For example, the first luminescent region LA1 may include a first main luminescent region MLA1 and a first surrounding luminescent region SLA1; the second luminescent region LA2 may include a second main luminescent region MLA2 and a second surrounding luminescent region SLA2; the third luminescent region LA3 may include a third main luminescent region MLA3 and a third surrounding luminescent region SLA3; and the fourth luminescent region LA4 may include a fourth main luminescent region MLA4 and a fourth surrounding luminescent region SLA4.

[0098] The main light-emitting areas MLA1, MLA2, MLA3, and MLA4 of each light-emitting area LA1, LA2, LA3, and LA4 can correspond to the first pixel limiting film. Figure 6 The first opening OPA1 of “PDL1”, and the surrounding light-emitting areas SLA1, SLA2, SLA3, and SLA4 can correspond to the second pixel defining film ( Figure 6 The second opening OPA2 of the “PDL2”. For example, the various surrounding light-emitting areas SLA1, SLA2, SLA3, and SLA4 can be in the second pixel defining film ( Figure 6 The second opening of the "PDL2" in OPA2, except for the first pixel limiting film ( Figure 6 The area outside the first opening OPA1 of “PDL1”.

[0099] Multiple luminescent regions LA1, LA2, LA3, and LA4 can be arranged, for example, as PenTile. ® Types, such as Diamond PenTile TM For example, the first light-emitting region LA1 and the third light-emitting region LA3 can be arranged spaced apart from each other in the second direction DR2, the second light-emitting region LA2 and the fourth light-emitting region LA4 can be spaced apart in the first direction DR1, and the first light-emitting region LA1 and the third light-emitting region LA3 can be spaced apart in the fourth direction DR4 or the fifth direction DR5.

[0100] In an exemplary embodiment, the areas or dimensions of the first light-emitting region LA1, the second light-emitting region LA2, the third light-emitting region LA3, and the fourth light-emitting region LA4 may be the same or different from each other. Figure 5In one embodiment, the areas or dimensions of the first light-emitting region LA1, the second light-emitting region LA2, the third light-emitting region LA3, and the fourth light-emitting region LA4 can be the same as each other. In another exemplary embodiment, the area of ​​the first light-emitting region LA1 can be larger than the areas of the second light-emitting region LA2, the third light-emitting region LA3, and the fourth light-emitting region LA4, and the area of ​​the third light-emitting region LA3 can be larger than the areas of the second light-emitting region LA2 and the fourth light-emitting region LA4.

[0101] The intensity of the emitted light can be changed by adjusting the area of ​​each light-emitting region LA1, LA2, LA3, and LA4, and the color perception of the image displayed on the display device 10 or electronic device 1 can be controlled by adjusting the area of ​​each light-emitting region LA1, LA2, LA3, and LA4. The size and area of ​​each light-emitting region LA1, LA2, LA3, and LA4 can be freely adjusted according to the desired color perception of the image displayed on the display device 10 and electronic device 1. Furthermore, the area of ​​each light-emitting region LA1, LA2, LA3, and LA4 can be related to luminous efficiency, the lifespan of the light-emitting element, etc., and can have a trade-off relationship with reflections caused by external light. The area of ​​each light-emitting region LA1, LA2, LA3, and LA4 can be adjusted by considering the above factors.

[0102] The display device 10 may include a light-shielding layer BM disposed on each of the light-emitting areas LA1, LA2, LA3, and LA4.

[0103] The light-shielding layer BM can be disposed across the entire surface of the display area DA. The light-shielding layer BM may include multiple apertures OPT1, OPT2, OPT3, and OPT4 respectively arranged corresponding to each of the plurality of light-emitting areas LA1, LA2, LA3, and LA4. Furthermore, the apertures OPT1, OPT2, OPT3, and OPT4 of the light-shielding layer BM may respectively correspond to a pixel-defining film (…). Figure 6 The light-shielding layer BM is arranged with openings OPA1 and OPA2 ("PDL1" and "PDL2"). The light-shielding layer BM can cover the display area DA, except for the areas in the display area DA where holes OPT1, OPT2, OPT3, and OPT4 are arranged. The holes OPT1, OPT2, OPT3, and OPT4 of the light-shielding layer BM can be areas from which light emitted from the light-emitting elements corresponding to the respective light-emitting areas LA1, LA2, LA3, and LA4 is emitted. The multiple holes OPT1, OPT2, OPT3, and OPT4 can include a first hole OPT1 overlapping with the first light-emitting area LA1, a second hole OPT2 overlapping with the second light-emitting area LA2, a third hole OPT3 overlapping with the third light-emitting area LA3, and a fourth hole OPT4 overlapping with the fourth light-emitting area LA4.

[0104] The area on the plane of each of the multiple holes OPT1, OPT2, OPT3, and OPT4 can be smaller than the area on the plane of each of the light-emitting regions LA1, LA2, LA3, and LA4. For example, the area on the plane of the first hole OPT1 can be smaller than the area on the plane of the first light-emitting region LA1. The area on the plane of the second hole OPT2 can be smaller than the area on the plane of the second light-emitting region LA2, the area on the plane of the third hole OPT3 can be smaller than the area on the plane of the third light-emitting region LA3, and the area on the plane of the fourth hole OPT4 can be smaller than the area on the plane of the fourth light-emitting region LA4.

[0105] In the following text, reference will be made to Figure 6 Explain the cross-sectional structure of the display device 10.

[0106] Reference Figure 6 The display device 10 may include a substrate SUB, a thin film transistor layer TFTL, a light-emitting element layer EML, an encapsulation layer TFEL, and a light-shielding layer BM.

[0107] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate SUB can include, but is not limited to, polymer resins such as polyimide (PI). As another example, the substrate SUB can include glass or metal materials.

[0108] The thin-film transistor layer (TFTL) may include a first buffer layer (BF1), a lower metal layer (BML), a second buffer layer (BF2), a first thin-film transistor (TFT1), a second thin-film transistor (TFT2), a gate insulating layer (GI), a first interlayer insulating layer (ILD1), a capacitor electrode (CPE), a second interlayer insulating layer (ILD2), a first protective layer (PAS1), and a first connection electrode (CNE1).

[0109] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic membrane capable of preventing the penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic membranes stacked alternately.

[0110] The lower metal layer BML can be disposed on the first buffer layer BF1. For example, the lower metal layer BML can be formed by a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof. The lower metal layer BML can be arranged to overlap with the semiconductor layers ACT1 and ACT2 of the respective thin-film transistors TFT1 and TFT2.

[0111] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic membrane capable of preventing the penetration of air or moisture. For example, the second buffer layer BF2 may include multiple inorganic membranes stacked alternately.

[0112] Each thin-film transistor (TFT1, TFT2) can be arranged on the second buffer layer BF2 and can constitute the pixel circuit of each of the multiple pixels. For example, the first thin-film transistor (TFT1) can be the driving transistor of the pixel circuit. Figure 4 The second thin-film transistor TFT2 can be the seventh transistor in the pixel circuit (DTR). Figure 4 (STR7). Each thin-film transistor TFT1 and TFT2 may include semiconductor layers ACT1 and ACT2, source electrodes SE1 and SE2, drain electrodes DE1 and DE2, and gate electrodes GE1 and GE2. For example, the first thin-film transistor TFT1 may include the first semiconductor layer ACT1, the first gate electrode GE1, the first source electrode SE1, and the first drain electrode DE1, and the second thin-film transistor TFT2 may include the second semiconductor layer ACT2, the second gate electrode GE2, the second source electrode SE2, and the second drain electrode DE2.

[0113] The first semiconductor layer ACT1 and the second semiconductor layer ACT2 can be disposed on the second buffer layer BF2. Each semiconductor layer ACT1 and ACT2 can overlap with each lower metal layer BML and each gate electrode GE1 and GE2 in the thickness direction, and can be insulated from each gate electrode GE1 and GE2 by the gate insulating layer GI. Each semiconductor layer ACT1 and ACT2 can be conductive to form the source and drain regions.

[0114] The gate insulating layer GI can be disposed on each semiconductor layer ACT1, ACT2. For example, the gate insulating layer GI can cover each semiconductor layer ACT1, ACT2 and the second buffer layer BF2, and can insulate each semiconductor layer ACT1, ACT2 from each gate electrode GE1, GE2. The gate insulating layer GI may include contact holes through which each source electrode SE1, SE2 and each drain electrode DE1, DE2 pass.

[0115] The first gate electrode GE1 and the second gate electrode GE2 can be disposed on the gate insulating layer GI. Each gate electrode GE1 and GE2 can place the gate insulating layer GI in the middle and overlap with each semiconductor layer ACT1 and ACT2.

[0116] The first interlayer insulating layer ILD1 may cover each gate electrode GE1, GE2 and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include contact holes through which each source electrode SE1, SE2 and each drain electrode DE1, DE2 pass. The contact holes of the first interlayer insulating layer ILD1 may connect with the contact holes of the gate insulating layer GI and the contact holes of the second interlayer insulating layer ILD2.

[0117] The capacitor electrode CPE can be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE can overlap with the first gate electrode GE1 in the thickness direction. The capacitor electrode CPE and the first gate electrode GE1 can form a capacitor.

[0118] The second interlayer insulating layer (ILD2) may cover the capacitor electrode CPE and the first interlayer insulating layer (ILD1). The second interlayer insulating layer (ILD2) may include contact holes through which the respective source electrodes SE1, SE2 and the respective drain electrodes DE1, DE2 pass. The contact holes of the second interlayer insulating layer (ILD2) may be connected to the contact holes of the first interlayer insulating layer (ILD1) and the contact holes of the gate insulating layer (GI).

[0119] Each source electrode SE1, SE2 and each drain electrode DE1, DE2 can be disposed on the second interlayer insulating layer ILD2. For example, the first source electrode SE1 and the first drain electrode DE1 can be disposed to overlap with the first semiconductor layer ACT1 and connected to the first semiconductor layer ACT1 respectively through contact holes. The second source electrode SE2 and the second drain electrode DE2 can be disposed to overlap with the second semiconductor layer ACT2 and connected to the second semiconductor layer ACT2 respectively through contact holes.

[0120] The first protective layer PAS1 can be disposed on each source electrode SE1, SE2 and each drain electrode DE1, DE2. The first protective layer PAS1 can protect each thin film transistor TFT1, TFT2. The first protective layer PAS1 may include a contact hole through which the first connection electrode CNE1 passes.

[0121] The first connection electrode CNE1 can be disposed on the first protective layer PAS1. The first connection electrode CNE1 can electrically connect the first source electrode SE1 and the first pixel electrode AE1 of the first thin film transistor TFT1 through the contact holes of the first protective layer PAS1.

[0122] The light-emitting element layer (EML) can be disposed on the thin-film transistor layer (TFTL). The EML may include a first light-emitting element (ED1), a second light-emitting element (ED2), a first pixel defining film (PDL1), a second pixel defining film (PDL2), and a sacrificial layer (SCR). The first light-emitting element (ED1) may include a first pixel electrode (AE1), a light-emitting layer (OEL), a common layer (CEL), and a common electrode (CE). The second light-emitting element (ED2) may include a second pixel electrode (AE2), a light-emitting layer (OEL), a common layer (CEL), and a common electrode (CE).

[0123] The sacrificial layer SCR can be disposed on the first protective layer PAS1 and the first connecting electrode CNE1. The sacrificial layer SCR can surround the first connecting electrode CNE1 in a plane and cover the edge of the first connecting electrode CNE1. The sacrificial layer SCR can expose a portion of the upper surface of the first connecting electrode CNE1. In order to form the tip TIP of the first pixel defining film PDL1 described later, the sacrificial layer SCR can include a conductive material. For example, the sacrificial layer SCR can include any one of silver (Ag), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof.

[0124] The first pixel defining film PDL1 may include a first opening OPA1 and is disposed on the first protective layer PAS1 and the sacrificial layer SCR. The first opening OPA1 of the first pixel defining film PDL1 may expose a portion of the first pixel electrode AE1. The first pixel defining film PDL1 may include polyimide (PI). In some embodiments, the first pixel defining film PDL1 may include a colorant of a mixture of red, green and blue, a black colorant, or carbon black.

[0125] The side surface of the first pixel defining film PDL1 may protrude outwards from the side surface of the sacrificial layer SCR. For example, the first pixel defining film PDL1 may include tipped points on its side and bottom surfaces that protrude outwards from the sacrificial layer SCR. The tipped points of the first pixel defining film PDL1 may function to stack the pixel electrodes AE1, AE2, and the light-emitting layer OEL, described later, in a spaced-apart manner. For example, the tipped points of the first pixel defining film PDL1 may stack the pixel electrodes AE1, AE2, and the light-emitting layer OEL in a separately stacked manner.

[0126] The first pixel electrode AE1 can be disposed on the first connecting electrode CNE1. The first pixel electrode AE1 can be disposed to overlap with the first opening OPA1 of the first pixel defining film PDL1. The first pixel electrode AE1 can be disposed on the upper surface of the first connecting electrode CNE1 and disposed to partially overlap with the tip TIP of the first pixel defining film PDL1. The first pixel electrode AE1 can be electrically connected to the first source electrode SE1 of the first thin film transistor TFT1 through the first connecting electrode CNE1.

[0127] The second pixel electrode AE2 can be disposed on the first pixel defining film PDL1. The second pixel electrode AE2 can be disposed spaced apart from the first pixel electrode AE1. The second pixel electrode AE2 can be disposed on the upper surface and side surface of the first pixel defining film PDL1. The second pixel electrode AE2 can be disposed such that it partially overlaps with the first pixel electrode AE1 on the side surface of the first pixel defining film PDL1. The second pixel electrode AE2 can be electrically connected to the second source electrode SE2 of the second thin film transistor TFT2 through a contact hole CH formed in the first pixel defining film PDL1.

[0128] The first pixel electrode AE1 and the second pixel electrode AE2 can be arranged spaced apart from each other and separated from each other by the tip TIP of the first pixel defining film PDL1. The first pixel electrode AE1 and the second pixel electrode AE2 can be reflective electrodes. The reflective electrodes can be formed by a stacked structure of a transparent conductive layer and a reflective layer. For example, they can be formed by a stacked structure of aluminum and ITO (ITO / Al / ITO) or a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0129] The second pixel defining film PDL2 may include a second opening OPA2 and is disposed on the first pixel defining film PDL1 and the second pixel electrode AE2. The second opening OPA2 of the second pixel defining film PDL2 may expose a portion of the second pixel electrode AE2 and may expose the first opening OPA1 of the first pixel defining film PDL1. The second pixel defining film PDL2 may include the same material as the first pixel defining film PDL1.

[0130] The light-emitting layer (OEL) can be disposed on the first pixel electrode AE1 and the second pixel electrode AE2. The OEL can include a first organic layer EL1 and a second organic layer EL2. The first organic layer EL1 can be disposed on the first pixel electrode AE1, and the second organic layer EL2 can be disposed on the second pixel electrode AE2. The area of ​​the first organic layer EL1 can be formed to be larger than the area of ​​the first opening OPA1 of the first pixel defining film PDL1. The side surface of the first organic layer EL1 can overlap with the first pixel defining film PDL1. The side surface of the second organic layer EL2 can contact the side surface of the second pixel defining film PDL2.

[0131] The first organic layer EL1 and the second organic layer EL2 can be arranged to be spaced apart from each other. As described above, due to the tip TIP of the first pixel defining film PDL1, the light-emitting materials can be stacked separately from each other when stacking the light-emitting layers OEL. That is, the light-emitting layer OEL may include the first organic layer EL1 and the second organic layer EL2 separated from each other by the tip TIP of the first pixel defining film PDL1.

[0132] A common layer CEL can be disposed on the light-emitting layer OEL and the second pixel-defining film PDL2. The common layer CEL can be disposed on the first organic layer EL1 to fill the area separated by the bottom surface of the first pixel-defining film PDL1 and the side surface of the sacrificial layer SCR. That is, the common layer CEL can be disposed continuously without being separated by the tip of the first pixel-defining film PDL1. The common layer CEL can contact the first pixel-defining film PDL1, the sacrificial layer SCR, the first organic layer EL1, and the second pixel-defining film PDL2, respectively. The common layer CEL can be disposed continuously throughout the entire pixel, without being differentiated according to multiple pixels. The common layer CEL can be a functional layer that contributes to the light-emitting function of the light-emitting layer OEL. For example, the common layer CEL can include any one or more of a charge generation layer, an electron transport layer, and an electron injection layer.

[0133] The common electrode CE can be arranged on the common layer CEL. For example, the common electrode CE can be implemented as a shared electrode for all pixels, rather than being distinguished according to multiple pixels. The common electrode CE can receive a common voltage or a low potential voltage. If each pixel electrode AE1, AE2 receives a voltage corresponding to the data voltage, and the common electrode CE receives a low potential voltage, a potential difference is formed between each pixel electrode AE1, AE2 and the common electrode CE, thereby allowing the light-emitting layer OEL to emit light.

[0134] The light-emitting element layer EML may include a first light-emitting region LA1, which may include a first main light-emitting region MLA1 and a first peripheral light-emitting region SLA1. The first main light-emitting region MLA1 may be a region emitting light from the first light-emitting element ED1, and the first peripheral light-emitting region SLA1 may be a region emitting light from the second light-emitting element ED2. The first main light-emitting region MLA1 may be a region on a plane surrounded by the side surface of the second pixel electrode AE2 (e.g., corresponding to the inner peripheral surface of the second pixel electrode AE2), and the first peripheral light-emitting region SLA1 may be a region on a plane extending from the side surface of the second pixel electrode AE2 to the side surface of the second organic layer EL2 of the light-emitting layer OEL. For example, the first peripheral light-emitting region SLA1 may be a region in the second opening OPA2 of the second pixel defining film PDL2, excluding the first main light-emitting region MLA1.

[0135] The first main light-emitting region MLA1 may overlap with the first opening OPA1 of the first pixel-defining film PDL1, the second opening OPA2 of the second pixel-defining film PDL2, and the first hole OPT1 of the light-shielding layer BM. The first peripheral light-emitting region SLA1 may not overlap with the first opening OPA1 of the first pixel-defining film PDL1 and the first hole OPT1 of the light-shielding layer BM, but may overlap with the second opening OPA2 of the second pixel-defining film PDL2. The area of ​​the first main light-emitting region MLA1 may be smaller than the area of ​​the first opening OPA1 of the first pixel-defining film PDL1 and smaller than the area of ​​the second opening OPA2 of the second pixel-defining film PDL2.

[0136] On the other hand, the encapsulation layer TFEL can be disposed on the light-emitting element layer EML. The encapsulation layer TFEL can be disposed on the common electrode CE to cover the light-emitting elements ED1 and ED2. The encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. The encapsulation layer TFEL may also include at least one organic film to protect the light-emitting element layer EML from impurities such as dust.

[0137] In an exemplary embodiment, the encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed between the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be an organic encapsulation layer.

[0138] The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may each comprise one or more inorganic insulating materials. These inorganic insulating materials may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0139] The second encapsulation layer TFE2 may include polymer-based materials. Polymer-based materials may include acrylic resins, epoxy resins, polyimides, and polyethylene, etc. For example, the second encapsulation layer TFE2 may include acrylic resins such as polymethyl methacrylate, polyacrylic acid, etc. The second encapsulation layer TFE2 can be formed by curing monomers or coating polymers.

[0140] The light-shielding layer BM can be disposed on the encapsulation layer TFEL. The light-shielding layer BM can overlap with the first pixel electrode AE1 and the second pixel electrode AE2, and includes a first aperture OPT1 disposed to overlap with the first main light-emitting region MLA1. For example, the first aperture OPT1 can be disposed to overlap with the first pixel electrode AE1, the first organic layer EL1, the first main light-emitting region MLA1, the first opening OPA1, and the second opening OPA2.

[0141] The area or size of the first aperture OPT1 can be smaller than the area or size of the first pixel electrode AE1, and can also be smaller than the area or size of the first main light-emitting region MLA1. Furthermore, the area or size of the first aperture OPT1 can be smaller than the area or size of the first opening OPA1 of the first pixel defining film PDL1. However, it is not limited to this; the area or size of the first aperture OPT1 can be equal to or larger than the area or size of the first pixel electrode AE1, and can also be equal to or larger than the area or size of the first main light-emitting region MLA1, to prevent light emitted from the first main light-emitting region MLA1 from being seen by the user from the side surface of the display device 10. Furthermore, the area or size of the first aperture OPT1 can also be equal to or larger than the area or size of the first opening OPA1 of the first pixel defining film PDL1.

[0142] The light-shielding layer BM may include a light-absorbing material. For example, the light-shielding layer BM may include inorganic black pigments or organic black pigments. Inorganic black pigments may be carbon black, and organic black pigments may include, but are not limited to, at least one of lactam black, perylene black, and aniline black. The light-shielding layer BM can prevent color mixing caused by visible light intrusion, thereby improving the color reproduction of the display device 10. In an exemplary embodiment, the light-shielding layer BM may have a thickness of about 1 μm to about 3 μm or about 1.5 μm.

[0143] According to one embodiment, the display device 10 can adjust the side surface visibility based on the light emission patterns of the first light-emitting element ED1 and the second light-emitting element ED2 in a light-emitting area (e.g., the first light-emitting area LA1).

[0144] As the first light-emitting mode, both the first light-emitting element ED1 and the second light-emitting element ED2 can emit light without restricting the visibility of the side surface. For example, in... Figure 4 As described above, in the first light-emitting mode, the driving voltage is transmitted through the first thin-film transistor TFT1 ( Figure 4 The "DTR" is applied to the first pixel electrode AE1, so that the first light-emitting element ED1 can emit light. Furthermore, the same driving voltage is applied to the second thin-film transistor TFT2. Figure 4 The "STR7" is also applied to the second pixel electrode AE2, so that the second light-emitting element ED2 can emit light. Figure 7 As illustrated, if both the first light-emitting element ED1 and the second light-emitting element ED2 are illuminated in the first light-emitting mode, the light emitted from the first light-emitting area LA1 can be seen by the user even when viewing the display device 10 from any direction.

[0145] Conversely, as a second light-emitting mode of the display device 10, only the first light-emitting element ED1 can emit light when it is necessary to limit the visibility of the side surface. In the second light-emitting mode, the driving voltage is transmitted through the first thin-film transistor TFT1 (… Figure 4 The "DTR" is applied to the first pixel electrode AE1, so that the first light-emitting element ED1 can emit light. Conversely, the second thin-film transistor TFT2 ( Figure 4 When the “STR7” is cut off, the driving voltage is not applied (e.g., cut off) to the second pixel electrode AE2, so that the second light-emitting element ED2 can not emit light.

[0146] For example, such as Figure 8 As illustrated, if only the first light-emitting element ED1 emits light in the second light-emitting mode, light can be emitted through the first hole OPT1 of the light-shielding layer BM, and the light is blocked by the light-shielding layer BM at a specific viewing angle. Since the second light-emitting element ED2 does not emit light, in the second light-emitting mode, the display device 10 allows only the user viewing from the front surface of the display area DA to see the image, while the user viewing from a specific viewing angle θ or a side surface cannot see the image. The specific viewing angle θ can be approximately 60 degrees or less. Therefore, the display device 10 can provide a privacy protection mode for the user.

[0147] The following will describe a method for manufacturing a display device 10 according to one embodiment.

[0148] Figures 9 to 15 This is a cross-sectional view showing the manufacturing method of a display device according to one embodiment, in accordance with the process. Figures 9 to 15 It shows the corresponding Figure 6 The manufacturing process of a cross-section of a subpixel of a display device.

[0149] First, refer to Figure 9A substrate SUB is provided in which a thin-film transistor layer (TFTL) is formed. For example, a first buffer layer (BF1), a lower metal layer (BML), a second buffer layer (BF2), a first thin-film transistor (TFT1), a second thin-film transistor (TFT2), a gate insulating layer (GI), a first interlayer insulating layer (ILD1), a capacitor electrode (CPE), a second interlayer insulating layer (ILD2), a first protective layer (PAS1), and a first connection electrode (CNE1) are sequentially formed on the substrate SUB. This structure can be formed using known techniques such as deposition, solution processing, and photolithography.

[0150] A sacrificial material layer SCRL is formed on the first connection electrode CNE1. The sacrificial material layer SCRL can be formed by patterning using a photolithography process after stacking conductive materials. The sacrificial material layer SCRL can be formed to completely cover the first connection electrode CNE1.

[0151] Next, a first pixel defining film PDL1 is formed on a substrate SUB on which the sacrificial material layer SCRL is formed. The first pixel defining film PDL1 can be formed using solution processes (e.g., spin coating, inkjet printing, slot coating, etc.). Then, a first opening OPA1 that exposes a portion of the upper surface of the sacrificial material layer SCRL is formed using a photolithography process.

[0152] Then, refer to Figure 10 A sacrificial SCR layer is formed using a first etching process. The first pixel defining film PDL1 is used as a mask to etch the sacrificial material layer SCRL to form the sacrificial SCR layer. The first etching process can be a wet etching process. The sacrificial material layer SCRL can be etched through an etchant coated with a first opening OPA1 to expose a portion of the first connection electrode CNE1. Furthermore, the sacrificial material layer SCRL is over-etched inwards from the side surface of the first pixel defining film PDL1, forming a tip (TIP) on the side surface of the first pixel defining film PDL1 that protrudes beyond the side surface of the sacrificial SCR layer.

[0153] Next, refer to Figure 11 A contact hole CH is formed using a second etching process. The contact hole CH can penetrate the first pixel defining film PDL1 and the first protective layer PAS1 to expose the second source electrode SE2 of the second thin-film transistor TFT2. The second etching process can be a dry etching process.

[0154] Then, refer to Figure 12A first pixel electrode AE1 and a second pixel electrode AE2 are formed on a substrate SUB with contact holes CH. The first pixel electrode AE1 and the second pixel electrode AE2 can be formed by patterning using a photolithography process after stacking electrode material layers on the substrate SUB. The electrode material layers are separated by the tip TIP of the first pixel defining film PDL1. The portion stacked on the first connecting electrode CNE1 can be formed as the first pixel electrode AE1, and the portion stacked on the first pixel defining film PDL1 can be patterned to form the second pixel electrode AE2. Therefore, the first pixel electrode AE1 and the second pixel electrode AE2 are formed separately from each other.

[0155] Next, a second pixel defining film PDL2 is formed on the first pixel defining film PDL1 and the second pixel electrode AE2. The second pixel defining film PDL2 can be formed using solution processes (e.g., spin coating, inkjet printing, slot coating, etc.). Then, a second opening OPA2 is formed using a photolithography process, exposing a portion of the upper surface of the second pixel electrode AE2 and the first pixel electrode AE1.

[0156] Then, refer to Figure 13 An emitting layer OEL is formed on the first opening OPA1 and the second opening OPA2. The emitting layer OEL can be formed by depositing a emitting material layer on the substrate SUB. The emitting material layer is separated by the tip TIP of the first pixel defining film PDL1. The portion deposited on the first pixel electrode AE1 can be formed as the first organic layer EL1, and the portion deposited on the second pixel electrode AE2 can be formed as the second organic layer EL2. Therefore, a first organic layer EL1 and a second organic layer EL2 are formed that are separated from each other.

[0157] Next, refer to Figure 14 A common layer CEL and a common electrode CE are sequentially formed on a substrate SUB on which the light-emitting layer OEL is formed. The common layer CEL can be formed by depositing a common material layer on the display area of ​​the substrate SUB. The common layer CEL can fill the first opening OPA1 of the first pixel defining film PDL1 and is deposited continuously along the light-emitting layer OEL. For example, the common layer CEL can fill the region separated by the first organic layer EL1, the sacrificial layer SCR, and the first pixel defining film PDL1.

[0158] A common electrode CE can be formed by stacking a common electrode material layer on the display area of ​​the substrate SUB. The common electrode CE can be formed by continuously stacking on the common layer CEL. Therefore, a first light-emitting element ED1 including a first pixel electrode AE1, a light-emitting layer OEL, a common layer CEL, and a common electrode CE and a second light-emitting element ED2 including a second pixel electrode AE2, a light-emitting layer OEL, a common layer CEL, and a common electrode CE are formed.

[0159] Then, refer to Figure 15 An encapsulation layer TFEL is formed on the common electrode CE. The encapsulation layer TFEL can be sequentially formed into a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 can be formed using chemical vapor deposition or physical vapor deposition, and the second encapsulation layer TFE2 can be formed using solution processing.

[0160] Next, a light-shielding layer BM is formed on the encapsulation layer TFEL. The light-shielding layer BM can be formed with a first hole OPT1 by photolithography after a light-shielding material layer is formed on the third encapsulation layer TFE3 of the encapsulation layer TFEL. Therefore, a display device according to one embodiment can be manufactured.

[0161] The manufacturing method of the above-described display device forms a first pixel electrode AE1 and a second pixel electrode AE2 separated from each other by a tip TIP structure of a first pixel defining film PDL1, and a light-emitting layer OEL including a first organic layer EL1 and a second organic layer EL2 separated from each other, thereby eliminating the need for separate masks for forming them.

[0162] In the following description, a display device 10 according to another embodiment will be described with reference to other accompanying drawings.

[0163] Figure 16 This is a top view showing one pixel of a display device according to another embodiment. Figure 17 It is along Figure 16 The sectional view taken by line X2-X2'. Figure 18 This is a schematic diagram showing the emission of a display device according to another embodiment in a first light-emitting mode. Figure 19 This is a schematic diagram illustrating a display device emitting light in a second light-emitting mode according to another embodiment.

[0164] Reference Figure 16 and Figure 17 This implementation method is the same as the one described above. Figures 5 to 8 The difference in this implementation is that the planar shape of the light-emitting regions LA1, LA2, LA3, and LA4 is circular, and they include a first light-shielding layer BM1 and a second light-shielding layer BM2. In the following description, repetitions of the above-described implementation will be omitted, and the differences will be explained.

[0165] like Figure 16As shown, the display device 10 may include pixels PX arranged in the display area DA. Pixel PX may include multiple light-emitting areas LA1, LA2, LA3, and LA4. The planar shape of the multiple light-emitting areas LA1, LA2, LA3, and LA4 may be circular. In this embodiment, the case where the planar shape of the multiple light-emitting areas LA1, LA2, LA3, and LA4 is circular is used as an example for explanation, but it is not limited to this, and they may also be formed into polygons other than rectangles.

[0166] Each of the light-emitting regions LA1, LA2, LA3, and LA4 may include main light-emitting regions MLA1, MLA2, MLA3, and MLA4 and surrounding light-emitting regions SLA1, SLA2, SLA3, and SLA4. For example, the first light-emitting region LA1 may include a first main light-emitting region MLA1 and a first surrounding light-emitting region SLA1; the second light-emitting region LA2 may include a second main light-emitting region MLA2 and a second surrounding light-emitting region SLA2; the third light-emitting region LA3 may include a third main light-emitting region MLA3 and a third surrounding light-emitting region SLA3; and the fourth light-emitting region LA4 may include a fourth main light-emitting region MLA4 and a fourth surrounding light-emitting region SLA4. Each main light-emitting region MLA1, MLA2, MLA3, and MLA4 of each light-emitting region LA1, LA2, LA3, and LA4 may correspond to a first pixel defining film (…). Figure 17 The first opening OPA1 of “PDL1”, and the surrounding light-emitting areas SLA1, SLA2, SLA3, and SLA4 can correspond to the second pixel defining film ( Figure 17 The second opening of “PDL2” is OPA2.

[0167] Reference Figure 16 and Figure 17 The display device 10 may include a first light-shielding layer BM1 and a second light-shielding layer BM2 disposed on each of the light-emitting areas LA1, LA2, LA3, LA4.

[0168] Multiple first light-shielding layers BM1 can be configured, and each first light-shielding layer BM1 can be arranged to correspond to a plurality of light-emitting regions LA1, LA2, LA3, and LA4. For example, the first light-shielding layer BM1 can be arranged to surround a portion of each light-emitting region LA1, LA2, LA3, and LA4 on a plane, and overlap with each light-emitting region LA1, LA2, LA3, and LA4. For example, the first light-shielding layer BM1 can have a donut shape that covers a portion of each light-emitting region LA1, LA2, LA3, and LA4 on a plane and surrounds it.

[0169] The first light-shielding layer BM1 may include multiple holes OPT1, OPT2, OPT3, and OPT4 arranged corresponding to each of the light-emitting regions LA1, LA2, LA3, and LA4, respectively. Furthermore, the holes OPT1, OPT2, OPT3, and OPT4 of the first light-shielding layer BM1 may correspond to pixel-defining films (…). Figure 17 The openings OPA1 and OPA2 of the "PDL1" and "PDL2" are arranged. The holes OPT1, OPT2, OPT3, and OPT4 of the first light-shielding layer BM1 can be areas that emit light from the light-emitting elements ED1 and ED2 corresponding to the respective light-emitting areas LA1, LA2, LA3, and LA4. The multiple holes OPT1, OPT2, OPT3, and OPT4 may include a first hole OPT1 overlapping with the first light-emitting area LA1, a second hole OPT2 overlapping with the second light-emitting area LA2, a third hole OPT3 overlapping with the third light-emitting area LA3, and a fourth hole OPT4 overlapping with the fourth light-emitting area LA4.

[0170] like Figure 17 As shown, the first light-shielding layer BM1 can be disposed on the encapsulation layer TFEL. The first light-shielding layer BM1 can overlap with the first pixel electrode AE1 and the second pixel electrode AE2, and can include a first aperture OPT1 that overlaps with the first main light-emitting region MLA1. For example, the first aperture OPT1 can be disposed to overlap with the first pixel electrode AE1, the first organic layer EL1, the first main light-emitting region MLA1, the first opening OPA1, and the second opening OPA2.

[0171] The area or size of the first aperture OPT1 can be smaller than the area or size of the first pixel electrode AE1, and can also be smaller than the area or size of the first main light-emitting region MLA1. Furthermore, the area or size of the first aperture OPT1 can be smaller than the area or size of the first opening OPA1 of the first pixel defining film PDL1. However, it is not limited to this; the area or size of the first aperture OPT1 can be equal to or larger than the area or size of the first pixel electrode AE1, and can also be equal to or larger than the area or size of the first main light-emitting region MLA1, to prevent light emitted from the first main light-emitting region MLA1 from being seen by the user from the side surface of the display device 10. Furthermore, the area or size of the first aperture OPT1 can also be equal to or larger than the area or size of the first opening OPA1 of the first pixel defining film PDL1.

[0172] In one embodiment, the width of the first light-shielding layer BM1 can satisfy the following conditions. The corner where the upper surface of the first light-shielding layer BM1 intersects with one side surface (e.g., the inner surface) can intersect with virtual line ①, which extends from the upper surface of the first pixel electrode AE1 where it intersects with the end of the second pixel electrode AE2 in the third direction DR3 (e.g., the thickness direction). Furthermore, the corner where the lower surface of the first light-shielding layer BM1 intersects with the other side surface (e.g., the outer surface) can intersect with virtual line ②, which extends from the upper surface of the first pixel electrode AE1 where it intersects with the end of the second pixel electrode AE2 in the third direction DR3 (e.g., the thickness direction) and passes through the bend CP of the second pixel electrode AE2. The bend CP of the second pixel electrode AE2 can be the portion corresponding to the portion of the second pixel electrode AE2 that intersects with the upper surface and side surface of the first pixel defining film PDL1. The angle at which the virtual line ① extends, based on the upper surface of the first pixel electrode AE1, can be 60 degrees or less.

[0173] Reference Figure 16 and Figure 17 The second light-shielding layer BM2 can be disposed on the encapsulation layer TFEL. The second light-shielding layer BM2 can be disposed across the entire surface of the display area DA. The second light-shielding layer BM2 may include multiple main holes MPT1, MPT2, MPT3, and MPT4 respectively disposed corresponding to each of the plurality of light-emitting areas LA1, LA2, LA3, and LA4. Furthermore, the main holes MPT1, MPT2, MPT3, and MPT4 of the second light-shielding layer BM2 can respectively correspond to the pixel defining film (…). Figure 17 The openings OPA1 and OPA2 of the "PDL1" and "PDL2" are arranged. The second light-shielding layer BM2 can cover the display area DA, except for the area in the display area DA where the main holes MPT1, MPT2, MPT3, and MPT4 are arranged. The main holes MPT1, MPT2, MPT3, and MPT4 of the second light-shielding layer BM2 can be areas that emit light emitted from the light-emitting elements corresponding to the respective light-emitting areas LA1, LA2, LA3, and LA4. The main holes MPT1, MPT2, MPT3, and MPT4 can include a first main hole MPT1 overlapping with the first light-emitting area LA1, a second main hole MPT2 overlapping with the second light-emitting area LA2, a third main hole MPT3 overlapping with the third light-emitting area LA3, and a fourth main hole MPT4 overlapping with the fourth light-emitting area LA4.

[0174] The first light-shielding layer BM1 can be disposed inside the main holes MPT1, MPT2, MPT3, and MPT4 of the second light-shielding layer BM2. For example, the main holes MPT1, MPT2, MPT3, and MPT4 of the second light-shielding layer BM2 can overlap with the first light-shielding layer BM1. The second light-shielding layer BM2 can be arranged to be spaced apart from the first light-shielding layer BM1 and surround the first light-shielding layer BM1 on a plane. The area on the plane of each of the main holes MPT1, MPT2, MPT3, and MPT4 of the second light-shielding layer BM2 can be larger than the area on the plane of each of the light-emitting regions LA1, LA2, LA3, and LA4, and can also be larger than the area on the plane of the first light-shielding layer BM1.

[0175] The surrounding holes SPT1, SPT2, SPT3, and SPT4 can be arranged between the first light-shielding layer BM1 and the second light-shielding layer BM2. The surrounding holes SPT1, SPT2, SPT3, and SPT4 can be areas of the main holes MPT1, MPT2, MPT3, and MPT4 other than the first light-shielding layer BM1 and the holes OPT1, OPT2, OPT3, and OPT4. For example, the surrounding holes SPT1, SPT2, SPT3, and SPT4 can be the area between the side surface of each of the main holes MPT1, MPT2, MPT3, and MPT4 and the outer surface of the first light-shielding layer BM1. The surrounding holes SPT1, SPT2, SPT3, and SPT4 can be arranged to overlap with the surrounding light-emitting areas SLA1, SLA2, SLA3, and SLA4, but not with the main light-emitting areas MLA1, MLA2, MLA3, and MLA4.

[0176] like Figure 17 As shown, the second light-shielding layer BM2 can be disposed on the encapsulation layer TFEL and spaced apart from the first light-shielding layer BM1. The second light-shielding layer BM2 may not overlap with the first pixel electrode AE1, and at least a portion of the second light-shielding layer BM2 may overlap with the second pixel electrode AE2. However, it is not limited to this; the second light-shielding layer BM2 may also not overlap with the second pixel electrode AE2. The first main aperture MPT1 of the second light-shielding layer BM2 may be disposed to overlap with the first main light-emitting region MLA1, the first pixel electrode AE1, the first organic layer EL1, the first main light-emitting region MLA1, the first opening OPA1, and the second opening OPA2.

[0177] According to one embodiment, the display device 10 can adjust the side surface visibility based on the light emission patterns of the first light-emitting element ED1 and the second light-emitting element ED2 in a light-emitting area (e.g., the first light-emitting area LA1).

[0178] As the first light-emitting mode, both the first light-emitting element ED1 and the second light-emitting element ED2 can emit light without restricting the visibility of the side surface. For example, in... Figure 4 As described above, in the first light-emitting mode, the driving voltage is transmitted through the first thin-film transistor TFT1 ( Figure 4 The "DTR" is applied to the first pixel electrode AE1, so that the first light-emitting element ED1 can emit light. Furthermore, the same driving voltage is applied to the second thin-film transistor TFT2. Figure 4 The "STR7" is also applied to the second pixel electrode AE2, so that the second light-emitting element ED2 can emit light. Figure 18 As illustrated, if both the first light-emitting element ED1 and the second light-emitting element ED2 are illuminated in the first light-emitting mode, the light emitted from the first light-emitting area LA1 can be seen by the user even when viewing the display device 10 from any direction.

[0179] Conversely, as a second light-emitting mode of the display device 10, only the first light-emitting element ED1 can emit light when it is necessary to limit the visibility of the side surface. In the second light-emitting mode, the driving voltage is transmitted through the first thin-film transistor TFT1 (… Figure 4 The "DTR" is applied to the first pixel electrode AE1, so that the first light-emitting element ED1 can emit light. Conversely, the second thin-film transistor TFT2 ( Figure 4 When the “STR7” is cut off, the driving voltage is not applied (e.g., cut off) to the second pixel electrode AE2, so that the second light-emitting element ED2 can not emit light.

[0180] For example, such as Figure 19 As illustrated, if only the first light-emitting element ED1 emits light in the second light-emitting mode, light can be emitted through the first hole OPT1 of the first light-shielding layer BM1, and the light is blocked by the first light-shielding layer BM1 at a specific viewing angle. Since the second light-emitting element ED2 does not emit light, in the second light-emitting mode, the display device 10 allows only the user viewing from the front surface of the display area DA to see the image, while the user viewing from a specific viewing angle θ or a side surface cannot see the image. The specific viewing angle θ can be approximately 60 degrees or less. Therefore, the display device 10 can provide a privacy protection mode for the user.

[0181] Figure 20 This is a cross-sectional view showing a display device according to yet another embodiment. Figure 21 This is a schematic diagram showing a display device emitting light in a first light-emitting mode according to yet another embodiment. Figure 22 This is a schematic diagram illustrating light emitted in a second light-emitting mode of a display device according to another embodiment.

[0182] Reference Figure 20 This implementation method is the same as the one described above. Figures 16 to 20The difference in the implementation method is that the first connecting electrode CNE1, the second pixel defining film PDL2, the common layer CEL, and the sacrificial layer SCR are omitted, and the arrangement of each light-emitting region LA1, LA2, LA3, and LA4 is the same as described above. Figure 16 same.

[0183] In a display device 10 according to one embodiment, a first pixel electrode AE1 and a second pixel electrode AE2 may be disposed on a first protective layer PAS1. The second pixel electrode AE2 may be disposed spaced apart from the first pixel electrode AE1 and surround the first pixel electrode AE1 in a plane. The first pixel defining film PDL1 may include a first opening OPA1 and a second opening OPA2 exposing the first pixel electrode AE1 and the second pixel electrode AE2. For example, the first opening OPA1 may overlap with the first pixel electrode AE1 to expose the first pixel electrode AE1, and the second opening OPA2 may overlap with the second pixel electrode AE2 to expose the second pixel electrode AE2.

[0184] The light-emitting layer (OEL) may include a first organic layer EL1 and a second organic layer EL2. The first organic layer EL1 and the second organic layer EL2 may emit light of the same color and are formed using the same process. The first organic layer EL1 may overlap with a first opening OPA1 and be disposed on a first pixel electrode AE1, and the second organic layer EL2 may overlap with a second opening OPA2 and be disposed on a second pixel electrode AE2.

[0185] The common electrode CE can be continuously arranged on the light-emitting layer OEL and the first pixel defining film PDL1. Therefore, the display device 10 can include a first light-emitting element ED1 and a second light-emitting element ED2 in the first light-emitting region LA1. The first light-emitting element ED1 includes a first pixel electrode AE1, a first organic layer EL1, and a common electrode CE, and the second light-emitting element ED2 includes a second pixel electrode AE2, a second organic layer EL2, and a common electrode CE. The first light-emitting element ED1 may include a first main light-emitting region MLA1, and the second light-emitting element ED2 may include a first peripheral light-emitting region SLA1. The first main light-emitting region MLA1 and the first peripheral light-emitting region SLA1 may not overlap each other.

[0186] The encapsulation layer TFEL can be arranged on the common electrode CE, and the first light-shielding layer BM1 and the second light-shielding layer BM2 can be arranged on the encapsulation layer TFEL.

[0187] The first light-shielding layer BM1 and the second light-shielding layer BM2 may be spaced apart from each other and disposed on the encapsulation layer TFEL. The first light-shielding layer BM1 may overlap with the first pixel electrode AE1 and the second pixel electrode AE2, and may include a first aperture OPT1 disposed to overlap with the first main light-emitting region MLA1. For example, the first aperture OPT1 may be disposed to overlap with the first pixel electrode AE1, the first organic layer EL1, the first main light-emitting region MLA1, and the first opening OPA1. The second light-shielding layer BM2 may not overlap with the first pixel electrode AE1, and at least a portion of the second light-shielding layer BM2 may overlap with the second pixel electrode AE2. The second light-shielding layer BM2 may include a first main aperture MPT1 disposed to overlap with the first main light-emitting region MLA1 and the first peripheral light-emitting region SLA1. The first main aperture MPT1 of the second light-shielding layer BM2 can be arranged to overlap with the first main light-emitting area MLA1, the first pixel electrode AE1, the second pixel electrode AE2, the first organic layer EL1, the second organic layer EL2, the first main light-emitting area MLA1, the first peripheral light-emitting area SLA1, the first opening OPA1, and the second opening OPA2.

[0188] The first light-shielding layer BM1 can be arranged in the first main hole MPT1 of the second light-shielding layer BM2. For example, the first main hole MPT1 of the second light-shielding layer BM2 can overlap with the first light-shielding layer BM1. The area on the plane of the first main hole MPT1 of the second light-shielding layer BM2 can be larger than the area on the plane of the first light-emitting region LA1, and can also be larger than the area on the plane of the first light-shielding layer BM1.

[0189] The first peripheral aperture SPT1 can be disposed between the first light-shielding layer BM1 and the second light-shielding layer BM2. The first peripheral aperture SPT1 can be the area in the first main aperture MPT1 other than the first light-shielding layer BM1 and the first aperture OPT1. For example, the first peripheral aperture SPT1 can be the area between the side surface of the first main aperture MPT1 and the outer surface of the first light-shielding layer BM1. The first peripheral aperture SPT1 can be arranged to overlap with the first peripheral luminescent region SLA1 but not with the first main luminescent region MLA1.

[0190] According to one embodiment, the display device 10 can adjust the side surface visibility based on the light emission patterns of the first light-emitting element ED1 and the second light-emitting element ED2 in a light-emitting area (e.g., the first light-emitting area LA1).

[0191] As the first light-emitting mode, both the first light-emitting element ED1 and the second light-emitting element ED2 can emit light without restricting the visibility of the side surface. For example, in... Figure 4 As described above, in the first light-emitting mode, the driving voltage is transmitted through the first thin-film transistor TFT1 ( Figure 4The "DTR" is applied to the first pixel electrode AE1, so that the first light-emitting element ED1 can emit light. Furthermore, the same driving voltage is applied to the second thin-film transistor TFT2. Figure 4 The "STR7" is also applied to the second pixel electrode AE2, so that the second light-emitting element ED2 can emit light. Figure 21 As illustrated, if both the first light-emitting element ED1 and the second light-emitting element ED2 emit light in the first light-emitting mode, the light emitted from the first light-emitting area LA1 can be seen by the user through the first main hole MPT1 of the second light-shielding layer BM2 (e.g., the first hole OPT1 and the first peripheral hole SPT1 of the first light-shielding layer BM1), even if the display device 10 is viewed from any direction.

[0192] Conversely, as a second light-emitting mode of the display device 10, only the first light-emitting element ED1 can emit light when it is necessary to limit the visibility of the side surface. In the second light-emitting mode, the driving voltage is transmitted through the first thin-film transistor TFT1 (… Figure 4 The "DTR" is applied to the first pixel electrode AE1, so that the first light-emitting element ED1 can emit light. Conversely, the second thin-film transistor TFT2 ( Figure 4 When the “STR7” is cut off, the driving voltage is not applied (e.g., cut off) to the second pixel electrode AE2, so that the second light-emitting element ED2 can not emit light.

[0193] For example, such as Figure 22 As illustrated, if only the first light-emitting element ED1 emits light in the second light-emitting mode, light can be emitted through the first hole OPT1 of the first light-shielding layer BM1, and the light is blocked by the first light-shielding layer BM1 at a specific viewing angle. Since the second light-emitting element ED2 does not emit light, in the second light-emitting mode, the display device 10 allows only the user viewing from the front surface of the display area DA to see the image, while the user viewing from a specific viewing angle θ or a side surface cannot see the image. The specific viewing angle θ can be approximately 60 degrees or less. Therefore, the display device 10 can provide a privacy protection mode for the user.

[0194] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art should understand that the invention can be implemented in other specific ways without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as exemplary in all respects and not restrictive.

Claims

1. A display device, characterized by comprising: include: substrate; A first thin-film transistor and a second thin-film transistor are disposed on the substrate; A protective layer is disposed on the first thin-film transistor and the second thin-film transistor; A connecting electrode is disposed on the protective layer and connected to the first thin-film transistor; A sacrificial layer covers the edges of the connecting electrodes; A first pixel defining film is disposed on the protective layer and the sacrificial layer, and includes a first opening; A first pixel electrode and a second pixel electrode, wherein the first pixel electrode is disposed on the connecting electrode and the second pixel electrode is disposed on the first pixel defining film and connected to the second thin film transistor; A second pixel defining film is disposed on the first pixel defining film and the second pixel electrode, and includes a second opening that overlaps with the first opening; The light-emitting layer includes a first organic layer disposed on the first pixel electrode and a second organic layer disposed on the second pixel electrode; A common layer is disposed on the light-emitting layer and the second pixel defining film; A common electrode is disposed on the common layer; An encapsulation layer is disposed on the common electrode; as well as A light-shielding layer is disposed on the encapsulation layer and includes holes that overlap with the first opening and the second opening.

2. The display device according to claim 1, characterized in that, The side surface of the first pixel defining film includes a tip protruding from the side surface of the sacrificial layer. The first pixel electrode and the second pixel electrode are separated from each other by the tip of the first pixel defining film. The first organic layer and the second organic layer are separated from each other by the tip of the first pixel-defined film.

3. The display device according to claim 1, wherein include: The first light-emitting element includes the first pixel electrode, the first organic layer, the common layer, and the common electrode; as well as The second light-emitting element includes the second pixel electrode, the second organic layer, the common layer, and the common electrode. The first light-emitting element includes a main light-emitting region, which overlaps with the first opening and corresponds to the inner peripheral surface of the second pixel electrode. The second light-emitting element includes a peripheral light-emitting region, which overlaps with the second pixel electrode, the second organic layer, the common layer, and the common electrode in the thickness direction. The main light-emitting area overlaps with the first opening, the second opening, and the hole, while the surrounding light-emitting area does not overlap with the first opening and the hole but overlaps with the second opening.

4. The display device according to claim 3, characterized in that, The area of ​​the main light-emitting region is smaller than the area of ​​the first opening of the first pixel defining film and the area of ​​the second opening of the second pixel defining film.

5. The display device according to claim 3, characterized in that, The area or size of the hole is smaller than the area or size of the first pixel electrode, the area or size of the main light-emitting region, or the area or size of the first opening of the first pixel defining film.

6. The display device according to claim 1, characterized in that, The light-shielding layer includes: a first light-shielding layer including the aperture; a second light-shielding layer spaced apart from the first light-shielding layer and surrounding the first light-shielding layer in a plane; and a surrounding aperture disposed between the first light-shielding layer and the second light-shielding layer. The surrounding hole does not overlap with the first opening but overlaps with the second opening.

7. The display device according to claim 6, characterized in that, The corner where the lower surface and side surface of the first light-shielding layer intersects with the virtual line. The virtual line passes through the bend of the second pixel electrode from the upper surface of the first pixel electrode, which intersects with the end of the second pixel electrode in the thickness direction. The bend of the second pixel electrode corresponds to the part where the upper surface and side surface of the first pixel electrode intersect.

8. A display device comprising a plurality of pixels, wherein each of the plurality of pixels comprises a plurality of sub-pixels, characterized in that, Each of the plurality of sub-pixels includes: substrate; A first thin-film transistor and a second thin-film transistor are disposed on the substrate; A protective layer is disposed on the first thin-film transistor and the second thin-film transistor; A first pixel electrode and a second pixel electrode are disposed on the protective layer. The first pixel electrode is connected to the first thin-film transistor, and the second pixel electrode is connected to the second thin-film transistor. A pixel defining film covers the edges of each of the first pixel electrode and the second pixel electrode, and includes a first opening overlapping the first pixel electrode and a second opening overlapping the second pixel electrode; The light-emitting layer includes a first organic layer disposed on the first pixel electrode and a second organic layer disposed on the second pixel electrode; A common electrode is disposed on the light-emitting layer and the pixel defining film; An encapsulation layer is disposed on the common electrode; and A first light-shielding layer and a second light-shielding layer are disposed on the encapsulation layer. The first light-shielding layer includes a hole that overlaps with the first opening. The second light-shielding layer surrounds the first light-shielding layer and includes a main hole that overlaps with the first light-shielding layer.

9. The display device of claim 8, wherein, include: The first light-emitting element includes the first pixel electrode, the first organic layer, and the common electrode; as well as The second light-emitting element includes the second pixel electrode, the second organic layer, and the common electrode. The second pixel electrode is arranged spaced apart from the first pixel electrode and surrounds the first pixel electrode on a plane. The first light-emitting element includes a main light-emitting area that overlaps with the first opening and the hole, and the second light-emitting element includes a surrounding light-emitting area that overlaps with the main hole and does not overlap with the main light-emitting area.

10. The display device according to claim 9, wherein Also includes: The surrounding holes are arranged between the first light-shielding layer and the second light-shielding layer. The surrounding holes do not overlap with the main light-emitting area but overlap with the surrounding light-emitting area.

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