Quantum bit packaging device

Abstract

This application proposes a quantum bit packaging device, relating to the field of chip packaging technology. The problem this application aims to solve is that quantum bit packaging devices are large in size, suffer from crosstalk between cables, and have low packaging density. The proposed quantum bit packaging device includes: a packaging base, in which a quantum chip is disposed; a packaging cover plate, disposed on the base and used to seal the packaging base; connectors, evenly distributed on the sidewalls of the packaging base in a predetermined number; and cables, which vertically connect to the quantum chip within the packaging base through the cover plate. The quantum bit packaging device of this embodiment reduces the size of the packaging device and crosstalk between cables, thereby increasing the packaging density.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a quantum bit packaging device. Background Technology

[0002] Quantum technology, especially quantum computing, has become a crucial frontier in global scientific research. Quantum computers utilize the principles of quantum mechanics for information processing and computation, with the qubit as its core component. Unlike the binary bits of traditional computers, qubits can exist in multiple states simultaneously. This quantum superposition and entanglement phenomenon offers quantum computers enormous potential to surpass classical computers, particularly in simulating complex physical systems, solving optimization problems, and machine learning.

[0003] The fabrication of superconducting qubits typically requires the use of micro- and nano-fabrication techniques to integrate them into superconducting circuits, forming qubit chips. These chips are usually based on devices such as microwave resonant cavities and superconducting circuits, and use integrated circuits to realize the transmission and processing of quantum information. However, most proposals for large-scale quantum circuits are made in a flat two-dimensional lattice. Therefore, to achieve future scalability, signals must be transmitted perpendicular to the two-dimensional circuit plane. Utility Model Content

[0004] In view of this, this application proposes a quantum bit packaging device that improves packaging density by reducing the size of the packaging device and crosstalk between cables.

[0005] This utility model provides a quantum bit packaging device for packaging a quantum chip, comprising: a packaging base, wherein the quantum chip is disposed within the packaging base; a packaging cover plate, wherein the packaging cover plate is disposed on the base and is used to seal the packaging base; connectors, wherein the connectors are evenly distributed on the side wall of the packaging base in a predetermined number; and a cable, wherein the cable is vertically connected to the quantum chip within the packaging base through the cover plate.

[0006] In one possible implementation, the packaging base is a cylindrical structure, and the outer wall of the packaging base is uniformly provided with a plurality of through holes. Threaded holes are symmetrically provided on both sides of the through holes. The through holes are used to insert the connector, and the threaded holes are used to fix the connector and the packaging base.

[0007] In one possible implementation, the packaging base has a groove at its center, and a square slot is provided inside the groove for placing the quantum chip.

[0008] In one possible implementation, multiple limiting plates are uniformly arranged on the outer periphery of the square groove, and a channel is formed between two adjacent limiting plates. The multiple channels correspond one-to-one with the through holes. The channels are used to place the wiring of the PCB board. In the usage state, the PCB board is bonded to the quantum chip with gold wires.

[0009] In one possible implementation, the surface of the encapsulation base is provided with a plurality of threaded holes, and the upper surface of the encapsulation cover is provided with a plurality of through holes. When the encapsulation cover and the encapsulation base are connected, the threaded holes and the through holes are threadedly connected one-to-one.

[0010] In one possible implementation, the encapsulation cover has a first plane whose dimensions are the same as the outer perimeter dimensions of the encapsulation base.

[0011] In one possible implementation, the encapsulation cover is further provided with a plurality of cylinders, and the encapsulation base is provided with a plurality of grooves. The shapes of the plurality of cylinders are adapted to the shapes of the grooves. When the encapsulation cover and the encapsulation base are connected, the cylinders extend into the grooves for connection.

[0012] In one possible implementation, the encapsulation cover is further provided with a protrusion, and the surface of the protrusion is provided with a plurality of limiting plates, and a channel is formed between adjacent limiting plates, and the channel is connected to the channel on the outer periphery of the quantum chip in a one-to-one correspondence.

[0013] In one possible implementation, the encapsulation cover has a plurality of through holes at its center, the diameter of which matches the diameter of the cable, and the cable is welded to the through holes.

[0014] In one possible implementation, the cable extends through the through-hole to the surface above the quantum chip, with a distance of 0.9 mm between the cable and the quantum chip. An insertion hole is also provided on the outer periphery of the through-hole for fixing a PIN pin, which is used to enhance the isolation between the cables.

[0015] The beneficial effects of this application are: This invention discloses a quantum bit packaging device, which connects a packaging cover plate and a packaging base. Cables are arranged on the cover plate, resulting in short and straight signal transmission lines, reducing potential attenuation or errors during signal transmission. Connectors are located on the outer circumference of the base, optimizing the structural density of the packaging device and avoiding signal distortion or short circuits that may occur in conventional packaging. This effectively reduces the size of the packaging device, minimizes crosstalk between cables, and ensures efficient signal transmission.

[0016] Other features and aspects of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0017] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.

[0018] Figure 1 This invention provides a schematic diagram of the structure of a quantum bit packaging device according to an embodiment of the present application. Figure 2 This diagram shows a disassembled schematic of a quantum bit packaging device according to an embodiment of this application; Figure 3 A cross-sectional view of a quantum bit packaging device according to an embodiment of this application is shown; Figure 4 A schematic diagram of the packaging base in the quantum bit packaging device according to an embodiment of this application is shown; Figure 5 This is a front view of the encapsulation cover in the quantum bit encapsulation device according to an embodiment of this application; Figure 6 This is a back view of the packaging cover in the quantum bit packaging device according to an embodiment of this application; Figure 7 This diagram illustrates a package cover with PIN pins in a quantum bit packaging device according to an embodiment of this application.

[0019] Figure label: 1-Encapsulation base; 101, 201, 202-Through holes; 203, 204-Insertion holes; 102, 105-Threaded holes; 106, 107-Groove; 103, 104, 208-Square groove; 2-Encapsulation cover; 205-First planar layer; 206-Cylinder; 207-Second planar layer; 3-Connector; 4-Cable; 5-Quantum chip; 6-PCB board; 7-PIN pin. Detailed Implementation

[0020] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0021] It should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application or to simplify the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0023] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0024] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0025] Figure 1 This invention provides a schematic diagram of the structure of a quantum bit packaging device according to an embodiment of the present application. Figure 2 This diagram shows a disassembled schematic of a quantum bit packaging device according to an embodiment of this application; Figure 3This illustration shows a cross-sectional view of a quantum bit packaging device according to an embodiment of this application. The present invention provides a quantum bit packaging device for packaging a quantum chip 5, comprising: a packaging base 1, with the quantum chip 5 disposed within the packaging base 1; a packaging cover 2, disposed on the base and used to seal the packaging base 1; connectors 3, evenly distributed on the sidewalls of the packaging base 1 in a predetermined number; and cables 4, vertically connected to the quantum chip 5 within the packaging base 1 via the cover. The connection between the packaging cover 2 and the packaging base 1, with the cables 4 arranged on the cover, results in short and straight signal transmission lines, reducing potential attenuation or errors during signal transmission. The connectors 3 are disposed on the outer circumferential surface of the packaging base 1, optimizing the structural density of the packaging device, ensuring efficient communication between the quantum chip 5 and external circuits, avoiding signal distortion or short-circuit problems that may occur in conventional packaging, effectively reducing the size of the packaging device, reducing crosstalk between cables 4, and ensuring efficient signal transmission.

[0026] Specifically, the main body of the packaging base 1 is a cylindrical structure. Several connectors 3 are connected to the side walls of the packaging base 1. A quantum chip 5 is disposed inside the packaging base 1. The packaging cover 2 is a circular plate that fits the opening of the packaging base 1, sealing the packaging base 1. Cables 4 are vertically connected to the quantum chip 5 inside the packaging base 1 through the packaging cover 2. In this embodiment, there are 22 connectors 3, positioned at the center of the height of the packaging base 1. It should be noted that the specific number of connectors 3 can be determined according to needs and the performance of the packaged chip. Figure 4 A schematic diagram of the packaging base 1 in the quantum bit packaging device according to an embodiment of this application is shown; Figure 5 This paper shows a front view of the packaging cover 2 in the quantum bit packaging device according to an embodiment of this application; Figure 6 The diagram shows a back view of the encapsulation cover 2 in the quantum bit encapsulation device according to an embodiment of this application. In one possible implementation, the encapsulation base 1 has a cylindrical structure. Multiple through holes 101 are uniformly arranged on the outer wall of the encapsulation base 1. Threaded holes 102 are symmetrically arranged on both sides of the through holes 101. The through holes 101 are used to insert a connector 3, and the threaded holes 102 are used to fix the connector 3 and the encapsulation base 1. A groove 107 is provided at the center of the encapsulation base 1, and a square groove 103 is provided within the groove 107 for placing the quantum chip 5.

[0027] Specifically, the packaging base 1 has a circular through hole 101 and a circular threaded hole 102 on its side wall. The through hole 101 and the threaded hole 102 are used to house the fixing connector 3. The connector 3 is a through-wall SMA connector, and the connector 3 is threadedly connected to the packaging base 1. The packaging base 1 has a cylindrical groove 107 in the middle and a square groove 103 at the center of the packaging base for placing the chip 5. The size of the square groove 103 matches the size of the chip 5. Square grooves 104 are arranged around the square groove 103, extending from the square groove 103 to the through hole 101 for placing the wiring of the PCB board 6. The PCB board 6 is soldered to the connector 3 and bonded to the chip 5 with gold wires. The chip 5 is a superconducting quantum bit chip with bit units on its surface. A resonant cavity is also provided below the square groove 103. The resonant cavity is used to suppress the resonant frequency to outside the operating frequency. The resonant cavity can effectively isolate and reduce the resonant frequencies that may appear in the system, avoiding interference from these frequencies to the quantum chip or circuit. By pushing the resonant frequency outside the operating frequency, the resonant cavity can reduce noise and instability caused by frequency resonance, thereby enhancing the performance of sensitive electronic components such as quantum chips.

[0028] In one possible implementation, multiple limiting plates are evenly arranged on the outer periphery of the square groove 103, forming a channel between adjacent limiting plates. Each channel corresponds to a through hole 101, and the channel is used to accommodate the wiring of the PCB board 6. In use, the PCB board 6 is bonded to the quantum chip 5 with gold wires. Multiple limiting plates surround the center of the packaging base 1 to form a square gap for accommodating the quantum chip 5, with gaps between adjacent limiting plates forming channels for accommodating the wiring of the PCB board 6.

[0029] In one possible implementation, the surface of the encapsulation base is provided with multiple threaded holes 105, and the encapsulation cover plate 2 is provided with multiple through holes 202. When the encapsulation cover plate 2 and the encapsulation base 1 are connected, the threaded holes 105 and the through holes 202 are threadedly connected one-to-one. The encapsulation cover plate 2 has a first plane 205, the size of which is the same as the outer periphery of the encapsulation base 1. The encapsulation cover plate 2 is also provided with multiple cylinders 206, and the encapsulation base 1 is provided with multiple corresponding grooves 106. The shapes of the multiple cylinders 206 are adapted to the shapes of the grooves 106. When the encapsulation cover plate 2 and the encapsulation base 1 are connected, the cylinders 206 extend into the grooves 106 for connection. The encapsulation cover plate 2 is also provided with protrusions, and the surface of the protrusions is provided with multiple limiting plates. Channels are formed between adjacent limiting plates, and the channels are connected one-to-one with the channels on the outer periphery of the quantum chip 5. The encapsulation cover 2 and the encapsulation base 1 have the same diameter. The encapsulation base 1 has multiple threaded holes 105, which correspond one-to-one with through holes 202. When the encapsulation cover 2 and the encapsulation base 1 are connected, the threaded holes 105 and the through holes 202 are threadedly connected. At the same time, the encapsulation cover 2 also has multiple cylinders 206, and the encapsulation base 1 has corresponding grooves 106. The cylinders 206 extend into the grooves 106 for connection, which is used to further seal the encapsulation cover 2 and the encapsulation base 1.

[0030] Specifically, such as Figure 4 and Figure 7 As shown, the packaging base 1 has a hollow annular structure in the middle, and a support for the quantum chip 5 is located at the bottom. A groove is provided in the middle of the support, and the area of ​​the groove is smaller than the area of ​​the quantum chip 5 to be packaged. Multiple limiting plates are provided on the upper surface around the groove of the support. A channel is formed between adjacent limiting plates, and the number of channels is the same as the number of connectors 3. The connectors 3 pass through the channels and communicate with the quantum chip 5 packaged inside. It should also be noted that in this embodiment, the multiple limiting plates form a rectangular placement platform along their inner edges towards the center. The rectangular placement platform matches the quantum chip 5 to be packaged. Furthermore, the groove in the middle of the support is located in the middle of the rectangular placement platform. It should be noted that the shape of the placement platform is consistent with the shape of the quantum chip 5 to be packaged. When the quantum chip 5 to be placed has other shapes, the shape of the placement platform is also the corresponding shape, enabling precise placement of the quantum chip 5 to be packaged.

[0031] Furthermore, in one embodiment, a second limiting plate structure matching the limiting plate of the support is also provided on the top surface facing the packaging base 1. It should be noted that the second limiting plate and the limiting plate structure on the support are in the same position. Preferably, as an alternative implementation, the first limiting plate and the second limiting plate are in the same position, but the first limiting plate and the second limiting plate can be configured to interlock with each other. As shown in the figure, the first limiting plate consists of two parts, one high and one low, and the second limiting plate also consists of two parts, one high and one low. The height positions of the two limiting plates are exactly opposite, forming a mutually fitting combination. After being snapped together, they fit together to form a through-hole structure on the side that matches the connector 3.

[0032] In one possible implementation, the package cover has multiple through holes 203 at its center, the diameter of which matches the diameter of the cable 4. The cable 4 is soldered to the through holes 203. The cable 4 extends through the through holes 203 to the surface of the quantum chip 5, with a spacing of 0.9 mm between the cable 4 and the quantum chip 5. Insertion holes are also provided on the outer periphery of the through holes 203 to secure PIN pins 7, which enhance the isolation between the cables 4. The spacing between the cable 4 and the quantum chip 5 provides sufficient space for gold wire bonding. During gold wire bonding, the relative positions of the quantum chip 5 and the cable 4 can be fine-tuned to ensure precise alignment of the connection points, improving the stability and reliability of the connection. Appropriate spacing can reduce heat transfer and mechanical stress between the quantum chip 5 and the cable 4, reduce the impact of thermal expansion on the connection points, and enhance the stability of the system under high temperature or long-term operating conditions.

[0033] Specifically, the upper wall of the encapsulation base 1 is provided with a threaded hole 105, and the encapsulation cover plate 2 is provided with a through hole 202. The encapsulation cover plate 2 is threadedly connected to the encapsulation base 1. The threaded hole 105 and the through hole 201 are positioned correspondingly. The encapsulation cover plate 2 is provided with a first plane 205. The outer dimensions of the first plane 205 are correspondingly set with the outer dimensions of the encapsulation base 1. The bottom surface of the encapsulation cover plate 2 is provided with a cylinder 206. The cylinder 206 is correspondingly set with a circular groove 106 for fixing the installation position of the encapsulation cover plate 2 and the encapsulation base 1. The lower wall of the encapsulation cover plate 2 is provided with a protruding cylindrical second plane 207. The cylinder 207 is installed in the groove 107. The size of the cylinder 207 matches the groove 107. The bottom of the encapsulation cover plate 2 is provided with a square groove 208. The square groove 208 is correspondingly set with a square groove 104. Multiple through holes 203 are provided in the center of the encapsulation cover plate 2. The diameter of the through holes 203 matches the diameter of the cable 4. The cable 4 is soldered to the through holes 203. The inner conductor of the cable 4 extends 0.9mm above the chip surface through the through holes 203, forming a waveguide cavity for signal transmission via air coupling. Insertion holes 204 are provided around the through holes 203 for mounting and fixing PIN pins 7. The size of the PIN pins matches the size of the insertion holes to enhance the isolation between cables. There are four insertion holes. When the PIN pins 7 are inserted into the insertion holes, they are inserted one-to-one and parallel to each other. The PIN pins 7 help to evenly distribute current and signals, reduce the possibility of electromagnetic interference and signal reflection, and optimize signal transmission quality. There are four PIN pins 7 on the side of one cable, which form a Faraday cage to enhance the isolation between cables.

[0034] In one possible implementation, the packaging base 1 and the packaging cover 2 are made of oxygen-free copper. The use of oxygen-free copper material allows the quantum chip 5 package to maintain good performance even in ultra-low temperature environments, further improving the high integration and high thermal conductivity of the quantum chip 5, and ensuring high-efficiency quantum bit signal transmission.

[0035] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A quantum bit packaging device for packaging quantum chips, characterized in that, include: A packaging base, in which the quantum chip is disposed; A packaging cover plate is disposed on the base and is used to seal the packaging base; Connectors, wherein the connectors are evenly distributed on the side wall of the packaging base in a predetermined number; A cable, which is vertically connected to the quantum chip within the packaging base via the cover plate.

2. The quantum bit packaging apparatus of claim 1, wherein, The encapsulation base is a cylindrical structure. Multiple through holes are evenly arranged on the outer wall of the encapsulation base. Threaded holes are symmetrically arranged on both sides of the through holes. The through holes are used to insert the connector, and the threaded holes are used to fix the connector and the encapsulation base.

3. The quantum bit packaging apparatus of claim 2, wherein, The packaging base has a groove at its center, and a square slot is provided inside the groove for placing the quantum chip.

4. The quantum bit packaging apparatus of claim 3, wherein, Multiple limiting plates are evenly arranged on the outer periphery of the square groove, and a channel is formed between two adjacent limiting plates. Each of the multiple channels corresponds to a through hole. The channel is used to place the wiring of the PCB board. In use, the PCB board is bonded to the quantum chip with gold wires.

5. The quantum bit packaging apparatus of claim 1, wherein, The surface of the encapsulation base is provided with multiple threaded holes, and the upper part of the encapsulation cover is provided with multiple through holes. When the encapsulation cover and the encapsulation base are connected, the threaded holes and the through holes are threadedly connected one-to-one.

6. The quantum bit packaging apparatus of claim 4, wherein, The encapsulation cover has a first plane, the size of which is the same as the outer perimeter of the encapsulation base.

7. The quantum bit packaging apparatus of claim 6, wherein, The encapsulation cover plate is also provided with a plurality of cylinders, and the encapsulation base is provided with a plurality of grooves. The shape of the plurality of cylinders is adapted to the shape of the grooves. When the encapsulation cover plate and the encapsulation base are connected, the cylinders extend into the grooves for connection.

8. The quantum bit packaging apparatus of claim 7, wherein, The encapsulation cover is also provided with protrusions, and the surface of the protrusions is provided with multiple limiting plates. A channel is formed between adjacent limiting plates, and the channel is connected to the channel on the outer periphery of the quantum chip in a one-to-one correspondence.

9. The quantum bit packaging apparatus of claim 1, wherein, The encapsulation cover has multiple through holes at its center, the diameter of which matches the diameter of the cable, and the cable is welded to the through holes.

10. The quantum bit packaging apparatus of claim 2, wherein, The cable extends through the through hole to the surface of the quantum chip. The distance between the cable and the quantum chip is 0.9 mm. An insertion hole is also provided on the outer periphery of the through hole. The insertion hole is used to fix the PIN pin and the PIN pin is used to enhance the isolation between the cables.

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