Interconnect structure and semiconductor device

Abstract

An interconnect structure and a semiconductor device, the interconnect structure for a semiconductor device includes a first bonding pad, a second bonding pad, and a first protective dummy. The first bonding pad has a first surface. The second bonding pad has a second surface that bonds the first surface of the first bonding pad. The first protective dummy is adjacent to the second bonding pad and has a third surface that is substantially coplanar with the second surface of the second bonding pad.

Description

Technical Field

[0001] This disclosure relates to an interconnect structure and a semiconductor device. Background Technology

[0002] When two different materials (e.g., different metals) come into electrical contact with each other in the presence of an electrolyte, the galvanic effect, also known as galvanic corrosion, can occur. This electrical contact can create a galvanic cell, with one material acting as the anode and the other as the cathode. A galvanic cell can lead to accelerated corrosion of the anode material.

[0003] Anode materials (e.g., materials with high electrochemical potential energy) may lose electrons (oxidation) and corrode. Cathode materials (e.g., materials with low electrochemical potential energy) may gain electrons (reduction) and avoid corrosion. Electrolytes may include, for example, water containing dissolved salts or acids. Electrolytes facilitate ion movement between the anode and cathode materials. Utility Model Content

[0004] Some embodiments disclosed herein provide an interconnect structure including a first bonding pad, a second bonding pad, and a first protective dummy. The first bonding pad has a first surface. The second bonding pad has a second surface that engages with the first surface of the first bonding pad. The first protective dummy is adjacent to the second bonding pad and has a third surface that is substantially coplanar with the second surface of the second bonding pad.

[0005] Some embodiments disclosed herein provide a semiconductor device including a first structure, a second structure, and an interconnect. The first structure includes a first bonding layer. The second structure is bonded to the first structure and includes a second bonding layer. The interconnect electrically couples the first structure to the second structure and includes a first bonding pad, a second bonding pad, and a first protective dummy. The first bonding pad is in the first bonding layer and has a first surface. The second bonding pad is in the second bonding layer and has a second surface, the second surface engaging the first surface of the first bonding pad. The first protective dummy is adjacent to the second bonding pad in the second bonding layer and has a third surface, the third surface being substantially coplanar with the second surface of the second bonding pad.

[0006] Some embodiments of this disclosure provide an interconnect structure including a first bonding pad, a second bonding pad, and a first protective dummy. The first bonding pad has a first surface. The second bonding pad has a second surface that engages with the first surface of the first bonding pad. The first protective dummy is adjacent to the second bonding pad and has a third surface that is substantially coplanar with the second surface of the second bonding pad, wherein the second bonding pad comprises a circle, and the first protective dummy is formed concentrically with the second bonding pad. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, the following detailed description will provide the best understanding of all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1A This is a vertical cross-sectional view of a semiconductor device according to one or more embodiments;

[0009] Figure 1B It is a transparent top view (e.g., a plan view) of a semiconductor device according to one or more embodiments;

[0010] Figure 1C According to one or more embodiments Figure 1A A detailed vertical cross-sectional view of region R1 in the image;

[0011] Figure 1D According to one or more embodiments Figure 1B A detailed top view (e.g., a plan view) of region R2 in the diagram;

[0012] Figure 2A This is a vertical cross-sectional view of an intermediate structure including an intermediary layer (e.g., an organic intermediary layer) formed on a first carrier substrate (e.g., a carrier wafer) according to an embodiment of the present disclosure;

[0013] Figure 2B It is a vertical cross-sectional view of an intermediate structure including an intermediate bonding layer after patterning, according to one or more embodiments;

[0014] Figure 2C This is a vertical cross-sectional view of an intermediate structure including a metal layer according to one or more embodiments;

[0015] Figure 2D According to one or more embodiments Figure 2C A schematic diagram of a CMP apparatus used to perform chemical mechanical polishing (CMP) on an intermediate structure;

[0016] Figure 2D Also included are top and vertical cross-sectional views of the intermediate bonding layer and the first protective dummy intermediate bonding layer after the CMP process;

[0017] Figure 2E It is a vertical cross-sectional view of an intermediate structure including an intermediate bonding layer with a polished surface, according to one or more embodiments;

[0018] Figure 2FIt is a vertical cross-sectional view of an intermediate structure including a first semiconductor die and a second semiconductor die according to one or more embodiments;

[0019] Figure 2G This is a vertical cross-sectional view illustrating an intermediate structure including a molding material layer, according to one or more embodiments;

[0020] Figure 2H This is a vertical cross-sectional view illustrating an intermediate structure including a plurality of C4 bumps according to one or more embodiments;

[0021] Figure 3 This is a flowchart illustrating a method for forming an intermediary layer module (e.g., a semiconductor device) according to one or more embodiments;

[0022] Figure 4A It is a top view of a plurality of interconnects having a first alternative design according to one or more embodiments;

[0023] Figure 4B It is along Figure 4A A vertical cross-sectional view of the interconnection with the first alternative design in cross section B-B';

[0024] Figure 5A It is a top view of the interconnects having a second alternative design according to one or more embodiments;

[0025] Figure 5B It is a top view of the interconnects having a third alternative design according to one or more embodiments;

[0026] Figure 5C It is a top view of the interconnects having a fourth alternative design according to one or more embodiments;

[0027] Figure 5D It is a top view of the interconnects having a fifth alternative design according to one or more embodiments;

[0028] Figure 6A It is a vertical cross-sectional view of the interconnects having a sixth alternative design according to one or more embodiments;

[0029] Figure 6B It is a bottom view of the interface in an interconnect having a sixth alternative design according to one or more embodiments;

[0030] Figure 6C It is a top view of the interface in an interconnect having a sixth alternative design according to one or more embodiments;

[0031] Figure 7AIt is a vertical cross-sectional view of the interconnects having a seventh alternative design according to one or more embodiments;

[0032] Figure 7B It is a bottom view of the joint interface in an interconnect having a seventh alternative design according to one or more embodiments;

[0033] Figure 7C It is a top view of the interface in an interconnect having a seventh alternative design according to one or more embodiments;

[0034] Figure 8 It is a vertical cross-sectional view of a package structure including an intermediary layer module according to one or more embodiments;

[0035] Figure 9 It is a vertical cross-sectional view of a packaged module including interconnects according to one or more embodiments;

[0036] Figure 10 It is a vertical cross-sectional view of a package structure including interconnects according to one or more embodiments.

[0037] [Symbol Explanation]

[0038] 1: First carrier substrate

[0039] 2: Second carrier substrate

[0040] 10: Intermediary Layer / Second Structure

[0041] 12: Dielectric material layer

[0042] 12a: Redistribution layer

[0043] 13: Intermediate bonding layer / Second bonding layer

[0044] 13s: Surface

[0045] 14: Low passivation layer

[0046] 14a: Intermediate low-bonding pad

[0047] 93: Low bonding layer / Second bonding layer

[0048] 110: Packaging substrate / second structure

[0049] 110c: Solder ball

[0050] 112: Interconnection Structure

[0051] 119: Encapsulation bottom filler layer

[0052] 120: Semiconductor Devices / Intermediate Layer Modules

[0053] 121:C4 bump

[0054] 127: Molding material layer / upper molding layer

[0055] 130: Interconnect / Interconnection Structure

[0056] 130D: Grain-side interconnect portion

[0057] 130I: Interconnection section on the intermediate layer side

[0058] 130-1: First Interconnect

[0059] 130-2: Second Interconnect

[0060] 130-3: Third Interconnect

[0061] 130-4: Fourth Interconnect

[0062] 131: Grain bonding pad / First bonding pad

[0063] 131s: Surface

[0064] 132: Intermediate joint pad / Second joint pad

[0065] 132L: Metal layer

[0066] 132s: Surface

[0067] 133: First protection is a sham

[0068] 133s: Surface

[0069] 133L: Metal layer

[0070] 133-1: First protection is a sham

[0071] 133-2: First protection is a sham

[0072] 134: Grain side perforation

[0073] 135: Intermediate layer side perforation

[0074] 136: Interconnection / First Connector

[0075] 136-1: First connector

[0076] 136-2: First connector

[0077] 140: Semiconductor die / first structure

[0078] 140a: Upper surface

[0079] 141: First semiconductor die

[0080] 142: Second semiconductor die

[0081] 145: Dielectric layer

[0082] 146: Grain bonding layer / First bonding layer

[0083] 146s: Surface

[0084] 150: Joint Interface

[0085] 160: Adhesive layer

[0086] 170: TIM layer

[0087] 190: Straight through hole

[0088] 200: CMP equipment

[0089] 201: Rotary Platform

[0090] 202: Grinding Pad

[0091] 203: Wafer carrier

[0092] 204: Grinding slurry distributor

[0093] 205: Grinding fluid

[0094] 233: Second protection is a dummy

[0095] 233s: Surface

[0096] 233-1: Second protection is a dummy

[0097] 233-2: Second protection is a dummy

[0098] 236: Second connector

[0099] 236-1: Second connector

[0100] 236-2: Second connector

[0101] 310: Steps

[0102] 320: Steps

[0103] 330: Steps

[0104] 340: Steps

[0105] 350: Steps

[0106] 800: Package Structure / Semiconductor Device

[0107] 900: Packaging structure / Packaging module / Semiconductor device

[0108] 920: Bottom semiconductor die / Second semiconductor die / Second structure

[0109] 922: Active Zone

[0110] 924: Silicon Block Area

[0111] 927: Molding material layer

[0112] 932: Low bonding pad / second bonding pad

[0113] 940: First structure / top semiconductor die

[0114] 942: Active Zone

[0115] 944: Silicon Block Area

[0116] 950: Joint Interface

[0117] 1000: Semiconductor Device / Packaging Structure

[0118] 1013: Low bonding layer / Second bonding layer

[0119] 1032: Low bonding pad / second bonding pad

[0120] 1035: Substrate side perforation

[0121] 1040: First Structure / Semiconductor Grain

[0122] 1050: Joint Interface

[0123] 1130: Encapsulation Cover

[0124] 1130a: Package covering the pin portion

[0125] 1130p: Encapsulation cover plate section

[0126] 1150: Reinforcing ring

[0127] A-A': Cross section

[0128] B-B': Cross section

[0129] C: Center

[0130] D133: Gavanny Loss

[0131] D1: Distance / First Distance

[0132] D233: Gavani Loss

[0133] D2: Distance / Second Distance

[0134] D3: First separation distance

[0135] D4: Second separation distance

[0136] L1: First Length

[0137] L2: Second Length

[0138] O132: Second mating pad opening / opening

[0139] O133: First protection dummy opening / opening

[0140] O14: Opening

[0141] O204: Opening

[0142] R1: Region

[0143] R2: Region

[0144] T1: Thickness

[0145] T2: Thickness

[0146] T3: Thickness

[0147] W120: Wafer

[0148] W1: Width / First Width

[0149] W2: Width / Second Width

[0150] W3: Width

[0151] W4: Width

[0152] x: direction

[0153] y: direction

[0154] z: Direction Detailed Implementation

[0155] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the content of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or words may be repeated in various examples. This repetition is for simplicity and clarity and is not, in itself, merely a relationship between the various embodiments and / or configurations discussed.

[0156] Furthermore, the spatially related terms used herein, such as “below,” “under,” “below,” “above,” “on,” etc., are for descriptive purposes to describe the relationship between one element or feature and another element or feature as shown in the figures. These spatially related terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Unless otherwise explicitly stated, each element having the same reference numerals is assumed to have the same material composition and thickness within the same thickness range.

[0157] The galvanic effect can occur during semiconductor manufacturing processes. It can be particularly relevant during chemical mechanical polishing (CMP) processes. When polishing composite films composed of different metals or metal-dielectric combinations, electrochemical interactions can occur between the different materials in the CMP polishing slurry, which may include an electrolyte solution. This interaction can lead to accelerated corrosion or oxidation of one material relative to another.

[0158] CMP (Continuous Metallurgy) polishing processes can be used to polish surfaces that incorporate different materials with varying electrochemical potential energies. The CMP polishing slurry acts as an electrolyte, enabling the formation of a galvanic cell between the different materials. Materials with higher electrochemical potential energies act as anodes and tend to oxidize (corrode) more readily, while materials with lower potential energies act as cathodes and are protected. Anode materials undergo oxidation reactions, leading to material removal or corrosion. Cathode materials undergo reduction reactions but are generally less affected.

[0159] The Gavanee effect can lead to uneven material removal rates. For example, in a copper / tantalum system, copper (as the anode) may corrode faster than tantalum (as the cathode), resulting in problems with planarization and film integrity. Accelerated corrosion of the anolyte can create defects, such as pitting or increased roughness on the wafer surface, which can negatively impact device performance and yield.

[0160] Semiconductor manufacturing employs a variety of mitigation strategies to address the galvanic effect during CMP processes. For example, the composition of the CMP slurry (including pH, oxidants, and inhibitors) can be controlled to reduce the galvanic effect. Inhibitors are added to the slurry to prevent excessive corrosion of the anodic material. Additives can be used to passivate surfaces or balance the electrochemical potentials of the different materials involved. The slurry composition can also be optimized to achieve balanced removal rates for all materials. External potentials can be applied during CMP to control electrochemical reactions. Process parameters such as downpressure, plateau speed, and slurry flow rate can also be optimized to reduce the effects of galvanic corrosion.

[0161] The galvanic effect during CMP processes may be particularly relevant to bonding processes (e.g., bonding that may include metal-to-metal and dielectric-to-dielectric bonding). For example, bonding can be used to join two structures together in a semiconductor device. A metal-to-metal bond can be formed between the bonding pads of the two structures. The bonding interface may include a metal-to-metal (e.g., copper-to-copper) interface between the surfaces of the bonding pads.

[0162] CMP (Concentrated Metallurgical Processing) can be used to planarize the surface of bonding pads (e.g., anode materials) in dielectric materials (e.g., cathode materials). Triboelectric motion and photoelectric effects during CMP processes (e.g., polishing processes) can contribute to the galvanic effect. The galvanic effect can lead to excessive removal of the bonding pad surface (e.g., copper surface) and metal loss (e.g., copper loss). Metal loss can increase the risk of increased interface resistance and reduced reliability.

[0163] At least one embodiment of this disclosure may include interconnects (e.g., protective interconnects) and semiconductor devices including the interconnects. The interconnects may be located at a bonding interface. At least one embodiment may include an improved design of the bonding interface. At least one embodiment may help reduce the risk of over-removal caused by the galvanic effect during a CMP process forming one or more bonding pads at the bonding interface. At least one embodiment may help reduce metal loss non-bond defects and improve yield.

[0164] Interconnects may include protective dummy elements (e.g., protective dummy patterning) surrounding at least one bonding pad within the interconnect. The protective dummy element may include, for example, a protective ring formed around the bonding pad within the interconnect. During the CMP process, charged ions may first contact the protective dummy element. The protective dummy element may neutralize the charged ions before contacting the bonding pad. Therefore, metal loss due to the galvanic effect can be suppressed or avoided.

[0165] At least one embodiment may include design rules for the protective dummy (e.g., protective dummy pattern design rules). Specifically, the width of the protective dummy may be greater than 0.01 μm (e.g., about 0.3 μm). The separation distance between the protective dummy and the bonding pad may be greater than 0.1 μm (e.g., about 0.5 μm). The distance between adjacent protective dummy (e.g., protective dummy-to-protective dummy distance) may be greater than 0.1 μm (e.g., about 2 μm). The thickness of the protective dummy may be greater than 0.1 μm (e.g., about 1.5 μm or 2 μm). The thickness of the bonding pad may be substantially the same as the thickness of the protective dummy.

[0166] In at least one embodiment, the protective dummy may connect to the bonding pad (e.g., a copper pad). The protective dummy may be electrically insulating (e.g., not connected to other circuitry). In at least one embodiment, the interconnect may include a protective dummy for both bonding pads. Therefore, at the bonding interface, both bonding pads may include a protective dummy.

[0167] Figure 1A This is a vertical cross-sectional view of a semiconductor device 120 according to one or more embodiments. Figure 1B It is a transparent top view (e.g., a plan view) of a semiconductor device 120 according to one or more embodiments. Figure 1A It is along Figure 1B The vertical cross-sectional view of the semiconductor device 120 at cross section A-A'. Figure 1C According to one or more embodiments Figure 1A A detailed vertical cross-sectional view of region R1 in the diagram. Figure 1D According to one or more embodiments Figure 1B A detailed top view (e.g., a plan view) of region R2 in the diagram.

[0168] Generally, semiconductor device 120 may include an interposer module. Semiconductor device 120 is not limited to an interposer module, but is described in detail below. Figures 1A to 1D The semiconductor device in the middle can be used as an intermediary layer module 120.

[0169] Interposer module 120 may include one or more semiconductor dies 140 (e.g., a first structure) on interposer 10 (e.g., a second structure). Semiconductor dies 140 may be bonded to interposer 10. Interposer module 120 may also include one or more interconnects 130 (e.g., protection interconnects). Interconnects 130 may electrically couple semiconductor dies 140 to interposer 10. Interposer module 120 is not limited to any particular configuration. Interposer module 120 may include, for example, flip chip-chip scale package (FCCSP) designs, chip-on-wafer-on-substrate designs, integrated fan-out designs, etc.

[0170] Interposer 10 is not necessarily limited to any particular material or configuration. Interposer 10 may include, for example, organic materials (e.g., dielectric polymers), inorganic materials (e.g., silicon), glass substrates, etc. In at least one embodiment, interposer 10 may include alternating stacked dielectric material layers 12 and redistribution layers 12a. The number of dielectric material layers 12 and / or redistribution layers 12a in interposer 10 is not limited by this disclosure.

[0171] In at least one embodiment, the dielectric layer 12 may include, for example, polyimide (PI), epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. In some embodiments, the redistribution layer 12a may include a conductive material. The conductive material may include metals, such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals. Other dielectric and conductive materials are within the scope of this disclosure.

[0172] The redistribution layer 12a may include a metallic interconnect structure, i.e., a metallic structure providing electrical connections between nodes in the structure. The redistribution layer 12a may include a metallic seed layer and a metallic filler material on the metallic seed layer. The metallic seed layer may include, for example, a titanium barrier layer and a copper seed layer. The titanium barrier layer may have a thickness ranging from 50 nm to 500 nm, and the copper seed layer may have a thickness ranging from 50 nm to 500 nm. The metallic filler material used for the redistribution layer 12a may include copper, nickel, or a combination of copper and nickel. Other suitable metallic filler materials are within the scope of this disclosure. The thickness of the metallic filler material deposited for each redistribution layer 12a may range from 2 micrometers to 40 micrometers, for example from 4 micrometers to 10 micrometers, although smaller or larger thicknesses may also be used.

[0173] In at least one embodiment, the redistribution layer 12a may include traces (lines) and vias connecting the traces to each other. The traces may be located on the dielectric material layer 12 and may extend along the x-direction (first horizontal direction) and the y-direction (second horizontal direction) on the upper surface of the dielectric material layer 12.

[0174] Intermediate layer 10 may also include inter-bonding layer 13 on the wafer side surface of intermediate layer 10. Inter-bonding layer 13 may include a dielectric material suitable for forming a bond. In particular, inter-bonding layer 13 may include silicon oxide, silicon nitride, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination of the above, or other suitable materials.

[0175] Interchange layer 10 may also include a low passivation layer 14 on the plate-side surface of interchange layer 10. Low passivation layer 14 may be formed of the same material as the interchange bonding layer 13. Low passivation layer 14 may include silicon oxide, silicon nitride, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination of the above, or other suitable materials.

[0176] Intermediate layer 10 may also include intermediate low-bond pads 14a in the lowest dielectric material layer 12. Intermediate low-bond pads 14a may bond to and electrically connect to redistribution layer 12a. Intermediate low-bond pads 14a may be selectively formed in low-passivation layer 14. In this embodiment, low-passivation layer 14 may at least partially cover intermediate low-bond pads 14a. That is, intermediate low-bond pads 14a may at least partially be exposed on the board-side surface of intermediate layer 10. Intermediate low-bond pads 14a may also include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, Ti, TiN, Ta, TaN, WN, etc.). Other suitable metallic materials are within the scope of this disclosure.

[0177] Intermediate module 120 may also include C4 bumps 121 on the board-side surface of intermediate layer 10. C4 bumps 121 allow intermediate module 120 to be bonded and electrically coupled, for example, to a package substrate (not shown). C4 bumps 121 may be formed on intermediate low-bond pads 14a on the board-side surface of intermediate layer 10. C4 bumps 121 may include an underbump metallurgy (UBM) layer (not shown) on the intermediate low-bond pads 14a. C4 bumps 121 may further include bonding pads and solder bumps, with bonding pads (e.g., copper / nickel bonding pads) (not shown) above the UBM layer and solder bumps (e.g., SnAg solder bumps) above the bonding pads.

[0178] Semiconductor dies 140 may be attached to the wafer side of the interposer 10. Semiconductor dies 140 may include one or more first semiconductor dies 141 and one or more second semiconductor dies 142. Although the interposer module 120 is shown as including a specific number of semiconductor dies 140 of a specific size and a specific arrangement, the number, size, and arrangement of the semiconductor dies 140 are not limited to any particular number, size, or arrangement. Specifically, the interposer module 120 may include any number, size, and arrangement of semiconductor dies 140.

[0179] Generally, the thickness of each semiconductor die 140 in the z-direction can be substantially the same. Therefore, the upper surfaces of each first semiconductor die 141 and second semiconductor die 142 can be substantially coplanar (e.g., formed in the same xy plane), and are collectively referred to as semiconductor die upper surface 140a.

[0180] Each semiconductor die 140 may include, for example, a single semiconductor die structure, a system on-chip die, or a system on integrated chips die, and may be implemented using wafer-on-a-chip technology or integrated fan-shaped packaging technology on a substrate. Specifically, each semiconductor die 140 may include, for example, semiconductor wafers or chiplets, logic dies (e.g., mobile application processors, microcontrollers, etc.) or memory dies (e.g., high-bandwidth memory (HBM) dies, hybrid memory cubes (HMC), dynamic random access memory (DRAM) dies, widened I / O dies, magnetic random access memory (M-RAM) dies, non-volatile memory (R-RAM) dies, flash memory (NAND) dies, static random access memory (SRAM), etc., for high-performance computing (HPC) applications, artificial intelligence (AI) applications, and 5G cellular network applications; central processing unit (CPU) dies; graphics processing unit (GPU) dies; field-programmable gate arrays; etc. Array (FPGA) chips, network chips, application-specific integrated circuit (ASIC) chips, artificial intelligence / deep neural network (DNN) accelerator chips, coprocessors, accelerators, on-chip memory buffers, high data rate transceiver chips, input / output interface chips, integrated passive device (IPD) chips, and power management chips (e.g., power management integrated circuits).PMIC (Power Microsystem Interface) chips, radio frequency (RF) chips, sensor chips, micro-electro-mechanical system (MEMS) chips, signal processing chips (e.g., digital signal processing (DSP) chips), front-end chips (e.g., analog front-end (AFE) chips), monolithic 3D heterogeneous chiplet stacking dies, etc. Other chips are within the scope of this disclosure. In at least one embodiment, the first semiconductor chip 141 may include a primary chip (e.g., a SOC chip), and the second semiconductor chip 142 may include ancillary chips (e.g., memory / SOC chips, HBM chips, etc.).

[0181] Each semiconductor die 140 may include a dielectric layer 145 on the side of the semiconductor die 140 facing the interposer 10. The dielectric layer 145 may be composed of the same material as the dielectric material layer 12 in the interposer 10. In at least one embodiment, the dielectric layer 145 may include, for example, silicon oxide, silicon nitride, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination of the above, or other suitable materials. Other suitable materials may also be used.

[0182] Each semiconductor die 140 may also include a die bonding layer 146 on the dielectric layer 145. The die bonding layer 146 may be composed of the same material as the intermediate bonding layer 13. The die bonding layer 146 may include a dielectric material suitable for forming a bond. In particular, the die bonding layer 146 may include silicon oxide, silicon nitride, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination of the above, or other suitable materials.

[0183] Intermediate layer module 120 may also include an upper molding layer 127 formed around semiconductor die 140. The upper molding layer 127 may have outer sidewalls substantially aligned with the outer sidewalls of the intermediate layer 10. The upper molding layer 127 may also have an upper surface that is substantially uniform (e.g., flat) with and substantially coplanar with the upper surface 140a of semiconductor die 140.

[0184] An upper molding layer 127 may be formed on the outer sidewall of each semiconductor die 140. The upper molding layer 127 may be bonded to the outer sidewall of each semiconductor die 140. An upper molding layer 127 may also be formed in the die-to-die gap between semiconductor dies 140, and the upper molding layer 127 may also be bonded to the inner sidewall of the semiconductor die 140. The upper molding layer 127 may also be bonded to the wafer side surface of the interposer 10 (e.g., interposer bonding layer 13).

[0185] In at least one embodiment, the upper molding layer 127 may be formed of a curable material that can be cured to form a hard, solid structure. The upper molding layer 127 may include, for example, an epoxy molding compound (EMC). In at least one embodiment, the upper molding layer 127 may include a polymeric material, particularly an epoxy-based polymeric material. Other suitable molding materials may also be used.

[0186] In at least one embodiment, the upper molding layer 127 may have a coefficient of thermal expansion (CTE) substantially similar to that of the intermediate layer 10. In at least one embodiment, the upper molding layer 127 may include additive materials (e.g., fillers added to a polymeric material) for improving the properties of the upper molding layer 127 (e.g., thermal conductivity, CTE, etc.). Additive materials may include, for example, metal powders, metal oxide powders, etc. Other materials in the upper molding layer 127 are within the scope of this disclosure.

[0187] exist Figure 1A As further shown, the semiconductor die 140 may be mounted on the interposer 10 such that the die bonding layer 146 of the semiconductor die 140 contacts the interposer bonding layer 13 of the interposer 10. The semiconductor die 140 can bond the interposer 10 by bonding formed at the interface (bonding interface) between the die bonding layer 146 and the interposer bonding layer 13.

[0188] An interconnect 130 may be formed at the interface between the die bonding layer 146 and the intermediate bonding layer 13. The interconnect 130 may include a die bonding pad 131 (first bonding pad) in the die bonding layer 146 (first bonding layer). The interconnect 130 may also include an intermediate bonding pad 132 (second bonding pad) in the intermediate bonding layer 13 (second bonding layer). The interconnect 130 may also include a first protective dummy 133 of the intermediate bonding pad 132 in the adjacent intermediate bonding layer 13.

[0189] like Figure 1AAs shown, the surface (first surface) of the die bonding pad 131 is accessible to the surface (second surface) of the intermediate bonding pad 132 at the bonding surface. Bonding may include bonding between the die bonding pad 131 and the intermediate bonding pad 132. The first protective dummy 133 may include a surface (third surface) that is substantially coplanar with the surface of the intermediate bonding pad 132. The first protective dummy 133 may be electrically insulating.

[0190] Interconnect 130 may also include a die-side via 134 in the dielectric layer 145 of the semiconductor die 140. The die-side via 134 may contact and electrically couple to the die bonding pad 131. Interconnect 130 may also include an interposer-side via 135 in the uppermost dielectric material layer 12 of the interposer 10. The interposer-side via 135 may contact and electrically couple to the interposer bonding pad 132.

[0191] Interconnect 130 may include a die-side interconnect portion 130D, which includes a die bonding pad 131 and a die-side via 134. Interconnect 130 may also include an interposer-side interconnect portion 130I, which includes an interposer bonding pad 132, a first protective dummy 133, and an interposer-side via 135.

[0192] The grain-side interconnect portion 130D (e.g., grain bonding pad 131 and grain-side via 134) may comprise one or more layers and may be formed of a metal, metal alloy, and / or other metal-containing compound (e.g., Cu, Al, Mo, Co, Ru, W, Ti, TiN, Ta, TaN, WN, etc.). In at least one embodiment, the grain-side interconnect portion 130D may comprise copper. Other suitable metallic materials are within the scope of this disclosure.

[0193] Intermediate-side interconnect portions 130I (e.g., intermediate bonding pads 132, first protective dummy 133, and intermediate-side vias 135) may be formed of the same material as the grain-side interconnect portions 130D. In at least one embodiment, the intermediate bonding pads 132 and the first protective dummy 133 may be formed of substantially the same material (e.g., copper). Intermediate-side interconnect portions 130I may include one or more layers and may be formed of metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, Ti, TiN, Ta, TaN, WN, etc.). In at least one embodiment, intermediate-side interconnect portions 130I may include copper. Other suitable metallic materials are within the scope of this disclosure.

[0194] See again Figure 1BFor ease of understanding, the semiconductor die 140 (including the die-side interconnect portion 130D) and the upper molding layer 127 have been omitted. Figure 1B The positions of the first semiconductor die 141 and the second semiconductor die 142 are shown by dashed lines. Figure 1B As shown, the surface spanning the intermediary bonding layer 13 can expose the surface of the intermediary bonding pad 132 (second surface) and the surface of the first protective dummy 133 (third surface).

[0195] like Figure 1B As further shown, the intermediate bonding pad 132 may have a substantially circular shape. The first protective dummy 133 may be formed around the intermediate bonding pad 132 and has a substantially annular shape (e.g., ring). The first protective dummy 133 and the intermediate bonding pad 132 may be substantially concentrically arranged. Other suitable shapes and arrangements of the intermediate bonding pad 132 and the first protective dummy 133 are within the scope of this disclosure.

[0196] Interconnects 130 may be arranged in the shape of one or more two-dimensional arrays. Specifically, interconnects 130 may be arranged in one or more columns extending along a first direction (e.g., the x-direction) and one or more rows extending along a second direction (e.g., the y-direction). Interconnects 130 may be substantially uniformly arranged over the regions of the first semiconductor die 141 and the second semiconductor die 142. The first protection dummy 133 may have substantially uniform spacing. In at least one embodiment, the first protection dummy 133 is spaced apart from adjacent first protection dummy 133 by a first distance D1 in the first direction (x-direction), the first distance D1 being greater than 0.1 μm (e.g., about 2 μm). The first protection dummy 133 may also be spaced apart from adjacent first protection dummy 133 by a second distance D2 in the second direction (y-direction), the second distance D2 being greater than 0.1 μm (e.g., about 2 μm). The first distance D1 and the second distance D2 may be substantially the same or different.

[0197] See again Figure 1C and Figure 1D A bonding interface 150 can be formed between the semiconductor die 140 (e.g., the second semiconductor die 142) and the interposer layer 10. Figure 1C The bonding interface 150 is shown in dashed lines. The bonding interface 150 may include a bonding (e.g., oxide-oxide bond) between the surface 13s of the intermediate bonding layer 13 and the surface 146s of the grain bonding layer 146. The bonding interface 150 also includes a bonding (e.g., metal-metal bond) between the first surface 131s of the grain bonding pad 131 and the second surface 132s of the intermediate bonding pad 132. Figure 1CAs shown, the second surface 132s of the intermediate bonding pad 132, the third surface 133s of the first protective dummy 133, and the surface 13s of the intermediate bonding layer 13 can all be substantially coplanar.

[0198] In at least one embodiment, the width W1 (e.g., diameter) of the grain bonding pad 131 may be greater than the width W2 (e.g., diameter) of the intermediate bonding pad 132 (e.g., see...). Figure 1D The first protective dummy 133 may have a width W3, which is smaller than the width W1 of the die bonding pad 131 and the width W2 of the intermediate bonding pad 132. The width W3 of the first protective dummy 133 may be greater than 0.01 μm (e.g., about 0.3 μm). The first separation distance D3 between the first protective dummy 133 and the intermediate bonding pad 132 may also be greater than 0.1 μm (e.g., about 0.5 μm).

[0199] Die bonding pad 131 may have a thickness T1, which is substantially the same as the thickness of die bonding layer 146. Intermediate bonding pad 132 may have a thickness T2 that is substantially the same as the thickness T1 of die bonding pad 131. The thickness T2 of intermediate bonding pad 132 may be substantially the same as or different from the thickness T3 of first protective dummy 133. In at least one embodiment, the thickness T3 of first protective dummy 133 may be greater than the width W3 of first protective dummy 133. In at least one embodiment, first protective dummy 133 may extend completely through intermediate bonding layer 13 or not completely through intermediate bonding layer 13. The thickness T2 of intermediate bonding pad 132 may be greater than 0.1 μm (e.g., about 1.5 μm or 2 μm). The thickness T3 of first protective dummy 133 may be greater than 0.1 μm (e.g., about 1.5 μm or 2 μm). In at least one embodiment, the thickness T2 of the intermediate bonding pad 132 and the thickness T3 of the first protective dummy 133 may both be substantially the same as the thickness of the intermediate bonding layer 13.

[0200] In at least one embodiment, the first separation distance D3 between the intermediate bonding pad 132 and the first protective dummy 133 may be greater than the width W3 of the first protective dummy 133. In at least one embodiment, the first separation distance D3 between the intermediate bonding pad 132 and the first protective dummy 133 may be at least 30% larger than the width W3 of the first protective dummy 133. In at least one embodiment, the width W3 and the first separation distance D3 of each first protective dummy 133 surrounding the entire outer periphery of the second bonding pad 132 are substantially uniform.

[0201] In at least one embodiment, the width W2 of the intermediate bonding pad 132 may be greater than the width W3 of the first protective dummy 133. In at least one embodiment, the width W2 of the intermediate bonding pad 132 may be at least twice the width W3 of the first protective dummy 133. In at least one embodiment, each distance D1 and distance D2 may be greater than the first separation distance D3, wherein distance D1 is between adjacent first protective dummy 133 in a first direction, distance D2 is between adjacent first protective dummy 133 in a second direction, and the first separation distance D3 is between the intermediate bonding pad 132 and the first protective dummy 133. In at least one embodiment, each distance D1 and distance D2 may be at least twice the first separation distance D3, wherein distance D1 is between adjacent first protective dummy 133 in a first direction, distance D2 is between adjacent first protective dummy 133 in a second direction, and the first separation distance D3 is between the intermediate bonding pad 132 and the first protective dummy 133.

[0202] Figures 2A to 2F Various intermediate structures in a method of forming an intermediary layer module 120 are illustrated according to one or more embodiments. Figure 2A This is a vertical cross-sectional view of an intermediate structure including an interposer 10 (e.g., an organic interposer) formed on a first carrier substrate 1 (e.g., a carrier wafer) according to an embodiment of this disclosure. The first carrier substrate 1 may include a circular wafer or a rectangular wafer. The lateral dimensions of the first carrier substrate 1 (e.g., the diameter of a circular wafer or one side of a rectangular wafer) may range from 100 mm to 500 mm, for example from 200 mm to 400 mm, although smaller and larger lateral dimensions may also be used. The first carrier substrate 1 may include a semiconductor substrate, an insulating substrate, or a conductive substrate. The first carrier substrate 1 may be transparent or opaque. The thickness of the first carrier substrate 1 may be sufficient to provide mechanical support for the array of interposers 10 formed thereon. For example, the thickness of the first carrier substrate 1 may range from 60 μm to 1 mm, although smaller and larger thicknesses may also be used.

[0203] An adhesive layer (not shown) may be applied to the top surface of the first carrier substrate 1. In one embodiment, the first carrier substrate 1 may include an optically transparent material, such as glass or sapphire. In this embodiment, the adhesive layer may include a light-to-heat conversion (LTHC) layer. The LTHC layer is a solvent-based coating applied using a spin coating method. The LTHC layer may form a layer that converts ultraviolet light into heat, causing the LTHC layer to lose its adhesiveness. Alternatively, the adhesive layer may include a thermally decomposing adhesive material. For example, the adhesive layer may include an acrylic pressure-sensitive adhesive that decomposes upon heating. The debonding temperature of the thermally decomposing adhesive material can be in the range of 150°C to 400°C. Other suitable thermally decomposing adhesive materials that decompose at other temperatures are within the scope of this disclosure.

[0204] Intermediate low-bond pads 14a may be formed on the adhesive layer. Intermediate low-bond pads 14a may comprise any metallization material used to bond the soldering material. Intermediate low-bond pads 14a may be formed by depositing (e.g., chemical vapor deposition, physical vapor deposition, or other suitable deposition techniques) one or more metal layers comprising metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, Ti, TiN, Ta, TaN, WN, etc.). The metal layer is then patterned using a photolithography process to form the intermediate low-bond pads 14a. The photolithography process may include forming a patterned photoresist mask (not shown) on the metallization material and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the metallization material through openings in the photoresist mask. The photoresist mask is then removed by ashing, dissolving, or consuming it during the etching process.

[0205] In at least one embodiment, the intermediate low-bond pad 14a may comprise a UBM layer stack deposited over the adhesive layer. The order of the material layers in the UBM layer stack may be selected such that solder material portions may subsequently bond to portions of the bottom surface of the UBM layer stack. Layer stacks that can be used for the UBM layer stack include, but are not limited to, stacks of Cr / Cr-Cu / Cu / Au, Cr / Cr-Cu / Cu, TiW / Cr / Cu, Ti / Ni / Au, and Cr / Cu / Au. Other suitable materials are within the scope of this disclosure. The thickness of the UBM layer stack may range from 5 micrometers to 60 micrometers, for example from 10 micrometers to 30 micrometers, although smaller or larger thicknesses may also be used. A photoresist layer may be applied over the UBM layer stack and may be photolithographically patterned to form an array of discretely patterned photoresist material portions. An etching process may be performed to remove unmasked portions of the UBM layer stack. The etching process may be an isotropic etching process or an anisotropic etching process. The retained portions of the UBM layer stack may form the intermediate low-bond pad 14a. In at least one embodiment, the intermediate low-bond pads 14a may be arranged in a two-dimensional array, which may be a two-dimensional periodic array, such as a rectangular periodic array. In at least one embodiment, the intermediate low-bond pads 14a may be formed as a controlled collapse chip connection (C4) bump structure.

[0206] Dielectric material layer 12 and redistribution layer 12a (e.g., metal traces and metal vias) are alternately formed on intermediate low-bond pad 14a. It should be understood that, although... Figure 2A Three dielectric material layers 12 and two redistribution layers 12a are shown. More or fewer dielectric material layers 12 and redistribution layers 12a are within the scope of this disclosure.

[0207] Each dielectric material layer 12 can be formed independently, for example by deposition (e.g., CVD, PVD, or other suitable deposition techniques) of a dielectric polymer such as polyimide (PI), phenylcyclobutene (BCB), or polybenzoxazole (PBO). Other suitable materials are within the scope of this disclosure. The thickness of the dielectric polymer layer can range from 4 micrometers to 60 micrometers, although smaller and larger thicknesses are also possible.

[0208] Next, the dielectric material layer 12 is patterned using a photolithography process to form via holes in the dielectric material layer 12. The photolithography process may include forming a patterned photoresist mask (not shown) on the dielectric material layer and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the dielectric material layer 12 through openings in the photoresist mask. The photoresist mask is removed by ashing, dissolving, or consuming the photoresist mask during the etching process.

[0209] Next, a redistribution layer 12a (e.g., metal traces and metal vias) is formed on the dielectric material layer 12. The redistribution layer 12a is formed on the dielectric material layer 12 and in the vias formed in the patterned dielectric material layer 12 by deposition (e.g., CVD, PVD, or other suitable deposition techniques) of one or more metal material layers including copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals. The redistribution layer 12a is then patterned using a photolithography process. The photolithography process may include forming a patterned photoresist mask (not shown) on the metal material layer and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the metal material through openings in the photoresist mask. The photoresist mask is then removed by ashing, dissolving, or consuming it during the etching process.

[0210] like Figure 2A As further shown, an interposer via 135 may be formed in the uppermost dielectric material layer 12. The interposer via 135 is formed using a process similar to that used to form the redistribution layer 12a. The uppermost dielectric material layer 12 is patterned using a photolithography process to form vias in the uppermost dielectric material layer 12. The photolithography process may include forming a patterned photoresist mask (not shown) on the uppermost dielectric material layer 12 and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the uppermost dielectric material layer 12 through openings in the photoresist mask. The photoresist mask is subsequently removed by ashing, dissolving, or consuming the photoresist mask during the etching process.

[0211] Next, one or more layers of a metallic material, including copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals, are deposited (e.g., CVD, PVD, or other suitable deposition techniques) on the uppermost dielectric material layer 12 and in the vias formed by patterning the uppermost dielectric material layer 12 to form an interposer 135. Then, one or more layers of the metallic material are removed (e.g., by CMP) to expose the upper surface of the interposer 135 and the upper surface of the uppermost dielectric material layer 12.

[0212] Next, an interposer bonding layer 13 is formed on the uppermost dielectric material layer 12 and the interposer side via 135. For example, the interposer bonding layer 13 is formed by deposition (e.g., CVD, PVD or other suitable deposition techniques) of a dielectric material layer including silicon oxide, silicon nitride, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination of the above or other suitable materials.

[0213] Figure 2B This is a vertical cross-sectional view of the intermediate structure including the intermediate bonding layer 13 after patterning, according to one or more embodiments. Figure 2BAs shown, the patterned intermediate bonding layer 13 forms an opening O132 for the intermediate bonding pad 132 and an opening O133 for the first protective dummy 133.

[0214] The interposer layer 13 is patterned using a photolithography process to form openings O132 and O133 within it. The photolithography process may include forming a patterned photoresist mask (not shown) on the interposer layer 13 and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the interposer layer 13 through the openings in the photoresist mask. The photoresist mask is subsequently removed by ashing, dissolving, or consuming it during the etching process.

[0215] Figure 2C This is a vertical cross-sectional view of an intermediate structure including metal layers 132L / 133L according to one or more embodiments. After forming openings O132 and O133 in the intermediate bonding layer 13, metal layers 132L / 133L may be deposited on the intermediate bonding layer 13. Metal layers 132L / 133L may substantially fill openings O132 and O133. Metal layers 132L / 133L may include metallic material for forming the intermediate bonding pad 132 and the first protective dummy 133. For example, metal layers 132L / 133L may be formed on the intermediate bonding layer 13 and in openings O132 and O133 by depositing (e.g., CVD, PVD, or other suitable deposition techniques) one or more layers of metal, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, Ti, TiN, Ta, TaN, WN, etc.).

[0216] It should be understood that this is only achieved when the intermediate bonding pad 132 and the first protective dummy 133 are formed of the same material. Figure 2B and Figure 2C The intermediate structure in the middle. The intermediate bonding pad 132 and the first protective dummy 133 can be selectively formed of different materials. In this embodiment, for example, an opening O132 can be formed, and a metal layer for forming the intermediate bonding pad 132 can be deposited and ground. Then, an opening O133 can be formed, and a metal layer for forming the first protective dummy 133 can be deposited and ground.

[0217] Figure 2D This is a schematic diagram of a CMP apparatus 200 performing a CMP process on an intermediate structure according to one or more embodiments. A deposition, such as..., is performed on the intermediate bonding layer 13. Figure 2C After the metal layer 132L / 133L shown, it is used in Figure 2D The CMP equipment 200 performs CMP process on wafer W120 (the intermediate structure carrying interposer module 120).

[0218] CMP apparatus 200 may include a rotary platform 201 having a polishing pad 202 on an upper surface of the rotary platform 201. CMP apparatus 200 may also include a wafer carrier 203 having a lower surface facing the polishing pad 202. A wafer W120 may be attached to the lower surface of the wafer carrier 203 such that a metal layer 132L / 133L on an interposer 13 faces the polishing pad 202. CMP apparatus 200 may also include a slurry dispenser 204 having an opening O204 for dispensing a polishing slurry 205 (e.g., liquid polishing slurry). The polishing slurry 205 may include one or more galvanic abrasives (e.g., SiO2, Al). x O y Materials such as Ca.

[0219] In the CMP process, the rotating platform 201 can rotate along a first direction, and the wafer carrier 203 can rotate along a second direction, which is opposite to the first direction. When the wafer carrier 203 and the rotating platform 201 are rotating and the polishing slurry 205 is being distributed on the polishing pad 202, the wafer carrier 203 can press the wafer W120 downward toward the polishing pad 202.

[0220] The CMP process can remove metal layers 132L / 133L from the surface 13s of the interposer layer 13. The CMP process can also grind and planarize the surfaces 13s of the interposer layer 13, the surface 132s of the interposer pad 132, and the surface 133s of the first protective dummy 133. The CMP process can be performed until the metal layers 132L / 133L are removed from the surface 13s of the interposer layer 13, such that the metal layers 132L / 133L remain only in the openings O132 and O133.

[0221] Figure 2D Also included are top and vertical cross-sectional views of the intermediate bonding layer 13, including the intermediate bonding pad 132 and the first protective dummy 133, after the CMP process. The first protective dummy 133 protects the intermediate bonding pad 132 from damage caused by the galvanic effect during CMP. Specifically... Figure 2D The top view and vertical cross-sectional view of the intermediate bonding layer 13 shown indicate that the area of ​​galvanic loss D133 may exist on the surface 133s of the first protective dummy 133. However, the area without galvanic loss may exist on the surface 132s of the intermediate bonding pad 132.

[0222] It should be understood that the first protection dummy 133 protects the intermediate bonding pad 132 from galvanic loss in processes other than CMP processes. For example, the first protection dummy 133 protects the intermediate bonding pad 132 in electrostatic effect-inducing processes such as wet clean spin coating, lithographic photoresist coating, and developing spin coating.

[0223] Figure 2E This is a vertical cross-sectional view of an intermediate structure including an intermediate bonding layer 13 having a polished surface 13s, according to one or more embodiments. Figure 2E As shown, after the CMP process, the polished surfaces 13s of the intermediate bonding layer 13, 132s of the intermediate bonding pad 132, and 133s of the first protective dummy 133 can be substantially coplanar. For simplicity, Figure 2E The region of galvanic loss D133 that may exist on the surface 133s of the first protective dummy 133 is omitted.

[0224] Figure 2F This is a vertical cross-sectional view of an intermediate structure including a first semiconductor die 141 and a second semiconductor die 142 according to one or more embodiments. For example, the first semiconductor die 141 and the second semiconductor die 142 are placed above the interposer 10 using an electromechanical pick-and-place (PNP) machine. The PNP machine can lower the first semiconductor die 141 and the second semiconductor die 142 onto the interposer 10 such that the die bonding layer 146 can contact the interposer bonding layer 13, and the die bonding pad 131 can contact the interposer bonding pad 132. At this time, the die-side interconnect portion 130D can be merged with the interposer-side interconnect portion 130I to complete the assembly of the interconnect 130.

[0225] Next, the first semiconductor die 141 and the second semiconductor die 142 are bonded to the interposer layer 10 by performing a bonding process (e.g., direct bonding). For example, the bonding process may form a metal-to-metal bond between the die bonding pad 131 and the interposer bonding pad 132. For example, the bonding process may also form a dielectric-to-dielectric bond (e.g., oxide-to-oxide bond) between the die bonding layer 146 and the interposer bonding layer 13. It should be understood that the bonding process may utilize fewer than all of the die bonding pads 131, fewer than all of the interposer bonding pads 132, fewer than all of the interposer bonding layer 13, and fewer than all of the die bonding layer 146.

[0226] For example, the bonding process may optionally include a surface preparation step, in which the surfaces of the semiconductor die 140 and the interposer 13 are prepared by cleaning and removing any contaminants or oxides that may interfere with bonding. The surface preparation step can help achieve optimal bonding quality. An alignment step may be performed, in which the semiconductor die 140 and the interposer 10 are more precisely aligned to help confirm the accurate positioning of the interconnects. For example, the alignment step may be performed using alignment marks or an optical alignment system. Once aligned, the semiconductor die 140 and the interposer 10 can be in closer contact. The bonding process can be performed at room temperature (room-temperature bonding) or at elevated temperatures (thermal bonding), depending on the specific bonding technology used.

[0227] In the bonding process, grain bonding pad 131 and intermediate bonding pad 132 can be activated to form chemical bonds at the atomic level (e.g., oxide-to-oxide bonding). In at least one embodiment, the oxide layers in the grain bonding layer 146 and intermediate bonding layer 13 can be contacted, allowing oxygen atoms to migrate between the grain bonding layer 146 and intermediate bonding layer 13 and form covalent bonds. In at least one embodiment, elevated temperature and pressure can be applied to form dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding). Simultaneously with the formation of dielectric-to-dielectric bonding, metal-to-metal bonding is formed between the metal layers of the grain bonding pad 131 and intermediate bonding pad 132. In at least one embodiment, the application of elevated temperature and pressure can form metal-to-metal bonding through diffusion or solid-state reaction.

[0228] Figure 2G This is a vertical cross-sectional view of an intermediate structure including a molding material layer 127 according to one or more embodiments. Liquid molding material (e.g., epoxy molding material) is dispensed using a suitable dispensing tool onto the surface. Figure 2F A molding material layer 127 is formed on the intermediate structure. The molding material layer 127 is distributed on the intermediate structure to have a height greater than the height of the upper surface 140a of the semiconductor die 140.

[0229] In at least one embodiment, the dispensing of the molding material can be automated. Specifically, various aspects of the dispensing process can be controlled by a computer via a control system (e.g., an electronic control system, a central processing unit (CPU)). In at least one embodiment, the control system can control the start of the dispensing of the molding material, the flow rate of the dispensing of the molding material, and the stop of the dispensing of the molding material. For example, the control system can be programmed to dispense a predetermined amount of molding material based on various input parameters. Input parameters may include, for example, the spatial volume surrounding the interposer 10, the size of the interposer 10, the size of the first semiconductor die 141, the size of the second semiconductor die 142, etc.

[0230] In at least one embodiment, the molding material of the molding material layer 127 may include a capillary material (e.g., a capillary underfill type material). The molding material may have a low viscosity. Specifically, the viscosity may be less than about 5000 cP at 10 rpm. In at least one embodiment, the molding material may include a low-viscosity suspension of a thermally conductive material (e.g., a metal, a metal oxide) in the prepolymer. Low viscosity may help facilitate the transport of the molding material around the first semiconductor grain 141, the second semiconductor grain 142, and the third semiconductor grain (not shown). Low viscosity may also help avoid the formation of voids in the molding material layer 127. In at least one embodiment, the molding material layer 127 may be substantially free of voids.

[0231] After the molding material layer 127 has been sufficiently cured, it can be planarized so that the upper surface of the molding material layer 127 is substantially coplanar with the upper surfaces of the first semiconductor die 141 and the second semiconductor die 142. The molding material layer 127 is planarized by, for example, grinding, chemical mechanical polishing (CMP) or other suitable planarization techniques.

[0232] Figure 2H This is a vertical cross-sectional view of an intermediate structure including C4 bump 121 according to one or more embodiments. After the molding material layer 127 has been cured and planarized (e.g., by grinding, CMP, etc.), the second carrier substrate 2 may be attached to the upper surface of the molding material layer 127 and the upper surface 140a of the semiconductor die 140. The intermediate structure can then be reversed and placed on the working surface.

[0233] Next, the first carrier substrate 1 can be detached from the interposer 10 to expose the interposer low bonding pad 14a on the board-side surface of the interposer 10. For example, the first carrier substrate 1 can be detached from the interposer 10 by deactivating the adhesive layer (not shown) that the first carrier substrate 1 was bonded to the interposer 10. The adhesive layer can be deactivated, for example, by thermal annealing at elevated temperatures (e.g., by an adhesive material for thermal deactivation) or by exposing the adhesive layer to ultraviolet light (e.g., by an adhesive material for ultraviolet-deactivated light).

[0234] Next, a low passivation layer 14 may be formed on the plate-side surface of the interposer 10. For example, the low passivation layer 14 may be formed by depositing a dielectric material layer (e.g., by CVD, PVD or other suitable deposition techniques) on the plate-side surface of the interposer 10.

[0235] Next, an opening O14 is formed in the low passivation layer 14 to expose the surface of the intermediate low bonding pad 14a. The opening O14 is formed by a photolithography process including forming a patterned photoresist mask (not shown) on the low passivation layer 14, and the exposed upper surface of the low passivation layer 14 is etched (e.g., wet etching, dry etching, etc.) through the opening in the photoresist mask. The photoresist mask is subsequently removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during the etching process.

[0236] Next, a C4 bump 121 may be formed on the intermediate structure. The C4 bump 121 may include, for example, a solder ball formed on the intermediate low-bond pad 14a by an electroplating process. The C4 bump 121 may contact the intermediate low-bond pad 14a through an opening O14 in the low-passivation layer 14. In at least one embodiment, one or more under-bump metallization (UBM) layers (not shown) are formed on the intermediate low-bond pad 14a. Then, the C4 bump 121 is formed to contact the intermediate low-bond pad 14a through the UBM layer.

[0237] In wafer-level processes, it is possible to simultaneously process wafer W120 (refer to...) Figure 2D An interposer module 120 is formed on the wafer W120. After the C4 bump 121 is formed, a sizing process can be performed to sizing the interposer module 120 on the wafer W120. For example, the sizing process can be performed by using a dicing machine to cut the interposer 10 (and the molding material layer 127 formed thereon) along dicing lines.

[0238] Figure 3This is a flowchart illustrating a method of forming an interposer module 120 (e.g., a semiconductor device) according to one or more embodiments. Step 310 includes providing a second structure including a second bonding layer. Step 320 includes forming a second bonding pad opening and a first protective dummy opening, the first protective dummy opening being adjacent to the second bonding pad opening in the second bonding layer. Step 330 includes forming a metal layer on the second bonding layer and in the second bonding pad opening and the first protective dummy opening. Step 340 includes performing chemical mechanical polishing (CMP) to form a second bonding pad and a first protective dummy, the second bonding pad being in the second bonding pad opening and the first protective dummy being in the first protective dummy opening, such that a third surface of the first protective dummy and a second surface of the second bonding pad are substantially coplanar. Step 350 includes bonding the first structure to the second structure such that the second bonding layer bonds to the first bonding layer of the first structure, and the second surface of the second bonding pad bonds to the first surface of the first bonding pad in the first bonding layer.

[0239] Figure 4A and Figure 4B A first alternative design for interconnect 130 is shown according to one or more embodiments. In particular, Figure 4A This is a top view of interconnect 130 with a first alternative design according to one or more embodiments. For ease of understanding, Figure 4A The grain bonding pad 131 and the grain side perforation 134 are omitted. Figure 4B It is a vertical cross-sectional view of interconnect 130 having a first alternative design according to one or more embodiments. Figure 4B It is along Figure 4A A vertical cross-sectional view of the interconnect 130 with the first alternative design in cross section B-B'.

[0240] like Figure 4A As shown, the interconnect 130 with the first alternative design may include a first interconnect 130-1, a second interconnect 130-2, a third interconnect 130-3, and a fourth interconnect 130-4. The interconnect 130 with the first alternative design and... Figures 1A to 1D The interconnects 130 in the present invention are substantially the same. However, interconnects 130 with a first alternative design may include a first protection dummy 133. The first protection dummy 133 may include a first protection dummy 133-1 and a first protection dummy 133-2. The first protection dummy 133 may have a substantially rectangular shape. Other shapes are within the scope of this disclosure.

[0241] The first protective dummy 133-1 and the first protective dummy 133-2 may be formed of the same material as the intermediate bonding pad 132. The first protective dummy 133-1 may have substantially the same size and substantially the same shape as the first protective dummy 133-2.

[0242] The first protective dummy 133-1 may have a first length L1 in the first direction (x-direction) and a second length L2 in the second direction (y-direction), wherein the second length L2 is less than the first length L1. The first protective dummy 133-2 may have a first length L1 in the second direction (y-direction) and a second length L2 in the first direction (x-direction), wherein the second length L2 is less than the first length L1. In at least one embodiment, the first length L1 may be at least twice the second length L2.

[0243] Interconnection 130 may also include interconnection 136, which includes first connector 136-1 and first connector 136-2. First connector 136-1 connects the first protective dummy 133-1 to a first side of the intermediate bonding pad 132, and first connector 136-2 connects the first protective dummy 133-2 to a second side of the intermediate bonding pad 132. Connector 136 may be formed of the same material as the first protective dummy 133-1 and the first protective dummy 133-2. The first side of the intermediate bonding pad 132 may be separated from the second side of the intermediate bonding pad 132 by approximately 90°. Therefore, the lines of first connector 136-1 and first connector 136-2 may intersect at the center C of the intermediate bonding pad 132, forming a substantially 90° angle. Other suitable angles of separation are within the scope of this disclosure.

[0244] like Figure 4A As shown, interconnects 130 can be arranged in an array, the array comprising columns in a first direction and rows in a second direction. Interconnects 130 arranged in columns of interconnects 130 such that first protection dummy 133-1 is substantially aligned in the first direction, and first protection dummy 133-2 is located on opposite sides of individual intermediate bonding pads 132. Interconnects 130 arranged in rows of interconnects 130 such that first protection dummy 133-2 is substantially aligned in the second direction, and first protection dummy 133-1 is located on opposite sides of individual intermediate bonding pads 132.

[0245] like Figure 4B As shown, the first connector 136 (e.g., 136-2) may have a thickness T3, which is substantially equal to the thickness of the first protective dummy 133 (e.g., 133-2). The first connector 136 may also have a length (e.g., in a first or second direction), which is substantially the same as the first separation distance D3 (e.g., greater than 0.1 μm (e.g., about 0.5 μm)).

[0246] like Figure 4B As further shown, the first protection dummy 133 can be used as and Figures 1A to 1DThe first protective dummy 133 has the same function as the first protective dummy 133. That is, the first protective dummy 133 can protect the intermediate bonding pad 132 from damage caused by galvanic during CMP. In particular, areas of galvanic loss D133 may exist on the surface 133s of the first protective dummy 133. However, areas without galvanic loss may exist on the surface 132s of the intermediate bonding pad 132.

[0247] Figures 5A to 5D Additional alternative designs for the interconnect 130 according to one or more embodiments are shown. For ease of understanding, Figures 5A to 5D The grain bonding pad 131 and the grain side perforation 134 are omitted. Specifically, Figure 5A This is a top view of interconnect 130 with a second alternative design according to one or more embodiments. Figure 5A As shown, the interconnect 130 with the second alternative design may include a first protection dummy 133 and a first connector 136, substantially the same as... Figure 4A and Figure 4B The first protective dummy 133 and the first connector 136 are the same. However, the first protective dummy 133 and the first connector 136 may be located on one side of the intermediate engagement pad 132 (e.g., only one side).

[0248] Figure 5B This is a top view of interconnect 130 with a third alternative design according to one or more embodiments. Figure 5B As shown, the interconnect 130 with the third alternative design may include a first protection dummy 133 and a first connector 136, substantially related to... Figure 4A and Figure 4B The first protective dummy 133 and the first connector 136 are identical. However, the first protective dummy 133 and the first connector 136 may be located on three sides of the intermediate engagement pad 132. The three sides may be separated by approximately 90°.

[0249] like Figure 5B As further shown, the first protective dummy 133 may have substantially the same shape (e.g., rectangular). However, the first protective dummy 133 may have different dimensions. In particular, the first protective dummy 133 may include different first lengths L1 and different second lengths L2.

[0250] Figure 5C This is a top view of interconnect 130 having a fourth alternative design according to one or more embodiments. Figure 5C As shown, the interconnect 130 with the fourth alternative design may include a first protection dummy 133 and a first connector 136, substantially related to... Figure 4A and Figure 4BThe first protective dummy 133 and the first connector 136 are identical. However, the first protective dummy 133 and the first connector 136 may be located on the four sides of the intermediate engagement pad 132. The four sides may be separated by approximately 90°. Furthermore, in a fourth alternative design, the first protective dummy 133 may have a substantially square shape.

[0251] Figure 5D This is a top view of interconnect 130 having a fifth alternative design according to one or more embodiments. Figure 5D As shown, the interconnect 130 with the fifth alternative design may include a first protection dummy 133 and a first connector 136, substantially related to... Figure 5C The first protective dummy 133 and the first connector 136 are identical. However, in the fifth alternative design, the first protective dummy 133 and the first connector 136 may have substantially different shapes, including, for example, rectangles, squares, ellipses, and truncated triangular shapes. Furthermore, the first connector 136 in the fifth alternative design may have different dimensions (e.g., lengths in the x and y directions). It should be understood that... Figures 5A to 5D One or more of the interconnects 136 can be omitted.

[0252] Figures 6A to 6C Various views of interconnect 130 having a sixth alternative design according to one or more embodiments. Figure 6A It is a vertical cross-sectional view of interconnect 130 with a sixth alternative design according to one or more embodiments. Figure 6B It is a bottom view of the mating interface 150 in the interconnect 130 having a sixth alternative design according to one or more embodiments. Figure 6C This is a top view of the mating interface 150 in the interconnect 130 having a sixth alternative design according to one or more embodiments.

[0253] like Figure 6A As shown, the interconnect 130 with the sixth alternative design can be connected to Figures 1A to 1D The interconnects 130 in the diagram are essentially the same. However, unlike... Figures 1A to 1D The interconnect 130 in the sixth alternative design may include a second protection dummy 233. The second protection dummy 233 may be formed in the die bonding layer 146 and around the die bonding pad 131.

[0254] In at least one embodiment, the second protective dummy 233 may have a shape (e.g., circular) substantially the same as the first protective dummy 133. The second protective dummy 233 may be formed of the same material as the die bonding pad 131. The second protective dummy 233 may have a thickness substantially the same as the thickness T1 of the die bonding pad 131. The second protective dummy 233 may have a width W4 (see figure). Figure 6B In essence, the width W3 of the first protection dummy 133 (see reference) Figure 6C The same. The second protective dummy 233 can be separated from the die bonding pad 131 by the second separation distance D4 (see reference). Figure 6B The second separation distance D4 is essentially the same as the first separation distance D3 (see reference). Figure 6C Similarly, the first separation distance D3 is between the first protective dummy 133 and the intermediate bonding pad 132. In at least one embodiment, the width W4 of the second protective dummy 233 may be greater than (e.g., at least 10%) the width W3 of the first protective dummy 133. In at least one embodiment, the second separation distance D4 may be greater than (e.g., at least 10%) the first separation distance D3.

[0255] The function of the second protection dummy 233 can be substantially similar to that of the first protection dummy 133. Specifically, during CMP processing of the surfaces 146s of the grain bonding layer 146, the surfaces 131s of the grain bonding pad 131, and the surfaces 233s (fourth surface) of the second protection dummy 233, the second protection dummy 233 can protect the grain bonding pad 131 from damage caused by the galvanic effect. The surfaces 233s and 131s of the grain bonding pad 131 can be substantially coplanar. In particular, areas of galvanic loss D233 can exist on the surface 233s of the second protection dummy 233. However, areas without galvanic loss can exist on the surface 131s of the grain bonding pad 131.

[0256] Figures 7A to 7C The interconnect 130 with a seventh alternative design is shown according to one or more embodiments. Figure 7A It is a vertical cross-sectional view of interconnect 130 having a seventh alternative design according to one or more embodiments. Figure 7B It is a bottom view of the mating interface 150 in the interconnect 130 having a seventh alternative design according to one or more embodiments. Figure 7C This is a top view of the mating interface 150 in the interconnect 130 having a seventh alternative design according to one or more embodiments. Figure 7A The view in is along Figure 7B The cross section B-B' and along Figure 7C A view of the cross section A-A' in the middle.

[0257] like Figure 7A As shown, the interconnect 130 with the seventh alternative design can be connected to Figure 4A and Figure 4BThe interconnect 130 with the first alternative design is substantially the same. That is, the interconnect 130 with the seventh alternative design includes a first protection dummy 133 and a first connector 136, the first connector 136 connecting the first protection dummy 133 to the intermediate bonding pad 132. However, in the seventh alternative design, the interconnect 130 may also include a second protection dummy 233 and a second connector 236, the second connector 236 connecting the second protection dummy 233 to the die bonding pad 131. The second protection dummy 233 may be substantially rectangular. Other shapes are within the scope of this disclosure.

[0258] The second protection virtuality 233 may include the second protection virtuality 233-1 and the second protection virtuality 233-2, the second protection virtuality 233-1 and... Figure 4A and Figure 4B The first protection dummy 133-1 is essentially similar to the second protection dummy 233-2. Figure 4A and Figure 4B The first protection dummy 133-2 is substantially similar. The second connector 236 may include a second connector 236-1 and a second connector 236-2, the second connector 236-1 and... Figure 4A and Figure 4B The first connector 136-1 is substantially similar to the second connector 236-2. Figure 4A and Figure 4B The first connector 136-2 is substantially similar. The second connector 236-1 can connect the second protection dummy 233-1 to the die bonding pad 131, and the second connector 236-2 can connect the second protection dummy 233-2 to the die bonding pad 131.

[0259] The functions of the second protection virtual device 233-1 and the second protection virtual device 233-2 are essentially the same as... Figures 6A to 6C The second protective dummy 233 functions similarly. Specifically, during CMP processing of the surfaces 146s of the grain bonding layer 146, 131s of the grain bonding pad 131, and 233s of the second protective dummy 233, the second protective dummy 233-1 and the second protective dummy 233-2 protect the grain bonding pad 131 from damage caused by the galvanic effect. In particular, areas of galvanic loss D233 may exist on the surfaces 233s of the second protective dummy 233-1 and / or the second protective dummy 233-2. However, areas without galvanic loss may exist on the surface 131s of the grain bonding pad 131.

[0260] Figure 8 This is a vertical cross-sectional view of a package structure 800 including an intermediary layer module 120 according to one or more embodiments. Figure 8As shown, the interposer module 120 can be mounted on the package substrate 110. The package substrate 110 may include a cored package substrate or a coreless package substrate. The package substrate 110 may include a ball-grid array (BGA), which includes solder balls 110c on the board-side surface of the package substrate 110.

[0261] Intermediate layer module 120 can be mounted on package substrate 110 via C4 bumps 121 on the side surface of intermediate layer 10. A package underfill layer 119 can be formed on and around the intermediate layer 10, below and surrounding it. The package underfill layer 119 can also be formed around the C4 bumps 121. The package underfill layer 119 thus securely holds the intermediate layer module 120 to the package substrate 110. The package underfill layer 119 can be formed of an epoxy-based polymeric material.

[0262] A thermal interface material (TIM) layer 170 may be formed on the upper surface 140a of the semiconductor die 140 and the upper surface of the molding material layer 127. The TIM layer 170 may include, for example, grease-type TIM, paste-type TIM, film-type TIM, gel-type TIM, graphite film TIM, liquid metal TIM (e.g., gallium-rich TIM), phase change material (PCM) TIM, etc. In at least one embodiment, the TIM layer 170 may include a low-melting-temperature metal TIM. PCM-type TIM may include, for example, polymer-based PCM TIM. PCM-type TIM can improve porosity and delamination issues, increase thermal contact resistance in the package structure 800, and improve thermal efficiency. In at least one embodiment, the PCM-type TIM can transform from a solid phase to a high-viscosity semi-liquid phase at approximately 60°C. In at least one embodiment, the TIM layer 170 may include gallium-based, indium-based, silver-based, solder-based, etc. Other types of TIMs in the TIM layer 170 are within the scope of this disclosure.

[0263] A TIM layer 170 may be formed on the interposer module 120 to dissipate heat generated during operation of the package structure 800 (e.g., operation of the semiconductor die 140). The TIM layer 170 may be attached to the interposer module 120, for example, using a thermally conductive adhesive. The TIM layer 170 may have low bulk thermal impedance and high thermal conductivity.

[0264] Package lid 1130 may be located on TIM layer 170 above interposer module 120 and connected to package substrate 110. Bond-line thickness (BLT) (e.g., the distance between package lid 130 and interposer module 120) may be less than about 100 μm, although larger or smaller distances may also be used. Package lid 1130 may include a plate portion 1130p formed on TIM layer 170 above interposer module 120. Package lid 1130 may also include a foot portion 1130a surrounding the outer periphery of plate portion 1130p. Foot portion 1130a may be secured to package substrate 110 by adhesive layer 160.

[0265] The encapsulation cover 1130 can be formed of, for example, a metal, ceramic, or polymer material. In at least one embodiment, the material of the encapsulation cover 1130 may include copper with a nickel-coated surface. The nickel-coated surface may have a thickness in the range of 1 μm to 10 μm. The encapsulation cover portion 1130p may have a plate-like shape (e.g., a planar shape) and be substantially parallel to the upper surface of the encapsulation substrate 110. For example, the encapsulation cover portion 1130p may be along... Figure 8 The xy plane extends in the package. The package cover portion 1130p may include an outer sidewall that is substantially aligned with the outer sidewall of the package cover foot portion 1130a. The upper surface of the package cover portion 1130p and the lower surface of the package cover portion 1130p may be substantially parallel.

[0266] An adhesive layer 160 may be formed on the package substrate 110 near the sidewall of the interposer module 120. The adhesive layer 160 bonds the package cover pin portion 1130a to the package substrate 110. The thickness of the adhesive layer 160 may range from 50 μm to 200 μm. The adhesive layer 160 may include, for example, a silicone adhesive (e.g., containing alumina, zinc oxide, resin, etc.) or an epoxy adhesive. Other suitable adhesives may be used. The adhesive layer 160 may contact the recessed upper surface of the back metal layer or the upper molding material layer.

[0267] Figure 9 This is a vertical cross-sectional view of a package module 900 including interconnects 130 according to one or more embodiments. Figure 9 As shown, the package module 900 may include a bottom semiconductor die 920 (e.g., a bottom die) and a top semiconductor die 940 (e.g., a top die), with the top semiconductor die 940 mounted on the bottom semiconductor die 920. The bottom semiconductor die 920 and the top semiconductor die 940 and... Figure 1A The semiconductor die 140 in the middle can be substantially the same.

[0268] The bottom semiconductor die 920 may include an active region 922 (e.g., including a transistor, diode, capacitor, etc.) and a silicon block region 924 on the active region 922. The top semiconductor die 940 may include an active region 942 and a silicon block region 944 on the active region 942. The molding material layer 927 is similar to... Figure 1A The molding material layer 127 can be formed on the bottom semiconductor die 920 and around the bottom semiconductor die 920 and on one side of the top semiconductor die 940. The package module 900 may also include C4 bumps 121 on the board side surface of the package module 900.

[0269] like Figure 9 As further shown, the bottom semiconductor die 920 may include and Figure 1A The intermediate bonding layer 13 is similar to the low bonding layer 93. The top semiconductor die 940 may include a dielectric layer 145 and a die bonding layer 146 on the dielectric layer 145. The top semiconductor die 940 can be bonded to the bottom semiconductor die 920 by bonding at a bonding interface 950, the bonding interface 950 being similar to... Figure 1C The bonding interface 950 is similar. Interconnect 130 can electrically couple the top semiconductor die 940 to the bottom semiconductor die 920 across the bonding interface 950.

[0270] Interconnect 130 may include a die bonding pad 131 and a die-side via 134, the die bonding pad 131 being in a die bonding layer 146 and the die-side via 134 being in a dielectric layer 145 of a top semiconductor die 940. Interconnect 130 may also include a low-side bonding pad 932 (and...) Figure 1A Similar to the intermediate bonding pad 132 in the middle) and the first protective dummy 133, the low bonding pad 932 is in the low bonding layer 93, and the first protective dummy 133 is in the low bonding layer 93 adjacent to the low bonding pad 932. Compared to Figure 1A In the package structure 900, the intermediate bonding pad 132 of the intermediate contact interposer side through-hole 135 can contact the through-via 190. The through-via 190 can connect to the active region 922 in the bottom semiconductor die 920.

[0271] Figure 10 This is a vertical cross-sectional view of a package structure 1000 including interconnects 130 according to one or more embodiments. Figure 10 As shown, the package structure 1000 may include a semiconductor die 1040 mounted on a package substrate 110. The package structure 1000 may also include a stiffener ring 1150, which is connected to the package substrate 110 surrounding the semiconductor die 1040 via an adhesive layer 160.

[0272] Semiconductor die 1040 and Figure 1A Any one of the semiconductor dies 1040 in the package can be substantially identical. The semiconductor dies 1040 can be bonded to the package substrate 110 via a bonding interface 1050, which is connected to... Figure 1C The bonding interface 150 is similar. The semiconductor die 1040 is electrically coupled to the package substrate 110 via interconnect 130.

[0273] The packaging substrate 110 may include a low bonding layer 1013, the low bonding layer 1013 and Figure 1A The intermediate bonding layer 13 is similar. The semiconductor die 1040 may include, for example, Figure 1A The interconnect 130 includes a dielectric layer 145 and a die bonding layer 146. The interconnect 130 may include a die bonding pad 131 and a die-side via 134, with the die bonding pad 131 in the die bonding layer 146 and the die-side via 134 in the dielectric layer 145 of the semiconductor die 1040. The interconnect 130 may also include a low-bond pad 1032 and a first protection dummy 133, with the low-bond pad 1032 in the low-bond layer 1013 (and...). Figure 1A Similar to the intermediate bonding pad 132 in the previous section), the first protective dummy 133 is in the low bonding layer 1013 of the adjacent low bonding pad 1032. The interconnect 130 may also include a substrate-side through-hole 1035 (similar to the previous section). Figure 1A(Similar to the intermediate side perforation 135 in the middle), the substrate side perforation 1035 connects the low bonding pad 1032 to the interconnect structure 112 in the package substrate 110.

[0274] For reference Figures 1A to 10 An interconnect structure 130 for semiconductor devices 120, 800, 900, and 1000. The interconnect structure 130 may include a first bonding pad 131, a second bonding pad 132, 932, and 1032, and a first protective dummy 133. The first bonding pad 131 has a first surface 131s, and the second bonding pads 132, 932, and 1032 have a second surface 132s. The second surface 132s engages with the first surface 131s of the first bonding pad 131. The first protective dummy 133 is adjacent to the second bonding pads 132, 932, and 1032 and has a third surface 133s. The third surface 133s is substantially coplanar with the second surface 132s of the second bonding pads 132, 932, and 1032.

[0275] In one embodiment, the first protective dummy 133 may include an electrically insulating metal protective dummy. In one embodiment, the first protective dummy 133 may be annular and surround the second bonding pads 132, 932, and 1032. In one embodiment, the second bonding pads 132, 932, and 1032 may be circular and the first protective dummy 133 may be formed concentrically with the second bonding pads 132, 932, and 1032. In one embodiment, the first protective dummy 133 may be separated from the second bonding pads 132, 932, and 1032 by a first separation distance D3, the first separation distance D3 being greater than the width W3 of the first protective dummy 133. In one embodiment, the first separation distance D3 may be at least 30% greater than the width W3 of the first protective dummy 133. In one embodiment, the width W3 of the first protective dummy 133 and the first separation distance D3 surrounding the entire outer periphery of the second bonding pads 132, 932, and 1032 are substantially uniform. In one embodiment, the first protective dummy 133 has a third thickness, the third thickness being greater than the width W3 of the first protective dummy 133. In one embodiment, the second bonding pads 132, 932, and 1032 have a second thickness substantially equal to the third thickness of the first protective dummy 133. In one embodiment, the second bonding pads 132, 932, 1032, and the first protective dummy 133 comprise the same metallic material. In one embodiment, the first bonding pad 131 has a first width W1, and the second bonding pads 132, 932, and 1032 have a second width W2, which is smaller than the first width W1. In one embodiment, the first protective dummy 133 may connect to the second bonding pads 132, 932, and 1032. In one embodiment, the interconnect structure 130 may further include a second protective dummy 233 adjacent to the first bonding pad 131 and having a fourth surface 233s substantially coplanar with the first surface 131s of the first bonding pad 131.

[0276] See again Figures 1A to 10Semiconductor devices 120, 800, 900, and 1000 may include first structures 140, 940, and 1040, second structures 10, 920, and 110, and interconnect 130. First structures 140, 940, and 1040 may include a first bonding layer 146. Second structures 10, 920, and 110 are bonded to first structures 140, 940, and 1040 and may include second bonding layers 13, 93, and 1013. Interconnect 130 electrically couples first structures 140, 940, and 1040 to second structures 10, 920, and 110. Interconnect 130 may include first bonding pads 131 and second bonding pads 132 and 932. 1032 and 1032 and a first protective dummy 133, a first bonding pad 131 in a first bonding layer 146 and having a first surface 131s, second bonding pads 132, 932, and 1032 in a second bonding layer 13, 93, and 1013 and having a second surface 132s, the second surface 132s engaging the first surface 131s of the first bonding pad 131, the first protective dummy 133 adjacent to the second bonding pads 132, 932, and 1032 in the second bonding layer 13, 93, and 1013 and having a third surface 133s, the third surface 133s being substantially coplanar with the second surface 132s of the second bonding pads 132, 932, and 1032.

[0277] In one embodiment, the first structures 140, 940, and 1040 may include semiconductor dies, and the second structures 10, 920, and 110 may include one of an interposer 10, a second semiconductor die 920, or a package substrate 110. In one embodiment, the interconnect 130 may include a plurality of interconnects 130, and the distances D1 and D2 between the interconnects 130 may be greater than a first separation distance D3, which lies between a first protective dummy 133 and second bonding pads 132, 932, and 1032 in the interconnect 130. In one embodiment, the first protective dummy 133 may connect to the second bonding pads 132, 932, and 1032. In one embodiment, the interconnect 130 may further include a second protective dummy 233, which is adjacent to the first bonding pad 131 and has a fourth surface 233s, which is substantially coplanar with the first surface 131s of the first bonding pad 131.

[0278] See again Figures 1A to 10A method for forming semiconductor devices 120, 800, 900, and 1000 may include providing second structures 10, 920, and 110, the second structures 10, 920, and 110 including second bonding layers 13, 93, and 1013; forming a second bonding pad opening O132 and a first protective dummy opening O133, the first protective dummy opening O133 being adjacent to the second bonding pad opening O132 in the second bonding layers 13, 93, and 1013; forming metal layers 132L / 133L on the second bonding layers 13, 93, and 1013 and within the second bonding pad opening O132 and the first protective dummy opening O133; and performing chemical mechanical polishing (CMP) to form the second bonding pads 132 and 93. 2. 1032 is in the second bonding pad opening O132 and the first protective dummy 133 is in the first protective dummy opening O133, such that the third surface 133s of the first protective dummy 133 is substantially coplanar with the second surfaces 132s of the second bonding pads 132, 932, and 1032, bonding the first structures 140, 940, and 1040 to the second structures 10, 920, and 110, such that the second bonding layers 13, 93, and 1013 can be bonded to the first bonding layer 146 of the first structures 140, 940, and 1040, and the second surfaces 132s of the second bonding pads 132, 932, and 1032 can be bonded to the first surface 131s of the first bonding pad 131 in the first bonding layer 146.

[0279] In one embodiment, the implementation of CMP may include protecting the second bonding pads 132, 932, 1032 from damage caused by the galvanic effect of the first protection dummy 133.

[0280] For reference Figures 1A to 10 An interconnect structure 130 for semiconductor devices 120, 800, 900, and 1000 is provided. The interconnect structure 130 may include a first bonding pad 131, second bonding pads 132, 932, and 1032, and a first protective dummy 133. The first bonding pad 131 has a first surface 131s, and the second bonding pads 132, 932, and 1032 have a second surface 132s. The second surface 132s engages with the first surface 131s of the first bonding pad 131. The first protective dummy 133 is adjacent to the second bonding pads 132, 932, and 1032 and has a third surface 133s. The third surface 133s is substantially coplanar with the second surface 132s of the second bonding pads 132, 932, and 1032. The second bonding pads 132, 932, and 1032 may be circular, and the first protective dummy 133 may be formed concentrically with the second bonding pads 132, 932, and 1032. The first protective dummy 133 can be separated from the second connecting pads 132, 932, and 1032 by a first separation distance D3, which is greater than the width W3 of the first protective dummy 133.

[0281] In one embodiment, the first protective dummy is separated from the second mating pad by a first separation distance, the first separation distance being greater than the width of the first protective dummy.

[0282] The features of many embodiments outlined above will enable those skilled in the art to better understand the viewpoint of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or adapting other processes and structures to achieve the same purpose and / or attain the same benefits as the embodiments described herein. Those skilled in the art will also understand that such equivalent architectures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An interconnect structure, characterized by, The interconnect structure includes: A first bonding pad having a first surface; A second bonding pad having a second surface that engages the first surface of the first bonding pad; and A first protective dummy is provided, which is adjacent to the second bonding pad and has a third surface that is substantially coplanar with the second surface of the second bonding pad.

2. The interconnect structure of claim 1, wherein, The first protective dummy includes a ring and surrounding the second bonding pad.

3. The interconnect structure of claim 1, wherein, The first bonding pad has a first width and the second bonding pad has a second width, the second width being smaller than the first width.

4. The interconnect structure of claim 1, wherein, The first protective device is dummy connected to the second bonding pad.

5. The interconnect structure of claim 1, wherein, Further includes: A second protective dummy is provided, which is adjacent to the first bonding pad and has a fourth surface that is substantially coplanar with the first surface of the first bonding pad.

6. A semiconductor device, characterized by comprising: include: A first structure, the first structure including a first bonding layer; A second structure, which joins the first structure and includes a second bonding layer; as well as An interconnect, electrically coupled from the first structure to the second structure, includes: A first bonding pad, the first bonding pad being in the first bonding layer and having a first surface; A second bonding pad, the second bonding pad being in the second bonding layer and having a second surface, the second surface engaging the first surface of the first bonding pad; and A first protective dummy is provided, which is adjacent to the second bonding pad in the second bonding layer and has a third surface that is substantially coplanar with the second surface of the second bonding pad.

7. The semiconductor device according to claim 6, wherein The first structure includes a semiconductor die, and the second structure includes one of an interposer, a second semiconductor die, or a packaging substrate.

8. The semiconductor device according to claim 6, wherein The interconnect includes multiple interconnects, and a distance between the multiple interconnects is greater than a first separation distance, which is between the first protective dummy and the second bonding pad in the multiple interconnects.

9. An interconnect structure, characterized by include: A first bonding pad having a first surface; A second bonding pad having a second surface that engages the first surface of the first bonding pad; as well as A first protective dummy is adjacent to the second bonding pad and has a third surface that is substantially coplanar with the second surface of the second bonding pad, wherein the second bonding pad comprises a circle and the first protective dummy is formed concentrically with the second bonding pad.

10. The interconnect structure of claim 9, wherein, The first protective dummy is separated from the second bonding pad by a first separation distance, which is greater than the width of the first protective dummy.

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