Semiconductor structure
By employing a diamond-ceramic composite structure on the substrate, the high thermal conductivity of diamond is utilized to conduct heat, thus solving the problem of insufficient thermal conductivity of the substrate, improving heat dissipation capacity and thermal cycling stability, and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN YICHI TECHNOLOGY CO LTD
- Filing Date
- 2025-06-27
- Publication Date
- 2026-07-31
AI Technical Summary
The current substrate has insufficient thermal conductivity, resulting in excessively high chip junction temperature, severe lifespan degradation, and brittle fracture under high-frequency thermal cycling. In addition, the manufacturing cost of diamond substrates is too high.
The system employs a composite structure of a diamond substrate and a ceramic substrate with higher thermal conductivity. The power chip is located on the diamond substrate with higher thermal conductivity. Heat is conducted through the diamond substrate, and the system is combined with an external heat sink and a thermal conductive layer to improve heat dissipation capacity and thermal cycling stability.
It improves the heat dissipation capacity of power chips and the thermal cycling stability of semiconductor structures, while reducing process costs and enhancing the bending strength and fracture toughness of the substrate.
Smart Images
Figure CN224583723U_ABST
Abstract
Description
[0001] This utility model was developed with the support of the Ministry of Industry and Information Technology's Project No. 163 of 2023, Project No.: 2340STCZB1921 / 163. Technical Field
[0002] This utility model relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure. Background Technology
[0003] With the rapid development of semiconductor technology, electronic devices are facing dual heat dissipation challenges brought about by two major technological evolution directions. In the field of industrial power electronics, in scenarios such as electric vehicle drive systems, 5G base station power amplifier modules, and data center servers, the operating power density of wide bandgap semiconductor devices such as silicon carbide (SiC) and gallium nitride (GaN) has exceeded 300 W / cm², and the local hot spot temperature can reach above 150 °C. In the field of consumer electronics, smartphone processor manufacturing processes have entered the 3 nm era, with transistor density exceeding 200 million / mm², while chip thermal design power has climbed to over 10 W.
[0004] However, current substrates still have shortcomings. Utility Model Content
[0005] The problem solved by this invention is how to improve the substrate to ensure insulation requirements while enhancing the substrate's heat dissipation capacity and the thermal cycling stability of the semiconductor structure.
[0006] To address the aforementioned problems, this utility model provides a semiconductor structure comprising: a substrate, the substrate including a first part and a second part, wherein the thermal conductivity of the first part is greater than that of the second part; and a power chip, wherein the projection of the power chip onto the surface of the substrate is at least partially located in the first part.
[0007] Optionally, the projection of the power chip onto the substrate does not exceed the range of the first part.
[0008] Optionally, it further includes a transition layer located between the substrate and the power chip, wherein the projection of the transition layer on the surface of the substrate at least partially overlaps with the projection of the power chip on the surface of the substrate.
[0009] Optionally, the transition layer includes a titanium carbide layer and a molybdenum carbide layer.
[0010] Optionally, the power chip is located on a first surface of the substrate.
[0011] Optionally, the substrate includes a first surface and a second surface; the power chip is located on the first surface; the semiconductor structure further includes a first thermally conductive layer located on the second surface.
[0012] Optionally, it further includes: a second thermally conductive layer, the second thermally conductive layer being located between the substrate and the power chip, and the projection of the power chip on the surface of the substrate being located within the projection range of the second thermally conductive layer on the surface of the substrate.
[0013] Optionally, the first part is connected to an external heat sink.
[0014] Optionally, it may also include a silicone grease encapsulation layer, which is located between the first part and the external heat sink.
[0015] Optionally, it may also include a connecting layer located between the first part and the second part.
[0016] Optionally, the connecting layer is a solder layer or an adhesive layer.
[0017] Compared with the prior art, the technical solution of this utility model has the following advantages:
[0018] In the semiconductor structure of this utility model, the projection of the power chip on the surface of the substrate is at least partially located in the first part, that is, at least part of the power chip is located on the first part with higher thermal conductivity. The heat generated by at least part of the power chip is conducted away through the first part with higher thermal conductivity, thereby improving the heat dissipation capacity of the power chip and the thermal cycling stability of the semiconductor structure. Attached Figure Description
[0019] Figure 1 This is a schematic cross-sectional view of a semiconductor structure.
[0020] Figure 2 Cross-sectional structural schematic diagrams of semiconductor structures according to some embodiments of this utility model;
[0021] Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure of some other embodiments of the present invention;
[0022] Figure 4 This is a cross-sectional schematic diagram of a semiconductor structure according to some embodiments of the present invention. Detailed Implementation
[0023] As can be seen from the background technology, current substrates still have shortcomings. The reasons for these shortcomings are analyzed below:
[0024] Please refer to Figure 1 A semiconductor structure includes: a substrate 100; and a power chip 101, wherein the power chip 101 is on the substrate 100.
[0025] The substrate 100 includes a first surface 100a and a second surface 100b, and the power chip 101 is located on the first surface 100a of the substrate 100.
[0026] The semiconductor structure further includes: a first thermally conductive layer 102, the first thermally conductive layer 102 being located on the first surface 100a, the first thermally conductive layer 102 being located between the substrate 100 and the power chip 101, and the projection of the power chip 101 on the surface of the substrate 100 being located within the projection range of the first thermally conductive layer 102 on the surface of the substrate 100.
[0027] The semiconductor structure further includes a second thermally conductive layer 103, which is located on the second surface 100b, and the projection of the power chip 101 on the surface of the substrate 100 is located within the projection range of the second thermally conductive layer 103 on the surface of the substrate 100.
[0028] Specifically, the substrate 100 is a ceramic substrate, and the substrate 100 includes an Al2O3 substrate, an AlN substrate, and a Si3N4 substrate.
[0029] The first thermally conductive layer 102 is a metal layer, and the second thermally conductive layer 103 is a metal layer. Specifically, the first thermally conductive layer 102 includes a copper layer, and the second thermally conductive layer 103 includes a copper layer.
[0030] However, the thermal conductivity of ceramic substrates 100 is insufficient. For example, the thermal conductivity of Al2O3 substrates is only 20 W / m·K to 35 W / m·K, and that of Si3N4 substrates is about 20 W / m·K to 80 W / m·K. This can lead to excessively high chip junction temperatures and severe lifespan degradation. Furthermore, the fracture toughness of most mainstream ceramic substrates is less than 6 MPa·m¹ / ², making them prone to brittle fracture under high-frequency thermal cycling.
[0031] Using diamond as the substrate material 100 can improve the heat dissipation performance of the chip, but it also greatly increases the cost of the process.
[0032] To solve the aforementioned technical problem, this utility model provides a semiconductor structure, comprising: a substrate, the substrate including a first part and a second part, wherein the thermal conductivity of the first part is greater than that of the second part; and a power chip, wherein the projection of the power chip on the surface of the substrate is at least partially located in the first part.
[0033] In the semiconductor structure of this utility model, the projection of the power chip on the surface of the substrate is at least partially located in the first part, that is, at least part of the power chip is located on the first part with higher thermal conductivity. The heat generated by at least part of the power chip is conducted away through the first part with higher thermal conductivity, which ensures the insulation requirements while improving the heat dissipation capacity of the power chip and the thermal cycling stability of the semiconductor structure.
[0034] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.
[0035] The semiconductor structure includes a substrate 200, which includes a first part I and a second part II, wherein the thermal conductivity of the first part I is greater than that of the second part II.
[0036] The thermal conductivity of the first part I is greater than that of the second part II, which helps to more efficiently conduct the heat generated by the heat-generating device to the outside of the heat-generating device and improve heat dissipation efficiency.
[0037] Specifically, in some embodiments of this invention, the first part I is a diamond substrate with a thermal conductivity of not less than 2000 W / m·K, and the second part II is a ceramic substrate with a thermal conductivity of 20 W / m·K to 80 W / m·K. The diamond substrate has nearly 100 times higher thermal conductivity than the ceramic substrate, which helps to more efficiently dissipate the heat generated by the heating device during operation to the outside. Furthermore, the composite structure substrate of the first part I and the second part II has a bending strength of 800 MPa and a fracture toughness greater than 10 MPa·m¹ / ², greatly improving the bending strength and fracture toughness of the substrate.
[0038] Specifically, in some embodiments of this utility model, the material of the first part I includes single-crystal diamond and polycrystalline diamond.
[0039] Specifically, in some embodiments of this invention, the second part II surrounds the first part I, and the first part I is square. In other embodiments, the first part I may also be other geometric shapes.
[0040] The substrate 200 includes a first surface 200a and a second surface 200b. The first portion I is connected to an external heat sink (not shown). Specifically, the second surface 200b of the first portion I of the substrate 200 is connected to the external heat sink.
[0041] The external heat sink reduces the temperature of the heat-generating device based on the principle of heat conduction. The heat from the heat-generating device is conducted to the external heat sink via the substrate. The external heat sink contacts the substrate and absorbs the heat, thereby reducing the temperature of the heat-generating component. The external heat sink includes a liquid cooling plate and heat pipes.
[0042] The semiconductor structure further includes a silicone grease encapsulation layer (not shown), which is located between the first part I and the external heat sink. The first part I and the external heat sink are connected through the silicone grease encapsulation layer.
[0043] For details, please continue to refer to [the website / information]. Figure 2 The semiconductor structure further includes a connection layer 201, which is located between the first part I and the second part II.
[0044] The connecting layer 201 is a solder layer or an adhesive layer. The first part I and the second part II are connected by processes such as active metal brazing or surface coating sintering.
[0045] For example, an embodiment of the present invention provides a method for forming a substrate 200.
[0046] Step S100: Provide a first substrate material layer and etch a groove in the first substrate material layer;
[0047] Step S101: Provide a second substrate material layer, and cut the second substrate material layer to obtain a first part I that matches the groove size;
[0048] Step S102: Apply adhesive evenly to the inner circumference of the groove to form a connecting layer 201, embed the first part I into the groove and cure it to form a substrate 200, the substrate 200 including the first part I and the second part II;
[0049] Step S103: Place the substrate 200 in a polishing fixture for planarization.
[0050] Specifically, in step S100, the first substrate material layer provides a structural basis for forming the second part II. The material of the first substrate material layer is a ceramic material, including Al2O3, AlN and Si3N4.
[0051] The first substrate material layer is etched by laser processing to form the groove, which defines the position of the first part I in this embodiment of the present invention.
[0052] The groove penetrates the first substrate material layer along its thickness direction, and the shape of the groove is determined according to process requirements. For example, the thickness of the first substrate material layer is approximately 0.3 mm; the depth of the groove is 0.3 mm, and the shape of the groove is a 5 mm × 5 mm square.
[0053] In some embodiments of this invention, the groove has a chamfer.
[0054] In step S101, the material of the second substrate material layer is diamond; the material of the second substrate material layer is cut using a laser processing method to form the first part I. For example, in some embodiments of this invention, the diamond blank is cut into 5 mm × 5 mm square pieces.
[0055] In step S102, the connecting layer 201 is located between the first part I and the second part II, so that the first part I is fixed to the second part II.
[0056] The connection layer 201 needs to provide insulation and serve as a thermal stress buffer and material fixation. The softening temperature of the connection layer 201 needs to be higher than the maximum junction temperature of the power device. The maximum junction temperature of a power device refers to the highest temperature at which its internal semiconductor PN junction or transistor junction region can operate stably for a long period without irreversible damage; it is a key parameter for measuring device reliability and performance. The higher the thermal conductivity of the substrate, the faster the heat dissipates from the junction region of the power device, and the slower the junction temperature rises at the same power consumption.
[0057] The thermal expansion coefficient of diamond, the material of the first part I, is smaller than that of most materials. Therefore, when the first part is embedded into the groove at room temperature and then cured at a higher temperature, the interfacial stress between the first part I and the second part II can be ignored.
[0058] In step S103, the surface of the substrate 200 is subjected to rough grinding, fine grinding and polishing until the surface roughness of the substrate 200 is no greater than 100 nm.
[0059] In other embodiments, the first substrate 200 material layer with grooves can also be obtained by preforming and sintering.
[0060] The semiconductor structure includes a power chip 202, the projection of which is at least partially located on the surface of the substrate 200 in the first part I.
[0061] The projection of the power chip 202 on the surface of the substrate 200 is at least partially located on the first part I, that is, at least part of the power chip 202 is located on the first part I. The thermal conductivity of the first part I is higher than that of the second part II. The heat generated by at least part of the power chip 202 is conducted away through the first part I, which has higher thermal conductivity. This helps to more efficiently conduct the heat generated by the power chip 202 during operation to the external heat sink. While ensuring insulation requirements, it improves the heat dissipation capacity of the power chip 202 and the thermal cycling stability of the semiconductor structure.
[0062] Thermal conduction refers to the process by which heat is transferred through the vibration or migration of particles (atoms, molecules, electrons, etc.) within a substance. Its core principle follows Fourier's law of heat conduction:
[0063] .
[0064] in,
[0065] Q: Heat transferred per unit time (heat dissipation power);
[0066] k: Thermal conductivity of the material (W / m·K), characterizing the material's ability to conduct heat;
[0067] A: Cross-sectional area for heat conduction;
[0068] ΔT: Temperature difference between the two sides of the material;
[0069] d: Material thickness.
[0070] Therefore, under the same temperature difference (ΔT), area (A), and thickness (d), the higher the thermal conductivity k, the greater the heat Q transferred per unit time, that is, the faster the heat dissipation rate.
[0071] Specifically, in some embodiments of this utility model, the first part I is a diamond substrate, and the second part II is a ceramic substrate. Diamond substrates have better thermal conductivity, while ceramic substrates are less expensive and provide insulation, mechanical support, and circuit wiring functionality. Using a diamond substrate 200 with higher thermal conductivity at the corresponding position of the power chip 202, and using a ceramic substrate 200 at other positions, can improve the heat dissipation capacity of the power chip 202 and the thermal cycling stability of the semiconductor structure while reducing manufacturing costs.
[0072] The power chip 202 is located on the first surface 200a. Specifically, the power chip 202 is located on the first surface 200a of the first part I.
[0073] The projection of the power chip 202 onto the substrate 200 does not exceed the range of the first part I. This includes situations where the projection of the power chip 202 onto the substrate 200 completely coincides with the first part I, and the projection of the power chip 202 onto the substrate 200 is located within the range of the first part I.
[0074] For details, please refer to Figure 2 In some embodiments of this utility model, the projection of the power chip 202 on the substrate 200 is located within the range of the first part I, so that the heat of the power chip 202 can be transferred to the external heat sink (not shown) through the diamond substrate 200, which helps to more efficiently conduct the heat generated by the power chip 202 during operation to the external heat sink and realize timely heat dissipation of the power chip 202.
[0075] The shape of the first part I is adapted to match the shape of the power chip 202, and the size of the first part I is adapted to match the size of the power chip 202. For example, in some embodiments of the present invention, when the power chip 202 is square, the shape of the first part I is correspondingly square; when the size of the power chip 202 is 5mm × 5mm, the size of the first part I is correspondingly not less than 5mm × 5mm.
[0076] In some embodiments of the present invention, the semiconductor structure further includes a transition layer (not shown), the transition layer being located between the substrate 200 and the power chip 202, and the projection of the transition layer on the surface of the substrate 200 at least partially overlapping the projection of the power chip 202 on the surface of the substrate 200.
[0077] The transition layer is adapted to enhance the bonding force between the first part I and the power chip 202 and improve the interface thermal resistance.
[0078] Diamond has a higher thermal conductivity than most metals. The heat generated by the power chip 202 is transferred to the first part I through the transition layer, and then directly to the external heat sink through the first part I. This avoids the thermal diffusion delay caused by the additional metal layer and improves the heat dissipation performance of the power chip 202.
[0079] Specifically, in some embodiments of this invention, the transition layer is formed by depositing titanium carbide (TiC) or molybdenum carbide (Mo2C) on the surface of the first part I. The thickness of the transition layer ranges from 50 nm to 200 nm.
[0080] In other embodiments, interface treatment and silver sintering can be performed on the surface of the first part I to enhance the bonding force between the first part I and the power chip 202 and improve the interface thermal resistance.
[0081] The similarities to the foregoing embodiments will not be repeated here. The differences from the foregoing embodiments are as follows, please refer to... Figure 3 The semiconductor structure further includes a first thermally conductive layer 300, which is located on the second surface 200b.
[0082] The projection of the power chip 202 onto the surface of the substrate 200 is located within the projection range of the first thermally conductive layer 300 onto the surface of the substrate 200.
[0083] The material of the first heat-conducting layer 300 includes one or more of the following metals: copper, aluminum, silver, gold, molybdenum, tungsten, and titanium.
[0084] The power chip 202 generates a lot of heat when it is working. The first thermal conductive layer 300 has good thermal conductivity and a large surface area, which can quickly conduct the heat generated by the power chip 202 away.
[0085] The projection of the power chip 202 on the surface of the substrate 200 is at least partially located on the first part I, that is, at least part of the power chip 202 is located on the first part I with higher thermal conductivity. The heat generated by at least part of the power chip 202 is conducted to the first thermal conductive layer 300 through the first part I with higher thermal conductivity and then transferred out, thereby improving the heat dissipation capacity of the power chip 202 and the thermal cycling stability of the semiconductor structure.
[0086] Specifically, in some embodiments of this utility model, the first part I is connected to the external heat sink through the first thermally conductive layer 300. That is, the heat generated by the power chip 202 is transferred to the first part I, then to the first thermally conductive layer 300, and finally to the external heat sink.
[0087] The similarities to the foregoing embodiments will not be repeated here. The differences from the foregoing embodiments are as follows, please refer to... Figure 4 The semiconductor structure further includes a second thermally conductive layer 400, which is located between the substrate 200 and the power chip 202, and the projection of the power chip 202 on the surface of the substrate 200 is located within the projection range of the second thermally conductive layer 400 on the surface of the substrate 200.
[0088] The material of the second heat-conducting layer 400 includes one or more of the following metals: copper, aluminum, silver, gold, molybdenum, tungsten, and titanium.
[0089] The power chip 202 generates a lot of heat when it is working. The second thermal conductive layer 400 has good thermal conductivity and a large surface area, which can quickly conduct the heat generated by the power chip 202 away.
[0090] At least a portion of the heat generated by the power chip 202 is transferred through the second thermal conductive layer 400 to the first part I, which has a higher thermal conductivity, then through the first part I to the first thermal conductive layer 300, and then through the first thermal conductive layer to the external heat sink, thereby improving the heat dissipation capacity of the power chip 202 and the thermal cycling stability of the semiconductor structure.
[0091] Specifically, the power chip 202 and the second thermal conductive layer 400 are physically connected through processes such as silver sintering.
[0092] In summary, the projection of the power chip 202 onto the surface of the substrate 200 is at least partially located on the first part I, that is, at least a portion of the power chip 202 is located on the first part I with higher thermal conductivity. The heat generated by at least a portion of the power chip 202 is conducted away through the first part I with higher thermal conductivity, thereby improving the heat dissipation capacity of the power chip 202 and the thermal cycling stability of the semiconductor structure.
[0093] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized by, include: A substrate, the substrate comprising a first part and a second part, wherein the thermal conductivity of the first part is greater than that of the second part; A power chip, wherein the projection of the power chip onto the surface of the substrate is at least partially located in the first part.
2. The semiconductor structure of claim 1, wherein, The projection of the power chip onto the substrate does not exceed the range of the first part.
3. The semiconductor structure of claim 1, wherein, Also includes: A transition layer is located between the substrate and the power chip, and the projection of the transition layer on the surface of the substrate at least partially overlaps with the projection of the power chip on the surface of the substrate.
4. The semiconductor structure of claim 3, wherein, The transition layer includes a titanium carbide layer and a molybdenum carbide layer.
5. The semiconductor structure of claim 1, wherein, The power chip is located on the first surface of the substrate.
6. The semiconductor structure of claim 1, wherein, The substrate includes a first surface and a second surface; The power chip is located on the first surface; The semiconductor structure further includes a first thermally conductive layer, which is located on the second surface.
7. The semiconductor structure of claim 1, wherein, Also includes: A second thermally conductive layer is located between the substrate and the power chip, and the projection of the power chip on the surface of the substrate is within the projection range of the second thermally conductive layer on the surface of the substrate.
8. The semiconductor structure of claim 1, wherein, The first part is connected to an external heat sink.
9. The semiconductor structure of claim 8, wherein, Also includes: A silicone grease encapsulation layer is located between the first part and the external heat sink.
10. The semiconductor structure of claim 1, wherein, Also includes: A connecting layer is located between the first part and the second part.
11. The semiconductor structure of claim 10, wherein, The connecting layer is a solder layer or an adhesive layer.