Power substrate and power module

Abstract

This utility model discloses a power substrate and a power module, applicable to the field of power device technology. A first metal layer is located on the bottom surface of an insulating layer and covers a first region on the top surface of the insulating layer along at least one side of the insulating layer. A second metal layer is located in a second region on the top surface of the insulating layer, and the first and second metal layers are isolated from each other on the top surface of the insulating layer. The insulating layer includes a main layer with the same material as the substrate of the power chip to be bonded. The main layer has an insulating film layer at least in the second region on the top surface, and the second metal layer is isolated from the main layer through the insulating film layer. By setting the main layer to be made of the same material as the substrate of the power chip to be bonded, it can be ensured that the thermal expansion coefficients of the insulating layer and the power chip are approximately the same, allowing the insulating layer to be set as a flat plate. Furthermore, by setting the first metal layer covering the insulating layer, the structural strength of the entire insulating layer can be increased, ensuring that the power substrate meets the required structural performance.

Description

Technical Field

[0001] This utility model relates to the field of power device technology, and in particular to a power substrate and a power module. Background Technology

[0002] A power semiconductor module is a device capable of high-frequency, high-voltage, and high-current output. It consists of multiple power chips arranged in a specific electrical topology and packaged into an integrated module, making it readily applicable in industrial, new energy, and electronic fields. The power substrate, as a key component of the power module, plays a crucial role in industries such as new energy vehicles. With continuous technological advancements and market development, power substrates are trending towards higher performance, lower cost, smaller size, and lighter weight.

[0003] In existing power module packaging structures, the power substrate plays a crucial role, providing electrical interconnection and insulation, corrosion protection, mechanical support, and heat dissipation channels for semiconductor chips. Currently, commonly used power substrates can be mainly classified into polymer substrates, insulating metal substrates, and ceramic substrates based on their materials. Due to the high voltage, high power, and high heat generation characteristics of power semiconductor modules, the use of polymer substrates and insulating metal substrates is greatly limited. Ceramic substrates, on the other hand, are the most widely used due to their high thermal conductivity, good heat resistance, high insulation, high strength, and thermal matching with chip materials.

[0004] Currently, the welding of power substrates and power chips typically requires a vacuum and high-temperature environment. In this environment, the difference in thermal expansion coefficients between the two components can cause the power substrate to bend. Therefore, the power substrate currently requires a certain degree of curvature, which is opposite to the direction of bending deformation caused by welding. Thus, the power substrate cannot be a flat plate before welding; a pre-existing curvature is needed for compensation and suppression. High precision in pre-curvature is required, making processing difficult. Excessive curvature leads to thick solder layers, which are prone to voids and high installation stress. Insufficient curvature results in high interface thermal resistance or poor sealing leading to leakage. Therefore, providing a power substrate with a flat structure that ensures good welding with the power chip is a problem urgently needing to be solved by those skilled in the art. Utility Model Content

[0005] The purpose of this invention is to provide a power substrate and a power module that can ensure good soldering between the power substrate and the power chip.

[0006] To solve the above-mentioned technical problems, this utility model provides a power substrate, comprising: a first metal layer, an insulating layer, and a second metal layer;

[0007] The insulating layer includes a top surface facing the power chip and a bottom surface away from the power chip. The first metal layer is located on the bottom surface of the insulating layer and covers a first region of the top surface of the insulating layer along at least one side of the insulating layer. The second metal layer is located in a second region of the top surface of the insulating layer. The first metal layer and the second metal layer are isolated from each other on the top surface of the insulating layer.

[0008] The insulating layer includes a main layer made of the same material as the substrate in the power chip to be bonded. The main layer has an insulating film layer in at least a second region on the top surface. The second metal layer is isolated from the main layer through the insulating film layer.

[0009] The first metal layer attached to the side of the insulating layer is provided with a connection structure for connecting to the outer shell.

[0010] By using the same substrate material for the main layer and the power chip to be bonded, it is ensured that the thermal expansion coefficients of the insulating layer and the power chip are approximately the same, preventing bending in high-temperature environments and allowing the insulating layer to be configured as a flat plate. Furthermore, by incorporating a first metal layer covering the insulating layer, the structural strength of the entire insulating layer is increased, ensuring that the power substrate meets the required structural performance.

[0011] The insulating layer provided in this application has a high coefficient of thermal expansion that matches the power chip. Whether in the vacuum high-temperature reflow soldering process or the high-temperature operating environment of the module, the deformation of the insulating layer is consistent with the deformation of the power chip, reducing the risk of power chip failure and improving device reliability. Furthermore, the power module in this solution uses a silicon wafer as a substrate, resulting in low material cost and high thermal conductivity, which is beneficial for reducing the size of the power chip and the overall device volume.

[0012] Optionally, the host layer comprises a silicon wafer, and the insulating film layer comprises an oxide layer.

[0013] This application uses silicon, the same material as the power chip, for the insulating layer. This ensures consistent thermal expansion and solves the problem of chip tearing caused by thermal stress during power chip soldering. At the same temperature, the deformation of both materials is identical with minimal error, avoiding tearing damage caused by differences in thermal expansion coefficients between the power chip and the power substrate during soldering. The solution provided in this application significantly reduces end-application costs by one-third, facilitating industrialization and commercial mass production and application. Furthermore, the power module in this solution uses a silicon wafer as the substrate, resulting in low material costs and high thermal conductivity, which helps to reduce the size of the power chip and the overall device volume.

[0014] Optionally, the oxide layer covers at least the top surface of the silicon wafer.

[0015] Optionally, the first metal layer covers all sides of the insulating layer from the bottom of the insulating layer to the edge of the top surface of the insulating layer.

[0016] Optionally, the surface of the first metal layer facing away from the insulating layer is provided with a protruding structure for heat dissipation.

[0017] Optionally, the protrusion structure includes heat dissipation pillars extending along the side away from the insulating layer, the heat dissipation pillars being distributed in an array.

[0018] In this application, the first metal layer can be used as a heat dissipation structure. Compared with traditional power modules, the power module of this application reduces the copper foil layer between the power substrate and the heat sink, significantly reducing the overall thermal resistance of the power module. Simultaneously, a metal with high thermal conductivity is used as the second metal layer. Due to its good flexibility at high temperatures, it further avoids power chip failure caused by inconsistent thermal expansion coefficients, further improving the production yield of the power module. The power module of this application has a lightweight structure, reduces multiple metal layers and solder, and features low cost and high reliability.

[0019] This application's power substrate requires no curved design or micro-curvature, features a thin solder layer, high welding quality, low residual stress, low leakage risk, and high reliability. This application also reduces thermal resistance, improving the lateral heat dissipation capacity of the power module by 1 to 10 times while reducing material usage, thus slightly improving heat dissipation performance while ensuring reliability.

[0020] Optionally, the first metal layer may be any of the following:

[0021] Aluminum layer, aluminum alloy layer, copper layer, copper-aluminum alloy layer;

[0022] And / or, the spacing width between the first metal layer and the second metal layer on the top surface of the insulating layer ranges from 0.5 mm to 1 mm.

[0023] Optionally, the second metal layer is a fluid metal layer that is fixed at the first temperature when the power chip is held in place.

[0024] This application uses a metal that is fluid at high temperatures as the second metal layer. Due to its excellent flexibility at high temperatures, it further avoids power chip failure caused by inconsistent coefficients of thermal expansion, thus further improving the production yield of the power module. The power module structure of this application is lightweight, reducing the number of metal layers and solder, and features low cost and high reliability.

[0025] Optionally, the first metal layer attached to the side of the insulating layer is provided with mounting holes extending in the thickness direction.

[0026] The present invention also provides a power module, including a power chip and a power substrate as described in any of the above claims, wherein the power chip is fixedly connected to the second metal layer.

[0027] This power module also has the aforementioned beneficial effects, which will not be elaborated upon here. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a power substrate provided in an embodiment of the present utility model;

[0030] Figure 2 for Figure 1 A schematic diagram of the structure after power chips are soldered onto a medium-power substrate;

[0031] Figure 3 This is a schematic diagram of another power substrate provided in an embodiment of the present invention;

[0032] Figure 4 An exploded view of a power module provided in an embodiment of this utility model;

[0033] Figure 5 This is a schematic diagram of the structure of a power module provided in an embodiment of the present utility model;

[0034] Figure 6 This is a top view schematic diagram of a power substrate fabricated in this embodiment;

[0035] Figure 7 for Figure 6 A sectional view along line AA.

[0036] In the figure: 1. Insulating layer, 2. First metal layer, 3. Second metal layer, 4. Power chip, 5. Mounting hole, 6. Raised structure, 7. Bonding wire, 8. Power pin, 9. Housing, 10. Encapsulation colloid, 11. Cover plate. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0038] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0039] The heat dissipation base plate structure for existing power semiconductor modules is usually made of solid metal (copper or silicon carbide aluminum AlSiC) plates, with a thickness of 3mm to 8mm. These are typically divided into flat-bottom indirect heat dissipation structures and integrated pin-fin direct cooling structures. The substrate of a power module, based on its application requirements, needs to possess high thermal conductivity (good thermal conductivity to effectively dissipate the heat generated by the power module), a reasonable coefficient of thermal expansion (similar to the chip's coefficient of thermal expansion to avoid thermal stress at the interface under high temperatures, which could lead to interface breakage or damage), high strength (sufficient mechanical strength to operate normally under high vibration), long lifespan (meeting the vehicle's design lifespan requirements, typically 15 years or more, with zero failures), small size, and low cost (avoiding excessively large assembly volume and reducing manufacturing costs). The ceramic substrate materials used in existing power modules, such as DBC or AMB ceramic substrates, are generally ceramic sheets made of Al2O3, AlN, Si3N4, or zirconium-doped Al2O3. Although these materials meet the needs of most application scenarios, they cannot simultaneously possess the advantages of high thermal conductivity, reasonable thermal expansion, low cost, and high strength. Therefore, they require adaptive selection for different application scenarios, resulting in low compatibility.

[0040] Meanwhile, the existing standard power module's overall structure consists of a chip, a DBC (Direct Bonded Copper) ceramic substrate, and a heat sink metal plate. The power chip transmits electrical functions through bonding wires or copper strips. The power chip, DBC ceramic substrate, and heat sink metal plate are connected by vacuum reflow soldering to achieve thermal conductivity, insulation, and corresponding electrical performance. When the power chip is working, it generates a large amount of heat. Most of this heat is transferred to the heat sink metal plate through the DBC ceramic substrate and dissipated through the flow of coolant. This packaging method has at least the following technical problems:

[0041] 1. Because this classic packaging module needs to be manufactured in a vacuum and high-temperature environment, the heat dissipation metal plate bends towards the back due to its smaller coefficient of thermal expansion than the DBC ceramic substrate (see "CN103794571A"). This bending leads to solder fatigue damage, and the DBC ceramic substrate and heat dissipation base plate are prone to soldering voids, which directly affect the heat dissipation of the overall system. At the same time, during soldering, the DBC ceramic substrate and the power chip will also deform due to the thermal stress generated by the high temperature, which can easily cause the power chip to over-deform and fail. Overall, the reliability is low, the production process requires strict settings, the fixture design is complex, and the production process is complicated and cumbersome.

[0042] Specifically, the power chip, ceramic substrate, and metal base plate are connected by soldering. Since the thermal expansion coefficients of each layer are different, temperature changes during the soldering and operation processes can cause the base plate to bend and deform, generating stress on the solder surface. Appropriate installation pressure is required between the base plate and the heat sink or cooling water tank to ensure optimal thermal contact, reduce interfacial thermal resistance, or seal the cooling water. This requires the finished module base plate (heat sink) to have a certain curvature. This curvature is opposite to the direction of the bending deformation caused by soldering; therefore, the base plate cannot be flat before soldering and must have a pre-existing curvature for compensation and suppression. High precision is required for the pre-curvature, making processing difficult. Excessive curvature results in a thick solder layer, easily causing voids and high installation stress; insufficient curvature leads to high interfacial thermal resistance or poor sealing and leakage.

[0043] 2. Due to the differences in the thermal expansion coefficients of various materials in the existing power module substrate, the current production process is relatively complex and has a high defect rate, which further leads to high production costs and is not conducive to the industrial application of power modules.

[0044] 3. In the prior art, the ceramic substrate typically includes an electrical connection layer, a ceramic layer and a metal connection layer from top to bottom. The metal connection layer is used to connect with the heat sink, and a heat dissipation structure is provided on the outside of the heat sink. At this time, the heat dissipation path from the power chip usually includes a solder layer → electrical connection layer → ceramic layer → metal connection layer → solder layer → heat sink → heat dissipation structure. This heat dissipation path is long and the heat dissipation efficiency is low.

[0045] Based on this, the present invention provides a power substrate comprising: a first metal layer, an insulating layer, and a second metal layer; the insulating layer includes a top surface facing the power chip and a bottom surface away from the power chip; the first metal layer is located on the bottom surface of the insulating layer and covers a first region of the top surface of the insulating layer along at least one side of the insulating layer; the second metal layer is located in a second region of the top surface of the insulating layer; the first metal layer and the second metal layer are isolated from each other on the top surface of the insulating layer; the insulating layer includes a main layer of the same material as the substrate of the power chip to be bonded; the main layer has an insulating film layer disposed at least in the second region of the top surface; the second metal layer is isolated from the main layer through the insulating film layer; the first metal layer attached to the side surface of the insulating layer is provided with a connection structure for connecting to the outer shell.

[0046] By using the same substrate material for the main layer and the power chip to be bonded, it is ensured that the thermal expansion coefficients of the insulating layer and the power chip are approximately the same, preventing bending in high-temperature environments and allowing the insulating layer to be configured as a flat plate. Furthermore, by incorporating a first metal layer covering the insulating layer, the structural strength of the entire insulating layer is increased, ensuring that the power substrate meets the required structural performance.

[0047] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] Example 1

[0049] Please refer to Figure 1 as well as Figure 2 , Figure 1 This is a schematic diagram of the structure of a power substrate provided in an embodiment of the present utility model; Figure 2 for Figure 1 A schematic diagram of the structure after power chips are soldered onto a medium-power substrate.

[0050] See Figure 1 as well as Figure 2In this embodiment, the power substrate includes a first metal layer 2, an insulating layer 1, and a second metal layer 3. The insulating layer 1 includes a top surface facing the power chip 4 and a bottom surface away from the power chip 4. The first metal layer 2 is located on the bottom surface of the insulating layer 1 and covers a first region of the top surface of the insulating layer 1 along at least one side. The second metal layer 3 is located in a second region of the top surface of the insulating layer 1. The first metal layer 2 and the second metal layer 3 are isolated from each other on the top surface of the insulating layer 1. The insulating layer 1 includes a main layer with the same material as the substrate of the power chip 4 to be bonded. The main layer has an insulating film layer at least in the second region of the top surface. The second metal layer 3 is isolated from the main layer through the insulating film layer. The first metal layer 2 attached to the side of the insulating layer 1 is provided with a connection structure for connecting to the outer shell 9.

[0051] The aforementioned insulating layer 1 is the main structure of the power substrate. It not only needs to provide certain mechanical properties, but also needs to have good heat dissipation performance and good insulation. In this embodiment, the insulating layer 1 can specifically be a flat plate structure, that is, the surface of the insulating layer 1 is flat and has no curvature. Therefore, the preparation of the insulating layer 1 is relatively simple.

[0052] Specifically, in this embodiment, the insulating layer 1 includes a main layer made of the same material as the substrate of the power chip 4 to be bonded, and an insulating film layer is disposed on the surface of the main layer. That is, in this embodiment, the insulating layer 1 specifically includes a main layer and an insulating film layer covering the surface of the main layer. The main layer is the main structure of the insulating layer 1, so the main layer can be a flat structure, that is, the surface of the main layer is flat and has no curvature. In this embodiment, the material of the main layer needs to be the same as the substrate material of the power chip 4 to be bonded, so that the thermal expansion coefficient of the insulating layer 1 is approximately the same as that of the power chip 4. This setting can ensure that the insulating layer 1 will not bend in a high-temperature environment due to the large difference in thermal expansion coefficients compared with the power chip 4, and ensure that no gap will be generated between the power substrate and the power chip 4 due to the difference in thermal expansion coefficients in a high-temperature environment. Therefore, the main layer can be configured as a flat structure, and the corresponding power substrate can be configured as a flat structure.

[0053] Since the material of the aforementioned main layer is the same as that of the substrate in power chip 4, it is typically a semiconductor material. This material usually has excellent thermal conductivity, but in order to ensure its insulation, in this embodiment, an insulating film layer needs to be formed on the surface of the main layer at least. This insulating film layer is usually attached to the surface of the main layer in the form of a film layer. It usually does not excessively affect the coefficient of thermal expansion of the insulating layer 1, but it can greatly improve its insulation, making the semiconductor material main layer suitable for power substrates.

[0054] The second metal layer 3 is mainly used for welding the power substrate and the power chip 4. The first metal layer 2, in this application, serves two purposes: heat dissipation and structural strength enhancement of the insulating layer 1, enabling it to achieve the structural strength required by the power substrate. Specifically, in this embodiment, the surface of the insulating layer 1 is divided into a top surface, a bottom surface, and a side surface. The top surface faces the power chip 4, and the bottom surface is away from the power chip 4. The first metal layer 2 is specifically located on the bottom surface of the insulating layer 1 and covers at least one side of the insulating layer 1 to a first region on the top surface. That is, the first metal layer 2 covers the insulating layer 1 from bottom to top along at least one side surface, typically covering the bottom surface, at least one side surface, and part of the top surface to increase the structural strength of the insulating layer 1. The second metal layer 3 is only located in a portion of the top surface of the insulating layer 1. Within the top surface of the insulating layer 1, the first region covered by the first metal layer 2 and the second region covered by the second metal layer 3 need to be isolated from each other to avoid direct contact between the first metal layer 2 and the second metal layer 3.

[0055] It should be noted that the aforementioned insulating film layer must be at least located in the second region on the top surface of the main body layer, meaning that this insulating film layer will isolate the second metal layer 3 from the main body layer. The second metal layer 3 is used for soldering to the power chip 4. In this case, the second metal layer 3 is electrically isolated from the main body layer in the thickness direction through the insulating film layer, and in the horizontal direction, the second metal layer 3 is physically separated from the first metal layer 2. Therefore, this structure ensures that the second metal layer 3 is electrically insulated from the first metal layer 2, preventing the first metal layer 2 from interfering with the circuitry of the power chip 4. In addition to the second region, the aforementioned insulating film layer can further cover the gap between the first and second regions, thereby ensuring that the first metal layer 2 and the second metal layer 3 are mutually insulated. In one feasible example, the aforementioned insulating film layer can at least cover the top surface of the main body layer to ensure that the first metal layer 2 and the second metal layer 3 are mutually insulated. In another feasible example, to facilitate the placement of the insulating film layer, the insulating film layer can cover the entire surface of the main body layer.

[0056] Specifically, in this embodiment, the main body layer includes a silicon wafer, and the insulating film layer includes an oxide layer. That is, in this embodiment, a silicon wafer can be used as the main body layer, and silicon is also the material used in the substrate of conventional power chip 4. The silicon wafer can be either a monocrystalline silicon wafer or a polycrystalline silicon wafer; no specific limitation is made here. Choosing silicon material of the same type as power chip 4 for the main body layer is beneficial for maintaining consistent thermal expansion coefficients, which can solve the technical problem of deformation caused by thermal stress during the welding process of power chip 4, leading to chip failure. In this embodiment, the insulating layer 1 uses the same silicon-based material as power chip 4, with the same or similar thermal expansion coefficients. At the same temperature, the deformation is the same with minimal error, avoiding the failure or damage of power chip 4 caused by deformation differences due to differences in thermal expansion coefficients between power chip 4 and the power substrate during the welding process.

[0057] The aforementioned oxide layer serves as an insulating film layer to ensure electrical isolation between the first metal layer 2 and the second metal layer 3. Typically, the oxide layer can cover at least the top surface of the silicon wafer. Alternatively, it can cover the entire surface of the silicon wafer to increase its insulation properties. It should be noted that this oxide layer needs to be a dense oxide layer, not an oxide layer formed by natural oxidation, to enhance its insulating performance.

[0058] Furthermore, the first metal layer 2 can cover all sides of the insulating layer 1 from its bottom surface to the edge of its top surface. That is, the first metal layer 2 can cover the insulating layer 1 from its bottom surface along all sidewalls to the edge of its top surface. In this case, the second metal layer 3 will be disposed in the central region of the top surface of the insulating layer 1, and the two layers are isolated from each other. The spacing between the first metal layer 2 and the second metal layer 3 needs to be determined based on parameters such as the electrical performance of the power substrate and the insulation performance of its insulating film layer, and is not specifically limited here. Assuming the spacing width between the first metal layer 2 and the second metal layer 3 is D1, the value of D1 is between 0.5 mm and 1 mm, preferably 0.8 mm. This structure, because the first metal layer 2 completely covers the sides of the insulating layer 1, can greatly increase the structural strength of the power substrate and also improve its heat dissipation performance. In this embodiment, multiple insulating layers 1 can be connected into a whole based on a first metal layer 2. The specific number of insulating layers 1 can be set according to actual conditions and is not specifically limited here.

[0059] In this embodiment, the material of the first metal layer 2 can be aluminum or copper, and the material of the second metal layer 3 can be aluminum, copper, or other metals, without specific limitations. The thickness of the insulating layer 1 is typically 0.2mm to 1.0mm, and the thickness of the second metal layer 3 is typically 0.1mm to 0.3mm. The thickness of the first metal layer 2 needs to be set according to the requirements of heat dissipation performance, structural strength, etc., without specific limitations. It should be noted that the second metal layer 3 is typically a patterned metal layer, which facilitates the electrical connection of the power chip 4. In this embodiment, the power chip 4 and the second metal layer 3 can be interconnected by solder, such as solder paste, solder pads, or active metal solder, and additional bonding wires 7 or bonding metal strips are required based on the power substrate and the power chip 4 for electrical connection and transmission. The required wiring needs to be set according to the actual situation, without specific limitations.

[0060] Furthermore, in this embodiment, the first metal layer 2 attached to the side of the insulating layer 1 may be provided with a connection structure for connecting to the outer casing 9. This connection structure is used to allow the power substrate to be fixedly connected to the outer casing 9 when packaging the power module. The specific content of this connection structure can be set according to the actual situation and is not specifically limited here. Specifically, in this embodiment, the first metal layer 2 attached to the side of the insulating layer 1 is provided with mounting holes 5 extending along the thickness direction. The mounting holes 5 serve as a connection structure and can be connected to the outer casing 9 by screws. It should be noted that the mounting holes 5 are provided on the first metal layer 2 attached to the side of the insulating layer 1, and specifically extend along the thickness direction, such as... Figure 1 As shown, it will not penetrate the insulating layer 1. Therefore, the mounting hole 5 can avoid affecting the structure of the insulating layer 1, that is, avoid drilling holes in semiconductor materials such as silicon to ensure that the insulating layer 1 has sufficient structural strength. In addition to setting the mounting hole 5 as a connection structure, other structures can also be set as connection structures, and no specific limitation is made here.

[0061] The power substrate provided in this embodiment, by setting the substrate material of the main layer and the power chip 4 to be bonded to be the same, can ensure that the thermal expansion coefficients of the insulating layer 1 and the power chip 4 are approximately the same, avoiding bending of the two in high-temperature environments, so that the insulating layer 1 can be set as a flat plate. Furthermore, by setting the first metal layer 2 covering the insulating layer 1, the structural strength of the entire insulating layer 1 can be increased, ensuring that the power substrate meets the required structural performance.

[0062] The thermal expansion coefficient of the insulating layer 1 provided in this application is highly compatible with that of the power chip 4. Whether in the vacuum high-temperature reflow soldering process or the high-temperature operating environment of the module, the deformation of the insulating layer 1 is consistent with that of the power chip 4, reducing the risk of power chip 4 failure and improving device reliability. At the same time, the power module of this solution uses silicon wafers as the main layer, which has low material cost and high thermal conductivity, which is conducive to reducing the size of the power chip 4 and the device volume.

[0063] The specific details of the power substrate provided in this application will be described in detail in the following embodiments.

[0064] Example 2

[0065] Please refer to Figure 3 , Figure 3 This is a schematic diagram of another power substrate provided in an embodiment of the present invention.

[0066] Unlike the embodiments described above, this embodiment further defines the structure of the power substrate based on the above embodiments. The remaining details have been described in detail in the above embodiments and will not be repeated here.

[0067] See Figure 3 In this embodiment, a raised structure 6 for heat dissipation is provided on the surface of the first metal layer 2 facing away from the insulating layer 1. This raised structure 6 is fixedly connected to the first metal layer 2, allowing heat to be transferred from the first metal layer 2 to the raised structure 6 for dissipation. The raised structure 6 increases the heat dissipation area relative to the first metal layer 2, and can be further integrated with heat dissipation components such as water cooling to improve the heat dissipation performance of the power substrate. It should be noted that the combination of the raised structure 6 and the first metal layer 2 is equivalent to a traditional heat sink; that is, in this embodiment, by directly providing the raised structure 6 on the surface of the first metal layer 2, the power substrate and the heat sink can be combined, resulting in a very short heat conduction path, which helps to improve the heat dissipation performance of the power substrate.

[0068] Specifically, in this embodiment, the protruding structure 6 includes heat dissipation pillars extending along the side away from the insulating layer 1, and the heat dissipation pillars are arranged in an array. The arrayed heat dissipation pillars, combined with the first metal layer 2, can form a PIN-FIN heat dissipation structure, wherein the first metal layer 2 serves as the substrate of the PIN-FIN heat dissipation structure. This structure can ensure that the power substrate has excellent heat dissipation performance, and ultimately further enhance the heat dissipation capability of the power module.

[0069] In this embodiment, the second metal layer 3 is a fluid metal layer that is fixed at the first temperature when the power chip 4 is in place. In this application, the power substrate and power chip 4 are soldered together at a relatively high temperature, referred to as the first temperature in this embodiment. In this embodiment, the second metal layer 3 needs to be fluid when the power substrate and power chip 4 are soldered at the first temperature. At this temperature, the second metal layer 3 itself can act as solder to solder the insulating layer 1 and power chip 4 together, without the need for additional solder. Therefore, after encapsulating the power chip 4, this structure can further reduce the use of one layer of solder in the heat dissipation path from the power chip 4 to the heat dissipation structure, thereby further improving heat dissipation performance. Furthermore, by setting the second metal layer 3 to be fluid at the first temperature, warping between the second metal layer 3 and the insulating layer 1 due to the difference in thermal expansion coefficients can be further avoided when soldering the power chip 4. The fluid second metal layer 3 can also effectively fill the gap between the insulating layer 1 and the power chip 4, ensuring a tight bond between them. The second metal layer 3 mentioned above at the first temperature can be in a liquid or semi-solid state, and there is no specific limitation here, as long as it has fluidity.

[0070] Typically, the aforementioned metal layer, which is in a liquid or semi-solid state at the first temperature, needs to be patterned. The purpose of this patterning is to ensure the formation of specific circuitry to facilitate electrical connections with the power chip 4, while also preventing the second metal layer 3 from flowing out of the insulating layer 1 and contacting the first metal layer 2 at the first temperature. Because this metal layer is fluid at the first temperature, it further prevents gaps between the second metal layer 3 and the insulating layer 1 caused by differences in their coefficients of thermal expansion during the soldering process. Simultaneously, the second metal layer 3 can directly fill the gaps between the insulating layer 1 and the power chip 4 caused by slight differences in their coefficients of thermal expansion, ensuring that the insulating layer 1 maintains a flat plate structure. In this embodiment, the second metal layer 3 can be an aluminum-based active metal (Al-Si-Ti series), and its specific material can be determined according to actual conditions; no specific limitations are made here.

[0071] In another feasible example, a solder layer is provided on the surface of the second metal layer 3 facing away from the insulating layer 1. This solder layer is used to fix the power chip 4. When the second metal layer 3 is a metal layer that is still solid at the first temperature, such as an aluminum layer or a copper layer, in this example, a solder layer can be further provided on the surface of the second metal layer 3 facing away from the insulating layer 1. This solder layer ensures a fixed connection between the power chip 4 and the second metal layer 3 during soldering. This solder layer also needs to be fluid at the first temperature to further avoid gaps between the second metal layer 3 and the power chip 4 due to differences in their coefficients of thermal expansion during soldering, ensuring that the insulating layer 1 can have a flat plate structure. The specific material of this solder layer can be set according to the actual situation and is not specifically limited here.

[0072] The power substrate provided in this embodiment integrates the function of a heat sink by setting a raised structure 6, reducing the length of the heat dissipation path and helping to improve heat dissipation performance. Using a metal layer with fluidity at a first temperature as the second metal layer 3 can further ensure that the power substrate can still form a good electrical connection with the power chip 4 under a flat structure, further reducing the failure problem caused by the inconsistency of the thermal expansion coefficients between the power chip 4 and the insulating layer 1, improving the reliability of the power module, and ensuring the product production yield.

[0073] The second metal layer 3 is formed by using a metal layer that is liquid at the first temperature, which further avoids the failure of the power chip 4 caused by inconsistent thermal expansion coefficients, improves the production yield of the power module, and reduces cost losses. Compared with the thermal stress compensation structure of the existing heat sink base plate, this application does not require an arc design, has a thin solder layer, good welding quality, low residual stress, low risk of leakage, and high reliability.

[0074] Example 3

[0075] Please refer to Figures 4 to 7 , Figure 4 An exploded view of a power module provided in an embodiment of this utility model; Figure 5 This is a schematic diagram of the structure of a power module provided in an embodiment of the present utility model; Figure 6 This is a top view of a power substrate in this embodiment; Figure 7 for Figure 6 A sectional view along line AA.

[0076] See Figures 4 to 7This embodiment also provides a power module, which includes a power chip 4 and a power substrate as provided in any of the above utility model embodiments. Specifically, the power chip 4 is fixedly connected to the second metal layer 3, thereby achieving a fixed connection between the power chip 4 and the power substrate. The structure of the power substrate can be referred to in the above embodiments and will not be repeated here. The specific structure of the power chip 4 can be referred to in the prior art, and will also not be repeated here.

[0077] In addition to the power chip 4 and power substrate mentioned above, the power module typically includes a cover plate 11, a housing 9, power pins 8, bonding wires 7, and encapsulating colloid 10. Specifically, the power module can be formed using the HPD (High Power Device) standard packaging method. Specifically, the power chip 4 can be arranged in a bridge circuit on the second metal layer 3, the bonding wires 7 are used for electrical connections between power chips 4 and with external circuits, the power pins 8 are used for controlling and sampling the power chip 4, and the entire module is encapsulated by the housing 9, potted, and dried.

[0078] For example, the power module shown in this application is a three-phase full-bridge power module with an HPD package. It can also be a half-bridge module or an H-bridge module, and the package can also be ME4, HP1, etc. This application does not impose any fixed limitations.

[0079] Since the power module of this embodiment is provided with the power substrate provided in the above-described utility model embodiment, the manufacturing cost of the power module is lower, the result is simpler, the heat dissipation is more efficient, and the performance is more stable.

[0080] The power substrate of this application exhibits a high degree of matching between its thermal expansion coefficient and that of the power chip 4. Whether during vacuum high-temperature reflow soldering in the production process or in the high-temperature operating environment of the module, the deformation of the power substrate is consistent with that of the power chip 4, reducing the risk of power chip 4 failure and improving the reliability of the power module. Furthermore, the power substrate of this application uses silicon wafers as the substrate, resulting in low material cost and high thermal conductivity, which is beneficial for reducing the size of the power chip 4 and the volume of the power module. Moreover, the use of an active metal as the second metal layer 3 further reduces the risk of power chip 4 failure, significantly improving product yield.

[0081] Compared to traditional power modules, this application's power module reduces the copper foil layer between the power substrate and the heat sink, significantly lowering the overall thermal resistance of the power module. Simultaneously, it employs a metal with high thermal conductivity as the second metal layer 3. Due to its excellent flexibility at high temperatures, it further avoids power chip 4 failure caused by inconsistent thermal expansion coefficients, further improving the production yield of the power module. This application's power module has a lightweight structure, reducing the number of metal layers and solder, resulting in low cost and high reliability.

[0082] This application's power substrate requires no curved design or micro-curvature, features a thin solder layer, high welding quality, low residual stress, low leakage risk, and high reliability. This application reduces thermal resistance, increasing the lateral heat dissipation capacity of the power module by 1 to 10 times while reducing material usage, thus improving heat dissipation performance while maintaining reliability. The manufacturing process of this application is significantly different from existing technologies. By using a high-temperature, fluid metal layer, production yield is improved, void ratio is reduced, and product reliability is enhanced, making it suitable for industrial mass production applications.

[0083] In this application, the insulating layer 1 is made of the same silicon material as the power chip 4. This facilitates synchronized thermal expansion and solves the problem of deformation caused by thermal stress during the welding process of the power chip 4, which can lead to chip tearing. At the same temperature, the deformation of the two layers is the same with minimal error, avoiding tearing and damage to the power chip 4 due to differences in thermal expansion coefficients between the power chip 4 and the power substrate during welding. The solution provided in this application significantly reduces the cost of end-applications by one-third, which is beneficial for industrialization and commercial mass production and application.

[0084] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0085] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0086] The power substrate and power module provided by this utility model have been described in detail above. Specific examples have been used to illustrate the principle and implementation of this utility model. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core idea of ​​this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made to this utility model without departing from the principle of this utility model, and these improvements and modifications also fall within the protection scope of the claims of this utility model.

Claims

1. A power substrate, characterized by, include: First metal layer, insulating layer, and second metal layer; The insulating layer includes a top surface facing the power chip and a bottom surface away from the power chip. The first metal layer is located on the bottom surface of the insulating layer and covers a first region of the top surface of the insulating layer along at least one side of the insulating layer. The second metal layer is located in a second region of the top surface of the insulating layer. The first metal layer and the second metal layer are isolated from each other on the top surface of the insulating layer. The insulating layer includes a main layer made of the same material as the substrate in the power chip to be bonded. The main layer has an insulating film layer in at least a second region on the top surface. The second metal layer is isolated from the main layer through the insulating film layer. The first metal layer attached to the side of the insulating layer is provided with a connection structure for connecting to the outer shell.

2. The power substrate of claim 1, wherein, The main body layer includes a silicon wafer, and the insulating film layer includes an oxide layer.

3. The power substrate of claim 2, wherein, The oxide layer covers at least the top surface of the silicon wafer.

4. The power substrate of claim 1, wherein, The first metal layer covers the entire side surface of the insulating layer from the bottom of the insulating layer to the edge of the top surface of the insulating layer.

5. The power substrate of claim 1, wherein, The surface of the first metal layer facing away from the insulating layer has a raised structure for heat dissipation.

6. The power substrate of claim 5, wherein, The protruding structure includes heat dissipation columns extending along the side away from the insulating layer, and the heat dissipation columns are distributed in an array.

7. The power substrate of claim 1, wherein, The first metal layer is any one of the following: Aluminum layer, aluminum alloy layer, copper layer, copper-aluminum alloy layer; And / or, the spacing width between the first metal layer and the second metal layer on the top surface of the insulating layer ranges from 0.5 mm to 1 mm.

8. The power substrate of any of claims 1-7, wherein, The second metal layer is a fluid metal layer that is used to fix the power chip at the first temperature.

9. The power substrate of any of claims 1-7, wherein, The first metal layer attached to the side of the insulating layer is provided with mounting holes extending in the thickness direction.

10. A power module, characterized by It includes a power chip and a power substrate as described in any one of claims 1 to 9, wherein the power chip is fixedly connected to the second metal layer.

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