Semiconductor structure
By setting recesses on the frame carrier, the bonding adhesive between the chip and the frame carrier is located within the recesses, which improves connection stability and area, solves the problem of unstable connection between semiconductor chips and frame carriers, and ensures the performance and stability of semiconductor power devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- RUINENG WEIEN SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2025-07-30
- Publication Date
- 2026-07-31
AI Technical Summary
Insufficient stability of the connection between the semiconductor chip and the frame carrier affects the performance and stability of semiconductor power devices.
A recess is formed by indenting the surface of the frame carrier on the side facing the chip. The projection of the chip and the projection of the recess overlap at least partially. Part of the structure of the adhesive is located inside the recess. The recess increases the connection area and surface roughness, and restricts the flowability of the adhesive.
This improves the connection stability between the chip and the frame carrier, reduces the probability of adhesive creeping up the chip side, reduces the risk of short circuits between different electrodes, and ensures the performance of semiconductor power devices.
Smart Images
Figure CN224583733U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor structure. Background Technology
[0002] Semiconductor power devices are structures that encapsulate microelectronic components or chips in a protective casing. They mainly consist of semiconductor chips and frame carriers. The frame carriers not only provide physical support and protection for the chips, but also support the connection, heat dissipation, and other functions of the semiconductor chips.
[0003] For semiconductor power devices, the connection stability between the semiconductor chip and the frame carrier directly affects their performance and stability during operation. Utility Model Content
[0004] The semiconductor structure provided in this application embodiment can improve the connection stability between the chip and the frame carrier.
[0005] This application provides a semiconductor structure, including:
[0006] Framework carrier;
[0007] The chip is disposed on one side of the frame carrier along its thickness direction;
[0008] A bonding adhesive is disposed between the chip and the frame carrier along the thickness direction, with the side of the bonding adhesive facing the chip connected to the chip and the side of the bonding adhesive facing the frame carrier connected to the frame carrier.
[0009] The frame carrier has a recessed portion formed on one side of its surface facing the chip. The projection of the chip in the thickness direction and the projection of the recess in the thickness direction overlap at least partially. A portion of the adhesive structure is located inside the recess.
[0010] In some embodiments, multiple recesses are provided, the projection of the chip in the thickness direction is located inside the projection outer contour of the multiple recesses in the thickness direction, and the projection of the adhesive in the thickness direction covers and extends beyond the projection outer contour of the multiple recesses in the thickness direction.
[0011] In some embodiments, the plurality of recesses includes a first recess that extends along a first direction, the first recess having a larger dimension in the first direction than its dimension in a second direction, and the first direction, the second direction, and the thickness direction intersecting each other.
[0012] The plurality of the first recesses are spaced apart along the second direction.
[0013] In some embodiments, the extension dimension of the first recess in the first direction is greater than the extension dimension of the chip in the first direction, and both ends of the first recess in the first direction extend beyond both ends of the chip in the first direction.
[0014] The plurality of first recesses include a first edge recess and a second edge recess located at the two side edges along the second direction, wherein the projection of the first edge recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction, and the projection of the second edge recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction.
[0015] In some embodiments, the plurality of recesses includes a second recess extending along the second direction, the second recess having a larger dimension in the second direction than its dimension in the first direction, and the second recess intersecting with and communicating with at least a portion of the first recess;
[0016] Multiple second recesses are distributed at intervals along the first recess.
[0017] In some embodiments, the extension dimension of the second recess in the second direction is greater than the extension dimension of the chip in the second direction, and both ends of the second recess in the second direction extend beyond both ends of the chip in the second direction.
[0018] The plurality of second recesses include a third edge recess and a fourth edge recess located at the two side edges along the first direction, wherein the projection of the third edge recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction, and the projection of the fourth edge recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction.
[0019] In some embodiments, the plurality of recesses include a third recess, the plurality of third recesses being spaced apart along the first direction and spaced apart along the second direction, wherein the first direction, the second direction and the thickness direction intersect each other.
[0020] In some embodiments, the plurality of third recesses include a first corner recess, a second corner recess, a third corner recess, and a fourth corner recess located at the edge position along the first direction and at the edge position along the second direction;
[0021] The projection of the first corner recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction, the projection of the second corner recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction, the projection of the third corner recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction, and the projection of the fourth corner recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction.
[0022] In some embodiments, the diameter of the recess near the chip end along the thickness direction is larger than the diameter of the recess away from the chip end along the thickness direction.
[0023] In a direction away from the chip along the thickness direction, the size of the recess gradually decreases in the first direction, which intersects the thickness direction.
[0024] In some embodiments, a plurality of recesses are provided, and the ratio between the projected outer contour of the plurality of recesses in the thickness direction and the projection of the chip in the thickness direction is M, where 1≤M≤1.3.
[0025] According to the semiconductor structure provided in this application, the semiconductor structure includes a chip, a frame carrier, and a bonding adhesive connecting the chip and the frame carrier. To improve the connection stability between the chip and the frame carrier while ensuring the performance of the semiconductor power device, a recess is formed on the side of the frame carrier facing the chip. The projection of the chip in the thickness direction at least partially overlaps the projection of the recess in the thickness direction, and a portion of the bonding adhesive structure is located inside the recess. When the bonding adhesive is disposed on the frame carrier, the portion of the bonding adhesive structure is located inside the recess. The recess increases the connection area between the bonding adhesive and the frame carrier, thereby improving the connection stability to a certain extent. Simultaneously, the recess also increases the surface roughness of the frame carrier, and the sidewalls of the recess can limit the bonding adhesive to a certain extent, reducing the flowability of the bonding adhesive on the frame carrier surface and decreasing the probability of the bonding adhesive flowing to the side of the chip. This reduces the climb rate of the bonding adhesive on the side of the chip, thereby reducing the probability of short circuits between different electrodes on both sides of the chip and ensuring the performance of the semiconductor power device. Attached Figure Description
[0026] The features, advantages, and technical effects of exemplary embodiments of this application will now be described with reference to the accompanying drawings.
[0027] Figure 1 A cross-sectional view of a semiconductor structure provided for some embodiments of this application;
[0028] Figure 2 This is a first top view schematic diagram of a semiconductor structure provided in some embodiments of this application;
[0029] Figure 3 This is a second top view schematic diagram of a semiconductor structure provided in some embodiments of this application;
[0030] Figure 4 This is a third top view schematic diagram of a semiconductor structure provided for some embodiments of this application.
[0031] Marker explanation:
[0032] 10. Frame carrier;
[0033] 20. Chips;
[0034] 30. Adhesive;
[0035] A1, Recess; A11, First Recess; A111, First Edge Recess; A112, Second Edge Recess; A12, Second Recess; A121, Third Edge Recess; A122, Fourth Edge Recess; A13, Third Recess; A131, First Corner Recess; A132, Second Corner Recess; A133, Third Corner Recess; A134, Fourth Corner Recess;
[0036] X, first direction; Y, second direction; Z, thickness direction.
[0037] In the accompanying drawings, the same parts use the same reference numerals. The drawings are not drawn to scale. Detailed Implementation
[0038] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.
[0039] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0040] Semiconductor power devices are structures that encapsulate microelectronic components or chips in a protective casing. They mainly consist of semiconductor chips and frame carriers. The frame carriers not only provide physical support and protection for the chips, but also support the connection, heat dissipation, and other functions of the semiconductor chips.
[0041] For semiconductor power devices, the connection stability between the semiconductor chip and the frame carrier directly affects their performance and stability during operation.
[0042] In related technologies, semiconductor power devices utilize a surface mount technology (SMT) process to electrically connect semiconductor chips and a mounting frame to achieve high electrical and thermal conductivity characteristics. However, further improvements are needed to enhance the reliability of the connection between the semiconductor chip and the mounting frame during the SMT process.
[0043] In view of this, please refer to Figure 1 and Figure 2 This application provides a semiconductor structure including a frame carrier 10, a chip 20, and a bonding adhesive 30 connecting the chip 20 and the frame carrier 10. The chip 20 is disposed on one side of the frame carrier 10 along its thickness direction Z. The bonding adhesive 30 is disposed between the chip 20 and the frame carrier 10 along the thickness direction Z, with the side of the bonding adhesive 30 facing the chip 20 connected to the chip 20 and the side of the bonding adhesive 30 facing the frame carrier 10 connected to the frame carrier 10. The surface of the frame carrier 10 facing the chip 20 is recessed inward to form a recess A1. The projection of the chip 20 in the thickness direction Z at least partially overlaps with the projection of the recess A1 in the thickness direction Z, and a portion of the bonding adhesive 30 is located inside the recess A1.
[0044] The semiconductor structure provided in this application is a structural form of some structural components in a semiconductor power device. Specifically, the semiconductor structure includes a chip 20, a frame carrier 10, and a connecting adhesive 30 connecting the chip 20 and the frame carrier 10. This application aims to improve the connection stability between the chip 20 and the frame carrier 10. This application does not impose any limitations on other structures in the semiconductor power device, such as pin structures.
[0045] In this embodiment, chip 20 is disposed on one side of frame carrier 10 along its thickness direction Z, and adhesive 30 is disposed between chip 20 and frame carrier 10 along its thickness direction Z. The side of adhesive 30 facing chip 20 is connected to chip 20, and the side of adhesive 30 facing frame carrier 10 is connected to frame carrier 10. Chip 20, as the core structure in a semiconductor device, realizes functions such as efficient power conversion, control, and protection within the semiconductor device. Frame carrier 10 is used to support and fix chip 20, while also externally connecting chip 20 to other structures. Exemplarily, corresponding electrodes in chip 20 are electrically connected to frame carrier 10, one end of the pin structure is connected to frame carrier 10, and the other end of the pin structure is exposed outside the semiconductor device and can be connected to other structures.
[0046] The chip 20 is connected to the frame carrier 10 by a bonding adhesive 30, which can be a conductive adhesive. For example, the bonding adhesive 30 includes pressureless sintered silver. The chip 20 and the frame carrier 10 are connected by pressureless sintered silver to meet the product characteristics of high conductivity and high thermal conductivity of semiconductor power devices.
[0047] When the chip 20 is connected to the frame carrier 10 using adhesive 30, the adhesive 30, being a gel-like material, will have a certain degree of fluidity at room temperature. In actual fabrication, insufficient coverage of the adhesive 30 may lead to poor connection stability between the chip 20 and the frame carrier 10, thus affecting the performance of the semiconductor power device. Simultaneously, during the connection process, the adhesive 30 can easily flow to the sides of the chip 20, creating a creeping phenomenon that could cause short circuits between different electrodes on both sides of the chip 20.
[0048] To improve the connection stability between the chip 20 and the frame carrier 10 while ensuring the performance of the semiconductor power device, in this embodiment, a recess A1 is formed by an inward indentation on the surface of the frame carrier 10 facing the chip 20. The projection of the chip 20 in the thickness direction Z and the projection of the recess A1 in the thickness direction Z at least partially overlap. A portion of the adhesive 30 is located inside the recess A1. The recess A1 is located on the side of the frame carrier 10 facing the chip 20. When the adhesive 30 is disposed on the frame carrier 10, a portion of the adhesive 30 is located inside the recess A1. The recess A1 increases the connection area between the adhesive 30 and the frame carrier 10, thereby improving the connection stability between them to a certain extent. When the chip 20 is placed on the adhesive 30, it exerts a certain squeezing effect on the adhesive 30. The recess A1 can accommodate the adhesive 30, and within the range of the recess A1, the adhesive 30 can be effectively covered. The coverage of the adhesive 30 on the carrier frame can be controlled by changing the range of the recess A1, thereby ensuring the connection stability between the chip 20 and the frame carrier 10. At the same time, the recess A1 can also increase the surface roughness of the frame carrier 10. The sidewall of the recess A1 can limit the adhesive 30 to a certain extent, thereby reducing the flow of the adhesive 30 on the surface of the frame carrier 10 and reducing the probability of the adhesive 30 flowing to the side of the chip 20. This reduces the degree of climbing of the adhesive 30 on the side of the chip 20, thereby reducing the probability of short circuits between different electrodes on both sides of the chip 20 and ensuring the performance of the semiconductor power device.
[0049] In summary, in this embodiment, the semiconductor structure is a structural form of a portion of the structural components in a semiconductor power device. The semiconductor structure includes a chip 20, a frame carrier 10, and a bonding agent 30 connecting the chip 20 and the frame carrier 10. To improve the connection stability between the chip 20 and the frame carrier 10 while ensuring the performance of the semiconductor power device, a recess A1 is formed by an inward indentation on the surface of the frame carrier 10 facing the chip 20. The projection of the chip 20 in the thickness direction Z and the projection of the recess A1 in the thickness direction Z at least partially overlap. A portion of the bonding agent 30 is located inside the recess A1. When the bonding agent 30 is disposed on the frame carrier 10, the portion of the bonding agent 30 is located inside the recess A1. The recess A1 increases the connection area between the bonding agent 30 and the frame carrier 10, thereby improving the connection stability between the bonding agent 30 and the frame carrier 10 to a certain extent. Meanwhile, the recess A1 can also improve the surface roughness of the frame carrier 10. The sidewall of the recess A1 can limit the adhesive 30 to a certain extent, thereby reducing the flow of the adhesive 30 on the surface of the frame carrier 10 and reducing the probability of the adhesive 30 flowing to the side of the chip 20. This reduces the degree of the adhesive 30 climbing on the side of the chip 20, thereby reducing the probability of short circuit between different electrodes on both sides of the chip 20 and ensuring the performance of the semiconductor power device.
[0050] In some embodiments, please refer to Figure 1 and Figure 2 Multiple recesses A1 are provided. The projection of chip 20 in the thickness direction Z is located inside the outer contour of the projection of multiple recesses A1 in the thickness direction Z. The projection of adhesive 30 in the thickness direction Z covers and extends beyond the outer contour of the projection of multiple recesses A1 in the thickness direction Z.
[0051] The frame carrier 10 has multiple recesses A1 on the side facing the chip 20. These recesses A1 can be spaced apart from each other on the frame carrier 10 or interconnected. When the adhesive 30 is applied to the frame carrier 10, in the thickness direction Z, part of the adhesive 30 is located inside the recesses A1, and part is located outside the recesses A1. The adhesive 30 located outside the recesses A1 is connected to the adhesive 30 located inside the different recesses A1 to form a whole. The side of the adhesive 30 facing away from the frame structure is connected to the chip 20.
[0052] Specifically, the distribution of the adhesive 30 on the frame carrier 10 is affected by the projected outer contour of the recess A1 in the thickness direction Z. In order to ensure the connection stability of the adhesive 30 on the frame carrier 10, the projection of the adhesive 30 in the thickness direction covers and extends beyond the projected outer contour of the multiple recesses A1 in the thickness direction Z. With the above arrangement, the adhesive 30 can fill the interior of each recess A1 and fill each recess A1 to the outside of the recess A1, so as to control the coverage area of the adhesive 30 on the frame carrier 10 by the arrangement of the recesses A1.
[0053] Furthermore, to ensure the connection stability between the chip 20 and the adhesive 30, the projection of the chip 20 in the thickness direction Z is located inside the outer contour of the projection of the plurality of recesses A1 in the thickness direction Z. When the adhesive 30 is disposed on the frame carrier 10, due to the placement of the recesses A1, the adhesive 30 can at least cover the placement range of the recesses A1, thereby forming a covering surface at the location where the recesses A1 are placed on the frame carrier 10. When the chip 20 is disposed on the adhesive 30, based on the fact that the projection of the chip 20 in the thickness direction Z is located inside the outer contour of the projection of the plurality of recesses A1 in the thickness direction Z, the adhesive 30 can connect all positions on the chip 20 to ensure the connection stability between the adhesive 30 and the chip 20.
[0054] In some embodiments, please refer to Figure 1 and Figure 2 The plurality of recesses A1 include a first recess A11, which extends along a first direction X. The size of the first recess A11 in the first direction X is larger than its size in the second direction Y. The first direction X, the second direction Y, and the thickness direction Z intersect each other. The plurality of first recesses A11 are distributed at intervals along the second direction Y.
[0055] In practical applications, the chip 20 can be circular or square, and the shape of the frame structure is set based on the shape of the chip 20. Taking a square chip 20 as an example, the frame carrier 10 is also set to be square. The connection surface between the chip 20 and the adhesive 30 is a square surface, which has a certain extension dimension in the first direction X and the second direction Y; the side of the frame structure facing the chip 20 is also a square surface, which also has a certain extension dimension in the first direction X and the second direction Y.
[0056] The plurality of recesses A1 includes a first recess A11. It is understood that the plurality of recesses A1 may include various types of recesses A1, and the shapes and dimensions of different types of recesses A1 differ. The first recess A11 is one type of recess A1 among the plurality of recesses A1. The first recess A11 extends along a first direction X, and its dimension in the first direction X is greater than its dimension in the second direction Y. The first direction X and the second direction Y can be two intersecting directions in a horizontal plane, and the thickness direction Z is a vertical direction.
[0057] The projection of the first recess A11 onto the thickness direction Z is rectangular. The first direction X is the length direction of the first recess A11, and the second direction Y is the width direction of the first recess A11. The two side walls of the first recess A11 along the second direction Y can restrict the flow of the adhesive 30 in the second direction Y, thereby reducing the probability of the adhesive 30 flowing to both sides of the chip 20 along the second direction Y. Similarly, the two side walls of the first recess A11 along the first direction X can also restrict the flow of the adhesive 30 in the first direction X, thereby reducing the probability of the adhesive 30 flowing to both sides of the chip 20 along the first direction X.
[0058] Multiple first recesses A11 can be provided, and the multiple first recesses A11 are distributed at intervals along the second direction Y. On the one hand, this can increase the connection area between the carrier frame and the adhesive 30, and on the other hand, it can improve the restriction effect on the flow of the adhesive 30 in the second direction Y, reduce the degree of climbing of the adhesive 30 on both sides of the chip 20 along the second direction Y, thereby reducing the probability of short circuit between different electrodes on both sides of the chip 20 along the second direction Y, and ensuring the performance of the semiconductor power device.
[0059] In some embodiments, please refer to Figure 1 and Figure 2 The first recess A11 extends beyond the chip 20 in the first direction X, and both ends of the first recess A11 extend beyond the chip 20 in the first direction X. The plurality of first recesses A11 include a first edge recess A111 and a second edge recess A112 located at the two side edges along the second direction Y. The projection of the first edge recess A111 in the thickness direction Z is at least partially outside the projection of the chip 20 in the thickness direction Z, and the projection of the second edge recess A112 in the thickness direction Z is at least partially outside the projection of the chip 20 in the thickness direction Z.
[0060] In the first direction X, the projection of the first recess A11 in the thickness direction Z is located outside the projection of the chip 20 in the thickness direction Z. When the adhesive 30 is located inside the first recess A11, the projection of the adhesive 30 in the thickness direction Z is located outside the projection of the chip 20 in the thickness direction Z, so as to ensure the adhesion of the adhesive 30 to the chip 20. Specifically, both ends of the first recess A11 extend beyond both ends of the chip 20 in the first direction X, so that the adhesive 30 can fully cover and adhere to the chip 20 in the first direction X.
[0061] In the second direction Y, a plurality of first recesses A11 are spaced apart. Among the plurality of first recesses A11, there are first edge recesses A111 and second edge recesses A112 located at the two side edges along the second direction Y. It can be understood that when the plurality of first recesses A11 are spaced apart along the second direction Y, some of the first recesses A11 are located relatively inside, and two first recesses A11 are located relatively at the edge. The two first recesses A11 located relatively at the edge are defined as the first edge recesses A111 and the second edge recesses A112, respectively, in order to indicate the relative positional relationship between the first recesses A11 and the chip 20 in the second direction Y.
[0062] In the second direction Y, the projection of the first recess A11 in the thickness direction Z is located outside the projection of the chip 20 in the thickness direction Z. Along one side of the second direction Y, the projection of the first edge recess A111 in the thickness direction Z is at least partially located outside the projection of the chip 20 in the thickness direction Z. The projection of the first edge recess A111 in the thickness direction Z may be partially located outside the projection of the chip 20 in the thickness direction Z, partially intersecting with the projection of the chip 20 in the thickness direction Z, or the projection of the first edge recess A111 in the thickness direction Z may be entirely located outside the projection of the chip 20 in the thickness direction Z. The arrangement of the second edge recess A112 is similar to that of the first edge recess A111, and will not be described again here. When the adhesive 30 is located inside the first recess A11, the projection of the adhesive 30 in the thickness direction Z is located outside the projection of the chip 20 in the thickness direction Z, so as to ensure the adhesion of the adhesive 30 to the chip 20.
[0063] In some embodiments, please refer to Figure 1 , Figure 2 and Figure 3 The plurality of recesses A1 include a second recess A12, which extends along a second direction Y. The size of the second recess A12 in the second direction Y is larger than its size in the first direction X. The second recess A12 intersects with and communicates with at least a portion of the first recesses A11. The plurality of second recesses A12 are spaced apart along the first recesses A11.
[0064] The plurality of recesses A1 includes a second recess A12. It is understood that the plurality of recesses A1 includes various similar recesses A1, with different types of recesses A1 having different shapes and dimensions. The second recess A12 is another type of recess A1 among the plurality of recesses A1, and its shape and dimensions differ from those of the first recess A11. The second recess A12 extends along a second direction Y, and its dimension in the second direction Y is greater than its dimension in the first direction X. The first direction X and the second direction Y can be two intersecting directions in a horizontal plane, and the thickness direction Z is a vertical direction.
[0065] The projection of the second recess A12 in the thickness direction Z is rectangular. The second direction Y is the length direction of the second recess A12, and the first direction X is the width direction of the second recess A12. The two side walls of the second recess A12 along the first direction X can restrict the flow of the adhesive 30 in the first direction X, thereby reducing the probability that the adhesive 30 flows to both sides of the chip 20 along the first direction X. Similarly, the two side walls of the second recess A12 along the second direction Y can also restrict the flow of the adhesive 30 in the second direction Y, thereby reducing the probability that the adhesive 30 flows to both sides of the chip 20 along the second direction Y.
[0066] Multiple second recesses A12 can be provided, and the multiple second recesses A12 are distributed at intervals along the first direction X. On the one hand, this can increase the connection area between the carrier frame and the adhesive 30, and on the other hand, it can improve the restriction effect on the flow of the adhesive 30 in the first direction X, reduce the degree of climbing of the adhesive 30 on both sides of the chip 20 along the first direction X, thereby reducing the probability of short circuit between different electrodes on both sides of the chip 20 along the first direction X, and ensuring the performance of the semiconductor power device.
[0067] The second recess A12 extends along the second direction Y and intersects and communicates with at least a portion of the first recess A11. When the adhesive 30 is disposed on the carrier frame, based on the intersection and communication between the second recess A12 and at least a portion of the first recess A11, the adhesive 30 can flow between the second recess A12 and the first recess A11 to improve the flatness of the adhesive 30.
[0068] In some embodiments, please refer to Figure 1 , Figure 2 and Figure 3The extension dimension of the second recess A12 in the second direction Y is greater than the extension dimension of the chip 20 in the second direction Y. Both ends of the second recess A12 in the second direction Y extend beyond both ends of the chip 20 in the second direction Y. The plurality of second recesses A12 include a third edge recess A121 and a fourth edge recess A122 located at the two side edges along the first direction X. The projection of the third edge recess A121 in the thickness direction Z is at least partially located outside the projection of the chip 20 in the thickness direction Z, and the projection of the fourth edge recess A122 in the thickness direction Z is at least partially located outside the projection of the chip 20 in the thickness direction Z.
[0069] In the second direction Y, the projection of the second recess A12 in the thickness direction Z is located outside the projection of the chip 20 in the thickness direction Z. When the adhesive 30 is located inside the second recess A12, the projection of the adhesive 30 in the thickness direction Z is located outside the projection of the chip 20 in the thickness direction Z, thus ensuring the adhesion of the adhesive 30 to the chip 20. Specifically, both ends of the second recess A12 extend beyond both ends of the chip 20 in the second direction Y, allowing the adhesive 30 to fully cover and adhere to the chip 20 in the second direction Y.
[0070] In the first direction X, a plurality of second recesses A12 are spaced apart. Among the plurality of second recesses A12, there are third edge recesses A121 and fourth edge recesses A122 located at the two side edges along the first direction X. It can be understood that when the plurality of second recesses A12 are spaced apart along the first direction X, some second recesses A12 are located relatively inside, and two second recesses A12 are located relatively at the edge. The two second recesses A12 located relatively at the edge are defined as the third edge recesses A121 and the fourth edge recesses A122, respectively, in order to indicate the relative positional relationship between the second recesses A12 and the chip 20 in the first direction X.
[0071] In the first direction X, the projection of the second recess A12 in the thickness direction Z is located outside the projection of the chip 20 in the thickness direction Z. Along one side of the first direction X, the projection of the third edge recess A121 in the thickness direction Z is at least partially located outside the projection of the chip 20 in the thickness direction Z. The projection of the third edge recess A121 in the thickness direction Z may be partially located outside the projection of the chip 20 in the thickness direction Z, partially intersecting with the projection of the chip 20 in the thickness direction Z, or the projection of the third edge recess A121 in the thickness direction Z may be entirely located outside the projection of the chip 20 in the thickness direction Z. The arrangement of the fourth edge recess A122 is similar to that of the third edge recess A121, and will not be described again here. When the adhesive 30 is located inside the second recess A12, the projection of the adhesive 30 in the thickness direction Z is located outside the projection of the chip 20 in the thickness direction Z, so as to ensure the adhesion of the adhesive 30 to the chip 20.
[0072] In some embodiments, please refer to Figure 1 and Figure 4 The plurality of recesses A1 include a third recess A13. The plurality of third recesses A13 are distributed at intervals along the first direction X and at intervals along the second direction Y. The first direction X, the second direction Y and the thickness direction Z intersect each other.
[0073] The plurality of recesses A1 includes a third recess A13. It is understood that the plurality of recesses A1 may include various types of recesses A1, with differences in shape and size between different types. The third recess A13 is yet another type of recess A1 among the plurality of recesses A1. The plurality of third recesses A13 are spaced apart along a first direction X and spaced apart along a second direction Y. The extension dimension of the third recess A13 in the first direction X and its extension dimension in the second direction Y can be approximately equal to facilitate the layout of the third recesses A13. For example, the projection of the third recess A13 in the thickness direction Z can be a square or a circle.
[0074] In some embodiments, the plurality of third recesses A13 include a first corner recess A131, a second corner recess A132, a third corner recess A133, and a fourth corner recess A134 located at an edge position along a first direction X and a second direction Y. The projection of the first corner recess A131 in the thickness direction Z is at least partially located outside the projection of the chip 20 in the thickness direction Z, the projection of the second corner recess A132 in the thickness direction Z is at least partially located outside the projection of the chip 20 in the thickness direction Z, the projection of the third corner recess A133 in the thickness direction Z is at least partially located outside the projection of the chip 20 in the thickness direction Z, and the projection of the fourth corner recess A134 in the thickness direction Z is at least partially located outside the projection of the chip 20 in the thickness direction Z.
[0075] In the first direction X, the projection of the third recess A13 in the thickness direction Z is located outside the projection of the chip 20 in the thickness direction Z. In the second direction Y, the projection of the third recess A13 in the thickness direction Z is also located outside the projection of the chip 20 in the thickness direction Z. When the adhesive 30 is located inside the third recess A13, the projection of the adhesive 30 in the thickness direction Z is located outside the projection of the chip 20 in the thickness direction Z, thus ensuring the adhesion of the adhesive 30 to the chip 20.
[0076] Specifically, a plurality of third recesses A13 are spaced apart along the first direction X and spaced apart along the second direction Y. Their projected outer contours in the thickness direction Z have a square structure. The plurality of third recesses A13 include a first corner recess A131, a second corner recess A132, a third corner recess A133, and a fourth corner recess A134 located at the four corners of this square structure. Taking the first corner recess A131 as an example, the projection of the first corner recess A131 in the thickness direction Z is at least partially located outside the projection of the chip 20 in the thickness direction Z. The projection of the first corner recess A131 in the thickness direction Z can be partially located outside the projection of the chip 20 in the thickness direction Z, partially intersecting with the projection of the chip 20 in the thickness direction Z, or the projection of the first corner recess A131 in the thickness direction Z can be entirely located outside the projection of the chip 20 in the thickness direction Z. The arrangement of the second corner recess A132, the third corner recess A133, and the fourth corner recess A134 is similar to that of the first corner recess A131, and will not be described again here.
[0077] In some embodiments, please refer to Figure 1 The diameter of the recess A1 at the end closer to the chip 20 along the thickness direction Z is larger than the diameter of the recess A1 at the end farther away from the chip 20 along the thickness direction Z. In the direction farther away from the chip 20 along the thickness direction Z, the size of the recess A1 gradually decreases in the first direction X, where the first direction X intersects the thickness direction Z.
[0078] To facilitate the molding of the recess A1, the diameter of the recess A1 at the end closer to the chip 20 along the thickness direction Z is larger than the diameter of the recess A1 at the end farther away from the chip 20 along the thickness direction Z. When the adhesive 30 is disposed on the frame carrier 10, the adhesive 30 includes a first part located inside the recess A1 and a second part located outside the recess A1 along the thickness direction Z. The first part and the second part are connected at the opening end of the recess A1. Through the above arrangement, the connection size between the first part and the second part at the opening end of the recess A1 is relatively large, ensuring the integrity and reliability of the adhesive 30's own structure.
[0079] Furthermore, in the direction away from the chip 20 along the thickness direction Z, the size of the recess A1 gradually decreases in the first direction X, and the sidewall of the recess A1 includes a beveled portion. When the chip 20 contacts the adhesive 30, the adhesive 30 exerts a certain degree of compression on the sidewall of the recess A1. Through the above arrangement, the compression direction of the sidewall of the recess A1 on the adhesive 30 can be made to intersect with the chip 20, thereby improving the connection between the chip 20 and the adhesive 30.
[0080] In some embodiments, please refer to Figures 1 to 4 Multiple recesses A1 are provided, and the ratio between the outer contour of the projection of the multiple recesses A1 in the thickness direction Z and the projection of the chip 20 in the thickness direction Z is M, where 1≤M≤1.3.
[0081] When multiple recesses A1 are provided, the coverage range of the adhesive 30 on the frame carrier 10 can be adjusted by the coverage range of the projected outer contour of the multiple recesses A1 in the thickness direction Z. By controlling the ratio between the projected outer contour of the multiple recesses A1 in the thickness direction Z and the projection of the chip 20 in the thickness direction Z to be greater than 1, the connection stability between the chip 20 and the frame carrier 10 can be guaranteed. By controlling the ratio between the projected outer contour of the multiple recesses A1 in the thickness direction Z and the projection of the chip 20 in the thickness direction Z to be less than 1.3, the adhesive 30 can avoid covering an excessive area and save the amount of adhesive 30 used.
[0082] Although the present invention has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of the invention. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.
Claims
1. A semiconductor structure, characterized by, include: Framework carrier; The chip is disposed on one side of the frame carrier along its thickness direction; A bonding adhesive is disposed between the chip and the frame carrier along the thickness direction, with the side of the bonding adhesive facing the chip connected to the chip and the side of the bonding adhesive facing the frame carrier connected to the frame carrier. The frame carrier has a recessed portion formed on one side of its surface facing the chip. The projection of the chip in the thickness direction and the projection of the recess in the thickness direction overlap at least partially. A portion of the adhesive structure is located inside the recess.
2. The semiconductor structure of claim 1, wherein, The recesses are provided in multiple ways. The projection of the chip in the thickness direction is located inside the outer contour of the projection of the multiple recesses in the thickness direction. The projection of the adhesive in the thickness direction covers and extends beyond the outer contour of the projection of the multiple recesses in the thickness direction.
3. The semiconductor structure of claim 2, wherein, The plurality of recesses includes a first recess that extends along a first direction, the size of the first recess in the first direction being larger than its size in a second direction, and the first direction, the second direction, and the thickness direction intersecting each other. The plurality of the first recesses are spaced apart along the second direction.
4. The semiconductor structure of claim 3, wherein, The first recess extends beyond the chip in the first direction, and both ends of the first recess extend beyond the chip in the first direction. The plurality of first recesses include a first edge recess and a second edge recess located at the two side edges along the second direction, wherein the projection of the first edge recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction, and the projection of the second edge recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction.
5. The semiconductor structure of claim 3, wherein, The plurality of recesses includes a second recess that extends along the second direction, the second recess having a larger dimension in the second direction than its dimension in the first direction, and the second recess intersecting with and communicating with at least a portion of the first recess; Multiple second recesses are distributed at intervals along the first recess.
6. The semiconductor structure of claim 5, wherein, The extension dimension of the second recess in the second direction is greater than the extension dimension of the chip in the second direction, and both ends of the second recess in the second direction extend beyond both ends of the chip in the second direction. The plurality of second recesses include a third edge recess and a fourth edge recess located at the two side edges along the first direction, wherein the projection of the third edge recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction, and the projection of the fourth edge recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction.
7. The semiconductor structure of claim 2, wherein, The plurality of recesses include a third recess, and the plurality of third recesses are spaced apart along a first direction and spaced apart along a second direction, wherein the first direction, the second direction and the thickness direction intersect each other.
8. The semiconductor structure of claim 7, wherein, The plurality of third recesses include a first corner recess, a second corner recess, a third corner recess, and a fourth corner recess located at the edge position along the first direction and at the edge position along the second direction; The projection of the first corner recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction, the projection of the second corner recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction, the projection of the third corner recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction, and the projection of the fourth corner recess in the thickness direction is at least partially located outside the projection of the chip in the thickness direction.
9. The semiconductor structure of any of claims 1-8, wherein, The diameter of the recess near the chip along the thickness direction is larger than the diameter of the recess away from the chip along the thickness direction. In a direction away from the chip along the thickness direction, the size of the recess gradually decreases in the first direction, which intersects the thickness direction.
10. The semiconductor structure of claim 1, wherein, The recess is provided in multiple ways, and the ratio between the projected outer contour of the multiple recesses in the thickness direction and the projection of the chip in the thickness direction is M, where 1≤M≤1.3.