Fan-out inductor package structure

Abstract

This invention provides a fan-out inductor packaging structure, comprising a silicon interposer. A first functional chip, conductive metal pillars, and electromagnetic material are disposed on the front side of the silicon interposer, and a second functional chip is integrated on the back side. The first and second functional chips are electrically connected through a redistribution layer and through-silicon via (TSV) technology. This fan-out inductor packaging structure, through a silicon interposer with TSVs and a three-dimensional stacked packaging structure, achieves precise stacking and efficient interconnection of multiple chips in three-dimensional space, and also integrates an inductor structure. The vertical stacking not only greatly expands the chip capacity, but also significantly shortens the signal transmission path through the conductive metal pillars, thereby effectively improving data processing speed and overall system performance. Simultaneously, this stacking method optimizes circuit layout, resulting in an unprecedented increase in integration density.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor packaging technology, and specifically relates to a fan-out type inductor packaging structure. Background Technology

[0002] Through-Silicon Via (TSV) technology is an advanced semiconductor packaging and interconnect technology. Its core principle lies in precisely drilling tiny holes directly into a silicon wafer and cleverly using high-performance conductive materials such as copper to fill these intricate channels. This process not only ensures good contact between the inner walls of the holes and the conductive material but also achieves efficient and stable vertical electrical connections between chips at different levels. Through this innovative approach, TSV technology breaks through the limitations of traditional two-dimensional chip design, enabling chips to be stacked and interconnected in three dimensions. This revolution significantly improves chip processing speed, data transmission efficiency, and overall integration. This technology can also be used for high-speed interconnection and high-density integration of chips such as sensors, processors, and memory.

[0003] While TSV technology makes three-dimensional chip stacking possible, the number of stacked layers is not unlimited. Factors such as packaging density, thermal management challenges, manufacturing costs, and technical feasibility all constrain the number of stacked layers. Therefore, how to maintain technological progress while reasonably balancing these factors has become a crucial issue facing the current development of TSV technology. Utility Model Content

[0004] The purpose of this invention is to provide a fan-out inductor packaging structure with an inductor structure and an optimized chip stacking layout, which improves the data processing speed and overall performance of the packaging structure while ensuring high integration.

[0005] To achieve the above objectives, this utility model provides a fan-out type inductor packaging structure, which includes: A silicon interposer has a front side and a back side. The front side has a first wiring layer and the back side has a second wiring layer. The silicon interposer has a plurality of through-silicon vias, which connect the first wiring layer and the second wiring layer. The first functional chip is integrated on the front side of the silicon interposer and is electrically connected to the first redistribution layer. The second functional chip is integrated on the back of the silicon interposer and is electrically connected to the second redistribution layer. A conductive metal pillar is disposed on the front side of the silicon interposer. The bottom surface of the conductive metal pillar is electrically connected to the first superwiring layer and is electrically connected to the second superwiring layer through a through-silicon via. The first molding compound is located on the front side of the silicon interposer and covers the first functional chip, the conductive metal pillar and the first redistribution layer, exposing the top surface of the conductive metal pillar. The second molding compound is located on the back side of the silicon interposer and encapsulates the second functional chip and the second wiring layer. The third wiring layer is located on the top surface of the first encapsulation part and is electrically connected to the conductive metal pillar; after electromagnetic material is placed on the surface of the third wiring layer, a fourth wiring layer is placed; the third and fourth wiring layers completely surround the electromagnetic material.

[0006] Preferably, micro pads are provided on the first and second wiring layers respectively.

[0007] Preferably, the height of the conductive metal pillar is greater than the height of the first functional chip.

[0008] Preferably, an underfill adhesive is provided between the first functional chip and the front side of the silicon interposer, and an underfill adhesive is also provided between the second functional chip and the back side of the silicon interposer.

[0009] Preferably, there are multiple first functional chips and multiple second functional chips.

[0010] Preferably, the electromagnetic material is NiFe material.

[0011] Preferably, the surface of the fourth wiring layer is provided with solder balls for connection with external circuits.

[0012] Compared with the prior art, the present invention has the following beneficial effects: This invention discloses a fan-out inductor packaging structure that, through a silicon interposer with through-silicon vias and a three-dimensional stacked packaging structure, achieves precise stacking and efficient interconnection of multiple chips in three-dimensional space, while also integrating an inductor structure. The vertical stacking not only significantly expands the chip capacity but also, through the placement of conductive metal pillars, significantly shortens the signal transmission path, thereby effectively improving data processing speed and overall system performance. Simultaneously, this stacking method optimizes circuit layout, resulting in an unprecedented increase in integration density. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the fan-out inductor packaging structure of this utility model; Figure 2 A schematic diagram of a silicon interposer with through-silicon vias (TSVs); Figure 3 This is a schematic diagram of the structure on the back side of the silicon interposer; Figure 4 A schematic diagram of a structure in which the first functional chip is integrated on the front side of a silicon interposer; Figure 5 This is a schematic diagram of a silicon interposer layer that integrates electromagnetic materials.

[0014] Reference numerals: 1. Silicon interposer; 101. Through-silicon via; 2. First redistribution layer; 3. Second redistribution layer; 4. First functional chip; 5. Second functional chip; 6. Conductive metal pillar; 7. First molding compound; 8. Second molding compound; 9. Third redistribution layer; 10. Electromagnetic material; 11. Fourth redistribution layer; 12. Solder ball; 13. Underfill adhesive. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings.

[0016] like Figure 1 As shown, this utility model provides a fan-out type inductor packaging structure, which includes: The silicon interposer 1 has a front side and a back side. The front side has a first super-wiring layer 2 and the back side has a second super-wiring layer 3. The silicon interposer 1 has a plurality of through-silicon vias 101, which connect the first super-wiring layer 2 and the second super-wiring layer 3. The first functional chip 4 is integrated on the front side of the silicon interposer 1 and is electrically connected to the first redistribution layer 2. The second functional chip 5 is integrated on the back of the silicon interposer 1 and is electrically connected to the second redistribution layer 3. A conductive metal pillar 6 is disposed on the front side of the silicon interposer 1. The bottom surface of the conductive metal pillar 6 is electrically connected to the first redistribution layer 2 and is electrically connected to the second redistribution layer 3 through a silicon via 101. In actual implementation, the height of the conductive metal pillar 6 is greater than the height of the first functional chip 4.

[0017] The first molding compound 7 is located on the front side of the silicon interposer 1, covering the first functional chip 4, the conductive metal pillar 6 and the first redistribution layer 2, so that the top surface of the conductive metal pillar 6 is exposed. The second molding compound 8 is disposed on the back side of the silicon interposer 1 and covers the second functional chip 5 and the second wiring layer 3. A third wiring layer 9 is disposed on the top surface of the first encapsulation portion 7 and electrically connected to the conductive metal pillar 6. After an electromagnetic material 10 is disposed on the surface of the third wiring layer 9, a fourth wiring layer 11 is then disposed. The third wiring layer 9 and the fourth wiring layer 11 completely surround the electromagnetic material 10. The electromagnetic material 10 can be made of NiFe material, which has excellent electromagnetic properties; other electromagnetic materials with excellent electromagnetic properties can also be used. The inductor chip stores and releases energy through the principle of electromagnetic induction. The inductor chip also has excellent signal filtering capabilities, accurately filtering out unwanted noise signals to ensure clear transmission of useful signals, providing a stable operating environment for the circuit, thereby improving the stability and reliability of the circuit.

[0018] The fourth wiring layer 11 has solder balls 12 on its surface for connection with external circuits.

[0019] Micropads are provided on the first wiring layer 2 and the second wiring layer 3 respectively. The first functional chip 4 is electrically connected to the first wiring layer 2 through the micropads. The second functional chip 5 is also electrically connected to the second wiring layer 3 through the micropads.

[0020] An underfill adhesive 13 is provided between the first functional chip 4 and the front side of the silicon interposer 1, and an underfill adhesive 13 is also provided between the second functional chip 5 and the back side of the silicon interposer 1. This is to ensure the stability of the first functional chip 4 and the second functional chip 5.

[0021] In practice, multiple first functional chips 4 and second functional chips 5 are provided.

[0022] The following describes the fabrication steps of the packaging structure, taking two of each of the first functional chip 4 and the second functional chip 5 as an example.

[0023] First, prepare as follows Figure 2 The silicon interposer 1 (i.e., the incoming TSV wafer) with through-silicon vias 101 is shown. The incoming TSV wafer is then descum+plasma cleaned to remove residual substances generated during the TSV manufacturing process.

[0024] Then, a second multi-layer wiring layer 3 and micropads are formed on the back side of the silicon interposer 1 using bumping processes such as photolithography, sputtering, and electroplating. A thermocompression bonding (TCB) process is used to bond the second functional chip with specific functions to the micropads, enhancing electrical connectivity. An underfill process is then used, where capillary effect allows the underfill adhesive 13 to naturally diffuse and fill the gaps between the second functional chip 5 and the silicon interposer 1, enhancing the strength and stability of the connection. The back side of the silicon interposer 1 is then encapsulated to form a second encapsulation portion 8. This second encapsulation portion 8 covers the second functional chip 5 and the second multi-layer wiring layer 3, preventing damage from the external environment, such as mechanical stress, moisture, and chemical corrosion, and ensuring the stability and reliability of the second functional chip 5 after encapsulation. The structure of the back side of the silicon interposer 1 is as follows. Figure 3 As shown.

[0025] The encapsulated silicon interposer 1 is flipped over, and its front side is formed again using bumping processes such as photolithography, sputtering, and electroplating to create the first redistribution layer 2 and micropads. A second electroplating process is then used to form conductive metal pillars 6, such as copper pillars, whose height is greater than that of the first functional chip 4. An advanced thermocompression bonding (TCB) process is used to tightly bond another first functional chip 4 with specific functions to the micropads. An underfill process is then used to fill the gaps between the first functional chip 4 and the silicon interposer 1, further enhancing the electrical connection and signal transmission efficiency between them. The front side of the silicon interposer 1 is then encapsulated to form the first encapsulation portion 7, which covers the first functional chip 4, the conductive metal pillars 6, and the first redistribution layer 2, preventing damage from the external environment and ensuring the stability and reliability of the first functional chip 4 after encapsulation. During this process, fine grinding is required to ensure that the top surface of the conductive metal pillars 6 is precisely exposed to meet the requirements of subsequent precision connections. A schematic diagram of the structure of the first functional chip 4 integrated on the front side of the silicon interposer 1 is shown below. Figure 4 As shown.

[0026] Furthermore, on one side of the top surface of the conductive metal pillar 6 (the top surface of the first molding compound 7), a third wiring layer 9 is first electroplated using a bumping process, followed by electroplating of materials with excellent electromagnetic properties such as NiFe. To construct the inductive function, a fourth wiring layer 11 needs to be electroplated again to ensure that the electromagnetic materials such as NiFe are completely surrounded by the third wiring layer 9 and the fourth wiring layer 11. A schematic diagram of the silicon interposer 1 integrating the electromagnetic material 10 is shown below. Figure 5 As shown.

[0027] Finally, through reflow, tiny and uniform solder balls 12 are precisely implanted into the surface of the fourth wiring layer 11 to establish a solid electrical connection, completing the solder ball implantation process. This forms a layer resembling... Figure 1 The fan-out inductor package structure is shown. The fan-out inductor packaging structure disclosed in this utility model achieves precise stacking and efficient interconnection of multiple chips in three-dimensional space through a silicon interposer 1 with through-silicon vias 101 and a three-dimensional stacked packaging structure, while also integrating an inductor structure. The vertical stacking not only greatly expands the chip capacity but also significantly shortens the signal transmission path through the placement of conductive metal pillars 6, thereby effectively improving data processing speed and overall system performance. Simultaneously, this stacking method optimizes circuit layout, resulting in an unprecedented increase in integration density.

[0028] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A fan-out inductor package structure, characterized by, include: A silicon interposer has a front side and a back side. The front side has a first wiring layer and the back side has a second wiring layer. The silicon interposer has a plurality of through-silicon vias, which connect the first wiring layer and the second wiring layer. The first functional chip is integrated on the front side of the silicon interposer and is electrically connected to the first redistribution layer. The second functional chip is integrated on the back of the silicon interposer and is electrically connected to the second redistribution layer. A conductive metal pillar is disposed on the front side of the silicon interposer. The bottom surface of the conductive metal pillar is electrically connected to the first superwiring layer and is electrically connected to the second superwiring layer through a through-silicon via. The first molding compound is located on the front side of the silicon interposer and covers the first functional chip, the conductive metal pillar and the first redistribution layer, exposing the top surface of the conductive metal pillar. The second molding compound is located on the back side of the silicon interposer and encapsulates the second functional chip and the second wiring layer. The third wiring layer is located on the top surface of the first encapsulation part and is electrically connected to the conductive metal pillar; after electromagnetic material is placed on the surface of the third wiring layer, a fourth wiring layer is placed; the third and fourth wiring layers completely surround the electromagnetic material.

2. The fan-out inductor package structure of claim 1, wherein, Micro pads are provided on the first and second wiring layers respectively.

3. The fan-out inductor package structure of claim 2, wherein, The height of the conductive metal pillar is greater than the height of the first functional chip.

4. The fan-out inductor package structure of claim 3, wherein, An underfill adhesive is provided between the first functional chip and the front side of the silicon interposer, and an underfill adhesive is also provided between the second functional chip and the back side of the silicon interposer.

5. The fan-out inductor package structure of claim 4, wherein, The first functional chip and the second functional chip are each provided in multiple forms.

6. The fan-out inductor package structure of claim 5, wherein, The electromagnetic material is NiFe.

7. The fan-out inductor package structure of claim 6, wherein, The fourth wiring layer has solder balls on its surface for connection with external circuits.

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