A chip package structure with side pads

Abstract

This utility model relates to the field of chip packaging technology and discloses a chip packaging structure with side pads, including a substrate and a bare die. The bottom edge of the substrate has multiple pad grooves arranged at intervals along the edge of the substrate. The side of each pad groove away from the substrate is open. The depth of the pad groove is less than the thickness of the substrate. Side pads are plated within the pad grooves. The bottom of each side pad has a pad hole, which is open on the side away from the substrate. The top surface of the substrate has a circuit pattern with substrate pads on the circuit pattern. The bare die is fixed to the top of the substrate, and the pads of the bare die are connected to the substrate pads via gold wires. The side pads on the side of the substrate of this utility model are less prone to oxidation, resulting in high solder climb height and high reliability during soldering.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, and in particular to a chip packaging structure with side pads. Background Technology

[0002] Currently, chip packaging is a crucial link in the semiconductor industry chain, responsible for transforming bare dies after wafer dicing into finished chips applicable to electronic devices through a series of processes. Its core objectives are to protect the chip, achieve electrical connections, manage heat, and adapt the chip to different application environments, such as mobile phones, computers, and servers. Common chip packaging methods include QFN (Quad Flat No-leads Package) and LGA (Land Grid Array) packaging. However, in existing LGA package structures, the pads are located on the bottom surface of the substrate, with no pads on the sides. This results in low solder climb height and low reliability when the substrate is soldered onto the PCB. Similarly, in existing LGA packages, the pads are located on the bottom of the substrate, with no pads on the sides, leading to low solder climb height and low reliability when the substrate is soldered onto the PCB. While QFN packages have leads on the sides of the lead frame, these exposed leads are prone to oxidation, preventing proper soldering and resulting in low solder climb height. Neither of these methods can meet the high-precision, high-density packaging requirements of applications such as automotive and consumer electronics. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide a chip packaging structure with side pads on the side of the substrate, which has high solder climbing height and high reliability during soldering.

[0004] To address the aforementioned technical problems, this utility model provides a chip packaging structure with side pads, including a substrate and a bare chip. The substrate has multiple pad grooves at its bottom edge, spaced apart along the edge of the substrate. The side of each pad groove away from the substrate is open. The depth of each pad groove is less than the thickness of the substrate. Side pads are plated within each pad groove. Pad holes are located at the bottom of each side pad, with the side of the pad hole away from the substrate being open. A circuit pattern is provided on the top surface of the substrate, and substrate pads are provided on the circuit pattern. The bare chip is fixed to the top of the substrate, and the pads of the bare chip are connected to the substrate pads via gold wires.

[0005] As a preferred embodiment of the present invention, the bottom of the side pad is provided with a solder pad extending toward the bottom of the substrate.

[0006] As a preferred embodiment of this utility model, there is a gap between two adjacent welding pieces and a solder resist layer is provided.

[0007] As a preferred embodiment of this utility model, the spacing between two adjacent welding pieces is 100μm-150μm.

[0008] As a preferred embodiment of the present invention, the side pad includes a copper layer covering the side pad and a gold layer plated on the copper layer.

[0009] As a preferred embodiment of this utility model, the circuit pattern is provided with surface mount pads, and surface mount devices are fixed on the surface mount pads.

[0010] As a preferred embodiment of this utility model, the thickness of the substrate is 250μm-415μm, and the depth of the pad groove is 150μm-170μm.

[0011] As a preferred embodiment of the present invention, the top of the substrate is covered with a molding compound layer, which encapsulates the bare chip.

[0012] As a preferred embodiment of this utility model, the substrate is covered with a removable protective cover, and the bare chip is disposed inside the protective cover.

[0013] This utility model provides a chip packaging structure with side pads. Compared with the prior art, its advantages are as follows: When the substrate of this chip packaging structure is soldered onto the PCB board, the side of the substrate is provided with side pads and pad holes. The side of the pad holes away from the substrate is open, so the side pads have enough space for solder paste to climb, resulting in a high solder climbing height on the side of the substrate. This solves the problems of difficult soldering on the side and low solder climbing height. The side pads are not easily oxidized, which can meet the requirements of high-density and high-precision packaging. Attached Figure Description

[0014] Figure 1 This is a structural diagram of the present invention;

[0015] Figure 2 This is a structural diagram of the bottom surface of the substrate of this utility model;

[0016] Figure 3 This is a structural diagram of the substrate of this utility model having a plastic sealing layer;

[0017] Figure 4 This is a fracture structure diagram of the present invention when the protective cover is provided;

[0018] In the figure, substrate 1; pad groove 11; side pad 12; copper layer 121; gold layer 122; pad hole 13; solder pad 14; barrier layer 15; bare chip 2; gold wire 21; substrate pad 3; surface mount pad 4; mounted device 5; molding compound 6; protective cover 7. Detailed Implementation

[0019] The specific embodiments of this utility model will be described in further detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate this utility model, but are not intended to limit its scope.

[0020] In the description of this utility model, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] like Figure 1-3 As shown, a preferred embodiment of the present invention provides a chip packaging structure with side pads 12, including a substrate 1 and a bare chip 2. A pad groove 11 is provided at the edge of the bottom surface of the substrate 1. Multiple pad grooves 11 are provided and spaced apart along the edge of the substrate 1. The side of the pad groove 11 away from the substrate 1 is open. Generally, the pad groove 11 is vertically oriented, and the depth of the pad groove 11 is less than the thickness of the substrate 1, meaning the pad groove 11 does not penetrate the substrate 1. Side pads 12 are plated within the pad grooves 11, meaning the side pads 12 are located on the side of the substrate 1. A pad hole 13 is provided at the bottom of the side pad 12. Generally, the pad hole 13 is vertically oriented, and the top of the hole does not penetrate the top of the side pad 12. The side of the pad hole 13 away from the substrate 1 is open. A circuit pattern (not shown in the figure) is provided on the top surface of the substrate 1, and substrate 1 pads are provided on the circuit pattern. The bare chip 2 is fixed to the top of the substrate 1, and the pads of the bare chip 2 are connected to the substrate 1 pads via gold wires 21.

[0022] The manufacturing process of this embodiment is as follows: Step 1: Cut the board to the required size and divide it into multiple substrate 1 areas. Then bake the board to dry the moisture, eliminate stress, prevent warping, and fix the size. Step 2: Drill the substrate 1 areas of the board using mechanical drilling and laser drilling. In addition to machining the required positioning holes and tool holes in the substrate 1 areas, countersunk holes for solder pads that do not penetrate the top surface of the board are also made at the bottom edge of the substrate 1 areas. After drilling, multiple solder pad grooves 11 are provided on both sides of the bottom of the substrate 1 areas, spaced apart along the edge of the substrate 1 areas. In this embodiment, the solder pad grooves 11 are semi-cylindrical. Step 3: Electroplat the entire board after drilling to form side solder pads 12 in the solder pad grooves 11. The shape of the side solder pads 12 is similar to that of the solder pad grooves. Step 11: The shape is appropriate, that is, the bottom of the side pad 12 is provided with pad hole 13, and the side of the pad hole 13 away from the substrate 1 is open; Step 4: Perform pattern transfer processing so that the top surface of the substrate 1 area forms a circuit pattern, wherein the circuit pattern is provided with substrate 1 pads; Step 5: Apply an ink layer to the substrate 1 area, and then open a window at the position corresponding to the pad of the circuit pattern in the ink layer, and then perform anti-oxidation treatment at the window position of the ink layer; Step 6: Fix the bare chip 2 (an independent bare chip 2 separated from the silicon wafer by the dicing process, which serves as the physical carrier of the semiconductor device and carries the complete integrated circuit structure) on the top surface of the substrate 1 area, and connect the pads (I / O pads) of the bare chip 2 to the pads of the substrate 1 through gold wire 21; Step 7: Cut the board along the edge of the substrate 1 area to obtain multiple chip package structures.

[0023] The working principle of this embodiment is as follows: Compared with the traditional LGA package, when the substrate 1 of this chip package structure is soldered on the PCB board, since the side of the substrate 1 is provided with side pads 12 and side pads 12 are provided with pad holes 13, and the side of the pad holes 13 away from the substrate 1 is open, the side pads 12 have enough space for solder paste to climb, so that the solder climbing height on the side of the substrate 1 is high, which solves the problem of difficult soldering on the side and low solder climbing height, improves mechanical connection performance (vibration and shock resistance) and heat dissipation performance, and has better reliability; compared with the traditional QFN package, the side pads 12 are not easy to oxidize, easy to store, and have a long shelf life. The substrate 1 can be a multi-layer design, and the circuit can be more refined, which can meet the high-density and high-precision packaging requirements. In addition, the traditional QFN package can only be connected by solder wire, while the substrate 1 of this embodiment can be used in the SMT process and can package various passive components.

[0024] For example, the bottom of the side pad 12 is provided with a solder tab 14 extending toward the bottom of the substrate 1 to improve the stability of the connection between the bottom of the side pad 12 and the substrate 1.

[0025] For example, there is a gap between two adjacent solder pads 14 and a solder resist layer (green ink) is provided to prevent molten solder paste from forming a "solder bridge" between adjacent pads and avoid short circuits.

[0026] For example, the spacing between two adjacent welded pieces 14 is 100μm-150μm, which makes the structure more compact while ensuring safety.

[0027] For example, the side pad 12 includes a copper layer 121 covered on the side pad 12 and a gold layer 122 plated on the copper layer 121. The properties of gold are relatively stable, which makes the side pad 12 less prone to oxidation.

[0028] For example, the circuit pattern has surface mount pads 4, and surface mount devices 5 (passive components) are fixed on the surface mount pads 4 for easy installation.

[0029] For example, the thickness of substrate 1 is 250μm-415μm, and the depth of pad recess 11 is 150μm-170μm to ensure sufficient solder crawling height.

[0030] For example, a molding compound 6 is provided on the top of the substrate 1, which encapsulates the bare chip 2. Specifically, after the bare chip 2 is mounted on the substrate 1, epoxy resin is used for injection molding on the substrate 1 to form the molding compound 6 that encapsulates the bare chip 2, thereby protecting the bare chip 2 as well as the circuits and devices on the substrate 1.

[0031] In other embodiments, such as Figure 4 As shown, a removable protective cover 7 is provided on the substrate 1, and the bare chip 2 is disposed inside the protective cover 7. The protective cover 7 can protect the bare chip 2 and gold wire 21 and other components on the substrate 1.

[0032] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present utility model, and these improvements and substitutions should also be considered within the protection scope of the present utility model.

Claims

1. A chip package structure with side pads, characterized in that The substrate includes a substrate and a bare die. Multiple pad grooves are provided at the edge of the bottom surface of the substrate and are spaced apart along the edge of the substrate. The side of each pad groove away from the substrate is open. The depth of each pad groove is less than the thickness of the substrate. Side pads are plated within each pad groove. Pad holes are provided at the bottom of each side pad, and the side of each pad hole is open away from the substrate. A circuit pattern is provided on the top surface of the substrate, and substrate pads are provided on the circuit pattern. The bare die is fixed to the top of the substrate, and the pads of the bare die are connected to the substrate pads via gold wires.

2. The chip-on-chip package structure with side-bonding pads of claim 1, wherein: The bottom of the side pad has a solder pad extending toward the bottom of the substrate.

3. The chip-on-chip package structure with side-bonding pads of claim 2, wherein: There is a gap between two adjacent welding pieces and a solder resist layer is provided.

4. The chip package structure with side pads according to claim 3, characterized in that: The spacing between two adjacent weld pieces is 100μm-150μm.

5. The chip-on-chip package structure with side-bonding pads of claim 1, wherein: The side pads include a copper layer covering the side pads and a gold layer plated on the copper layer.

6. The chip-on-chip package structure with side-bonding pads of claim 1, wherein: The circuit pattern has surface mount pads, and surface mount devices are fixed on the surface mount pads.

7. The chip-on-chip package structure with side-bonding pads of claim 1, wherein: The thickness of the substrate is 250μm-415μm, and the depth of the pad groove is 150μm-170μm.

8. The chip-on-chip package structure with side-bonding pads of claim 1, wherein: The substrate is covered with a molding compound layer on top, which encapsulates the bare chip.

9. The chip-on-chip package structure with side-bonding pads of claim 1, wherein: The substrate is covered with a removable protective cover, and the bare chip is disposed inside the protective cover.

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