Semiconductor package

Abstract

This invention provides a semiconductor package comprising an interconnect substrate, a semiconductor die, and an underfill. The semiconductor die is disposed on the interconnect substrate and has a first top surface extending along a first direction. The underfill includes a body portion and an extension portion. The body portion is disposed between the interconnect substrate and the semiconductor die. The extension portion is connected to the body portion, wherein the extension portion is adjacent to the semiconductor die and has a second top surface extending along the first direction.

Description

Technical Field

[0001] This utility model relates to a semiconductor package. Background Technology

[0002] The miniaturization of semiconductor devices and electronic components has made it possible to integrate more devices and components into a given volume, achieving high integration density across a wide range of semiconductor devices and / or electronic components. Currently, integrated circuits are incorporating increasingly more functions, resulting in larger and larger sizes. Utility Model Content

[0003] This invention provides a semiconductor package comprising: an interconnect substrate; a semiconductor die disposed on the interconnect substrate and having a first top surface extending along a first direction; and a bottom filler comprising: a body portion disposed between the interconnect substrate and the semiconductor die; and an extension portion connected to the body portion, wherein the extension portion is adjacent to the semiconductor die and has a second top surface extending along the first direction.

[0004] This invention provides a semiconductor package comprising: an interconnect substrate; a die disposed above and electrically coupled thereto on the interconnect substrate, wherein the die has an upper sidewall and a lower sidewall connected to the upper sidewall; an underfill laterally surrounding the die; and an insulating encapsulator encapsulating the die and the underfill, wherein the upper sidewall of the die extends along a first direction, the lower sidewall of the die has an interface with the insulating encapsulator, and the interface extends along a second direction different from the first direction.

[0005] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0006] The various aspects of the embodiments of this utility model are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 , Figure 3 , Figure 5 , Figure 11 , Figure 17 , Figure 18 and Figure 19 Schematic cross-sectional views are shown of various stages of manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0008] Figure 2 and Figure 20Schematic plan views are shown illustrating various stages of manufacturing a semiconductor package according to some embodiments of this disclosure.

[0009] Figure 4 A schematic enlarged plan view showing the cut lines of a corresponding device region for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0010] Figures 6 to 10 Schematic enlarged cross-sectional views of various embodiments of the semiconductor die and underfill at the cut-out area in the semiconductor package according to this disclosure are shown respectively.

[0011] Figures 12 to 16 Schematic enlarged cross-sectional views of various embodiments of the semiconductor die, underfill, and insulating encapsulator at the cutout region in the semiconductor package according to the present disclosure are shown respectively.

[0012] Figure 21 A schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure is shown.

[0013] Figure 22 A schematic cross-sectional view showing the application of a semiconductor package according to some embodiments of this disclosure.

[0014] Figure 23 A schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure is shown. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components, values, operations, materials, arrangements, or similar elements are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or similar elements are contemplated. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0017] In addition, for ease of explanation, terms such as "first," "second," "third," "fourth," "fifth," "sixth," and "seventh" may be used in this document to describe similar or different components or features illustrated in the figure, and may be used interchangeably depending on the order of their existence or the context of the description.

[0018] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (e.g., those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant art and this disclosure, and shall not be interpreted as having an idealized or overly formal meaning unless expressly defined herein.

[0019] This disclosure may also include other features and processes. For example, test structures may be included to aid in the verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. These test structures may, for example, include test pads formed in redistribution layers or on a substrate to enable testing of 3D packages or 3DIC devices, use of probes and / or probe cards, and similar operations. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with testing methods including intermediate verification of known good dies to improve yield and reduce costs.

[0020] It should be understood that the following embodiments of this disclosure provide applicable concepts that can be embodied in various specific contexts. The embodiments are intended to provide further explanation but are not intended to limit the scope of this disclosure. Specific embodiments described herein relate to a semiconductor package including a semiconductor die disposed on a circuit structure and an underfill filling between the semiconductor die and the circuit structure, wherein the underfill is trimmed to partially or completely detach from the outermost surface of the semiconductor die. In some embodiments of this disclosure, delamination between the trimmed underfill and the underlying circuit structure can be suppressed or eliminated. Furthermore, due to the trimming of the underfill, the underfill formation window is enlarged. The manufacture of such a semiconductor package is compatible with current and / or advanced manufacturing processes.

[0021] In some embodiments, the manufacturing method is part of a wafer-level packaging process. It should be understood that additional processes may be provided before, during, and after the illustrated methods, and only a few other processes may be briefly described herein. In this disclosure, it should be understood that the illustrations of components in all figures are schematic and not drawn to scale. In all the various views and illustrative embodiments of this disclosure, components similar to or substantially identical to those previously illustrated will use the same reference numerals, and certain details or descriptions of the same components (e.g., materials, forming processes, positioning configurations, electrical connections, etc.) will not be repeated. For clarity of illustration, the figures are illustrated using orthogonal axes (X, Y, and Z) of a Cartesian coordinate system, according to which the views are oriented; however, this disclosure is not specifically limited thereto.

[0022] Figure 1 , Figure 3 , Figure 5 , Figure 11 , Figure 17 , Figure 18 and Figure 19 A schematic cross-sectional view is shown of various stages in the manufacture of a semiconductor package SP1 according to some embodiments of this disclosure. Figure 2 and Figure 20 A schematic plan view showing the various stages in manufacturing the semiconductor package SP1 is provided. Figure 1 , Figure 3 , Figure 5 , Figure 11 , Figure 17 , Figure 18 and Figure 19 It is along Figure 2 The cross-section of line AA depicted in the plan view. Figure 4 Shown by Figure 2 The dashed box B in the diagram shows a schematic enlarged plan view of the cutting lines SL1 and SL2 of the corresponding device area DR for manufacturing semiconductor package SP1. Figures 6 to 10 They are shown separately. Figure 5 A schematic enlarged cross-sectional view of the semiconductor die and underfill at the cut-out area in various embodiments of a semiconductor package, which consists of... Figure 5 The dashed box C in the text indicates (for example, Figure 6 The dashed box c1 in the middle Figure 7 The dashed box c2 in the middle Figure 8 The dashed box c3 in the middle Figure 9 The dashed box c4 and / or Figure 10 (dummy box c5 in the text). Figures 12 to 16 They are shown separately. Figure 11 A schematic enlarged cross-sectional view of the semiconductor die, underfill, and insulating encapsulation at the cut-out area in a semiconductor package, representing various embodiments thereof. Figure 11 The dashed box D in the text indicates (for example, Figure 12 The dashed frame d1 in the middle Figure 13 The dashed frame d2 in the middle Figure 14 The virtual box d3 in Figure 15 The dashed frame d4 and / or Figure 16 (d5 in the dashed box).

[0023] refer to Figure 1 and Figure 2 In some embodiments, a semiconductor component 300 is provided. In some embodiments, the semiconductor component 300 is an interposer. In some embodiments, the semiconductor component 300 is an integrated circuit component or a component including a silicon substrate. In some embodiments, the semiconductor component 300 is in the form of a wafer or panel when considered in a top view or plan view along direction Z (e.g., the XY plane). The semiconductor component 300 may be in the form of a wafer size having a diameter of approximately 4 inches or greater. The semiconductor component 300 may be in the form of a wafer size having a diameter of approximately 6 inches or greater. The semiconductor component 300 may be in the form of a wafer size having a diameter of approximately 8 inches or greater. Alternatively, the semiconductor component 300 may be in the form of a wafer size having a diameter of approximately 12 inches or greater. In some embodiments, the semiconductor component 300 includes a device region DR and a peripheral region PR surrounding the device region DR, wherein the device region DR includes a plurality of regions R1 arranged in an array along directions X and Y, wherein each region R1 is positioned (or predetermined) for placing a semiconductor die to be included in a semiconductor package SP1. Directions X, Y, and Z may be different from each other. For example, direction X is perpendicular to direction Y, and directions X and Y are independently perpendicular to direction Z. Figure 1 As shown. In this disclosure, direction Z can be referred to as the stacking or vertical direction, direction X and / or direction Y can be referred to as the lateral or flush direction, and the XY plane defined by direction X and direction Y can be referred to as a plan view or top view.

[0024] In some embodiments, each region R1 includes more than one semiconductor die. For illustrative purposes, as Figure 2 As shown, each region R1 may include four semiconductor dies 100, which may be arranged in a 2×2 array. However, this disclosure is not limited to this, and the number of semiconductor dies in each region R1 may be one, two, three, four or more, depending on the requirements and design specifications. As long as the shape / profile (in the XY plane) of each region R1 remains appropriate (e.g., rectangular or square), it allows the region R1 to be positioned to facilitate subsequent process arrangements.

[0025] In some embodiments, the semiconductor component 300 includes a substrate 310, a plurality of vias 320, a redistribution circuit structure 330, a bonding layer 340, a redistribution circuit structure 350, a bonding layer 360, and a plurality of conductive terminals 370 (see reference). Figure 19 The semiconductor component 300 may include a substrate 310, a plurality of vias 320, a bonding layer 340, a redistribution structure 350, a bonding layer 360, and a plurality of conductive terminals 370. Alternatively, the semiconductor component 300 may include a substrate 310, a plurality of vias 320, a bonding layer 340, a bonding layer 360, and a plurality of conductive terminals 370. Alternatively, the semiconductor component 300 may include a substrate 310, a plurality of vias 320, a bonding layer 340, a bonding layer 360, and a plurality of conductive terminals 370. Alternatively, the semiconductor component 300 may include a substrate 310, a plurality of vias 320, a redistribution structure 330, a bonding layer 340, a bonding layer 360, and a plurality of conductive terminals 370. Alternatively, the bonding layer 340 and / or the bonding layer 360 may be omitted. Alternatively, the conductive terminals 370 may be omitted. The semiconductor component 300 may be referred to as an interconnect substrate or structure or an interconnect substrate or structure.

[0026] In some embodiments, substrate 310 is a wafer, such as a bulk semiconductor substrate, a silicon-on-insulator (SOI) substrate, a multilayer semiconductor substrate, etc. Substrate 310 can be a semiconductor material, such as silicon or germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Alloy SiGe can be formed over a silicon substrate. The SiGe substrate can be strained. In alternative embodiments, other substrates, such as multilayer substrates or gradient substrates, can also be used. Substrate 310 can be doped or undoped. Substrate 310 can include a variety of devices (not shown) (also referred to as semiconductor devices) formed therein. These devices can include active devices, passive devices, or combinations thereof. These devices can include integrated circuit devices. These devices can include transistors, capacitors, resistors, diodes, photodiodes, fuses, jumpers, inductors, or other similar devices. These devices may function as memory, processors, sensors, amplifiers, power distribution, input / output circuitry, etc. Each device may be referred to as a semiconductor component. For example, active and / or passive devices (e.g., transistors, capacitors, resistors, diodes, photodiodes, fuse assemblies, jumpers, inductors, etc.) are formed in substrate 310 and / or on surface S310f of substrate 31. In some embodiments, surface S310f is referred to as the active surface (or front side) of substrate 310. Alternatively, substrate 310 may be substantially devoid of active and passive devices, providing only routing functionality.

[0027] In some embodiments, a via 320 is formed in a substrate 310, extending from a surface S310f of the substrate 310 to a location within the substrate 310, and is not exposed by a surface S310b of the substrate 310, wherein surface S310b is opposite to surface S310f along the stacking direction Z. The via 320 can be formed by forming a plurality of grooves in the substrate 310 (by means of, for example, etching, milling, laser technology, or combinations thereof) and depositing a conductive material in the plurality of grooves. The conductive material can be formed by electrochemical plating processes, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, or the like. An optional thin dielectric layer (not shown) can be formed in the grooves, for example, by using an oxidation technique, to separate the substrate 310 and the via 320. A thin barrier layer (not shown) may be conformally formed in the groove, for example by CVD, ALD, PVD, thermal oxidation, or combinations thereof, to separate the substrate 310 from the optional thin dielectric layer. The thin barrier layer may comprise nitrides or oxides of nitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tungsten nitride, combinations thereof, or the like. Excess conductive material, the thin barrier layer, and the optional thin dielectric layer are removed from the surface S310f of the substrate 310 by, for example, a chemical mechanical polishing (CMP) process. Therefore, the via 320 may comprise conductive material, a thin barrier layer between the conductive material and the substrate 310, and an optional dielectric layer between the thin barrier layer and the substrate 310. Throughout this specification, the term "copper" is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing trace amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

[0028] In some embodiments, the redistribution structure 330 is formed on the surface S310f of the substrate 310 and is electrically connected to the substrate 310. In a particular embodiment, the redistribution structure 330 includes a dielectric structure 332 and one or more metallization layers 334 disposed within the dielectric structure 332 for providing routing functionality. For example, the dielectric structure 332 includes one or more dielectric layers such that the dielectric layers and the metallization layer 334 are formed sequentially, with a metallization layer 334 sandwiched between the two dielectric layers. Figure 1As shown, portions of the top surface of the top layer of metallization layer 334 can be exposed by the top portion of dielectric structure 332 (e.g., the top dielectric layer), and portions of the bottom surface of the bottom layer of metallization layer 334 can be exposed by the bottom portion of dielectric structure 332 (e.g., the bottom dielectric layer). However, this disclosure is not limited to this. For example, the top surface (not shown) of the top layer of metallization layer 334 and the top surface (not shown) of the top dielectric layer of dielectric structure 332 are substantially flush. In this case, the top surface (not shown) of the top layer of metallization layer 334 and the top surface (not shown) of the top dielectric layer of dielectric structure 332 can be substantially coplanar. On the other hand, for example, the bottom surface (not shown) of the bottom layer of metallization layer 334 and the bottom surface (not shown) of the bottom dielectric layer of dielectric structure 332 are substantially flush. In this case, the bottom surface (not shown) of the lowest layer of metallization layer 334 can be substantially coplanar with the bottom surface (not shown) of the lowest dielectric layer of dielectric structure 332.

[0029] The dielectric structure 332 may be made of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable dielectric material, and may be formed by deposition or the like. The metallization layer 334 may be or include a patterned copper layer or other suitable patterned metal layer, and may be formed by electroplating or deposition. However, this disclosure is not limited thereto. Alternatively, the metallization layer 334 may be formed by a single damascene or a double damascene method. The number of metallization and dielectric layers included in the redistribution structure 330 is not limited thereto and may be specified and selected according to requirements and design layout.

[0030] The vias 320 can be connected to portions of the bottom surface of the metallization layer 334 exposed by the bottom dielectric layer of the dielectric structure 332, as shown. Figure 1 As shown. In other words, the redistribution wiring structure 330 is electrically connected to the via 320. The redistribution wiring structure 330 can also be electrically connected, through direct contact therebetween, to active and / or passive devices embedded in or formed on the surface S310f of the substrate 310 (if any). In some embodiments, via the redistribution wiring structure 330, the via 320 is electrically coupled to the substrate 310 and / or active and / or passive devices embedded in or formed on the surface S310f of the substrate 310 (if any).

[0031] In some embodiments, a bonding layer 340 is formed on a redistributed circuit structure 330, wherein the redistributed circuit structure 330 is disposed between the bonding layer 340 and the substrate 310. For example, the bonding layer 340 includes a dielectric layer 342 and a plurality of connection pads 344 disposed in the dielectric layer 342, wherein the connection pads 344 are electrically connected to the redistributed circuit structure 330 through direct contact with the metallization layer 334. For example, as... Figure 1 As shown, the connector pad 344 penetrates and is laterally covered by the dielectric layer 342, wherein the top surface (not shown) of the connector pad 344 is exposed in an accessible manner by the dielectric layer 342. The bonding layer 340, which includes the dielectric layer 342 and the connector pad 344, may be referred to as a bonding structure, a connection layer, or a connection structure of the semiconductor component 300. In some embodiments, the top surface of the connector pad 344 is substantially flush with the top surface (not shown) of the dielectric layer 342. In other words, the top surface of the connector pad 344 and the top surface of the dielectric layer 342 are substantially coplanar. In this disclosure, the top surface of the connector pad 344 and the top surface of the dielectric layer 342 may sometimes together form the front or outermost surface of the semiconductor component 300 for connection to another component (e.g., semiconductor die 100).

[0032] An optional seed layer (not shown) may be formed before forming the connector pad 344 and after forming the dielectric layer 342 to facilitate the formation of the connector pad 344. In some embodiments, the bonding layer 340 may be formed by, but not limited to, the following: forming a blanket layer of dielectric material over the redistributed circuit structure 330; patterning the blanket layer of dielectric material to form a dielectric layer 342 having a plurality of openings (not shown) penetrating the dielectric layer 342 and exposing the exposed portion of the top surface of the top layer of the metallization layer 334 in an accessible manner; optionally forming a blanket layer of seed material over the dielectric layer 342, the blanket layer of seed material extending into the openings to pad the openings and contacting the exposed portion of the top surface of the top layer of the metallization layer 334; forming a blanket layer of conductive material over the blanket layer of seed material and filling the openings; patterning the blanket layer of conductive material to form a plurality of connection pads 344; using the connection pads 344 as an etching mask to pattern the blanket layer of seed material and form corresponding optional seed layers, thereby forming the bonding layer 340. In some embodiments, the optional seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the optional seed layer comprises a titanium layer and a copper layer above the titanium layer, or two titanium layers and a copper layer sandwiched between the two titanium layers. The optional seed layer can be formed using, for example, sputtering. Similarly, if desired, an optional seed layer (not shown) may be employed to facilitate the formation of the metallization layer 334. This disclosure is not limited thereto.

[0033] continue Figure 1 and Figure 2 In some embodiments, at least one semiconductor die is disposed above the substrate 310 of the semiconductor component 300 within each region R1. For illustrative purposes and for simplicity, Figure 1 Only two semiconductor dies 100 are shown in the image. Figure 2 Only four semiconductor dies 100 are shown. In some embodiments, each semiconductor die 100 includes a semiconductor substrate 110, an interconnect structure 120 disposed on the semiconductor substrate 110, a passivation layer 130 disposed on the interconnect structure 120, and a plurality of vias 140 passing through the passivation layer 130 and disposed on the interconnect structure 120. Figure 1 As shown, the semiconductor substrate 110 has a front surface S110f and a back surface S110b opposite to the front surface S110f. An interconnect structure 120 is located on the front surface S110f of the semiconductor substrate 110, wherein the interconnect structure 120 is sandwiched between the semiconductor substrate 110 and the passivation layer 130, and sandwiched between the semiconductor substrate 110, for example, via 140.

[0034] In some embodiments, the semiconductor substrate 110 is a silicon substrate including active devices (e.g., transistors and / or memory, such as N-type metal-oxide-semiconductor (NMOS) and / or P-type metal-oxide-semiconductor (PMOS) components, etc.) and / or passive devices (e.g., resistors, capacitors, inductors, etc.) formed therein. In some embodiments, such active and passive devices are formed in a front-end-of-line (FEOL) process. In alternative embodiments, the semiconductor substrate 110 is a bulk silicon substrate (e.g., a single-crystal bulk silicon substrate), a doped silicon substrate, an undoped silicon substrate, or an SOI substrate, wherein the dopant of the doped silicon substrate may be an N-type dopant, a P-type dopant, or a combination thereof. This disclosure is not limited thereto. Alternatively, the semiconductor substrate 110 may comprise other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. For example, the semiconductor substrate 110 has an active surface, sometimes referred to as the top side (e.g., the front surface S110f), and a non-active surface, sometimes referred to as the bottom side (e.g., the back surface S110b).

[0035] In some embodiments, the interconnect structure 120 includes one or more alternately stacked interlayer dielectric layers 122 and one or more patterned conductive layers 124. For example, the interlayer dielectric layer 122 is a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials, and is formed by methods such as deposition. For example, the patterned conductive layer 124 is a patterned copper layer or other suitable patterned metal layer, and is formed by electroplating or deposition. However, this disclosure is not limited thereto. Alternatively, the patterned conductive layer 124 can be formed by a single damascene method or a double damascene method. The number of interlayer dielectric layers 122 and the number of patterned conductive layers 124 can be less than or more than [number missing]. Figure 1 The quantities shown can be specified and selected according to requirements and / or design layout; this disclosure is not specifically limited thereto. In some embodiments, the interconnect structure 120 is formed in a back-end-of-line (BEOL) process. In one embodiment, as... Figure 1 As shown, a patterned conductive layer 124 is sandwiched between interlayer dielectric layers 122, wherein the surface of the outermost layer of the patterned conductive layer 124 is at least partially exposed by the outermost layer of the interlayer dielectric layer 122 to connect to subsequently formed components for electrical connection (e.g., with via 140); the surface of the innermost layer of the patterned conductive layer 124 is at least partially exposed by the innermost layer of the interlayer dielectric layer 122 and is electrically connected to active devices and / or passive devices included in the semiconductor substrate 110.

[0036] In some embodiments, such as Figure 1 As shown, a passivation layer 130 is formed on the interconnect structure 120, wherein a portion of the interconnect structure 120 is covered by and in contact with the passivation layer 130, while the remaining portion of the interconnect structure 120 is exposed in an accessible manner by the passivation layer 130. Figure 1 As shown, for example, passivation layer 130 has a substantially planar surface (e.g., outermost surface S130a). In some embodiments, the outermost surface S130a of passivation layer 130 is flat and may have a high degree of flatness and smoothness, which is beneficial for subsequently formed layers / assemblies (e.g., via 140). In some embodiments, passivation layer 130 comprises a polyimide (PI) layer, a polybenzoxazole (PBO) layer, a silicon dioxide-based (inorganic) layer, or other suitable polymer (or organic) layer, and is formed by deposition, etc. This disclosure is not limited thereto. This disclosure does not specifically limit the thickness of passivation layer 130, as long as passivation layer 130 maintains its high degree of flatness and smoothness. In this disclosure, the outermost surface S130a of passivation layer 130 may be referred to as the front (or active) side of semiconductor die 100.

[0037] In some embodiments, via 140 is formed on the interconnect structure 120 and on the semiconductor substrate 110, and the sidewalls of via 140 are at least partially covered by a passivation layer 130. In some embodiments, such as Figure 1 As shown, all vias 140 penetrate the passivation layer 130 to physically contact the surface of the outermost layer of the patterned conductive layer 124 exposed by the outermost layer of the interlayer dielectric layer 122. The vias 140 are electrically connected to active and / or passive devices included in the semiconductor substrate 110 via interconnect structures 120. In some embodiments, the vias 140 physically contacting the interconnect structure 120 extend away from the outermost surface S130a of the passivation layer 130. For simplicity, Figure 1 Only five vias 140 are shown in the semiconductor die 100 for illustration purposes, but it should be noted that more than five vias 140 can be formed; this disclosure is not limited to this.

[0038] In some embodiments, the via 140 is formed by photolithography, electroplating, photomask lift-off, or any other suitable method. Electroplating processes may include electroplating, electroless plating, or similar processes. For example, the via 140 may be formed by, but not limited to, forming a mask pattern (not shown) covering the passivation layer 130 and having a plurality of openings (not shown) corresponding to the surface of the outermost layer of the patterned conductive layer 124 exposed by the outermost layer of the interlayer dielectric layer 122; patterning the passivation layer 130 to form a plurality of contact openings (not shown) therein to expose the surface of the outermost layer of the patterned conductive layer 124 exposed by the outermost layer of the interlayer dielectric layer 122; forming a metal material by electroplating or deposition to fill the openings formed in the mask pattern and the contact openings formed in the passivation layer 130 to form the via 140; and then removing the mask pattern. The passivation layer 130 may be patterned by etching processes such as dry etching, wet etching, or combinations thereof. The mask pattern can be removed by an acceptable ashing process and / or photoresist stripping process, such as using oxygen plasma. In one embodiment, the via 140 is made of a metallic material such as copper or a copper alloy.

[0039] In some embodiments, the via 140 can be independently circular, elliptical, triangular, or similar in shape, in the vertical projection of the (stacked) direction Z of the semiconductor substrate 110, the interconnect structure 120, and the passivation layer 130 onto the front surface S110f of the semiconductor substrate 110. This disclosure does not limit the shape of the via 140. The shape and number of vias 140 can be specified and selected based on requirements and design layout, and can be adjusted by changing the shape and number of contact openings formed in the passivation layer 130.

[0040] Alternatively, the via 140 may be formed by, but not limited to, the following: forming a first mask pattern (not shown) covering the passivation layer 130, the first mask pattern having a plurality of first openings (not shown) corresponding to the surface of the outermost layer of the patterned conductive layer 124 exposed by the outermost layer of the interlayer dielectric layer 122; patterning the passivation layer 130 to form a plurality of contact openings (not shown) therein to expose the surface of the outermost layer of the patterned conductive layer 124 exposed by the outermost layer of the interlayer dielectric layer 122; removing the first mask pattern; conformally forming a metal seed layer over the passivation layer 130; forming a second mask pattern (not shown) covering the metal seed layer, wherein the second mask pattern has a plurality of second openings (not shown) to expose the contact openings formed in the passivation layer 130; forming a metal material by electroplating or deposition to fill the second openings formed in the second mask pattern and the contact openings formed in the passivation layer 130; removing the second mask pattern; and then removing the metal seed layer not covered by the metal material to form the via 140.

[0041] In some embodiments, the metal seed layer is referred to as a metal layer, which may comprise a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the metal seed layer includes titanium, copper, molybdenum, tungsten, titanium nitride, titanium-tungsten, combinations thereof, etc. For example, the metal seed layer may include a titanium layer and a copper layer above the titanium layer. The metal seed layer may be formed using, for example, sputtering, PVD, etc.

[0042] In some embodiments, the semiconductor die 100 further includes a sealing ring 150 embedded in the interconnect structure 120 to surround the patterned conductive layer 124 within the interlayer dielectric layer 122. Due to the sealing ring 150, the interconnect structure 120 (e.g., between the interlayer dielectric layer 122 and the patterned conductive layer 124) is protected from physical damage and / or exposure to moisture or hydrogen in the environment.

[0043] In some embodiments, for each semiconductor die 100, the sidewalls of the semiconductor substrate 110, the sidewalls of the interconnect structure 120, and the sidewalls of the passivation layer 130 are substantially aligned with each other in the Z direction and together form the sidewall SW100 of the semiconductor die 100. For example, the outermost surface of the illustrated via 140 (e.g., not flush with) protrudes away from the outermost surface S130a of the passivation layer 130, as shown. Figure 1 As shown. Alternatively, the outermost surface of the shown via 140 may be substantially flush with and substantially coplanar with the outermost surface S130a of the passivation layer 130.

[0044] It should be understood that, in some embodiments, the semiconductor die 100 described independently herein may be referred to as a semiconductor chip or an integrated circuit (IC). In some embodiments, the semiconductor die 100 is independently a logic chip (e.g., a central processing unit (CPU), graphics processing unit (GPU), neural network processing unit (NPU), deep learning processing unit (DPU), tensor processing unit (TPU), system-on-a-chip (SoC), application processor (AP), integrated circuit system (SoC), and microcontroller); a power management chip (e.g., a power management integrated circuit (PMIC) chip); a wireless and radio frequency (RF) chip; a baseband (BB) chip; a sensor chip (e.g., a photo / image sensor chip); a microelectromechanical system (MEMS) chip; a signal processing chip (e.g., a digital signal processing (DSP) chip); a front-end die (e.g., an analog front-end (AFE) chip); a application-specific chip (e.g., an application-specific integrated circuit (ASIC)); a field-programmable gate array (FPGA); a combination thereof; any suitable logic circuit; or the like. The semiconductor die 100 may independently be or include a digital chip, an analog chip, or a mixed-signal chip. Semiconductor die 100 can be a chip or a combined IC, such as a WiFi chip that includes both RF and digital chips.

[0045] In alternative embodiments, each of the semiconductor dies 100 independently includes a memory chip (e.g., a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a synchronous dynamic random access memory (SDRAM), a resistive random access memory (RRAM) chip, a magnetoresistive random access memory (MRAM) chip, a NAND flash memory, a wide I / O memory (WIO) chip, a high bandwidth memory (HBM) chip, or the like), which may or may not have a controller. In alternative embodiments, the semiconductor die 100 is independently an artificial intelligence (AI) engine, such as an AI accelerator; an AI server, a high-performance computing (HPC) system, a high-power computing device, a cloud computing system, a network system, an edge computing system, an immersive memory computing system (ImMC), a SoIC system, etc.; combinations thereof; or the like. In other alternative embodiments, the high-power semiconductor die 100 may independently be an electrical and / or optical input / output (I / O) interface chip, an integrated passive device (IPD) chip, a voltage regulator (VR) chip, a local silicon interconnect (LSI) chip (with or without deep trench capacitor (DTC) features), or a local silicon interconnect chip with multi-layer functions (e.g., electrical and / or optical network circuit interfaces, IPD, VR, DTC, etc.). The type of semiconductor die 100 may be independently selected and specified according to requirements and design specifications, and this disclosure does not impose specific limitations on it.

[0046] In some embodiments, all semiconductor dies 100 are of the same type. In alternative embodiments, some of the semiconductor dies 100 are of different types, while some of the semiconductor dies 100 are of the same type. In further alternative embodiments, all semiconductor dies 100 are of different types. In some embodiments, all semiconductor dies 100 are of the same size. In alternative embodiments, some of the semiconductor dies 100 are of different dimensions, while some of the semiconductor dies 100 are of the same size. In further alternative embodiments, all semiconductor dies 100 are of different dimensions. In some embodiments, all semiconductor dies 100 are of the same shape. In alternative embodiments, some of the semiconductor dies 100 are of different shapes, while some of the semiconductor dies 100 are of the same shape. In another alternative embodiment, all semiconductor dies 100 are of different shapes. The type, size, and shape of each semiconductor die 100 are independent of each other and can be selected and specified according to requirements and design layout, and this disclosure is not limited thereto.

[0047] like Figure 1 and Figure 2 As shown, the semiconductor die 100 can be bonded to the semiconductor assembly 300. For example, the semiconductor die 100 is picked up and placed on the semiconductor assembly 300, and bonded to the semiconductor assembly 300 by flip-chip bonding. For example, some of the connection pads 344 and vias 140 are connected via a plurality of solder areas 200 to bond the semiconductor die 100 to the semiconductor assembly 300. In some embodiments, the semiconductor die 100 is electrically coupled to and connected to the semiconductor assembly 300 through the solder areas 200. The solder may contain lead or lead-free solder, and may contain Sn-Ag, Sn-Cu, Sn-Ag-Cu, etc. The solder areas 200 may be referred to as connectors, conductive connectors, or conductive components.

[0048] In some embodiments, for each region R1, the underfill 400 at least fills the gap between the semiconductor die 100 and the semiconductor component 300 (e.g., the bonding layer 340) and covers the sidewalls of the via 140 and the sidewalls of the solder region 200. The solder region 200 and the connection pad 140 protruding from the passivation layer 130 of the semiconductor die 100 are covered (e.g., in physical contact with) by the underfill 400. In some embodiments, the underfill 400 filling the gap between the semiconductor die 100 and the redistributed wiring structure 330 in one region R1 is not connected to another underfill 400 filling the gap between the semiconductor die 100 and the redistributed wiring structure 330 in another region R1, such as... Figure 2 and combined Figure 4 As shown. Figure 1As shown, the sidewall SW100 of the semiconductor die 100 is at least partially covered by an underfill 400, wherein the underfill 400 in contact with the sidewall SW100 of the semiconductor die 100 at the periphery of region R1 has a triangular portion. This triangular portion of the underfill 400 near the periphery of region R1 and at the sidewall SW100 can be referred to as an underfill fillet. The underfill 400 can be any acceptable material, such as polymers, epoxy resins, molded underfills, etc. The underfill 400 can be formed by underfill dispensing, capillary flow processes, or any other suitable method. The underfill 400 improves the bonding strength between the semiconductor die 100 and the semiconductor assembly 300. For example, the underfill 400 in each region R1 has a first surface S400b in contact with the semiconductor component 300, a second surface S400t opposite to the first surface S400b, and a third surface SW400 extending (e.g., connected) from the first surface S400b to the second surface S400t. Figure 1 As shown, the third surface SW400 can be positioned at the sidewall SW100 of the semiconductor die 100 located on the periphery of each region R1, and the second surface S400t can be substantially flush with the back surface 110b of the semiconductor die 100.

[0049] refer to Figures 3 to 5 In some embodiments, along the cutting lines SL1 and SL2... Figure 1 The structure undergoes a pre-cutting process, in which the underfill 400 is partially removed. For example, in each region R1, at least the underfill 400 is pre-cut to partially remove the underfill 400 disposed on the sidewall SW100 of the semiconductor die 100 surrounding each region R1. That is, the triangular portion of the underfill 400 disposed on the sidewall SW100 of the semiconductor die 100 near the periphery of each region R1 can be removed from the sidewall SW100 of the semiconductor die 100 surrounding each region R1, such as... Figure 5 As shown. The pre-cutting process can include a finishing process performed by direct blade cutting. For example, the pre-cutting process is a mechanical cutting process performed with blade 60, which includes a blade body and a plurality of diamond particles distributed on the outer surface of the blade body, wherein the outer surface of the blade body is configured to contact the object to be cut during the pre-cutting process. The lateral dimension W60 (referred to as the blade width) of the blade 60 (e.g., the blade body) can be approximately from 300 μm to 1000 μm, but other suitable blade widths may optionally be utilized. That is, the pre-cutting process can be a contact cutting process. In some embodiments, the pre-cutting process stops at the underfill 400. In other words, for example, the pre-cutting process does not cut through the underfill 400, such as... Figure 3 and Figure 5 As shown. Due to the removal of the underfill filler rounded corners (e.g., the triangular portion of underfill 400), stress accumulation at the location can be reduced, thereby suppressing or eliminating delamination between the underfill (e.g., the trimmed underfill 400) and the underlying circuit structure (e.g., semiconductor component 300) near the periphery of region R1. Additionally, the underfill formation window is enlarged due to the pre-cutting process. In some embodiments, the pre-cutting process includes a single cutting process. As... Figure 3 and Figure 5 Combination Figure 4 As shown, after the pre-cutting process, a plurality of trenches 54 are formed, wherein each trench 54 is defined by two adjacent dicing lines (corresponding to different regions R1). For example, the trenches 54 are in the form of a grid. In some embodiments, during the removal of the underfill filler rounded corners, the sidewalls SW100 of the semiconductor die 100 that are in contact with the underfill filler rounded corners to be removed are also slightly removed, wherein the sidewalls SW100 of the semiconductor die 100 undergoing the removal process may be referred to below as the patterned sidewalls SW100' of the semiconductor die 100. In this disclosure, for illustrative purposes, the patterned sidewalls SW100' of the semiconductor die 100 may be... Figures 6 to 10 (also Figures 12 to 16 In a magnified view, it can be shown in more detail as patterned sidewalls SW100A, SW100B, SW100C, or SW100D. The surface S400 of the bottom filler 400 is... Figures 6 to 10 (also Figures 12 to 16 The surface S400A or surface S400B can be shown in more detail in the enlarged view; however, this disclosure is not limited thereto.

[0050] In some embodiments, such as Figure 4 As shown, in the vertical projection within each region R1, the lateral dimension D1 (as measured in the Y direction) between two directly adjacent semiconductor dies 100 can range from approximately 20 μm to 150 μm, but other suitable lateral dimensions can be used alternatively. Figure 4 As shown, in the vertical projection within each region R1, the lateral dimension D2 (as measured in direction X) between two adjacent semiconductor dies 100 can range from approximately 20 μm to 150 μm, but other suitable lateral dimensions can be used alternatively. On the other hand, as Figure 4 As shown, in the vertical projection on the semiconductor component 300, the lateral dimension D3 between two adjacent regions R1 (as measured in the Y direction) can range from approximately 1500 μm to 3000 μm, but can also be other suitable lateral dimensions. Figure 4As shown, in the vertical projection on the semiconductor component 300, the lateral dimension D4 between two adjacent regions R1 (measured in direction X) can range from approximately 1500 μm to 3000 μm, but other suitable lateral dimensions can be used alternatively. For example, in the pre-dicing process, as the underfill filler rounded corners are removed, a portion of the semiconductor die 100 is also removed because the blade 60 may overlap with the semiconductor die 100 along dicing lines SL1 and / or SL2. During the pre-dicing process, the patterned conductive layer 124 of the interconnect structure 120 remains protected by the sealing ring 150. Figure 5 As shown, for example, after a pre-cutting process, the underfill 400 in each region R1 has a first surface S400b in contact with the semiconductor component 300, a second surface S400t opposite to the first surface S400b and substantially coplanar with the back surface S110b of the semiconductor die 100, a surface S400 opposite to the first surface S400b and extending laterally to (e.g., joining) the patterned sidewall of the semiconductor die 100, a third surface SW400 continuously extending from (e.g., connecting) the first surface S400b to the surface S400, a vertically extending surface (not shown) connected to the second surface S400t and substantially aligned with the patterned sidewall of the semiconductor die 100, and a laterally extending surface (not shown) connected to the vertically extending surface and the third surface SW400 and substantially aligned with the surface S400, wherein the third surface SW400 connects the laterally extending surface and the first surface S400b. In some embodiments, in direction Z, the distance between the first surface S400b and the second surface S400t is greater than the distance between the first surface S400b and surface S400. In some embodiments, in a cross-sectional view along direction Z, the vertically extending surface is sandwiched between two adjacent patterned sidewalls. In some embodiments, in a top view (e.g., XY plane), the laterally extending surface is sandwiched between two adjacent portions (or portions) of surface S400 of the bottom filler 400.

[0051] In some embodiments, combined with Figures 3 to 5 During the pre-cutting process, the lateral removal length L of the semiconductor die 100 (measured along the X or Y direction, such as...) Figure 3 (As shown) less than or substantially equal to 1.5% of the total thickness of the semiconductor die 100, the vertical cut depth d (measured along direction Z, such as...) Figure 5The thickness of the semiconductor die 100 (as shown) is greater than or substantially equal to 75% of the total thickness of the semiconductor die 100. In a non-limiting example, the total thickness of the semiconductor die 100 may be 750 μm. The lateral removal length L may be referred to as the cutting length of the semiconductor die 100, and the vertical cutting depth d may be referred to as the cutting depth of the cutting step performed in the pre-cutting process. Due to the vertical cutting depth d, delamination caused by stress accumulation due to the underfill (e.g., untrimmed underfill 400) can be suppressed or eliminated.

[0052] like Figure 4 and Figure 5 As shown, an underfill 400 is disposed between the semiconductor die 100 and the semiconductor assembly 300, and further extends to surround the edge of the semiconductor die 100. A portion P1 of the underfill 400 located within region R1 and not pre-cut has a surface S400t, a portion P2 of the underfill 400 located outside region R1 and pre-cut has a surface S400, and a portion P3 of the underfill 400 is disposed between the semiconductor die 100 and the semiconductor assembly 300. For example, portion P2 connects to and surrounds (e.g., continuously surrounds) portion P1, and portion P3 connects to portions P1 and P2. The first portion P1 can be in the form of a grid or a mesh. On the other hand, the second portion P2 can be in the form of a continuous frame. For each region R1, portion P1 can be referred to as an inner extension or branch portion of the underfill 400, portion P2 can be referred to as an outer extension, extension portion, extension portion, peripheral portion, or edge portion of the underfill 400, and portion P3 can be referred to as a central portion or main body portion of the underfill 400. like Figure 4 As shown, for example, portions P1, P2, and P3 of the underfill 400 are integral. In some embodiments, portions P1 and P2 in each region R1 do not overlap with the semiconductor die 100. For example, portion P1 is disposed between the semiconductor dies 100 in each region R1, and portion P2 is disposed along the edge of the semiconductor die 100 in each region R1. In some embodiments, along the Z direction, the maximum height H1 of portion P1 is greater than the maximum height H2 of portion P2.

[0053] As a non-restrictive example, such as Figure 5 and Figure 6 As shown, a pre-cutting process is performed along cutting lines SL1 and SL2, resulting in multiple grooves 54 ( Figure 5 The combination shown in the dashed box Figure 4The trench 54 is formed by removing a portion of the semiconductor die 100 and a portion of the underfill 400 in each region R1. After forming the trench 54, the semiconductor die 100 (pre-cut) disposed around each region R1 has a patterned sidewall SW100A, which includes a surface S1 and a surface S2 connected to the surface S1. The underfill 400 has a surface S400A opposite to the first surface S400b and connected to the third surface SW400. Surface S400A includes a surface S6, which abuts against surface S2 and the outermost surface S130a. Figure 5 and Figure 6 As shown, for example. In some embodiments, surface S1 is a planar surface, such as a substantially perpendicular plane. In some embodiments, surface S2 is a non-planar surface, such as a curved surface with a radius of curvature in the range of approximately 0.5 μm to 5.0 μm. In some embodiments, surface S6 is a planar surface, such as a substantially horizontal plane. Figure 6 As shown, the outermost surface S130a of the semiconductor die 100 (e.g., a passivation layer) can be physically connected to the surface S2 of the patterned sidewall SW100A and contact (e.g., covered by) the underfill 400, wherein the surface S2 can be physically connected and continuously extended between the surface S1 and the outermost surface S130a, and the surface S1 can be physically connected and continuously extended between the surface S2 and the back surface S110b. For example, a portion of the semiconductor die 100 with the patterned sidewall SW100A on the surface S1 has a first lateral dimension, and a portion of the semiconductor die 100 with the patterned sidewall SW100A on the surface S2 has a second lateral dimension, wherein the first lateral dimension is substantially constant, and the second lateral dimension gradually tapers from the outermost surface S130a to the back surface S110b. Figure 6 As shown, surface S2 can extend continuously between surface S1 and surface S6. In some embodiments, surface S6 is substantially flush with the outermost surface S130a. In other words, surface S6 can be substantially coplanar with the outermost surface S130a, as... Figure 6 As shown.

[0054] As a non-restrictive example, such as Figure 5 and Figure 7 As shown, a pre-cutting process is performed along cutting lines SL1 and SL2, resulting in multiple grooves 54 ( Figure 5 The combination shown in the dashed box Figure 4The trench 54 is formed by removing a portion of the semiconductor die 100 and a portion of the underfill 400 in each region R1. After forming the trench 54, the semiconductor die 100 (pre-cut) disposed around each region R1 has a patterned sidewall SW100B, the patterned sidewall SW100B including a surface S1, a surface S2 connected to surface S1, a surface S3 connected to surface S2, and a surface S4 connected to surface S3, wherein the underfill 400m has a surface S400A opposite to the first surface S400b and connected to the third surface SW400, the surface S400A including a surface S6, the surface S6 abutting against surfaces S3 and S4, as shown. Figure 5 and Figure 7 As shown, for example. In some embodiments, surface S1 is a planar surface, such as a substantially vertical plane. In some embodiments, surface S2 is a non-planar surface, such as a curved surface with a radius of curvature in the range of approximately 0.5 μm to 5.0 μm. In some embodiments, surface S3 is a planar surface, such as a substantially horizontal plane. In some embodiments, surface S4 is a planar surface, such as a substantially vertical plane. In some embodiments, surface S6 is a planar surface, such as a substantially horizontal plane. Figure 7 As shown, the outermost surface S130a of the semiconductor die 100 (e.g., a passivation layer) can be physically connected to surface S4 of the patterned sidewall SW100B and contact with (e.g., covered by) the underfill 400. Surface S4 can be physically connected to and extend continuously between the outermost surface S130a and surface S3, and contact with (e.g., covered by) the underfill 400. Surface S3 can be physically connected to and extend continuously between surfaces S2 and S4. Surface S2 can be physically connected to and extend continuously between surfaces S1 and S3. Surface S1 can be physically connected to and extend continuously between the back surface S110b and surface S2. For example, a portion of surface S1 of semiconductor die 100 having patterned sidewalls SW100B has a first lateral dimension, a portion of surface S2 of semiconductor die 100 having patterned sidewalls SW100B has a second lateral dimension, and a portion of surface S4 of semiconductor die 100 having patterned sidewalls SW100B has a third lateral dimension, wherein the first lateral dimension is substantially constant, the second lateral dimension gradually tapers from surface S3 towards the back surface S110b, and the third lateral dimension is substantially constant and larger than the first lateral dimension of the first portion and the second lateral dimension of the second portion. Figure 7As shown, surface S1 can be recessed from surface S4, and surfaces S2 and 3 can extend continuously between surfaces S1 and S6. In some embodiments, surface S3 is substantially flush with surface S6. In other words, surface S3 can be substantially coplanar with surface S6, as... Figure 7 As shown. In some embodiments, a portion of the semiconductor die 100 extending from surface S2 to surface S4 and having a length corresponding to surface S3 may be referred to as the extension portion P4 of the semiconductor die 100. Figure 7 As shown, the extended portion P4 is plate-shaped and extends along the XY plane.

[0055] As a non-restrictive example, such as Figure 5 and Figure 8 As shown, a pre-cutting process is performed along cutting lines SL1 and SL2, resulting in multiple grooves 54 ( Figure 5 The combination shown in the dashed box Figure 4 The trench 54 is formed by removing a portion of the semiconductor die 100 and a portion of the underfill 400 in each region R1. After forming the trench 54, the semiconductor die 100 (after a pre-cutting process) disposed around each region R1 has a patterned sidewall SW100A, the patterned sidewall SW100A including a surface S1 and a surface S2 connected to the surface S1, wherein the underfill 400 has a surface S400B opposite to the first surface S400b and connected to the third surface SW400, the surface S400B including a surface S5 and a surface S6 connected to the surface S5, wherein the surface S5 abuts against the surface S2 and the outermost surface S130a, as shown. Figure 5 and Figure 8 As shown. In some embodiments, surface S1 is a planar surface, such as a substantially perpendicular plane. In some embodiments, surface S2 is a non-planar surface, such as a curved surface with a radius of curvature ranging from approximately 0.5 μm to 5.0 μm. In some embodiments, surface S5 is a non-planar surface, such as a curved surface with a radius of curvature ranging from approximately 0.5 μm to 5.0 μm. The radius of curvature of surface S2 may be substantially the same as that of surface S5. In some embodiments, surface S6 is a planar surface, such as a substantially horizontal plane. Figure 8 As shown, the outermost surface S130a of the semiconductor die 100 (e.g., a passivation layer) can be physically connected to the surface S2 of the patterned sidewall SW100A and contact with the underfill 400 (e.g., covered by the underfill 400), wherein surface S2 can be physically connected and continuously extended between surface S1 and the outermost surface S130a, and surface S1 can be physically connected and continuously extended between surface S2 and the back surface S110b. On the other hand, in Figure 5 and Figure 8In this configuration, surface S6 can be physically connected to surface S5 and the third surface SW400 and extends continuously between surface S5 and the third surface SW400. For example, a portion of surface S1 of semiconductor die 100 having patterned sidewalls SW100A has a first lateral dimension, and a portion of surface S2 of semiconductor die 100 having patterned sidewalls SW100A has a second lateral dimension, wherein the first lateral dimension is substantially constant, and the second lateral dimension gradually tapers from the outermost surface S130a to the back surface S110b. Figure 8 As shown, surface S2 can extend continuously between surface S1 and surface S5, and surface S5 can extend continuously between surface S2 and surface S6. In some embodiments, surface S6, which does not contact the semiconductor die 100, is located below the outermost surface S130a. In other words, there is a height difference between the outermost surface S130a and surface S6.

[0056] As a non-restrictive example, such as Figure 5 and Figure 9 As shown, a pre-cutting process is performed along cutting lines SL1 and SL2, resulting in multiple grooves 54 ( Figure 5 The combination shown in the dashed box Figure 4 The trench 54 is formed by removing a portion of the semiconductor die 100 and a portion of the underfill 400 in each region R1. After forming the trench 54, the semiconductor die 100 (pre-cut) disposed around each region R1 has a patterned sidewall SW100C, the patterned sidewall SW100C including a surface S1, wherein the underfill 400 has a surface S400B opposite to the first surface S400b and connected to the third surface SW400, the surface S400B including a surface S5 and a surface S6 connected to the surface S5, the surface S5 abutting against the surface S1 and the outermost surface S130a, for example, as Figure 5 and Figure 9 As shown. In some embodiments, surface S1 is a planar surface, such as a substantially perpendicular plane. In some embodiments, surface S5 is a non-planar surface, such as a curved surface with a radius of curvature in the range of approximately 0.5 μm to 5.0 μm. In some embodiments, surface S6 is a planar surface, such as a substantially horizontal plane. Figure 9 As shown, the outermost surface S130a of the semiconductor die 100 (e.g., a passivation layer) can be physically connected to the surface S1 of the patterned sidewall SW100C and contact (e.g., be covered by) the underfill 400, wherein the surface S1 can be physically connected to the outermost surface S130a and the back surface S110b and extend continuously therebetween. On the other hand, in Figure 5 and Figure 9In this configuration, surface S6 can be physically connected to surface S5 and third surface SW400 and extends continuously between surface S5 and third surface SW400. For example, a portion of surface S1 of semiconductor die 100 having patterned sidewalls SW100C has a first lateral dimension, wherein the first lateral dimension is substantially constant. Figure 9 As shown, surface S5 can extend continuously between surface S1 and surface S6. In some embodiments, surface S6, which does not contact the semiconductor die 100, is located below the outermost surface S130a. In other words, there is a height difference between the outermost surface S130a and surface S6.

[0057] As a non-restrictive example, such as Figure 5 and Figure 10 As shown, a pre-cutting process is performed along cutting lines SL1 and SL2, resulting in multiple grooves 54 ( Figure 5 The combination shown in the dashed box Figure 4 The trench 54 is formed by removing a portion of the semiconductor die 100 and a portion of the underfill 400 in each region R1. After forming the trench 54, the semiconductor die 100 (pre-cut) disposed around each region R1 has a patterned sidewall SW100D, the patterned sidewall SW100D including a surface S1, a surface S2 connecting to the surface S1, and a surface S4 connected to the surface S2, wherein the underfill 400 has a surface S400B opposite to the first surface S400b and connected to the third surface SW400, the surface S400B including a surface S5 and a surface S6 connected to the surface S5, the surface S5 abutting against the surface S1 and the outermost surface S130a, as shown. Figure 5 and Figure 10 As shown, for example. In some embodiments, surface S1 is a planar surface, such as a substantially vertical plane. In some embodiments, surface S2 is a non-planar surface, such as a curved surface with a radius of curvature ranging from approximately 0.5 μm to 5.0 μm. In some embodiments, surface S4 is a planar surface, such as a substantially vertical plane. In some embodiments, surface S5 is a non-planar surface, such as a curved surface with a radius of curvature ranging from approximately 0.5 μm to 5.0 μm. In some embodiments, surface S6 is a planar surface, such as a substantially horizontal plane. Figure 10 As shown, the outermost surface S130a of the semiconductor die 100 (e.g., a passivation layer) can be physically connected to the surface S4 of the patterned sidewall SW100D and contact with the underfill 400 (e.g., covered by the underfill 400), wherein surface S2 can be physically connected to and continuously extend therebetween surfaces S1 and S4, and surface S4 can be physically connected to and continuously extend between surface S2 and the outermost surface S130a. On the other hand, in Figure 5 and Figure 10In this configuration, surface S6 can be physically connected to surface S5 and third surface SW400 and extends continuously between surface S5 and third surface SW400. For example, a portion of surface S1 of semiconductor die 100 having patterned sidewalls SW100D has a first lateral dimension, wherein the first lateral dimension is substantially constant. Figure 10 As shown, surface S5 can extend continuously between surface S2 and surface S6. In some embodiments, surface S6, which does not contact the semiconductor die 100, is located below the outermost surface S130a. In other words, there is a height difference between the outermost surface S130a and surface S6.

[0058] refer to Figure 11 In some embodiments, an insulating encapsulation 500 is formed over the semiconductor component 300 to cover the semiconductor die 100, the underfill 400, and the semiconductor component 300 exposed therefrom. For example, the insulating encapsulation 500 at least fills the gaps between semiconductor dies 100 disposed in regions R1, the gaps between semiconductor dies 100 disposed between adjacent regions R1, and the gaps between underfill 400 disposed between adjacent regions R1. In some embodiments, the semiconductor die 100 and the underfill 400 are surrounded and covered by the insulating encapsulation 500. Figure 11 As shown, the back surface S110b (e.g., a non-active surface) of the semiconductor die 100 is not exposed in a tangible manner by the surface S500 of the insulating encapsulation 500. However, this disclosure is not limited thereto. In this case, the semiconductor die 100 and the underfill 400 are embedded in and encapsulated by the insulating encapsulation 500, and the semiconductor assembly 300 is covered by the insulating encapsulation 500.

[0059] In some embodiments, the insulating encapsulation 500 is a molding compound formed by a molding process. In some embodiments, the insulating encapsulation 500 includes a polymer (e.g., epoxy resin, phenolic resin, silicone resin, or other suitable resin), a dielectric material, or other suitable material. In alternative embodiments, the insulating encapsulation 500 may include an acceptable insulating encapsulation material. The insulating encapsulation 500 may also include inorganic fillers or inorganic compounds (e.g., silica, clay, etc.) that can be added therein to optimize the coefficient of thermal expansion (CTE) of the insulating encapsulation 500, but this disclosure is not limited thereto. The insulating encapsulation 500 may be referred to as a sealant, a dielectric encapsulation, or an encapsulation. For example, the formation of the insulating encapsulation 500 may include, but is not limited to, overmolding the semiconductor die 100 with an insulating encapsulation material and patterning the insulating encapsulation material to form the insulating encapsulation 500. The insulating encapsulation material may be patterned by a planarization process until a substantially flush and flat surface (e.g., S500) is obtained therefrom. Due to the insulating encapsulation 500, the bonding strength between the semiconductor die 100, the underfill 400 and the semiconductor assembly 300 is further enhanced, and the semiconductor die 100 is protected from damage caused by external contact.

[0060] Planarization processes can be performed, for example, by mechanical polishing, CMP, etching, or a combination thereof. Etching can include dry etching, wet etching, or a combination thereof. Optionally, a cleaning process can be performed after the planarization process to clean and remove any residues generated during the planarization process. However, this disclosure is not limited thereto, and planarization processes can be performed by any other suitable method.

[0061] For example, as the insulating encapsulation 500 is formed, the trench 54 is filled by the insulating encapsulation 500. In some embodiments, the insulating encapsulation 500 covers the back surface S110b of the semiconductor die 100 exposed by the underfill 400 and the patterned sidewalls SW100' (e.g., Figures 12 to 16 The patterned sidewalls SW100A to SW100D depicted in the image have been respectively... Figures 6 to 10 (discussed in the middle), the third surface SW400 and surface S400 of the bottom filler 400 (e.g., Figures 12 to 16 Surfaces S400A to S400B shown have been respectively... Figures 6 to 10 (discussed in the middle), and semiconductor component 300 exposed by semiconductor die 100 and underfill 400.

[0062] refer to Figure 17 In some embodiments, a planarization process is performed to expose the via 320 from the substrate 310. Prior to performing the planarization process, the via 320 can be... Figure 11The structure is flipped (e.g., flipped up and down along the stacking direction Z) and placed on the holding device 50. For example, such as Figure 17 As shown, the surface S500 of the insulating encapsulation 500 is in contact with the holding device 50 to properly secure this structure during the planarization process. For example, the holding device 50 may be an adhesive tape, a carrier film, or a suction cup. This disclosure is not limited thereto. In some embodiments, a portion of the substrate 310 is removed by the planarization process to expose the via 320, such that the surface S310b of the substrate 310 and the surface S320 of the via 320 are substantially flush with each other. In other words, the surface S310b of the substrate 310 and the surface S320 of the via 320 are substantially coplanar with each other. Figure 17 As shown, the surface S320 of the via 320 is exposed in an accessible manner through the surface S310b of the substrate 310. In this disclosure, since the via 320 extends through the substrate 310, the via 320 may be referred to as a substrate via, semiconductor via, or through-silicon-via (TSV) 320 (when the substrate 310 is a silicon substrate).

[0063] In some embodiments, the planarization process may include a polishing process, a CMP process, an etching process, or a combination thereof; however, this disclosure is not limited thereto. After planarization, a cleaning process may be selectively performed, such as cleaning and removing residues generated during the planarization process. However, this disclosure is not limited thereto, and the planarization process may be performed by any other suitable method.

[0064] refer to Figure 18 In some embodiments, the redistribution structure 350 and the bonding layer 360 are sequentially formed on the substrate 310. For example, the redistribution structure 350 is formed on the surface S310b of the substrate 310 and is electrically connected to the substrate 310. In a particular embodiment, the redistribution structure 350 includes a dielectric structure 352 and one or more metallization layers 354 disposed within the dielectric structure 352 for providing routing functionality. For example, the dielectric structure 352 includes one or more dielectric layers such that the dielectric layers and the metallization layer 354 are sequentially formed, with a metallization layer 354 sandwiched between the two dielectric layers. Figure 18As shown, portions of the top surface of the top layer of metallization layer 354 may be exposed by the top portion of dielectric structure 352 (e.g., the top dielectric layer), and portions of the bottom surface of the bottom layer of metallization layer 354 may be exposed by the bottom portion of dielectric structure 352 (e.g., the bottom dielectric layer); however, this disclosure is not limited thereto. For example, the top surface (not shown) of the top layer of metallization layer 354 and the top surface (not shown) of the top dielectric layer of dielectric structure 352 are substantially flush. In this case, the top surface (not shown) of the top layer of metallization layer 354 and the top surface (not shown) of the top dielectric layer of dielectric structure 352 may be substantially coplanar. On the other hand, for example, the bottom surface (not shown) of the bottom layer of metallization layer 354 and the bottom surface (not shown) of the bottom dielectric layer of dielectric structure 352 are substantially flush. In this case, the bottom surface (not shown) of the lowest layer of metallization layer 354 can be substantially coplanar with the bottom surface (not shown) of the lowest dielectric layer of dielectric structure 352. The formation and materials of the redistribution circuit structure 350 (including dielectric structure 352 and metallization layer 354) are as described above. Figure 1 The redistribution circuit structure 330 (including dielectric structure 332 and metallization layer 334) described herein is formed in substantially the same or similar materials, and will not be described further here.

[0065] The vias 320 can be connected to portions of the bottom surface of the metallization layer 354 exposed by the bottom dielectric layer of the dielectric structure 352, as shown. Figure 18 As shown. In other words, the redistributed circuit structure 350 is electrically connected to the via 320. In some embodiments, the redistributed circuit structure 350 is electrically coupled to the redistributed circuit structure 330 through the via 320. In some embodiments, the redistributed circuit structure 350 is electrically coupled to active and / or passive devices (if any) embedded in the substrate 310 or formed on the surface S310f of the substrate 310 through the via 320 and the redistributed circuit structure 330. In some embodiments, the redistributed circuit structure 350 is electrically coupled to the bonding layer 340 through the via 320 and the redistributed circuit structure 330. In some embodiments, the redistributed circuit structure 350 is electrically coupled to the semiconductor die 100 through the via 320, the redistributed circuit structure 330, the bonding layer 340, and the solder region 200.

[0066] In some embodiments, a bonding layer 360 is formed on a redistributed circuit structure 350, wherein the redistributed circuit structure 350 is disposed between the bonding layer 360 and the substrate 310. For example, the bonding layer 360 includes a dielectric layer 362 and a plurality of connection pads 364 disposed in the dielectric layer 362, wherein the connection pads 364 are electrically coupled to the redistributed circuit structure 350 through direct contact with the metallization layer 354. For example, as... Figure 18As shown, the connector pad 364 penetrates and is laterally covered by the dielectric layer 362, wherein the top surface (not shown) of the connector pad 364 is exposed in an accessible manner by the dielectric layer 362. The bonding layer 360, comprising the dielectric layer 362 and the connector pad 364, may be referred to as a bonding structure, connection layer, or connection structure of the semiconductor component 300. In some embodiments, the top surface of the connector pad 364 is substantially flush with the top surface (not shown) of the dielectric layer 362. In other words, the top surface of the connector pad 364 and the top surface of the dielectric layer 362 are substantially coplanar. In this disclosure, the top surface of the connector pad 364 and the top surface of the dielectric layer 362 may sometimes together form the back side or outermost surface of the semiconductor component 300 for connection to another component (e.g., conductive terminal 370).

[0067] continue Figure 18 In some embodiments, conductive terminals 370 are formed over a bonding layer 360, wherein the bonding layer 360 is disposed between the redistribution wiring structure 350 and the conductive terminals 370. The conductive terminals 370 include microbumps, metal pillars, controlled collapse chip connection (C4) bumps (e.g., which may have a size of about 80 μm, but are not limited to), ball grid array (BGA) bumps (e.g., which may have a size of about 400 μm, but are not limited to), bumps formed by electroless nickel-immersion gold technique (ENIG), bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. The conductive terminals 370 may be referred to as connectors, conductive links, or conductive components for external connection to the semiconductor assembly 300. In some embodiments, at least some of the conductive terminals 370 are electrically coupled to the semiconductor die 100 through the bonding layer 360, the redistribution circuit structure 350, the via 320, the redistribution circuit structure 330, the bonding layer 340, and the solder area 200. In some embodiments, at least some of the conductive terminals 370 are electrically coupled to active and / or passive devices (if any) embedded in the substrate 310 or formed on the surface S310f of the substrate 310 through the bonding layer 360, the redistribution circuit structure 350, the via 320, and the redistribution circuit structure 330.

[0068] refer to Figure 19 and Figure 20In some embodiments, a dicing (or unification) process is performed to cut through the insulating enclosure 500 and the semiconductor component 300, thereby forming multiple separate and individual semiconductor packages SP1 having a chip-on-wafer (CoW) structure. The semiconductor package SP1 may be referred to as a CoW package. The dicing (or unification) process may be or includes a wafer dicing process, including mechanical blade sawing or laser cutting. Conductive terminals 370 may be referred to as conductive connectors or input / output (I / O) terminals for each semiconductor package SP1. It is worth noting that... Figure 20 This is a planar schematic diagram before cutting, where the cutting process is carried out along the cutting line SL3.

[0069] Before the cutting process, Figure 18 The structure can be released from holding device 50 and transferred to another holding device (not shown) for fixation during cutting (or simplification) processes. Figure 18 The structure includes a conductive terminal 370 that can be held by another holding device. In some embodiments, a cutting (or unifying) process is performed before releasing the conductive terminal 370 from the other holding device. For example, the other holding device may be an adhesive tape, a carrier film, or a suction cup.

[0070] Figure 21 A schematic cross-sectional view of a semiconductor package (e.g., SP2) according to some alternative embodiments of the present disclosure is shown. Figure 21 Semiconductor package SP2 and Figure 19 Similar to the SP1 semiconductor package, the difference lies in that... Figure 21 In the semiconductor package SP2, the semiconductor die 100 is exposed by the insulating encapsulator 500. Components similar to or substantially the same as those previously described will use the same reference numerals, and certain details or descriptions of the same components (e.g., materials, forming processes, positioning configurations, etc.) will not be repeated here.

[0071] refer to Figure 21 In some embodiments, the back surface S110b (e.g., a non-active surface) of the semiconductor die 100 may be exposed in an accessible manner through the surface S500 of the insulating encapsulation 500. For example... Figure 21 As shown in the semiconductor package SP2, the back surface S110b (e.g., a non-active surface) of the semiconductor die 100 can be substantially flush with the surface S500 of the insulating enclosure 500. In this case, the back surface S110b (e.g., a non-active surface) of the semiconductor die 100 can be substantially coplanar with the surface S500 of the insulating enclosure 500. That is, the semiconductor die 100 is laterally packaged by the insulating enclosure 500. In this case, each of the semiconductor dies 10 is also planarized in a planarization process.

[0072] Semiconductor packages SP1, SP2, or modifications thereof can be further mounted onto another external / attached electronic component, such as onto a circuit structure including a motherboard, package substrate, printed circuit board (PCB), printed circuit board, and / or other carrier capable of carrying integrated circuits. As a non-limiting example, semiconductor packages SP1, SP2, or modifications thereof may be integrated fan-out (InFO) packages, InFO packages with a package-on-package (PoP) structure, chip-on-wafer-on-substrate (CoWoS) packages, flip-chip packages with InFO packages, or similar packages, or may be part of an InFO package, an InFO package with a PoP structure, a CoWoS package, a flip-chip package with InFO packages, or similar packages. This disclosure is not limited thereto.

[0073] Figure 22 A schematic cross-sectional view illustrating the application of semiconductor packages according to some embodiments of this disclosure is shown. Components similar to or substantially the same as those previously described will be referred to using the same reference numerals, and certain details or descriptions of the same components (e.g., materials, forming processes, positioning configurations, etc.) will not be repeated herein.

[0074] refer to Figure 22 In some embodiments, a component assembly SC is provided, comprising a first component C1 and a second component C2 disposed above the first component C1. The first component C1 may be or may contain a circuit structure, such as a motherboard, a package substrate, another PCB, a printed circuit board, an interposer, and / or other carrier capable of hosting an integrated circuit. In some embodiments, the second component C2 mounted on the first component C1 is similar to one of the semiconductor packages SP1, SP2, or modifications thereof. In a non-limiting example, one or more semiconductor packages (e.g., one or more semiconductor packages SP1, SP2, and / or modifications thereof) may be electrically coupled to the first component C1 via a plurality of terminals CT. As previously described, the terminals CT may be conductive terminals 370.

[0075] In some embodiments, an underfiller UF is formed between the first component C1 and the second component C2 to at least laterally cover the terminal CT. Alternatively, the underfiller UF may be omitted. The underfiller UF can be any acceptable material, such as a polymer, epoxy resin, molded underfiller, etc. In one embodiment, the underfiller can be formed by underfiller dispensing, capillary flow process, or any other suitable method. The bonding strength between the first component C1 and the second component C2 is enhanced due to the underfiller UF.

[0076] This disclosure is not limited thereto; alternatively, the semiconductor package disclosed herein may be in the form of an InFO package comprising a single semiconductor die (e.g., 100) surrounded by a trimmed underfill (e.g., 400), as previously described in Figures 3 to 5 and combined Figures 6 to 10 As described. In such an alternative embodiment, the sidewalls of the single semiconductor die (e.g., 100) may also be slightly removed to form patterned sidewalls, wherein the positioning configuration between the patterned sidewalls of the single semiconductor die within the InFO package and the trimmed underfill can be referenced. Figures 6 to 10 This allows for the suppression or elimination of delamination between the trimmed underfill and the underlying structure (e.g., interconnect substrates or structures; such as carriers, semiconductor substrates, or redistribution structures included in InFO packages). Furthermore, the underfill formation window is enlarged due to the trimming of the underfill. The fabrication of this semiconductor package is compatible with current and / or advanced manufacturing processes. For example, as... Figure 23 As shown, the semiconductor package SP3 (referred to as the InFO package) includes a redistribution structure 1330 (including one or more metallization layers 1334 and dielectric structures 1332), a semiconductor die 100 disposed above the redistribution structure 1330 and electrically coupled to the redistribution structure 1330 through a solder area 1200, an underfill 400 disposed between the semiconductor die 100 and the redistribution structure 1330, an insulating encapsulation 1500 encapsulating the semiconductor die 100 and the underfill 400, and a plurality of conductive terminals 1370 disposed above the redistribution structure 1330 and electrically coupled to the redistribution structure 1330. Figure 23As shown, the underfill 400 can cover the solder area 1200 and the via 140 protruding from the passivation layer 130, and the insulating encapsulation 1500 can cover the semiconductor die 100, the underfill 400, and the redistribution structure 1330 exposed from the semiconductor die 100 and the underfill 400. In some embodiments, the back surface S110b of the semiconductor die 100 is covered by the insulating encapsulation 1500. Alternatively, the back surface S110b of the semiconductor die 100 can be exposed in an accessible manner through the insulating encapsulation 1500.

[0077] For example, underfill 400 is located between semiconductor die 100 and redistributed wiring structure 1330, and further extends to surround the edge of semiconductor die 100. Underfill 400 includes a portion P3 sandwiched between semiconductor die 100 and redistributed wiring structure 1330, and a portion P2 located outside semiconductor die 100 and pre-cut to have a surface S400. Portion P2 can be in the form of a continuous frame. Sometimes, portion P2 can be referred to as an extension, peripheral portion, extension portion, or edge portion of underfill 400, while portion P3 can be referred to as the body portion or central portion of underfill 400. Portions P3 and P2 of underfill 400 can be connected to each other. Figure 23 As shown, for example, portions P3 and P2 of the bottom filler 400 are integral. In a non-limiting example, along direction Z, the maximum height of portion P3 is greater than the maximum height of portion P2 (in combination with...). Figure 8 / Figure 14 and Figure 9 / Figure 15 (See reference). In the non-restrictive example, along direction Z, the maximum height of part P3 is less than the maximum height of part P2 (in conjunction with...). Figure 7 / Figure 13 and Figure 10 / Figure 16 (See reference). In the non-restrictive example, along direction Z, the maximum height of part P3 is substantially equal to the maximum height of part P2 (in conjunction with...). Figure 6 / Figure 12 (Reference). The redistributed circuit structure 1330 can be referred to as an interconnect substrate or structure, or an internal interconnect substrate or structure.

[0078] The semiconductor package SP3 can be formed by, but is not limited to, the following methods: forming a redistribution structure 1330 on a temporary carrier (not shown); performing flip-chip bonding to attach the semiconductor die 100 to the redistribution structure 1330 via solder areas 1200; forming an underfill material (not shown) above the redistribution structure 1330 to fill the gap between the redistribution structure 1330 and the semiconductor die 100, wherein the underfill material surrounds the semiconductor die 100; performing a pre-dicing process to form an underfill 400, which has a location between the redistribution structure 1330 and the semiconductor die 100. The portion P3 between the dies 100 and the portion P2 surrounding the semiconductor die 100 are redistributed; the underfill 400 and the semiconductor die 100 are encapsulated within an insulating enclosure 1500, which is further composed of a redistribution circuit structure covering the underfill 400 and the exposed semiconductor die 100; a temporary carrier is debonded from the redistribution circuit structure 1330; and a conductive terminal 1370 is disposed on the redistribution circuit structure 1330, the conductive terminal 1370 being electrically coupled to the semiconductor die 100 via the redistribution circuit structure 1330 and the solder area 1200. Details of the semiconductor die 100 and the underfill 400 are already provided. Figures 1 to 19 This has been discussed previously, so it will not be repeated here for simplicity. Furthermore, the formation, materials, and details of the solder area 1200, the redistribution circuit structure 1330 (including the metallization layer 1334 and the dielectric structure 1332), the conductive terminal 1370, and the insulating encapsulation 1500 can be found in [the relevant documentation / contact information]. Figures 1 to 19 The solder area 200, the redistribution circuitry 330 (including the metallization layer 334 and the dielectric structure 332), the conductive terminals 370, and the insulating encapsulation 500 discussed are similar or substantially the same in formation, materials, and details, and therefore will not be repeated here. In some embodiments, after the conductive terminals 1370 are formed, a dicing (singleification) process is performed to separate multiple semiconductor packages SP3 in wafer form (physically interconnected) into individual and discrete semiconductor packages SP3.

[0079] Similarly, the semiconductor package SP3 and / or its modifications can be further mounted onto another external / additional electronic component, such as onto a circuit structure including a motherboard, package substrate, printed circuit board (PCB), interposer, printed circuit board, and / or other carrier capable of carrying integrated circuits. As a non-limiting example, the semiconductor package SP3 or its modifications can be an InFO package, an InFO package with a PoP structure, a CoW package, a CoWoS package, a flip-chip package with an InFO package, or a similar package, or can be a part of an InFO package, an InFO package with a PoP structure, a CoW package, a CoWoS package, a flip-chip package with an InFO package, or a similar package. This disclosure is not limited thereto.

[0080] According to some embodiments, a semiconductor package includes an interconnect substrate, a semiconductor die, and an underfill. The semiconductor die is disposed on the interconnect substrate and has a first top surface extending along a first direction. The underfill includes a body portion and an extension portion. The body portion is disposed between the interconnect substrate and the semiconductor die. The extension portion is connected to the body portion, wherein the extension portion is adjacent to the semiconductor die and has a second top surface extending along the first direction.

[0081] In some embodiments, in the semiconductor package, a first height of the body portion is greater than a second height of the extension portion along the stacking direction of the interconnect substrate and the semiconductor die. In some embodiments, in the semiconductor package, a first height of the body portion is substantially equal to the second height of the extension portion along the stacking direction of the interconnect substrate and the semiconductor die. In some embodiments, in the semiconductor package, a first height of the body portion is less than the second height of the extension portion along the stacking direction of the interconnect substrate and the semiconductor die. In some embodiments, in the semiconductor package, a portion of the semiconductor die is laterally covered by the underfill, and the surface of the portion of the semiconductor die is substantially flush with the surface of the extension portion of the underfill. In some embodiments, in the semiconductor package, the extension portion has a bottom surface and a second top surface opposite the bottom surface, the bottom surface contacting the interconnect substrate, and the second top surface comprising a planar surface that engages the semiconductor die. In some embodiments, in the semiconductor package, the extension has a bottom surface and a second top surface opposite to the bottom surface, the bottom surface contacting the interconnect substrate, and the second top surface includes a planar surface extending along the first direction and a curved surface connected to the planar surface, the curved surface extending continuously from the planar surface to the semiconductor die.

[0082] According to some embodiments, a semiconductor package includes an interconnect substrate, a die, an underfill, and an insulating encapsulator. The die is disposed on and electrically coupled to the interconnect substrate, wherein the die has an upper sidewall and a lower sidewall connected to the upper sidewall. The underfill laterally surrounds the die. The insulating encapsulator encapsulates the die and the underfill. The upper sidewall of the die extends along a first direction, and the lower sidewall of the die has an interface with the insulating encapsulator, the interface extending along a second direction different from the first direction.

[0083] In some embodiments, in the semiconductor package, the lower sidewall includes a curved surface. In some embodiments, in the semiconductor package, the curved surface has a radius of curvature in the range of about 0.5 μm to 5.0 μm. In some embodiments, in the semiconductor package, the lower sidewall includes a curved surface extending along the second direction, a vertical surface extending along the first direction, and a transverse surface extending in a direction substantially perpendicular to the first direction, wherein the transverse surface extends continuously between the curved surface and the vertical surface. In some embodiments, in the semiconductor package, the lower sidewall includes a curved surface extending along the second direction and a vertical surface extending along the first direction, wherein the curved surface extends continuously between the vertical surface and the upper sidewall. In some embodiments, in the semiconductor package, the underfill includes a planar upper surface. In some embodiments, in the semiconductor package, the underfill includes a planar upper surface and a curved surface connecting the planar upper surface, and the curved surface contacts the die. In some embodiments, in the semiconductor package, the curved surface has a radius of curvature in the range of about 0.5 μm to 5.0 μm.

[0084] According to some embodiments, a method of manufacturing a semiconductor package includes the steps of: bonding a semiconductor die to an interconnect substrate via a plurality of connectors; distributing an underfill material laterally around the plurality of connectors, wherein the underfill material includes a central portion and an extension laterally around the central portion; and removing the extension of the extension to expose the sidewalls of the semiconductor die.

[0085] In some embodiments, in the method, removing the portion of the extension of the underfill material includes performing a pre-cutting process to remove the portion of the extension and the portion of the semiconductor die in contact with the portion of the extension. In some embodiments, in the method, removing the portion of the extension of the underfill material includes performing a trimming process, and after the trimming process, the extension includes a planar surface engaging with the sidewall of the semiconductor die. In some embodiments, in the method, removing the portion of the extension of the underfill material includes performing a trimming process, and after the trimming process, the extension includes a planar surface and a curved surface connected to the planar surface, wherein the curved surface extends from the planar surface to the sidewall of the semiconductor die. In some embodiments, the method further includes encapsulating the semiconductor die and the underfill material in an insulating encapsulation.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor package, characterized by, include: Interconnect substrate; A semiconductor die disposed on the interconnect substrate and having a first top surface extending along a first direction; as well as Underfiller, including: The main body is disposed between the interconnect substrate and the semiconductor die; as well as An extension portion is connected to the main body portion, wherein the extension portion is adjacent to the semiconductor die and has a second top surface extending along the first direction.

2. The semiconductor package of claim 1, wherein, Along the stacking direction of the interconnect substrate and the semiconductor die, the first height of the main body portion is greater than the second height of the extension portion.

3. The semiconductor package of claim 1, wherein, Along the stacking direction of the interconnect substrate and the semiconductor die, the first height of the main body portion is substantially equal to the second height of the extension portion.

4. The semiconductor package according to claim 1, characterized in that, Along the stacking direction of the interconnect substrate and the semiconductor die, the first height of the main body portion is less than the second height of the extension portion.

5. The semiconductor package according to claim 1, characterized in that, The portion of the semiconductor die is laterally covered by the underfiller, and the surface of the portion of the semiconductor die is substantially flush with the surface of the extended portion of the underfiller.

6. The semiconductor package of claim 1, wherein, The extension has a bottom surface and a second top surface opposite the bottom surface, the bottom surface contacting the interconnect substrate, and The second top surface includes a planar surface, and the planar surface is engaged with the semiconductor die.

7. The semiconductor package of claim 1, wherein, The extension has a bottom surface and a second top surface opposite the bottom surface, the bottom surface contacting the interconnect substrate, and The second top surface includes a planar surface extending along the first direction and a curved surface connected to the planar surface, and the curved surface extends continuously from the planar surface to the semiconductor die.

8. A semiconductor package, characterized by, include: Interconnect substrate; A die is disposed above and electrically coupled to the interconnect substrate, wherein the die has an upper sidewall and a lower sidewall connected to the upper sidewall; Bottom filler, laterally surrounding the core; as well as An insulating encapsulation body encapsulates the core and the bottom filler. The upper sidewall of the die extends along a first direction, and the lower sidewall of the die has an interface with the insulating encapsulation, and the interface extends along a second direction different from the first direction.

9. The semiconductor package of claim 8, wherein, The lower sidewall includes a curved surface.

10. The semiconductor package of claim 9, wherein, The curved surface has a radius of curvature in the range of approximately 0.5 μm to 5.0 μm.

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