Semiconductor device

Abstract

A semiconductor device includes an active device, an interconnect structure, a dielectric bonding layer, a first bonding pad, and a second bonding pad. The active device is located along a substrate. The interconnect structure is located above the active device and includes a metal pad. The dielectric bonding layer is located above the metal pad. The first bonding pad is embedded in the dielectric bonding layer and is electrically connected to the metal pad. The second bonding pad is embedded in the dielectric bonding layer and is electrically isolated from the first interconnect structure. In a plan view, the second bonding pad includes a conductor frame surrounding the first bonding pad.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density is due to the iteration reduction of the minimum feature size, which allows more components to be integrated into a given area. With the increasing demand for miniaturized electronic devices, a trend has emerged towards smaller and more innovative semiconductor die packaging technologies. One example of such packaging systems is Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package or component is stacked on top of a bottom semiconductor package or component to provide a high degree of integration and component density. PoP technology typically enables the production of enhanced, compact semiconductor devices on printed circuit boards (PCBs). Utility Model Content

[0003] The purpose of this invention is to provide a semiconductor device to solve at least one of the above-mentioned problems.

[0004] This invention provides a semiconductor device according to several embodiments. The semiconductor device includes an active device, an interconnect structure, a dielectric bonding layer, a first bonding pad, and a second bonding pad. The active device is located along a substrate. The interconnect structure is above the active device and includes a metal pad. The dielectric bonding layer is above the metal pad. The first bonding pad is embedded in the dielectric bonding layer and is electrically connected to the metal pad. The second bonding pad is embedded in the dielectric bonding layer and is electrically isolated from the first interconnect structure. In a plan view, the second bonding pad includes a conductor frame surrounding the first bonding pad.

[0005] According to one embodiment of the present invention, the conductor frame is continuous.

[0006] According to one embodiment of the present invention, the conductor frame is discontinuous.

[0007] According to one embodiment of the present invention, the first bonding pad has a circular shape in the plan view, and the conductor frame has a rectangular frame shape in the plan view.

[0008] According to one embodiment of the present invention, the first bonding pad has a circular shape in the plan view, and the conductor frame of the second bonding pad has a circular frame shape in the plan view.

[0009] According to one embodiment of the present invention, the first bonding pad includes a plurality of bonding pads, wherein the conductor frame of the second bonding pad extends around and between each of the plurality of bonding pads.

[0010] This utility model provides a semiconductor device in several embodiments. The semiconductor device includes a first integrated circuit, a first bonding structure, a second bonding structure, and a second integrated circuit. The first integrated circuit is located on a first substrate and includes a first device layer, a first interconnect structure, and a first metal pad. The first bonding structure is located on the first integrated circuit and includes a first dielectric bonding layer, a first conductive bonding pad, and a first thermally conductive bonding pad. The first conductive bonding pad is embedded in the first dielectric bonding layer and electrically connected to the first metal pad and the first interconnect structure. The first thermally conductive bonding pad is embedded in the first dielectric bonding layer and electrically isolated from the first interconnect structure. The second bonding structure is located on the first bonding structure and in physical contact with it. The second integrated circuit is located on the second bonding structure.

[0011] According to one embodiment of the present invention, the second bonding structure includes: a second dielectric bonding layer bonded to the first dielectric bonding layer; a second conductive bonding pad embedded in the second dielectric bonding layer; and a second thermally conductive bonding pad embedded in the second dielectric bonding layer.

[0012] According to one embodiment of the present invention, the second conductive bonding pad is bonded to the first conductive bonding pad, wherein the second thermally conductive bonding pad is bonded to the first thermally conductive bonding pad, wherein the second conductive bonding pad is electrically connected to the second integrated circuit, and wherein the second thermally conductive bonding pad is electrically isolated from the first integrated circuit and the second integrated circuit.

[0013] According to one embodiment of the present invention, in a plan view, the first thermally conductive bonding pad includes a continuous conductor frame surrounding the first conductive bonding pad, and in the same plan view, the second thermally conductive bonding pad includes a discontinuous conductor frame surrounding the second conductive bonding pad. Attached Figure Description

[0014] The concept of embodiments of this utility model will be better understood by referring to the following detailed description and the accompanying drawings. It should be noted that, according to standard industry practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of illustration.

[0015] Figures 1 to 2C A cross-sectional view is shown during an intermediate step in the process of forming an integrated circuit die, according to some embodiments.

[0016] Figure 3A cross-sectional view is shown during an intermediate step in the process of forming a semiconductor package, according to some embodiments.

[0017] Figures 4A to 4C A cross-sectional view is shown during an intermediate step in the process of forming an integrated circuit die, according to some embodiments.

[0018] Figure 5 A cross-sectional view is shown during an intermediate step in the process of forming a semiconductor package, according to some embodiments.

[0019] Figures 6A to 6F A cross-sectional view is shown during an intermediate step in the process of forming an integrated circuit die, according to some embodiments.

[0020] Figures 7 to 10 A cross-sectional view is shown during an intermediate step in the process of forming a semiconductor package, according to some embodiments.

[0021] The attached figures are labeled as follows:

[0022] 50, 50A, 50B: Integrated circuit chips

[0023] 50H: Hot Zone

[0024] 52: Substrate / Semiconductor Substrate

[0025] 54: Device

[0026] 56: Interlayer dielectric

[0027] 58: Conductive embolism

[0028] 60: Interconnection Structure

[0029] 62: Pad

[0030] 64: Passivation film

[0031] 80: Joint structure

[0032] 82: Dielectric bonding layer

[0033] 84E: Conductive pad

[0034] 84T: Thermal pad

[0035] 84T C :aisle

[0036] 84T N :node

[0037] 84T R :track

[0038] 84T W :window

[0039] 150: Semiconductor Packaging

[0040] D1: Diameter

[0041] D2, D3, D4: Distance

[0042] D5: Diameter

[0043] D 2H :distance

[0044] P1, P2: Spacing

[0045] W1, W2, W3, W4: Width

[0046] W 1H W 2H :width Detailed Implementation

[0047] The following disclosure provides numerous different embodiments or examples to implement various features of the present invention. Specific examples of components and configurations are described below to simplify the description of the present invention. Of course, these specific examples are merely illustrative and not intended to limit the embodiments of the present invention. For example, in the following description, reference to a first feature being formed on or above a second feature indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself limit the relationship between the various embodiments and / or configurations described.

[0048] In addition, spatially related terms such as “below,” “under,” “lower,” “above,” “higher,” and similar terms may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and another element or feature(s). Besides the orientations shown in the accompanying drawings, these spatially related terms are intended to include different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein may be interpreted accordingly.

[0049] According to some embodiments, a semiconductor package can be formed by bonding a first integrated circuit die to a second integrated circuit die. The integrated circuit die can be formed with a bonding structure including bonding pads embedded in a dielectric bonding layer. According to various embodiments, the bonding pads of the integrated circuit die can include electrical pads for transmitting electrical signals and thermal pads for heat dissipation. As discussed in more detail below, the thermal pads can be manufactured with high design flexibility, allowing them to include various shapes, depths, and locations to achieve heat dissipation benefits. The bonding structures can be bonded to each other in a face-to-face attachment of the integrated circuit dies. Therefore, integrated circuit dies and semiconductor packages can be manufactured with higher throughput, improved performance, and higher reliability.

[0050] Various embodiments will be described below in specific contexts. Specifically, a system-on-a-chip (SoIC) package of the chip-on-wafer (CoW) type is described. However, various embodiments can also be applied to other types of semiconductor packaging technologies, such as integrated fan-out (InFO) packages. Embodiments in which a first integrated circuit die (e.g., in the form of a monolithic die) is attached to a second integrated circuit die (e.g., in the form of a wafer) are discussed below. It should be understood that the first integrated circuit die can remain in wafer form, while the second integrated circuit die is in monolithic die form. Alternatively, the first and second integrated circuit dies can be attached to each other, with both being in wafer form or both being monolithic dies.

[0051] Figures 1 to 10 The diagram illustrates intermediate steps in forming an integrated circuit die 50 and bonding two integrated circuit dies 50A / 50B together, wherein one or both integrated circuit dies are formed with a bonding structure 80, the bonding structure 80 including a conductive pad 84E (e.g., an electrical bonding pad) and one or more thermal pads 84T (e.g., a thermal bonding pad). As described below, the thermal pad 84T may be in the form of a conductive frame (e.g., a continuous or discontinuous conductive frame) or one or more other discrete conductive elements.

[0052] Figure 1Intermediate steps for forming an integrated circuit die 50 are shown, including forming an integrated circuit (e.g., device 54 and interconnect structure 60) on a substrate 52 and forming a bonding structure 80 on the integrated circuit. One or more integrated circuit dies 50 may be further processed and packaged together into a semiconductor package 150. The integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof.

[0053] Integrated circuit dies 50 can be formed at the wafer level, including being singulated in subsequent steps to form different device regions of multiple integrated circuit dies (not shown separately). Integrated circuit dies 50 can be processed according to applicable manufacturing processes to form integrated circuits. For example, integrated circuit die 50 includes a semiconductor substrate 52, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 can include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used. Semiconductor substrate 52 has an active surface sometimes referred to as the front side (e.g., Figure 1The surface facing upwards) and the non-active surface sometimes referred to as the rear side (e.g., Figure 1 (Surface facing downwards).

[0054] Device 54 (represented by a transistor) may be formed in a device layer on the front surface of semiconductor substrate 52. Device 54 may be an active device (e.g., a transistor, diode, etc.), a capacitor, a resistor, etc. Interlayer dielectric (ILD) 56 is located on the front surface of semiconductor substrate 52. Interlayer dielectric 56 surrounds and may cover device 54. Interlayer dielectric 56 may include one or more dielectric layers formed of materials such as phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc.

[0055] Conductive plugs 58 extend through the interlayer dielectric 56 to electrically and physically couple device 54. For example, when device 54 is a transistor, conductive plugs 58 may couple the gate and / or source / drain regions of the transistor. Conductive plugs 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or combinations thereof. Interconnect structures 60 are located on the interlayer dielectric 56 and conductive plugs 58. Interconnect structures 60 interconnect device 54 to form an integrated circuit. Interconnect structures 60 may be formed, for example, by metallization patterns in a dielectric layer on the interlayer dielectric 56. Metallization patterns include metal lines and vias formed in one or more low-k dielectric layers. The metallization patterns of interconnect structures 60 are electrically coupled to device 54 through conductive plugs 58.

[0056] The integrated circuit die 50 may also include pads 62 (e.g., metal pads), such as aluminum pads, for external interconnection. The pads 62 are located on the active side of the integrated circuit die 50, for example, within and / or on the interconnect structure 60. One or more passivation films 64 may be disposed on the pads 62.

[0057] In some embodiments, some pads 62 can be used as test pads prior to performing additional processing steps. For example, these pads 62 can be probed as part of wafer acceptance testing, circuit testing, known-good die (KGD) testing, etc. Probing can be performed to verify the functionality of device 54 (e.g., active or passive device), other electrical components, or various electrical connections within the integrated circuit. For example, probing can be performed by contacting the pads 62 with probes (not specifically shown). Integrated circuit dies 50 within the wafer that pass the circuit probe test will be considered known-good dies and can be used for further processing after subsequent monolithization processes.

[0058] Figures 2A to 2C The formation of a bonding structure 80 is illustrated, which includes bonding pads 84, for example, within a dielectric bonding layer 82. The bonding pads 84 include conductive pads 84E and one or more thermal pads 84T, wherein the conductive pads 84E are used to transmit electrical signals of the integrated circuit die 50, and the thermal pads 84T are used to dissipate heat through and from the integrated circuit die 50. The bonding pads 84 are used to attach the integrated circuit die 50 to another semiconductor component (see, for example, [link to example]). Figure 3 Specifically, conductive pad 84E can be bonded to the bonding pad of another integrated circuit die 50, while thermal pad 84T can also help attach integrated circuit die 50 to another integrated circuit die 50.

[0059] According to some embodiments, a dielectric bonding layer 82 may be formed on the pad 62 and the interconnect structure 60. The dielectric bonding layer 82 may be any material suitable for achieving dielectric-to-dielectric bonding. In some embodiments, the dielectric bonding layer 82 may include silicon oxide, silicon nitride, silicon oxynitride, etc., and the dielectric bonding layer 82 may be deposited using a suitable deposition process (e.g., PVD, CVD, ALD, etc.). The conductive pad 84E may be formed using a dual damascene process or using one or more single damascene processes. The thermal pad 84T may be formed in parallel (e.g., simultaneously) with the conductive pad 84E using a single damascene process.

[0060] Bonding pads 84 can then be formed in and through the dielectric bonding layer 82. Bonding pads 84 can be formed from a similar material (e.g., copper) and using a similar process as described above with respect to interconnect structure 60. In some embodiments, openings are formed in the dielectric bonding layer 82. Some of these openings may have a total depth within the dielectric bonding layer 82, some may extend through the dielectric bonding layer 82 and passivation film 64 to expose the underlying pads 62, and some may further extend beyond the pads 62 to expose other upper metallization layers of the interconnect structure 60.

[0061] The openings can be patterned into the dielectric bonding layer 82 and the passivation film 64 using photolithography or any suitable method (e.g., utilizing multiple photomasking and etching steps). Conductive material is then deposited in the respective openings, and a removal process is performed to remove excess conductive material from the upper surface of the dielectric bonding layer 82. The removal process may include a planarization step, which can be performed to make the surfaces of the bonding pads 84 and the dielectric bonding layer 82 substantially horizontal. For example, the removal process may include chemical mechanical polishing (CMP), abrasive polishing, or combinations thereof.

[0062] Conductive pad 84E is a bonding pad 84 extending to pad 62 and / or interconnect structure 60 for electrical connection. Conductive pad 84E is embedded in dielectric bonding layer 82 and may extend partially through passivation film 64. As shown, conductive pad 84E has landing pad portions flush with the main surface of dielectric bonding layer 82. Conductive pad 84E also has through-hole portions extending through dielectric bonding layer 82 (and passivation film 64) for physical and electrical connection to pad 62.

[0063] Thermal pad 84T is a bonding pad 84 that maintains electrical isolation from the integrated circuit (e.g., pad 62 and interconnect structure 60) of integrated circuit die 50. Thermal pad 84T is also embedded in dielectric bonding layer 82. As shown, thermal pad 84T may include a landing pad portion without a via portion. It should be noted that other embodiments of thermal pad 84T may include via portions (see...). Figure 10 ).

[0064] As described above, in some embodiments, the conductive pad 84E is formed using a dual damascene process, while the thermal pad 84T is formed using a single damascene process. The single damascene process for the thermal pad 84T can be performed in parallel (e.g., simultaneously) with the dual damascene process for the conductive pad 84E. For example, one of the etching steps that forms the opening for the conductive pad 84E can also form the opening for the thermal pad 84T, and conductive material can be deposited and planarized for both the conductive pad 84E and the thermal pad 84T simultaneously, similar to the above. It should be understood that the sub-processes for forming the conductive pad 84E and the thermal pad 84T can be performed in any suitable order (or in parallel).

[0065] Figure 2B and Figure 2C A plan view of the bonding structure 80 (e.g., dielectric bonding layer 82, conductive pad 84E, and thermal pad 84T) of an integrated circuit die 50 according to various embodiments is shown. In the illustrated embodiments, the thermal pad 84T may be a conductor frame (e.g., a conductor frame, such as a continuous conductor frame) extending around and between the bonding pads 84. Figure 2BIt shows a configuration consisting of 84T orbitals. R Defined rectangular (e.g., square) opening or window 84T W The thermal pad is 84T, and Figure 2C It shows a configuration consisting of 84T orbitals. R Defined spherical (e.g., circular) opening or window 84T W 84T thermal pad.

[0066] The upper surface of the bonding structure 80 has a metal density based on the proportion of bonding pads 84 embedded in the dielectric bonding layer 82. For example, the metal density can range from 50% to 80%, such as from 60% to 70%, due to the presence of thermal pads 84T. In such embodiments, conductive pads 84E may account for about 10% or less of the metal density, while thermal pads 84T account for the remainder. For example, the presence of thermal pads 84T can increase the metal density by 6 to 7 times. Therefore, the thermal resistance of the integrated circuit die 50 can be reduced by up to 90% to 95%, thereby improving the heat dissipation benefits of the integrated circuit die 50. A metal density greater than 50% (e.g., greater than 60%) ensures sufficient heat dissipation benefits. Conversely, a metal density less than 80% (e.g., less than 70%) ensures that the upper surface of the bonding structure 80 includes a sufficient proportion of the dielectric bonding layer 82 for reliable bonding (see [link to documentation]). Figure 3 ).

[0067] refer to Figure 2B The conductor frame of the thermal pad 84T may include vertical rails 84T. R Defined rectangular (e.g., square) window 84T W As shown in the figure, window 84T W The rectangular frame contains conductive pads 84E. For example, in the illustrated embodiment, four tracks 84T... R Connect to form a window with 84T W The frame, window 84T W It accommodates a conductive pad 84E. Optionally, some windows 84T W It can be large enough to accommodate two, four or more conductive pads 84E (or none), for example Figure 2B The right side portion shows the window 84T that accommodates two conductive pads 84E. W The conductive pads 84E are spaced apart by a pitch P1, which is between 2 and 10 times the diameter D1 (e.g., the critical dimension) of the conductive pads 84E. This results in window 84T... W It can have a width W1 ranging from twice the diameter D1 to 0.5 times the spacing P1. Additionally, the track is 84T. R It can have a width W2 ranging from approximately equal to the diameter D1 to 0.8 times the spacing P1.

[0068] Therefore, orbit 84T R The width W2 is at least as large as the critical dimension (e.g., diameter D1) to avoid or reduce patterning challenges, while also maintaining a sufficient distance D2 from the conductive pad 84E to prevent parasitic effects. Furthermore, components of the thermal pad 84T (e.g., track 84T) R and window 84T W It can have a spacing P2 that is substantially the same as the spacing P1 (or for a window 84T that accommodates multiple conductive pads 84E). W (For example, having a multiple of the spacing P1). Forming the bonding structure 80 within these dimensions achieves the described heat dissipation benefits while preventing parasitic effects between the conductive pad 84E and the thermal pad 84T.

[0069] As further shown in the figure, the conductive pad 84E can be considered as framing at least a portion of the thermal pad 84T. For example, the four tracks 84T of the thermal pad 84T... R The parts that meet or intersect (e.g., node 84T) N The area is framed by at least four conductive pads 84E. Specifically, four of these conductive pads 84E include pads surrounding node 84T. N The four corners of the frame. In some embodiments, other conductive pads 84E among these conductive pads 84E may include portions of one or more sides of the frame. As shown, node 84T N It can have a cross shape or a rectangle (e.g., a square).

[0070] refer to Figure 2C The conductor frame of the thermal pad 84T may include convex tracks 84T. R Defined spherical (e.g., circular or elliptical) window 84T W As shown in the figure, window 84T W A conductive pad 84E is accommodated within an elliptical (e.g., spherical or circular) frame. For example, in the illustrated embodiment, four tracks 84T... R Connect to form a window with 84T W The frame, window 84T W It accommodates a conductive pad 84E. In some embodiments (for specific illustration), some windows 84T W It can accommodate two, four, or more conductive pads 84E (or none). As described above, the conductive pads 84E are spaced apart by a pitch P1, which is between 2 and 10 times the diameter D1 (e.g., the critical dimension) of the conductive pads 84E. In this way, window 84T... WIt can have a width W1 (e.g., diameter) ranging from twice the diameter D1 to 0.5 times the spacing P1. Additionally, the track 84T... R It can have a width W2 ranging from approximately equal to the diameter D1 to 0.8 times the spacing P1.

[0071] Therefore, orbit 84T R The width W2 is at least as large as the critical dimension (e.g., diameter D1) to avoid patterning challenges, while also maintaining a sufficient distance D2 from the conductive pad 84E to prevent parasitic effects. As shown, the distance D2 can be substantially consistent around the periphery of the conductive pad 84E. Furthermore, components of the thermal pad 84T (e.g., track 84T) R and window 84T W The spacing P2 can be substantially the same as the spacing P1. Forming the bonding structure 80 within these dimensions achieves the described heat dissipation benefits while preventing parasitic effects between the conductive pad 84E and the thermal pad 84T.

[0072] As further shown in the figure, the conductive pad 84E can be considered as framing at least a portion of the thermal pad 84T. For example, the four tracks 84T of the thermal pad 84T... R The parts that meet or intersect (e.g., node 84T) N The thermal pad 84T is framed by at least four conductive pads 84E. Specifically, four of these conductive pads 84E comprise the four corners of a frame surrounding this portion of the thermal pad 84T. In some embodiments, the other conductive pads 84E may comprise portions of one or more sides of the frame. As shown, node 84T N It can have a concave cross shape or a rectangular shape (e.g., a square) with concave corners.

[0073] Based on how the thermal pad 84T achieves the aforementioned benefits, it should be understood that these benefits are influenced by the shape of the conductor frame of both the conductive pad 84E and the thermal pad 84T. For example, in an embodiment with a circular conductive pad 84E, the thermal pad 84T may be formed with a circular conductor frame to allow for an increase in the metal density of the bonding structure 80 while maintaining sufficient distance D2 to reduce parasitic effects. Similarly, in an embodiment with a rectangular conductive pad 84E, the thermal pad 84T may be formed with a rectangular conductor frame to allow for an increase in the metal density of the bonding structure 80 while maintaining sufficient distance D2 to reduce parasitic effects.

[0074] exist Figure 3In various embodiments, a semiconductor package 150 is formed by attaching (e.g., bonding) one integrated circuit die 50A (e.g., a first die) to another integrated circuit die 50B (e.g., a second die). As described above, one or both of these integrated circuit dies 50A / 50B can be logic dies (e.g., CPU, GPU, SoC, application processor (AP), microcontroller, etc.), memory dies (e.g., DRAM dies, SRAM dies, etc.), power management dies (e.g., PMIC dies), radio frequency (RF) dies, sensor dies, MEMS dies, signal processing dies (e.g., DSP dies), front-end dies (e.g., AFE dies), etc., or combinations thereof. Although two integrated circuit dies 50A / 50B are described and shown, any suitable number of dies can be attached to each other. In some embodiments, integrated circuit dies 50A and integrated circuit dies 50B are of the same or similar type. In other embodiments, integrated circuit die 50A is a memory die, while integrated circuit die 50B is a logic die, or vice versa. Either of the two integrated circuit dies 50A / 50B can be a logic device or a memory device as described above. In some embodiments, the two integrated circuit dies 50A / 50B can be the same type of die, such as a SoC die. The two integrated circuit dies 50A / 50B can be formed using the same technology node process or can be formed using different technology node processes. For example, integrated circuit die 50B can be made using a more advanced process node than integrated circuit die 50A, or vice versa. Other combinations of the two integrated circuit dies 50A / 50B can be utilized. Any suitable combination can be used.

[0075] In some embodiments, after forming the bonding structure 80, a singulation process may be performed to separate the integrated circuit die 50 from other integrated circuit dies 50 within the wafer. The singulated integrated circuit die 50 (e.g., a known good die among integrated circuit dies 50) will be attached to other semiconductor components (e.g., another integrated circuit die 50), as discussed in more detail below. In some embodiments, the integrated circuit die 50 may remain in wafer form and be attached to other die-form or wafer-form semiconductor components. For example, multiple integrated circuit dies 50 may be attached together to form a semiconductor package 150, such as a system on an integrated chip (SoIC) package of the chip-on-wafer (CoW) type. In the illustrated embodiment, the bottom die may be a wafer or a singulated integrated circuit die 50, while the top die may be a singulated integrated circuit die 50.

[0076] The two integrated circuit chips, 50A and 50B, can be combined with the above. Figures 2A to 2C The embodiments of the described integrated circuit die 50 may be similar or different. For example, the two integrated circuit dies 50A / 50B may be combined. Figure 2B The described exemplary embodiments, in combination Figure 2C The exemplary embodiments described herein, or each thereof, are as follows. As described above, the integrated circuit die 50B can remain in wafer form to be attached to a monolithic integrated circuit die 50A. Although one integrated circuit die 50A is shown, more than one integrated circuit die 50A can be attached to form a semiconductor package 150.

[0077] According to various embodiments, integrated circuit die 50A is bonded to integrated circuit die 50B via respective bonding structures 80, each bonding structure 80 including bonding pads 84 (e.g., conductive pads 84E and thermal pads 84T) and dielectric bonding layers 82.

[0078] Still referencing Figure 3 Integrated circuit die 50A is bonded to integrated circuit die 50B using, for example, dielectric-to-dielectric and metal-to-metal bonding processes. The two integrated circuit dies 50A / 50B are bonded in a face-to-face configuration. For example, integrated circuit die 50A is shown facing down, with the front side of integrated circuit die 50A facing the front side of integrated circuit die 50B, and integrated circuit die 50B is shown facing up. The dielectric bonding layer 82 of integrated circuit die 50A can be directly bonded to the dielectric bonding layer 82 of integrated circuit die 50B, and the bonding pad 84 of integrated circuit die 50A can be directly bonded to the bonding pad 84 of integrated circuit die 50B. For example, corresponding conductive pads 84E of the two integrated circuit dies 50A / 50B can be directly bonded, and corresponding thermal pads 84T of these integrated circuit dies 50A / 50B can be directly bonded.

[0079] In some embodiments, the bonding between the respective dielectric bonding layers 82 is a dielectric-to-dielectric (e.g., oxide-to-oxide) bonding, etc. The bonding process also directly bonds the respective conductive pads 84E and the respective thermal pads 84T via direct metal-to-metal bonding. Therefore, the electrical connection between integrated circuit dies 50A and 50B is provided by the physical and electrical connection of the conductive pads 84E. Additionally, the thermal conductivity connection between integrated circuit dies 50A and 50B is enhanced by the physical connection of the thermal pads 84T. In some embodiments, the interface also includes a dielectric-to-metal interface between the two integrated circuit dies 50A / 50B, wherein the respective conductive pads 84E and / or thermal pads 84T are not perfectly aligned and / or have different dimensions.

[0080] The bonding process may begin by applying a surface treatment to one or both of the respective bonding structures 80 (e.g., dielectric bonding layer 82). The surface treatment may include plasma treatment. The plasma treatment may be performed in a vacuum environment. Following the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to one or both of the dielectric bonding layers 82.

[0081] After securing the integrated circuit die 50A to the mounting base (not shown) using a vacuum or suitable tool, a bonding process can be performed by aligning the bonding pad 84 of the integrated circuit die 50A with the bonding pad 84 of the integrated circuit die 50B. When the two integrated circuit dies 50A / 50B are aligned, the corresponding conductive pad 84E and thermal pad 84T can overlap. After alignment, the integrated circuit dies 50A / 50B are moved toward each other (e.g., the integrated circuit die 50A moves downward toward the integrated circuit die 50B).

[0082] The bonding process includes a pre-bonding step during which the dielectric bonding layer 82 and bonding pad 84 of the integrated circuit die 50A are brought into contact with those of the integrated circuit die 50B. In some embodiments (not specifically shown), the vacuum or other tool used to hold the integrated circuit die 50A to the holder may be adjusted such that the central region of the integrated circuit die 50A bends outward (e.g., downward as shown) toward the integrated circuit die 50B. Alternatively, a pin may be pressed against the rear side of the integrated circuit die 50A to induce bending toward the integrated circuit die 50B. The pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). The bonding process is then continued by performing annealing, for example, at a temperature between about 150°C and about 400°C for a duration between about 0.5 hours and about 3 hours, such that the metals (e.g., copper) of the respective bonding pads 84 diffuse into each other, thereby forming a direct metal-to-metal bond. In other embodiments, other direct bonding processes (e.g., using adhesives, polymer-to-polymer bonding, etc.) may be used. It is worth noting that the integrated circuit die 50A is bonded to the integrated circuit die 50B without the use of solder connections (e.g., microbumps, etc.).

[0083] Following the attachment process, the semiconductor package 150 may undergo further processing (not specifically shown). For example, gap filler material may be formed on and between adjacent integrated circuit dies 50A; additional semiconductor components may be attached to the semiconductor package 150; external connectors may be formed; and / or the semiconductor package 150 may be attached to a package substrate. At any suitable stage, the structure may undergo additional testing (e.g., thermal cycling testing).

[0084] Figures 4A to 4CAn additional embodiment of the integrated circuit die 50 is shown. Figure 5 The formation of an additional embodiment of semiconductor package 150 is shown. Unless otherwise described, these embodiments may be formed similarly to those described above with respect to their analogues.

[0085] exist Figures 4A to 4C In the process, the integrated circuit die 50 may include a thermal pad 84T in the form of a conductor frame, similar to the combination described above. Figure 2B and Figure 2C The description, though slightly different, suggests that, for example, the thermal pad 84T can consist of multiple discontinuous elements (e.g., a discontinuous conductor frame composed of multiple discrete thermal pads 84T), such that adjacent windows 84T... W 84T through narrow openings or channels C They are interconnected. Figure 4B Show Figure 2B An exemplary discontinuous alternative to the rectangular frame, while Figure 4C Show Figure 2C An exemplary discontinuous alternative to a circular frame.

[0086] Figure 4B and Figure 4C A plan view of the bonding structure 80 (e.g., dielectric bonding layer 82, conductive pad 84E, and thermal pad 84T) of an integrated circuit die 50 according to various embodiments is shown. In the illustrated embodiment, the thermal pad 84T may be a conductor frame (e.g., a conductor framework) extending around and between the conductive pad 84E. Figure 4B 84T shows a window with a rectangular (e.g., square) opening. W The thermal pad is 84T, and Figure 4C 84T shows an opening or window with a spherical (e.g., circular) shape. W 84T thermal pad.

[0087] The upper surface of the bonding structure 80 has a metal density based on the proportion of bonding pads 84 embedded in the dielectric bonding layer 82. For example, the metal density can range from 50% to 60% due to the presence of thermal pads 84T. In such embodiments, conductive pads 84E may account for about 10% or less of the metal density, while thermal pads 84T account for the remainder. For example, the presence of thermal pads 84T can increase the metal density by 5 to 6 times. Therefore, the thermal resistance of the integrated circuit die 50 can be reduced by up to 85% to 90%, thereby improving the heat dissipation benefits of the integrated circuit die 50. A metal density greater than 50% ensures sufficient heat dissipation benefits. Conversely, a metal density less than 60% ensures that the upper surface of the bonding structure 80 includes a sufficient proportion of the dielectric bonding layer 82 for reliable bonding (see [link to documentation]). Figure 5 ).

[0088] refer to Figure 4B The conductor frame of the thermal pad 84T can include essentially vertical rails 84T. R Defined and by channel 84T C Connected rectangular (e.g., square) windows 84T W As shown in the figure, window 84T W The content is a conductive pad 84E. Optionally, some windows are 84T. W It can be large enough to accommodate two, four or more conductive pads 84E, for example Figure 4B The right side of the window 84T is shown W .

[0089] As further shown in the figure, the conductive pad 84E can be considered as enclosing at least a portion of the thermal pad 84T. For example, in conjunction with the above... Figure 2B Similar to the description, the thermal pad 84T has four tracks. R The parts that meet or intersect (e.g., node 84T) N The thermal pad 84T is framed by at least four conductive pads 84E, such that four of these conductive pads 84E include the four corners of the frame surrounding the thermal pad 84T. In some embodiments, the other conductive pads 84E may include portions of one or more sides of the frame. As described above, the entirety of this continuous portion of the thermal pad 84T may be referred to as a node 84T. N Specifically, these four conductive pads 84E include the four corners of the frame surrounding this portion of the thermal pad 84T. As shown in the figure, node 84T N It can have a cross shape or a rectangle (e.g., a square).

[0090] To achieve similar benefits, unless otherwise stated, the relative dimensions of the features may be combined with those above. Figure 2B Similar to those described. These dimensions include the spacing P1 of the conductive pad 84E, the diameter D1 of the conductive pad 84E (e.g., the critical dimension), and the window 84T. W Width W1, Track 84T R Width W2, Track 84T R The distance D2 (e.g., along channel 84T) C The orbit is 84T R The imaginary lines and the spacing P2 of the thermal pads 84T. Additionally, the width W3 of the thermal pads 84T represents adjacent and parallel channels 84T. C The spacing between them. As shown in the figure, the nearest point of the thermal pad 84T can be a distance D3 from the conductive pad 84E. In some embodiments, the bonding structure 80 can be formed to achieve bonding with the above. Figure 2B The same metal density is discussed, while maintaining a sufficient distance D3 (with) Figure 2B(Compared to the distance D2) to prevent parasitic effects.

[0091] refer to Figure 4C The conductor frame of the thermal pad 84T can include substantially convex tracks 84T. R Defined and by channel 84T C Connected spherical (e.g., circular or elliptical) windows 84T W As shown in the figure, window 84T W The content is a conductive pad 84E. In some embodiments (not specifically shown), some windows 84T W It can accommodate two, four, or more conductive pads 84E. To achieve similar benefits, unless otherwise stated, the relative dimensions of the features can be combined with the above. Figure 2C Similar to those described. These dimensions include the spacing P1 of the conductive pad 84E, the diameter D1 of the conductive pad 84E, and the window 84T. W Width W1, Track 84T R Width W2, Track 84T R The distance D2 (e.g., along channel 84T) C The orbit is 84T R The imaginary lines and the spacing P2 of the thermal pads 84T. Additionally, the width W3 of the thermal pads 84T represents adjacent and parallel channels 84T. C The interval between them. As shown in the figure, the nearest point of the thermal pad 84T can be a distance D3 from the conductive pad 84E, which can be approximately the same around the periphery of the conductive pad 84E. In some embodiments, the bonding structure 80 can be formed to achieve bonding with the above. Figure 2C The same metal density is discussed, while maintaining a sufficient distance D3 (with) Figure 2C (Compared to the distance D2) to prevent parasitic effects.

[0092] As further shown in the figure, the conductive pad 84E can be considered as enclosing at least a portion of the thermal pad 84T. For example, in conjunction with the above... Figure 2C Similar to the description, the thermal pad 84T has four tracks. R The parts that meet or intersect (e.g., node 84T) N The thermal pad 84T is framed by at least four conductive pads 84E, such that four of these conductive pads 84E include the four corners of the frame surrounding the thermal pad 84T. In some embodiments, the other conductive pads 84E may include portions of one or more sides of the frame. As described above, the entirety of this continuous portion of the thermal pad 84T may be referred to as a node 84T. N Specifically, the four conductive pads 84E include the four corners of a spherical (e.g., circular or elliptical) frame surrounding this portion of the thermal pad 84T. As shown in the figure, node 84TN It can have a concave cross shape or a rectangular shape (e.g., a square) with concave corners.

[0093] although Figure 4B and Figure 4C The embodiments utilize ratio Figure 2B and Figure 2C While the embodiments may feature more complex patterns, these embodiments offer additional benefits. Specifically, the discontinuous conductor frame of the thermal pad 84T further reduces the risk of parasitic effects by being divided into discrete components. Additionally, the extra openings between the thermal pads 84T (e.g., channels 84T) C This can reduce the risk of misalignment during subsequent bonding processes and / or reduce manufacturing costs by using less conductive material. Furthermore, regarding... Figure 4B In one embodiment, channel 84T C Located along window 84T W The closest point to the mating pad 84. Therefore, the nearest point is at a distance D3 from pad 84, which can be greater than distance D2. Alternatively or additionally, window 84T W The width W1 can be smaller, so that the distance D2 can be smaller than the above. Figure 2B The distance D2 being discussed.

[0094] exist Figure 5 In some embodiments, a semiconductor package 150 is formed by attaching (e.g., bonding) one integrated circuit die 50A (e.g., a first die) to another integrated circuit die 50B (e.g., a second die). This can be combined with the above. Figure 3 The attachment process is performed similarly as described above. The two integrated circuit dies, 50A / 50B, can be combined with the above. Figures 4A to 4C The embodiments of the described integrated circuit die 50 may be similar or different. For example, the two integrated circuit dies 50A / 50B may be combined. Figure 4B The described exemplary embodiments, in combination Figure 4C The exemplary embodiments described herein, or each thereof. Additionally, either of the two integrated circuit chips 50A / 50B can be the combination described above. Figures 2A to 2C The exemplary embodiments discussed herein. In this way, the patterns of the corresponding bonding structures 80 of the two integrated circuit dies 50A / 50B can be different, allowing some portions of the thermal pad 84T to be bonded to corresponding portions of the dielectric bonding layer 82 of the opposing integrated circuit dies 50A / 50B (e.g., channel 84T). C Align the position.

[0095] As described above, after the attachment process, the semiconductor package 150 can undergo further processing (not specifically shown). For example, gap filler material can be formed on and between adjacent integrated circuit dies 50A, additional semiconductor components can be attached to the semiconductor package 150, external connectors can be formed, and / or the semiconductor package 150 can be attached to a package substrate. At any suitable stage, the structure can undergo additional testing (e.g., thermal cycling testing).

[0096] exist Figures 6A to 6F In this embodiment, the integrated circuit die 50 may include thermal pads 84T having a specific shape or location to provide more heat dissipation from specific locations of the integrated circuit die 50 (compared to other locations of the integrated circuit die 50). For example, the integrated circuit of the integrated circuit die 50 may include a hot zone 50H that generates or accumulates heat at a higher rate than other regions of the integrated circuit die 50. In some embodiments, the hot zone 50H may be located in areas of the integrated circuit die 50 containing higher power density, such as in the core region. According to various embodiments, the thermal pad 84T may include discrete conductive elements located between some conductive pads 84E (see [link to documentation]). Figures 6B to 6D ), a discrete conductor frame located between and around some or all of the bonding pads 84 (see Figure 6E and Figure 6F (or a combination thereof).

[0097] According to various embodiments, the thermal pad 84T can reduce local thermal resistance within the hot zone 50H by up to 85% to 90%. This benefit can be achieved through a local metal density ranging from 50% to 60% (e.g., thermal pad 84T and conductive pad 84E within the hot zone 50H), wherein the conductive pad 84E accounts for about 10% or less of the metal density, while the thermal pad 84T accounts for the remainder of the metal density. For example, the presence of the thermal pad 84T can increase the metal density by 5 to 6 times.

[0098] Figure 6B A plan view is shown of a thermal pad 84T inserted between several conductive pads 84E, wherein the thermal pad 84T has a rectangular (e.g., square) shape. This shape is beneficial for heat dissipation in the hot zone 50H because the corners of the rectangle are close to the conductive pads 84E. This shape is also advantageous for direct bonding because the heat dissipation benefits can be achieved with a lower local metal density.

[0099] As shown in the figure, the conductive pad 84E can have a diameter D1 and a spacing P1 as described above in conjunction with the previous embodiments. Additionally, the element shown in the thermal pad 84T can have a width W4 ranging from twice the diameter D1 to 0.8 times the spacing P1. Therefore, the element is kept at a distance D4 from the conductive pad 84E, a distance D4 that is sufficiently large to prevent parasitic effects.

[0100] As further shown in the figure, the conductive pad 84E can be considered as framing at least a portion of the thermal pad 84T. For example, similar to the above, a portion of the thermal pad 84T can be framed by at least four conductive pads 84E, such that four of these conductive pads 84E include the four corners of a frame surrounding the thermal pad 84T. In some embodiments, the other conductive pads 84E may include portions of one or more sides of the frame. As described above, the entirety of this continuous portion of the thermal pad 84T can be referred to as node 84T. N Specifically, these four conductive pads 84E include the four corners of the frame surrounding this portion of the thermal pad 84T. As shown, the entire thermal pad 84T can be framed, and the nodes 84T N They have the same rectangular (e.g., square) shape accordingly.

[0101] Figure 6C A plan view is shown of a thermal pad 84T inserted between several conductive pads 84E, wherein the thermal pad 84T has a parallelogram (e.g., rhombus or diamond) shape. This shape facilitates heat dissipation in the hot zone 50H by increasing the local metal density while maintaining a sufficient distance from the conductive pads 84E to prevent parasitic effects.

[0102] As shown in the figure, the conductive pad 84E can have a diameter D1 and a spacing P1 as described above in conjunction with the previous embodiments. Additionally, the illustrated element of the thermal pad 84T can have a width W4 ranging from 2 or 3 times the diameter D1 to substantially equal to the spacing P1 (e.g., a maximum of 1.1 times the spacing P1). Therefore, the illustrated element maintains a distance D2 from the bonding pad 84, a distance D2 that is sufficiently large to prevent parasitic effects.

[0103] As further shown in the figure, the conductive pad 84E can be considered as framing at least a portion of the thermal pad 84T. For example, similar to the above, a portion of the thermal pad 84T can be framed by at least four conductive pads 84E, such that four of these conductive pads 84E include the four corners of a frame surrounding the thermal pad 84T. In some embodiments, the other conductive pads 84E may include portions of one or more sides of the frame. As described above, the entirety of this continuous portion of the thermal pad 84T can be referred to as node 84T. N Specifically, these four conductive pads 84E include the four corners of the frame surrounding this portion of the thermal pad 84T. As shown, the entire thermal pad 84T can be framed, and the nodes 84T N Correspondingly, they have the same parallelogram (e.g., rhombus or diamond) shape.

[0104] Figure 6DA plan view is shown of a thermal pad 84T inserted between several conductive pads 84E, wherein the thermal pad 84T has an elliptical (e.g., circular) shape. This shape facilitates heat dissipation in the hot zone 50H while simplifying process steps (e.g., patterning and conductive material deposition processes) by reducing the number of sharp edges and corners of the bonding structure 80.

[0105] As shown in the figure, the conductive pad 84E can have a diameter D1 and a spacing P1 as described above in conjunction with the previous embodiments. Additionally, the illustrated element of the thermal pad 84T can have a diameter D5 ranging from 2 or 3 times the diameter D1 to substantially equal to the spacing P1 (e.g., a maximum of 1.1 times the spacing P1). Therefore, the illustrated element maintains a distance D2 from the bonding pad 84, a distance D2 that is sufficiently large to prevent parasitic effects.

[0106] As further shown in the figure, the conductive pad 84E can be considered as framing at least a portion of the thermal pad 84T. For example, similar to the above, a portion of the thermal pad 84T can be framed by at least four conductive pads 84E, such that four of these conductive pads 84E include the four corners of a frame surrounding the thermal pad 84T. In some embodiments, the other conductive pads 84E may include portions of one or more sides of the frame. As described above, the entirety of this continuous portion of the thermal pad 84T can be referred to as node 84T. N Specifically, these four conductive pads 84E include the four corners of the frame surrounding this portion of the thermal pad 84T. As shown, the entire thermal pad 84T can be framed, and the nodes 84T N They correspondingly have the same elliptical (e.g., circular) shape.

[0107] Figure 6E A plan view of a thermal pad 84T according to some embodiments is shown. This thermal pad 84T is a partial conductor frame extending around and between some conductive pads 84E. (In conjunction with the above) Figure 2B , Figure 2C , Figure 4B and Figure 4C Similar to what has been described, this partial frame is advantageous for heat dissipation in the hot zone 50H. However, this partial frame offers the advantage of concentrating heat dissipation benefits in specific locations while maintaining a low overall metal density throughout the bonding structure 80 to improve the direct bonding process. According to various embodiments, the thermal pad 84T can be as described above. Figure 2C The circular conductor frame described and / or as combined above Figure 4B and Figure 4C The discontinuous conductor frame described herein. Thus, the bonding structure 80 (including the thermal pad 84T) can include the bonding described above. Figures 2A to 2C and Figures 4A to 4C The dimensions described.

[0108] As further shown in the figure, the conductive pad 84E can be considered as framing at least a portion of the thermal pad 84T. For example, the four tracks 84T of the thermal pad 84T... R The parts that meet or intersect (e.g., node 84T) N The thermal pad 84T is framed by at least four conductive pads 84E. Specifically, four of these conductive pads 84E include the four corners of the frame surrounding this portion of the thermal pad 84T. As shown in the figure, based on the layout of the frames of the conductive pads 84E and the thermal pad 84T, node 84T... N It can be T-shaped (e.g., T-shaped connector), L-shaped, etc.

[0109] Figure 6F The above text is combined Figures 2A to 2C and Figures 4A to 4C A plan view of the described variant of the thermal pad 84T, wherein window 84T W and track 84T R Different sizes can be included. Specifically, the thermal pad 84T can be a conductor frame (or a discontinuous conductor frame) with a higher density above the hot zone 50H compared to other areas of the integrated circuit die 50. This reduces the overall metal density to improve direct bonding processes. Although shown as a continuous rectangular frame (e.g., similar to...), Figure 2B However, the thermal pad 84T can be a similar variant of other exemplary shapes and styles of conductor frames (see [link to documentation]). Figure 2C , Figure 4B and Figure 4C ).

[0110] For example, the bonding structure 80 (including the thermal pad 84T) may include the bonding described above. Figures 2A to 2C and Figures 4A to 4C The dimensions within the described range. Specifically, window 84T. W Width W above the hot zone 50H 1H The distance D between thermal pad 84T and conductive pad 84E 2H It can approach the lower point within the relevant range of width W1 and distance D2, respectively. Additionally, track 84T... R Width W 2H It can approach the upper point of the relevant range of width W2. Furthermore, the opposite may also apply to those dimensions in other areas of the thermal pad 84T that are far from the hot zone 50H.

[0111] As further shown in the figure, the conductive pad 84E can be considered as framing at least a portion of the thermal pad 84T. For example, the four tracks 84T of the thermal pad 84T... R The parts that meet or intersect (e.g., node 84T) NThe thermal pad 84T is framed by at least four conductive pads 84E. Specifically, four of these conductive pads 84E comprise the four corners of a frame surrounding this portion of the thermal pad 84T. In some embodiments, the other conductive pads 84E may comprise portions of one or more sides of the frame. As shown, this frame is also similar to... Figure 6E In the context of the accompanying discussion, node 84T N It can have a cross shape, a rectangle shape, a T shape, an L shape, etc.

[0112] Figure 7 and Figure 8 This illustrates, according to some embodiments, attaching an integrated circuit die 50A to an integrated circuit die 50B to form a semiconductor package 150. This can be combined with the above description. Figure 3 and Figure 5 The above describes the process of performing the attachment. The two integrated circuit dies, 50A / 50B, can be combined with the above. Figures 6A to 6F (Including combinations thereof) and / or embodiments of the integrated circuit die 50 described above in conjunction with other embodiments are similar to or different from those described above.

[0113] In some embodiments, the thermal pad 84T of the integrated circuit die 50A is disposed on the hot zone 50H of the integrated circuit die 50A, and the thermal pad 84T of the integrated circuit die 50B is disposed on the hot zone 50H of the integrated circuit die 50B. Figure 7 An exemplary embodiment is provided in which the thermal zones 50H of two integrated circuit dies 50A and 50B are aligned such that the corresponding thermal pads 84T are paired and can also be substantially aligned. Figure 8 An exemplary embodiment is provided in which the thermal zones 50H of two integrated circuit dies 50A and 50B overlap but do not need to be aligned, such that some corresponding thermal pads 84T are paired, while other thermal pads 84T remain unpaired.

[0114] Figure 9 and Figure 10 The illustration shows an integrated circuit die 50A attached to an integrated circuit die 50B to form a semiconductor package 150 according to some embodiments. Specifically, these embodiments may include any examples or variations of applicable embodiments of the integrated circuit die 50 to form variations of the semiconductor package 150 described above.

[0115] exist Figure 9In this embodiment, the thermal pad 84T can be formed to a thickness different from the landing pad portion of the conductive pad 84E. For example, as shown with respect to integrated circuit die 50A, the thermal pad 84T can have a smaller thickness than the landing pad portion of the conductive pad 84E. Conversely, as shown with respect to integrated circuit die 50B, the thermal pad 84T can have a larger thickness than the landing pad portion of the conductive pad 84E. It should be understood that any combination of these thermal pads 84T (e.g., having larger, smaller, or equal thicknesses) can be included in any integrated circuit die 50A / 50B.

[0116] According to some embodiments, the thermal pad 84T can be formed partially in parallel with the conductive pad 84E. For example, the openings for the thermal pad 84T can be formed separately from the openings for the conductive pad 84E to allow for different shapes and depths of etching. After forming both sets of openings, conductive materials for both the conductive pad 84E and the thermal pad 84T can be deposited and planarized simultaneously, similar to what has been described above.

[0117] Embodiments involving a thermal pad 84T having a greater thickness than the conductive pad 84E can provide greater heat dissipation benefits in the integrated circuit die 50 (or a specific location therein, such as the hot zone 50H). Conversely, embodiments involving a thermal pad 84T having a smaller thickness than the conductive pad 84E can achieve sufficient heat dissipation benefits in the integrated circuit die 50 (or a specific location therein, as needed) while utilizing less conductive material.

[0118] exist Figure 10 In this context, the thermal pad 84T can be formed to include both a landing pad portion and a through-hole portion, as described in conjunction with the conductive pad 84E (see example...). Figures 2A to 2C Similarly, thermal pads 84T and conductive pads 84E can be formed simultaneously in a dual damascene process or multiple single damascene processes. For example, as shown with respect to integrated circuit die 50A, all thermal pads 84T can be formed to include both landing pad portions and via portions. Additionally, as shown with respect to integrated circuit die 50B, some thermal pads 84T located above the hot zone 50H can be formed to include both landing pad portions and via portions, while other thermal pads 84T (e.g., laterally offset from the hot zone 50H) can be formed to have landing pad portions but no via portions. Various types of thermal pads 84T can be formed similarly to those described above in similar embodiments.

[0119] In some embodiments, the via portions of the thermal pad 84T may extend to substantially the same depth as the via portions of the conductive pad 84E. In other embodiments (not specifically shown), the via portions of the thermal pad 84T may extend to a greater or lesser depth than the via portions of the conductive pad 84E. Furthermore, the depth of the via portions of the thermal pad 84T may vary within the integrated circuit die 50. For example, some thermal pads 84T may have larger via depths to increase heat dissipation benefits at multiple locations, while others may have smaller via depths to reduce parasitic effects with near-end conductive features (e.g., pad 62). Additionally, some thermal pads 84T may extend to some pads 62, such as dummy metal pads 62 that can be electrically isolated from the integrated circuit.

[0120] As described above, after the attachment process, the semiconductor package 150 can undergo further processing (not specifically shown). For example, gap filler material can be formed on and between adjacent integrated circuit dies 50A, additional semiconductor components can be attached to the semiconductor package 150, external connectors can be formed, and / or the semiconductor package 150 can be attached to a package substrate. At any suitable stage, the structure can undergo additional testing (e.g., thermal cycling testing).

[0121] This invention provides various advantages. Specifically, the bonding structure 80 can be formed with a thermal pad 84T to improve heat dissipation of the integrated circuit in the integrated circuit die 50. For example, embodiments of the thermal pad 84T may include a continuous or discontinuous conductor frame extending around and between the conductive pad 84E. Additionally, embodiments of the thermal pad 84T may include elements located near the hot zone 50H of the integrated circuit die 50. Furthermore, embodiments of the thermal pad 84T may include a partial conductor frame located near the hot zone 50H or a conductor frame with a large local metal density located near the hot zone 50H. Therefore, the thermal pad 84T can be formed in parallel with the conductive pad 84E, requiring little or no additional process steps to fabricate the semiconductor package 150 and achieve heat dissipation benefits.

[0122] In some embodiments, a method of forming a semiconductor device includes forming a device layer along a substrate; forming a first interconnect structure over the device layer; forming a metal pad over the first interconnect structure; forming a plurality of first bonding pads over the first interconnect structure and electrically connecting them to the first interconnect structure; and forming a second bonding pad over the first interconnect structure and electrically isolating it from the first interconnect structure, wherein, in a plan view, the first bonding pad includes four corners of a frame surrounding a portion of the second bonding pad. In some embodiments, the method further includes bonding an integrated circuit die to the first and second bonding pads. In some embodiments, the integrated circuit die includes a second interconnect structure, a plurality of third bonding pads, and a fourth bonding pad, the third bonding pads electrically connecting the second interconnect structure to the first bonding pads, and the fourth bonding pads physically contacting the second bonding pads. In some embodiments, the fourth bonding pad is electrically isolated from the second interconnect structure. In some embodiments, the first and second bonding pads are embedded in a first dielectric bonding layer, the third and fourth bonding pads are embedded in a second dielectric bonding layer, and bonding the integrated circuit die includes directly bonding the first dielectric bonding layer to the second dielectric bonding layer, directly bonding the first bonding pad to the third bonding pad, and directly bonding the second bonding pad to the fourth bonding pad. In some embodiments, in a plan view, the second bonding pad forms a rectangular frame surrounding one of the first bonding pads. In some embodiments, in a plan view, the second bonding pad forms a circular frame surrounding one of the first bonding pads. In some embodiments, the second bonding pad forms a continuous conductor frame around and between each of the first bonding pads. In some embodiments, forming the second bonding pad includes forming a plurality of bonding pads, and the bonding pads form discontinuous conductor frames around and between each of the first bonding pads.

[0123] In some embodiments, a semiconductor device includes an active device, an interconnect structure, a dielectric bonding layer, a first bonding pad, and a second bonding pad. The active device is located along a substrate. The interconnect structure is located above the active device and includes a metal pad. The dielectric bonding layer is located above the metal pad. The first bonding pad is embedded in the dielectric bonding layer and is electrically connected to the metal pad. The second bonding pad is embedded in the dielectric bonding layer and is electrically isolated from the first interconnect structure. In a plan view, the second bonding pad includes a conductor frame surrounding the first bonding pad. In some embodiments, the conductor frame is continuous. In some embodiments, the conductor frame is discontinuous. In some embodiments, the first bonding pad has a circular shape in a plan view, and the conductor frame has a rectangular frame shape in a plan view. In some embodiments, the first bonding pad has a circular shape in a plan view, and the conductor frame of the second bonding pad has a circular frame shape in a plan view. In some embodiments, the first bonding pad includes a plurality of bonding pads, and the conductor frame of the second bonding pad extends around and between each of the bonding pads.

[0124] In some embodiments, a semiconductor device includes a first integrated circuit, a first bonding structure, a second bonding structure, and a second integrated circuit. The first integrated circuit is situated on a first substrate and includes a first device layer, a first interconnect structure, and a first metal pad. The first bonding structure is situated on the first integrated circuit and includes a first dielectric bonding layer, a first conductive bonding pad, and a first thermally conductive bonding pad. The first conductive bonding pad is embedded in the first dielectric bonding layer and electrically connected to the first metal pad and the first interconnect structure. The first thermally conductive bonding pad is embedded in the first dielectric bonding layer and electrically isolated from the first interconnect structure. The second bonding structure is situated on the first bonding structure and in physical contact with it. The second integrated circuit is situated on the second bonding structure. In some embodiments, the second bonding structure includes a second dielectric bonding layer, a second conductive bonding pad, and a second thermally conductive bonding pad. The second dielectric bonding layer is bonded to the first dielectric bonding layer, and the second conductive bonding pad is embedded in the second dielectric bonding layer. In some embodiments, the second conductive bonding pad is bonded to the first conductive bonding pad, and the second thermally conductive bonding pad is bonded to the first thermally conductive bonding pad. In some embodiments, the second conductive bonding pad is electrically connected to the second integrated circuit, and the second thermally conductive bonding pad is electrically isolated from the first integrated circuit and the second integrated circuit. In some embodiments, in a plan view, the first thermally conductive bonding pad includes a continuous conductor frame surrounding the first conductive bonding pad, and in a plan view, the second thermally conductive bonding pad includes a discontinuous conductor frame surrounding the second conductive bonding pad.

[0125] The foregoing outlines the features of numerous embodiments to enable those skilled in the art to better understand the various embodiments of this utility model. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of this utility model to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this utility model. Various changes, substitutions, and modifications can be made to the embodiments of this utility model without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, characterized by comprising: include: An active device, along a substrate; An interconnect structure is provided on the active device, the interconnect structure including a metal pad; A dielectric bonding layer is placed on the metal pad; A first bonding pad is embedded in the dielectric bonding layer, and the first bonding pad is electrically connected to the metal pad; as well as A second bonding pad is embedded in the dielectric bonding layer and is electrically isolated from the interconnect structure. In a plan view, the second bonding pad includes a conductor frame surrounding the first bonding pad.

2. The semiconductor device according to claim 1, wherein The conductor frame is continuous.

3. The semiconductor device according to claim 1, wherein The conductor frame is discontinuous.

4. The semiconductor device according to claim 1, wherein The first bonding pad has a circular shape in the plan view, and the conductor frame has a rectangular frame shape in the plan view.

5. The semiconductor device according to claim 1, wherein The first bonding pad has a circular shape in the plan view, and the conductor frame of the second bonding pad has a circular frame shape in the plan view.

6. The semiconductor device according to claim 1, wherein The first bonding pad includes a plurality of bonding pads, wherein the conductor frame of the second bonding pad extends around and between each of the plurality of bonding pads.

7. A semiconductor device, characterized by comprising: include: A first integrated circuit, on a first substrate, the first integrated circuit comprising: First device layer; A first interconnect structure; and First metal pad; A first bonding structure, on the first integrated circuit, the first bonding structure comprising: A first dielectric bonding layer; A first conductive bonding pad is embedded in the first dielectric bonding layer, and the first conductive bonding pad is electrically connected to the first metal pad and the first interconnect structure; and A first thermally conductive bonding pad is embedded in the first dielectric bonding layer, and the first thermally conductive bonding pad is electrically isolated from the first interconnect structure; A second joining structure, which is on top of and in physical contact with the first joining structure; and A second integrated circuit is disposed on the second bonding structure.

8. The semiconductor device according to claim 7, wherein The second joining structure includes: A second dielectric bonding layer is bonded to the first dielectric bonding layer; A second conductive bonding pad is embedded in the second dielectric bonding layer; and A second thermally conductive bonding pad is embedded in the second dielectric bonding layer.

9. The semiconductor device according to claim 8, wherein The second conductive bonding pad is bonded to the first conductive bonding pad, wherein the second thermally conductive bonding pad is bonded to the first thermally conductive bonding pad, wherein the second conductive bonding pad is electrically connected to the second integrated circuit, and wherein the second thermally conductive bonding pad is electrically isolated from the first integrated circuit and the second integrated circuit.

10. The semiconductor device according to claim 8, wherein In a plan view, the first thermally conductive bonding pad includes a continuous conductor frame surrounding the first conductive bonding pad, and in the same plan view, the second thermally conductive bonding pad includes a discontinuous conductor frame surrounding the second conductive bonding pad.

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