Package substrate and package structure

Abstract

This invention provides a packaging substrate and a packaging structure. The packaging substrate includes a core, a first dielectric layer, a second dielectric layer, and a fiber-reinforced dielectric layer. The first dielectric layer is located on a first side of the core. The second dielectric layer is located on a second side of the core, opposite to the first side of the core. The fiber-reinforced dielectric layer is located on at least one of the first side and the second side of the core.

Description

Technical Field

[0001] This utility model relates to a packaging substrate and a packaging structure. Background Technology

[0002] Cracks in semiconductor packaging substrates can be caused by a variety of factors, typically related to mechanical, thermal, and environmental stresses. For example, mechanical stresses may be generated during testing, assembly, and attaching the packaging substrate to a printed circuit board (PCB). Thermal stresses can be caused by thermal cycling or a mismatch in the coefficients of thermal expansion (CTE). Environmental stresses can be caused by exposure to moisture or corrosive chemicals.

[0003] Manufacturers can use various strategies to suppress crack formation in semiconductor packaging substrates. Using materials with similar coefficients of thermal expansion can reduce crack formation. Other strategies focus on increasing the rigidity of the packaging substrate to reduce crack formation. For example, adding a rigid core to the packaging substrate is often used to provide substrate rigidity. Manufacturers can also insert rigid structures such as metal pillars into the packaging substrate to enhance its rigidity. Utility Model Content

[0004] The purpose of this invention is to provide a packaging substrate to solve at least one of the above-mentioned problems.

[0005] This invention provides a packaging substrate including a core, a first dielectric layer, a second dielectric layer, and a fiber-reinforced dielectric layer. The first dielectric layer is located on a first side of the core. The second dielectric layer is located on a second side of the core, opposite to the first side of the core. The fiber-reinforced dielectric layer is located on at least one of the first side and the second side of the core.

[0006] According to one embodiment of the present invention, the fiber-reinforced dielectric layer includes a dielectric material and a fiber sheet, wherein the fiber sheet is embedded in the dielectric material, and the fiber sheet includes either a woven fiber sheet or a fiber mesh sheet.

[0007] According to one embodiment of the present invention, there is a die mounting region; a ring mounting region adjacent to the die mounting region; and a partition region located between the die mounting region and the ring mounting region, wherein the fiber-reinforced dielectric layer is located in the partition region.

[0008] According to one embodiment of the present invention, the fiber-reinforced dielectric layer includes: an upper fiber-reinforced dielectric layer located on the first side of the core; and a lower fiber-reinforced dielectric layer located on the second side of the core.

[0009] According to one embodiment of the present invention, the upper fiber-reinforced dielectric layer is located on an upper surface of the first dielectric layer, and the upper fiber-reinforced dielectric layer includes a fiber sheet and a plurality of upper metal vias, the plurality of upper metal vias extending through the fiber sheet, wherein the first dielectric layer includes a plurality of first metal interconnect structures, and the plurality of upper metal vias are electrically coupled to the plurality of first metal interconnect structures.

[0010] According to one embodiment of the present invention, the lower fiber-reinforced dielectric layer is located on a lower surface of the second dielectric layer, and the lower fiber-reinforced dielectric layer includes a fiber sheet and a plurality of lower metal vias, the plurality of lower metal vias extending through the fiber sheet, wherein the second dielectric layer includes a plurality of second metal interconnect structures, and the plurality of lower metal vias are electrically coupled to the plurality of second metal interconnect structures.

[0011] This utility model provides a packaging structure including a packaging substrate and a semiconductor module. The packaging substrate includes a core and an upper fiber-reinforced dielectric layer. The core includes multiple through-holes. The upper fiber-reinforced dielectric layer is located on a first side of the core and includes multiple upper metal vias electrically coupled to the through-holes. The semiconductor module is attached to the packaging substrate on the first side of the core and includes multiple solder bumps that respectively contact the upper metal vias.

[0012] According to one embodiment of the present invention, it further includes: a reinforcing ring surrounding the semiconductor module on the packaging substrate, wherein the packaging substrate includes a partition region separating the reinforcing ring from the semiconductor module, and the upper fiber-reinforced dielectric layer is located in the partition region.

[0013] According to one embodiment of the present invention, it further includes: a lower fiber-reinforced dielectric layer located on a second side of the core, including a plurality of lower metal vias; and a ball grid array attached to the packaging substrate on the second side of the core, and electrically coupled to a plurality of through-holes in the core through the plurality of lower metal vias.

[0014] According to one embodiment of the present invention, it further includes: a first dielectric layer located between the core and the upper fiber-reinforced dielectric layer; a second dielectric layer located between the core and the lower fiber-reinforced dielectric layer; an embedded upper fiber-reinforced dielectric layer embedded in the first dielectric layer; and an embedded lower fiber-reinforced dielectric layer embedded in the second dielectric layer.

[0015] This utility model provides a method for forming a semiconductor substrate, including forming a first dielectric layer on a first side of a core, forming a second dielectric layer on a second side of the core, the second side of the core being opposite to the first side of the core, and forming a fiber-reinforced dielectric layer on at least one of the first side or the second side of the core. Attached Figure Description

[0016] The embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, many features are not shown to scale and are only used for illustrative purposes. In fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly demonstrate the features of this utility model.

[0017] Figure 1 It is a vertical cross-sectional view of a packaging substrate according to one or more embodiments.

[0018] Figure 2A This is a schematic diagram of a first fiber sheet in a fiber-reinforced dielectric layer according to one or more embodiments.

[0019] Figure 2B This is a schematic diagram of a first fiber sheet having a first alternative configuration in a fiber-reinforced dielectric layer according to one or more embodiments.

[0020] Figure 3A It is a vertical cross-sectional view of the packaging structure according to one or more embodiments.

[0021] Figure 3B It is a plan view (top view) of the packaging structure according to one or more embodiments.

[0022] Figure 3C It is a vertical cross-sectional view of the upper fiber-reinforced dielectric layer according to one or more embodiments.

[0023] Figure 3D It is a vertical cross-sectional view of the lower fiber-reinforced dielectric layer according to one or more embodiments.

[0024] Figure 4A It is a vertical cross-sectional view of an intermediate structure including a first dielectric layer on a core, according to one or more embodiments.

[0025] Figure 4B It is a vertical cross-sectional view of an intermediate structure including an upper fiber-reinforced dielectric layer according to one or more embodiments.

[0026] Figure 4C It is a vertical cross-sectional view of an intermediate structure including a second dielectric layer on a core, according to one or more embodiments.

[0027] Figure 4D It is a vertical cross-sectional view of an intermediate structure including a lower fiber-reinforced dielectric layer according to one or more embodiments.

[0028] Figure 4E It is a vertical cross-sectional view of an intermediate structure according to one or more embodiments, wherein a semiconductor module can be mounted on a packaging substrate (e.g., via a flip chip bonding (FCB) process).

[0029] Figure 4F It is a vertical cross-sectional view of an intermediate structure in which an underfill layer of a package can be formed on a package substrate according to one or more embodiments.

[0030] Figure 4G This is a vertical cross-sectional view of an intermediate structure on a packaging substrate for applying adhesive according to one or more embodiments.

[0031] Figure 4H The figure is a vertical cross-sectional view of an intermediate structure for attaching (e.g., mounting) a reinforcing ring on a package substrate according to one or more embodiments.

[0032] Figure 4I This is a vertical cross-sectional view of an intermediate structure in which multiple solder balls can be formed on a packaging substrate according to one or more embodiments.

[0033] Figure 5 This is a flowchart of a method for manufacturing a semiconductor package according to one or more embodiments.

[0034] Figure 6 This is a flowchart of a method for manufacturing a semiconductor package according to one or more embodiments.

[0035] Figure 7 It is a vertical cross-sectional view of a packaging structure having a first alternative configuration according to one or more embodiments.

[0036] Figure 8A It is a vertical cross-sectional view of a packaging structure having a second alternative configuration according to one or more embodiments.

[0037] Figure 8B It is a top view (plan view) of a package structure having a second alternative configuration according to one or more embodiments.

[0038] The attached figures are labeled as follows:

[0039] 10: Intermediary layer

[0040] 12: Dielectric material layer

[0041] 12a: Redistribution layer

[0042] 13: Upper passivation layer

[0043] 14: Lower passivation layer

[0044] 14a: Intermediate layer lower bonding pad

[0045] 20: Fiber-reinforced dielectric layer

[0046] 42: Fiber

[0047] 100: Package structure

[0048] 110: Packaging substrate

[0049] 110a: Die Mounting Area

[0050] 110b: Ring mounting area

[0051] 110c: Separate regions

[0052] 110d: Ball grid array region

[0053] 110e: External packaging substrate area

[0054] 112: Core

[0055] 112a: Through hole

[0056] 113: Upper solder mask layer

[0057] 114: First dielectric layer

[0058] 114b: First metal interconnect structure

[0059] 114b-U: Top layer metal wire

[0060] 115: Lower solder mask layer

[0061] 116: Second dielectric layer

[0062] 116b: Second metal interconnect structure

[0063] 116b-L: Bottom layer metal wire

[0064] 120: Semiconductor Module

[0065] 121:C4 bump

[0066] 127: Upper molding layer

[0067] 128: Microbumps

[0068] 129: Encapsulation bottom filler layer

[0069] 140: Upper fiber-reinforced dielectric layer

[0070] 141,241,341,441: Dielectric materials

[0071] 141a: Top portion of dielectric material

[0072] 141b: Bottom portion of dielectric material

[0073] 142,242,342,442: Fiber sheets

[0074] 145: Upper metal through-hole

[0075] 150: Reinforcing ring

[0076] 160: Adhesive

[0077] 180: Semiconductor die

[0078] 180a: Top surface of semiconductor grain

[0079] 181: First semiconductor die

[0080] 182: Second semiconductor die

[0081] 183: Third semiconductor die

[0082] 185: Grain passivation layer

[0083] 185a: Grain bonding pad

[0084] 190: Ball grid array

[0085] 191: Solder ball

[0086] 240: Lower fiber-reinforced dielectric layer

[0087] 241a: Top portion of dielectric material

[0088] 241b: Bottom portion of dielectric material

[0089] 245: Lower layer metal through hole

[0090] 246: Bonding pad

[0091] 340: Embedded upper fiber-reinforced dielectric layer

[0092] 440: Embedded lower fiber reinforced dielectric layer

[0093] 510, 520, 530, 610, 620, 630, 640: Steps

[0094] O42, O112, O113, O141, O142, O241, O242: Opening

[0095] O115: Solder mask opening

[0096] W110c, W110e: Width Detailed Implementation

[0097] The following discloses many different embodiments or examples to implement the various features provided. Specific examples of elements and their arrangements are described below to illustrate the present invention. These embodiments are merely illustrative and should not be construed as limiting the scope of the present invention. For example, the specification mentions that a first feature is formed on a second feature, which includes embodiments where the first and second feature are in direct contact, and also embodiments where there are other features between the first and second feature, meaning the first and second feature are not in direct contact. Furthermore, repeated reference numerals or designations may be used in different embodiments; these repetitions are merely for the purpose of clearly and simply describing the present invention and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0098] Furthermore, spatially related terms may be used, such as "below," "below," "lower," "above," "higher," and similar terms. These spatially related terms are used to facilitate the description of the relationship between one or more elements or features in the illustrations and to one or more other elements or features. These spatially related terms include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially related adjectives used will also be interpreted according to the orientation after the turn. Unless otherwise expressly stated, each element with the same reference numeral is assumed to have the same material composition and a thickness within the same thickness range.

[0099] A core-based substrate (e.g., an Ajinomoto Build-up Film (ABF) core packaging substrate) may include a core and build-up dielectric layers located on either side of this core. The core may include, for example, glass fiber reinforced in epoxy resin (e.g., FR-4), thermosetting resins such as bismaleimide-triazine (BT resin), polyimide, and / or ceramic materials (e.g., alumina, aluminum nitride). The build-up dielectric layers may include filler-based dielectric films (e.g., epoxy resin, polyimide, etc.) for complete redistribution layers (RDL).

[0100] However, core-based substrates may encounter problems after post-component level reliability (CLR) testing, particularly during thermal cycling (TC) and high-temperature stress (HTS) testing. A major failure mode may be resin film cracking caused by high encapsulation stress. In particular, resin-based dielectric films may not be able to withstand high bending stresses during encapsulation reliability testing. This dielectric film may have weaker portions on the top and / or bottom sides of the encapsulation substrate.

[0101] In applications with large unit dimensions (such as artificial intelligence (AI) and high-performance computing (HPC) applications), the failure rate of the package substrate can be particularly high. Package substrates with large volume and / or multi-layer structures (such as multiple redistribution layers) may generate large packaging stresses, leading to cracks in the package substrate during package-level reliability testing.

[0102] One or more embodiments of this invention may include a robust (e.g., crack-resistant) packaging substrate capable of passing package-level reliability testing (e.g., component-level reliability testing). This packaging substrate may include a fiber-reinforced dielectric layer that strengthens the packaging substrate and prevents cracking of the dielectric film on the top and / or bottom sides of the packaging substrate. The fiber-based dielectric layer within the packaging substrate helps ensure the entire packaging substrate remains intact after component-level reliability testing and inhibits crack propagation based on test results. Simultaneously, the fiber-based dielectric layer maintains the same continuity function as a typical build-up dielectric layer.

[0103] In at least one embodiment, the applied fiber reinforcement layer (e.g., a crack-resistant layer) may be formed on both outer layers of the package substrate. The fiber reinforcement layer enables the package substrate to withstand high stresses from bending at the package level during reliability testing. The fiber reinforcement layer may, for example, include fiber-based dielectric films applied to the top and bottom sides of the package substrate.

[0104] Fiber-based dielectric films may also include blind vias, wiring, and solder pads to maintain continuity. Fiber-based dielectric films (such as crack-resistant layers containing fibers) can protect the package substrate from the effects of packaging-level bending stresses, inhibiting (e.g., preventing) the initial formation of cracks and their propagation into inner layers during reliability testing. Fiber-based dielectric films can enhance rigidity, improve crack resistance on both sides of the package substrate, and ensure that the package substrate remains intact after reliability testing.

[0105] In at least one embodiment, the fiber reinforcement layer (e.g., a crack-resistant layer) may be formed on both sides of the outer layer of the packaging substrate, or it may be formed at other locations. Including an additional fiber reinforcement layer can further improve the crack resistance of the packaging substrate.

[0106] Encapsulation substrates with fiber reinforcement layers (e.g., ABF encapsulation substrates) can withstand package-level reliability testing induced by high stresses from large-size packages (e.g., larger than 60mm x 60mm) in HPC / AI applications. The fiber reinforcement layer can suppress cracking of the package substrate dielectric layer after package-level testing (e.g., thermal cycling and high-temperature stress testing). The encapsulation substrate can be manufactured by applying fiber-based additive films to the top and bottom sides of the outer layer to prevent (e.g., inhibit) initial cracks or crack growth caused by encapsulation stress after reliability testing.

[0107] In at least one embodiment, the components of the packaging substrate may include a core-based ABF substrate, a large volume size, a dielectric layer for wiring, a fiber reinforcement layer (e.g., a dielectric layer containing fiber cloth), a solder mask layer (e.g., a solder mask), solder bumps with a predetermined spacing (e.g., C4 bumps), a plurality of metal vias in the top fiber reinforcement layer, a plurality of vias in the bottom fiber reinforcement layer, a semiconductor module (e.g., chip-on-wafer (CoW), multi-chip module (McM), interposer module, etc.), and a reinforcement ring (e.g., a packaging ring).

[0108] In at least one embodiment, one or more fibers (e.g., fiber layers) may exist in the form of a fabric within the dielectric material of the uplayer of the packaging substrate. These fiber layers may be composed of inorganic materials such as glass, silicon dioxide (SiO2), aluminum oxide (Al2O3), calcium (Ca), boron (B), magnesium (Mg), etc. The volume of the packaging substrate may be greater than approximately 2500 mm². 2 The thickness of the fiber-reinforced dielectric layer can be greater than approximately 20 μm, and the thickness of the contained fiber cloth layer can be greater than approximately 10 μm. The bump spacing of the semiconductor dies or semiconductor modules mounted on the packaging substrate can be greater than approximately 90 μm. The aspect ratio of the metal vias located in the upper fiber-reinforced dielectric layer can be between 0.3 and 1. The aspect ratio of the metal vias located in the lower fiber-reinforced dielectric layer can be between 0.2 and 0.9.

[0109] Figure 1 This is a vertical cross-sectional view of a packaging substrate 110 according to one or more embodiments. The packaging substrate 110 may include a large-sized packaging substrate 110. In at least one embodiment, the area of ​​the packaging substrate 110 (e.g., in the xy plane) may be greater than about 2500 mm². 2In at least one embodiment, the area of ​​the packaging substrate 110 may be greater than approximately 60 mm x 60 mm. In at least one embodiment, the packaging substrate 110 may be used in a packaging structure for high-performance computing (HPC) / artificial intelligence (AI) applications.

[0110] like Figure 1 As shown, the package substrate 110 may include a die mounting region 110a located on the wafer side (e.g., top side) of the package substrate 110. The die mounting region 110a may be configured to subsequently mount one or more semiconductor dies, semiconductor modules, or interposer modules. The package substrate 110 may also include a ring mounting region 110b located on the die side of the package substrate 110. The ring mounting region 110b may at least partially surround the die mounting region 110a. The ring mounting region 110b may be configured to mount a base portion of a reinforcing ring or package cover. The package substrate 110 may also include a separation region 110c separating the ring mounting region 110b from the die mounting region 110a.

[0111] The package substrate 110 may further include a ball-grid array (BGA) region 110d located on the board side (e.g., bottom side) of the package substrate. The ball-grid array region 110d may be configured to mount solder balls 191 of the ball-grid array 190. For example... Figure 1 As shown, the ball grid array region 100d can overlap with the wafer mounting region 100a, the ring mounting region 100b, and the partition region 100c.

[0112] like Figure 1 As further shown, the packaging substrate 110 may include a core 112, a first dielectric layer 114 located on a first side (e.g., the die side) of the core 112, and a second dielectric layer 116 located on a second side (e.g., the board side) of the core 112, wherein the second side of the core 112 is opposite to the first side of the core 112.

[0113] The packaging substrate 110 may further include a fiber-reinforced dielectric layer 20, which may be located on at least one side of the core 112, either a first side or a second side. In at least one embodiment, the fiber-reinforced dielectric layer 20 may include an upper fiber-reinforced dielectric layer 140 located on the first side of the core 112 and a lower fiber-reinforced dielectric layer 240 located on the second side of the core 112. The fiber-reinforced dielectric layer 20 may help suppress cracking in the packaging substrate 110.

[0114] The packaging substrate 110 may include a build-up film substrate, such as an Ajinomoto build-up film (ABF) substrate. That is, in at least one embodiment, each of the first dielectric layer 114 and the second dielectric layer 116 may include an ABF layer. In at least one embodiment, each of the first dielectric layer 114 and the second dielectric layer 116 may include at least five build-up layers.

[0115] Core 112 can help provide rigidity to the packaging substrate 110. Core 112 may include, for example, epoxy resin, bismaleimide-triazine resin (BT resin), polyimide and / or ceramic materials (e.g., alumina, aluminum nitride). Other suitable dielectric materials are also included within the scope of this invention.

[0116] The core 112 may also include a reinforcing material sheet embedded therein. The reinforcing material sheet may, for example, include a sheet of fiberglass cloth (e.g., a woven fiberglass cloth sheet). In at least one embodiment, the core 112 may include a sheet of fiberglass cloth embedded in an epoxy resin (e.g., FR-4). The core 112 may, for example, include a woven fiberglasssheet laminate.

[0117] The core 112 may include one or more through-holes 112a. The through-holes 112a may extend from the lower surface of the core 112 to the upper surface of the core 112. The through-holes 112a may allow electrical coupling between the first dielectric layer 114 and the second dielectric layer 116. The through-holes 112a may include one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), cobalt (Co), ruthenium (Ru), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.). Other suitable metallic materials are also included within the scope of this invention.

[0118] A first dielectric layer 114 may be formed on the upper surface of the core 112. The first dielectric layer 114 may comprise multiple layers, particularly including build-up films (e.g., ABF). The first dielectric layer 114 may also comprise organic materials, such as polymeric materials. Specifically, the first dielectric layer 114 may comprise multiple layers, which may include dielectric polymeric materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also included within the scope of this invention.

[0119] The first dielectric layer 114 may further include one or more first metal interconnect structures 114b. The first metal interconnect structure 114b may include a redistribution layer (RDL) structure. The first metal interconnect structure 114b may contact the through-hole 112a in the core 112. The first metal interconnect structure 114b may include a metal layer (e.g., copper wire) and metal vias connecting the metal layers. The first metal interconnect structure 114b may include an uppermost metal line 114b-U located on the upper surface of the first dielectric layer 114. The first metal interconnect structure 114b may include one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), cobalt (Co), ruthenium (Ru), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.). Other suitable metallic materials are also included within the scope of this invention.

[0120] A second dielectric layer 116 may be formed on the lower surface of the core 112. The second dielectric layer 116 may also comprise multiple layers, particularly including build-up films (e.g., ABF). The second dielectric layer 116 may also comprise organic materials, such as polymeric materials. Specifically, the second dielectric layer 116 may comprise dielectric polymeric materials, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also included within the scope of this invention.

[0121] The second dielectric layer 116 may further include one or more second metal interconnect structures 116b. The second metal interconnect structure 116b may contact the through-hole 112a in the core 112 and may be electrically coupled to the first metal interconnect structure 114b through the through-hole 112a. The second metal interconnect structure 116b may include a metal layer (e.g., copper wire) and metal vias connecting the metal layers. The second metal interconnect structure 116b may include the lowest metal line 116b-L located on the lower surface of the second dielectric layer 116. The second metal interconnect structure 116b may include one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), cobalt (Co), ruthenium (Ru), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.). Other suitable metallic materials are also included within the scope of this invention.

[0122] An upper fiber-reinforced dielectric layer 140 may be formed on the first dielectric layer 114. In at least one embodiment, the upper fiber-reinforced dielectric layer 140 may be included within an extension layer of the first dielectric layer 114. The upper fiber-reinforced dielectric layer 140 may include a dielectric material 141 and one or more fiber sheets 142 embedded in the dielectric material 141. The dielectric material 141 may be similar to the material in the first dielectric layer 114. The dielectric material 141 may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also included within the scope of this invention.

[0123] The thickness of dielectric material 141 (in the z-direction) may be less than the thickness of the first dielectric layer 114. In at least one embodiment, the thickness of dielectric material 141 may be between 10% and 40% of the thickness of the first dielectric layer 114. In at least one embodiment, the thickness of dielectric material 141 may be greater than about 20 μm. In at least one embodiment, the thickness of dielectric material 141 may be at least twice the thickness of fiber sheet 142. Other thicknesses are also included within the scope of this invention.

[0124] The fiber sheet 142 can be configured as a fabric having one or more fiber layers (e.g., fiber layers). The fiber sheet 142 can be composed of inorganic materials such as glass, silicon dioxide (SiO2), aluminum oxide (Al2O3), calcium (Ca), boron (B), magnesium (Mg), etc. Other suitable dielectric materials are also included within the scope of this invention. The thickness of the fiber sheet 142 can be greater than about 10 μm. Other thicknesses are also included within the scope of this invention.

[0125] The upper fiber-reinforced dielectric layer 140 may also include a plurality of upper metal vias 145 (e.g., blind vias with solder on pad (SOP) or pre-solder on the substrate) located in the die mounting region 110a of the package substrate 110. These upper metal vias 145 may be configured to contact solder bumps (e.g., C4 bumps) of semiconductor wafers or semiconductor modules (e.g., interposer modules) mounted on the package substrate 110.

[0126] The spacing of the upper metal vias 145 can be substantially the same as the bump spacing of the semiconductor wafer or semiconductor module to be mounted on the package substrate 110. In at least one embodiment, the spacing of the upper metal vias 145 can be greater than about 90 μm. However, other spacing values ​​for the upper metal vias 145 are also included within the scope of this invention.

[0127] The upper surface of the upper metal via 145 may be substantially coplanar with the upper surface of the dielectric material 141. The upper metal via 145 may extend through an opening in the fiber sheet 142 and contact the uppermost metal line 114b-U of the first metal interconnect structure 114b. The upper metal via 145 may have a substantially trapezoidal cross-sectional shape. The aspect ratio of the upper metal via 145 may be between 0.3 and 1. Other cross-sectional shapes and aspect ratios are also included within the scope of this invention.

[0128] The upper fiber-reinforced dielectric layer 140 may extend to cover the entire package substrate 110. Specifically, the upper fiber-reinforced dielectric layer 140 may be located in the die mounting region 110a, the ring mounting region 110b, and the separation region 110c between the die mounting region 110a and the ring mounting region 110b. The separation region 110c may be particularly prone to cracking, therefore positioning the upper fiber-reinforced dielectric layer 140 in the separation region 110c can particularly help suppress cracks in the package substrate 110 (e.g., cracks in the first dielectric layer 114).

[0129] The packaging substrate 110 may further include an upper solder mask layer 113 (e.g., a solder mask layer) located on the upper fiber-reinforced dielectric layer 140. The upper solder mask layer 113 may comprise a thin polymer material (e.g., an epoxy polymer). The thickness of the upper solder mask layer 113 may be between about 5 μm and 50 μm. In at least one embodiment, the thickness of the upper solder mask layer 113 may be between about 10 μm and 30 μm. Upper solder mask layers 113 with greater or lesser thicknesses may be used.

[0130] The upper solder mask 113 may cover the upper metal vias 145 and other metal features (e.g., conductive lines, copper lines) on the wafer side surface of the package substrate 110. The upper solder mask 113 may protect the upper metal vias 145 and other metal features from oxidation. The upper solder mask 113 may also prevent the formation of solder bridges (e.g., accidental electrical coupling) between metal features that are close to each other.

[0131] A lower fiber-reinforced dielectric layer 240 may be formed on the bottom surface of the second dielectric layer 116. In at least one embodiment, the lower fiber-reinforced dielectric layer 240 may be included within an extension layer of the second dielectric layer 116. The lower fiber-reinforced dielectric layer 240 may include a dielectric material 241 and one or more fiber sheets 242 embedded in the dielectric material 241. The dielectric material 241 may be substantially similar to the material in the second dielectric layer 116. The dielectric material 241 may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also included within the scope of this invention.

[0132] The thickness of dielectric material 241 (in the z-direction) may be less than the thickness of the second dielectric layer 116. In at least one embodiment, the thickness of dielectric material 241 may be between 10% and 40% of the thickness of the second dielectric layer 116. In at least one embodiment, the thickness of dielectric material 241 may be greater than about 20 μm. In at least one embodiment, the thickness of dielectric material 241 may be at least twice the thickness of fiber sheet 142. In at least one embodiment, the thickness of dielectric material 241 may be greater than the thickness of dielectric material 141 in the upper fiber-reinforced dielectric layer 140. Other thicknesses are also included within the scope of this invention.

[0133] The fiber sheet 242 can be configured as a fabric having one or more layers of fibers (e.g., fiber layers). The fiber sheet 242 can be composed of inorganic materials such as glass, silicon dioxide (SiO2), aluminum oxide (Al2O3), calcium (Ca), boron (B), magnesium (Mg), etc. Other suitable dielectric materials are also included within the scope of this invention. The thickness of the fiber sheet 242 can be greater than about 10 μm. Other thicknesses are also included within the scope of this invention.

[0134] The lower fiber-reinforced dielectric layer 240 may also include a plurality of lower metal vias 245 located in the ball grid array region 110d of the package substrate 110. These lower metal vias 245 may be configured to contact the solder balls 191 of the ball grid array 190 to be formed on the board-side surface of the package substrate 110. The spacing of the lower metal vias 245 may be substantially the same as the spacing of the solder balls of the ball grid array 190.

[0135] The spacing of the lower metal vias 245 can be greater than the spacing of the upper metal vias 145. The size of the lower metal vias 245 can be greater than the size of the upper metal vias 145. Specifically, the thickness of the lower metal vias 245 can be greater than the thickness of the upper metal vias 145. The width of the lower metal vias 245 can also be greater than the width of the upper metal vias 145.

[0136] The lower surface of the lower metal via 245 may be substantially coplanar with the lower surface of the dielectric material 241. The lower metal via 245 may extend through an opening in the fiber sheet 142 and contact the lowermost metal line 116b-L of the second metal interconnect structure 116b. The lower metal via 245 may have a substantially trapezoidal cross-sectional shape. The aspect ratio of the lower metal via 245 may be between 0.2 and 0.9. Other cross-sectional shapes and aspect ratios are also included within the scope of this invention.

[0137] like Figure 1As further shown, the package substrate 110 may also include bonding pads 246 that contact the surface of the underlying metal via 245. These bonding pads 246 may be formed on the lower surface of the dielectric material 241. The width of the bonding pads 246 may be greater than the width of the underlying metal via 245. The bonding pads 246 may be configured as the mounting surface of the solder balls 191 of the ball grid array 190. The bonding pads 246 may be made of the same material as the underlying metal via 245. Other materials are also included within the scope of this invention.

[0138] The lower fiber-reinforced dielectric layer 240 may extend to cover the entire package substrate 110. Specifically, the lower fiber-reinforced dielectric layer 240 may be located in the ball grid array region 110d. In at least one embodiment, the lower fiber-reinforced dielectric layer 240 may be located below the separation region 110c, which particularly helps to suppress cracks in the package substrate 110 (e.g., cracks in the second dielectric layer 116).

[0139] The packaging substrate 110 may further include a lower solder mask layer 115 (e.g., a solder mask layer) located on the lower fiber-reinforced dielectric layer 240 and the bonding pads 246. The lower solder mask layer 115 may comprise a thin polymer material (e.g., an epoxy polymer). The thickness of the lower solder mask layer 115 may be between about 5 μm and 50 μm. In at least one embodiment, the thickness of the lower solder mask layer 115 may be between about 10 μm and 30 μm. The lower solder mask layer 115 may have a greater or lesser thickness.

[0140] The lower solder mask 115 may cover the lower metal vias 245 and other metal features (e.g., conductive lines, copper lines) on the side surface of the package substrate 110. The lower solder mask 115 may protect the lower metal vias 245 and other metal features from oxidation. The lower solder mask 115 may also prevent the formation of solder bridges (e.g., accidental electrical coupling) between metal features that are close to each other.

[0141] Figure 2A This is a schematic diagram of fiber sheets 142, 242 in the fiber-reinforced dielectric layer 20 according to one or more embodiments. Figure 2A As shown, fiber sheets 142 and 242 may include fiber mesh sheets. The fiber mesh sheet may include fibers 42 extending along a first direction and fibers 42 extending along a second direction perpendicular to the first direction. These fibers 42 may be composed of glass, silicon dioxide (SiO2), aluminum oxide (Al2O3), calcium (Ca), boron (B), magnesium (Mg), etc. The diameter of the fibers 42 may be greater than about 10 μm. The fiber mesh sheet may also include openings O42 located between the fibers 42. The openings O42 may have a substantially square shape. The area of ​​the openings O42 may be 100 μm. 2 Up to 5000μm 2The scope of this invention also includes openings of varying sizes, both large and small.

[0142] Figure 2B These are images of fiber sheets 142, 242 in a fiber-reinforced dielectric layer 20 having a first alternative configuration, according to one or more embodiments. Figure 2B As shown, the fiber sheets 142 and 242 having a first alternative configuration may include woven fiber cloth. The woven fiber cloth may include fibers 42 extending in a first direction and interwoven with fibers 42 extending in a second direction (perpendicular to the first direction). The weave type of the woven fiber cloth may include plain weave, satin weave, etc. Other types of weave are also included within the scope of this invention. The fibers 42 in the woven fiber cloth may be composed of glass, silicon dioxide (SiO2), aluminum oxide (Al2O3), calcium (Ca), boron (B), magnesium (Mg), etc., and may have a diameter greater than about 10 μm. The woven fiber cloth may also include openings O42 located between the fibers 42. The area of ​​the openings O42 may be 25 μm. 2 Up to 1000μm 2 The scope of this invention also includes openings of varying sizes, both large and small.

[0143] According to one or more embodiments, Figures 3A to 3D Various views of the package structure 100, including the package substrate 110, are shown. According to one or more embodiments, Figure 3A This is a vertical cross-sectional view of the packaging structure 100. According to one or more embodiments, Figure 3B This is a plan view (top view) of the package structure 100. Figure 3A perspective along Figure 3B Line segment A-A' in the diagram. According to one or more embodiments, Figure 3C This is a vertical cross-sectional view of the upper fiber-reinforced dielectric layer 140. According to one or more embodiments, Figure 3D This is a vertical cross-sectional view of the lower fiber-reinforced dielectric layer 240.

[0144] like Figure 3A As shown, the package structure 100 may include a package substrate 110. The package structure 100 may also include a semiconductor module 120 (e.g., wafer-on-wafer (CoW)) mounted on the package substrate 110, and a reinforcing ring 150 surrounding the semiconductor module 120 on the package substrate 110. In at least one embodiment, the semiconductor module 120 may include a high-performance computing (HPC) module of multiple wafers. In at least one embodiment, the semiconductor module 120 may be replaced by a multi-wafer module (McM).

[0145] Semiconductor module 120 can be mounted in die mounting area 110a of packaging substrate 110 (see reference). Figure 1 The reinforcing ring 150 can be mounted on the ring mounting area 110b of the package substrate 110 (see reference). Figure 1 On the semiconductor module 120 and the reinforcing ring 150, the partition region 110c of the encapsulation substrate 110 (see reference). Figure 1 Separate them.

[0146] In at least one embodiment, the semiconductor module 120 may include one or more semiconductor dies 180 located on the interposer layer 10. The semiconductor die 180 may include any combination of a first semiconductor die 181, a second semiconductor die 182, and a third semiconductor die 183. The semiconductor module 120 is not limited to any particular configuration. The semiconductor module 120 may include, for example, a flip chip-chip-chip scale package (FC-CSP) design, a chip-on-wafer-on-substrate (CW-CSP) package design, an integrated fan-out design, etc.

[0147] Interposer 10 is not limited to any particular material or configuration. Interposer 10 may include, for example, organic materials (e.g., dielectric polymers), inorganic materials (e.g., silicon), glass substrates, etc. In at least one embodiment, interposer 10 may include alternating stacked multilayer dielectric material layers 12 and multilayer redistribution layers 12a. The number of dielectric material layers 12 and / or redistribution layers 12a in interposer 10 is not limited to the scope described in this invention.

[0148] In at least one embodiment, the dielectric material layer 12 may include, for example, polyimide (PI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzobisoxazole (PBO), or other suitable polymer-based dielectric materials. The redistribution layer 12a may include a conductive material, such as a metal or metal alloy. In at least one embodiment, the redistribution layer 12a may include copper, aluminum, nickel, titanium, or combinations thereof, or other suitable metals or metal alloys.

[0149] The redistribution layer 12a may include a metallic interconnect structure, i.e., a metallic structure of nodes within an electrically coupled structure. The redistribution layer 12a may include a metal seed layer and a metallic filler material deposited on the metal seed layer. The metal seed layer may, for example, include a stack of a titanium barrier layer and a copper seed layer. The thickness of the titanium barrier layer may be between 50 nm and 500 nm, while the thickness of the copper seed layer may be between 50 nm and 500 nm. The metallic filler material of the redistribution layer 12a may include copper, nickel, or a copper-nickel alloy. Other suitable metallic filler materials are also included within the scope of this invention. The thickness of the metallic filler material deposited in each redistribution layer 12a may be between 2 μm and 40 μm, for example, 4 μm to 10 μm, although smaller or larger thicknesses may also be used.

[0150] In at least one embodiment, the redistribution layer 12a may include a plurality of lines (wires) and a plurality of vias connecting these lines. These lines may be located on the dielectric material layer 12 and extend along the x-direction (first horizontal direction) and y-direction (second horizontal direction) on the upper surface of the dielectric material layer 12.

[0151] The wafer-side surface of the interposer 10 may include an upper passivation layer 13. The upper passivation layer 13 may include, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, benzocyclobutene (BCB), silicon carbide (SiC), phosphosilicate glass (PSG), alumina (Al2O3), titanium nitride (TiN), or combinations thereof or other suitable materials.

[0152] The plate-side surface of the interposer 10 may also include a lower passivation layer 14. The lower passivation layer 14 may be made of the same material as the upper passivation layer 13. The lower passivation layer 14 may, for example, include silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, benzocyclobutene (BCB), silicon carbide (SiC), phosphosilicate glass (PSG), alumina (Al2O3), titanium nitride (TiN), or combinations thereof or other suitable materials.

[0153] Intermediate layer 10 may further include a lower intermediate bonding pad 14a located on the bottom dielectric material layer 12. The lower intermediate bonding pad 14a may bond to and electrically connect to the redistribution layer 12a. The lower intermediate bonding pad 14a may be formed in the lower passivation layer 14. The lower passivation layer 14 may at least partially cover the lower intermediate bonding pad 14a. That is, the lower intermediate bonding pad 14a may at least partially expose the plate-side surface of the intermediate layer 10. The lower intermediate bonding pad 14a may, for example, include one or more layers and may include metals, metal alloys and / or other metal-containing compounds (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), cobalt (Co), ruthenium (Ru), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), etc.). Other suitable metallic materials are also included within the scope of this invention.

[0154] The semiconductor module 120 may also include a plurality of C4 bumps 121 located on the side surface of the interposer 10. These C4 bumps 121 may be formed on the under-interposer bonding pads 14a on the side surface of the interposer 10. The C4 bumps 121 may engage and electrically couple to the upper metal vias 145 in the upper fiber-reinforced dielectric layer 140. The C4 bumps 121 may include a pre-soldered metal layer (UBM layer) (not shown) located on the under-interposer bonding pads 14a. The C4 bumps 121 may also include contact pads (e.g., copper / nickel contact pads) (not shown) located on the UBM layer, and solder bumps (e.g., tin-silver (SnAg) solder bumps) located on the contact pads.

[0155] Semiconductor dies 180 may be attached to the wafer side of the interposer layer 10. Semiconductor dies 180 may include one or more first semiconductor dies 181, one or more second semiconductor dies 182, and one or more third semiconductor dies 183. In at least one embodiment, the first semiconductor die 181 may include a system-on-chip (SoC) die, the second semiconductor die 182 may include a high bandwidth memory (HBM) die, and the third semiconductor die 183 may include an input / output (I / O) die. Although the illustrated semiconductor module 120 includes a specific number of semiconductor dies 180 and has a specific size and arrangement, the number, size, and arrangement of the semiconductor dies 180 are not limited to any specific number, size, and arrangement. Specifically, the semiconductor module 120 may include any number, size, and arrangement of semiconductor dies 180.

[0156] Generally speaking, the thickness of each semiconductor die 180 is substantially the same in the z direction. Therefore, the upper surfaces of each first semiconductor die 181, second semiconductor die 182 and third semiconductor die 183 are substantially coplanar (e.g., located in the same xy plane) and are collectively referred to as semiconductor die upper surface 180a.

[0157] Each semiconductor die 180 may include, for example, a single semiconductor die structure, a system-on-a-chip (SoC), or an integrated system-on-a-chip (SoC), and may be implemented using on-wafer-on-substrate packaging technology or on-substrate integrated fan-out technology. Specifically, each semiconductor die 180 may include semiconductor wafers or chiplets, logic dies (e.g., mobile application processors, microcontrollers, etc.), or memory dies (e.g., high bandwidth memory (HBM) dies, hybrid memory cube (HMC) dies, dynamic random access memory (DRAM) dies, wide I / O dies, M-RAM dies, R-RAM dies, NAND dies, static random access memory (SRAM) dies, etc.) for high-performance computing (HPC) applications, artificial intelligence (AI) applications, or 5G mobile network applications. Other related components include central processing unit (CPU) chips, graphics processing unit (GPU) chips, field-programmable gate array (FPGA) chips, network chips, application-specific integrated circuit (ASIC) chips, and artificial intelligence / deep neural network chips. Network (AI / DNN) accelerator chips, coprocessors, accelerators, on-chip buffer memory, high-speed data transmission receiver chips, I / O interface chips, IPD chips, power management chips (e.g., power management integrated circuit (PMIC) chips), radio frequency (RF) chips, sensor chips, micro-electro-mechanical-system (MEMS) chips, signal processing chips (e.g., digital signal processing (DSP) chips), front-end chips (e.g., analog front-end (AFE) chips), monolithic 3D heterogeneous chiplet stacking dies, etc. Other chips are also within the scope of this invention.In at least one embodiment, the first semiconductor die 181 may include a master die (e.g., a SoC die), while the second semiconductor die 182 and the third semiconductor die 183 may include auxiliary dies (e.g., memory / SoC dies, HBM dies, etc.).

[0158] The bottom surface of the semiconductor die 180 may include a grain passivation layer 185. The grain passivation layer 185 may include, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, benzocyclobutene (BCB), silicon carbide (SiC), phosphosilicate glass (PSG), alumina (Al2O3), titanium nitride (TiN), or combinations thereof or other suitable materials.

[0159] The semiconductor die 180 may also include a die bonding pad 185a located in the die passivation layer 185. The die bonding pad 185a may be electrically connected to the redistribution layer 12a of the interposer layer 10 via microbumps 128. The die bonding pad 185a may include one or more layers, and may include metals, metal alloys and / or other metal-containing compounds (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), cobalt (Co), ruthenium (Ru), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), etc.). Other suitable metallic materials are also included within the scope of this invention.

[0160] The semiconductor module 120 may also include an upper molding layer 127 surrounding the semiconductor die 180. The outer sidewalls of the upper molding layer 127 may be substantially aligned with the outer sidewalls of the interposer 10. The upper surface of the upper molding layer 127 may be substantially uniform (e.g., flat) and substantially coplanar with the upper surface 180a of the semiconductor die 180.

[0161] The upper molding layer 127 may be formed on the outer sidewall of each semiconductor die 180. The upper molding layer 127 may be bonded to the outer sidewall of each semiconductor die 180. The upper molding layer 127 may also fill the inter-die gaps between semiconductor dies 180 and be bonded to the inner sidewall of semiconductor die 180. The upper molding layer 127 may also be bonded to the wafer side surface of the interposer 10 (e.g., the upper passivation layer 13).

[0162] In at least one embodiment, the upper molding layer 127 may be made of a curable material that, upon curing, forms a rigid solid structure. The upper molding layer 127 may, for example, comprise an epoxy molding compound (EMC). In at least one embodiment, the upper molding layer 127 may comprise a polymeric material, particularly an epoxy-based polymeric material. Other suitable molding materials may also be used.

[0163] In at least one embodiment, the coefficient of thermal expansion (CTE) of the upper molding layer 127 may be substantially the same as that of the intermediate layer 10. In at least one embodiment, the upper molding layer 127 may include materials (e.g., filler materials added to a polymer material) added to improve its properties (e.g., thermal conductivity, coefficient of thermal expansion, etc.). The added materials may include, for example, metal powders, metal oxide powders, etc. Other materials in the upper molding layer 127 are also included within the scope of this invention.

[0164] A reinforcing ring 150 may be mounted on a packaging substrate 110 and surround the semiconductor module 120. The reinforcing ring 150 may be securely attached to the packaging substrate 110 using an adhesive 160 (e.g., silicone adhesive or epoxy adhesive). The reinforcing ring 150 may be made of metal, such as nickel-plated copper or aluminum alloy. The reinforcing ring 150 provides rigidity to the packaging substrate 110. In at least one embodiment, a package cap may be used instead of the reinforcing ring 150, covering the semiconductor module 120 and secured to the packaging substrate 110 by the adhesive 160.

[0165] The ball grid array (BGA) 190 includes multiple solder balls 191 and can be formed on the board-side surface of the package substrate 110. The solder balls 191 enable the package structure 100 to be securely mounted on a substrate, such as a printed circuit board (PCB), and electrically coupled to the PCB substrate. The solder balls 191 can contact bonding pads 246 on the underlying fiber-reinforced dielectric layer 240.

[0166] Refer again Figure 3B For ease of understanding, Figure 3B The bottom filler layer 129 of the package is omitted. For example... Figure 3B As shown, the semiconductor module 120 may be located in the central region of the packaging substrate 110. The center of the semiconductor module 120 (in the x and y directions) may be substantially aligned with the center of the packaging substrate 110. The semiconductor module 120 may have a substantially rectangular shape. Other shapes are also included within the scope of this invention.

[0167] The partition region 110c of the packaging substrate 110 may surround the entire periphery of the semiconductor module 120. The partition region 110c may have a substantially uniform width W110c over the entire periphery of the semiconductor module 120. The partition region 110c may have a substantially frame-like shape.

[0168] The reinforcing ring 150 may form around the entire periphery of the semiconductor module 120. The solder balls 191 of the ball grid array 190 may be located below the reinforcing ring 150 and below the semiconductor module 120. The reinforcing ring 150 may have a frame shape. The reinforcing ring 150 may have a substantially rectangular shape. Other shapes are also included within the scope of this invention. The center of the reinforcing ring 150 (in both the x and y directions) may be substantially aligned with the center of the package substrate 110 and / or the semiconductor module 120.

[0169] The packaging substrate 110 may include an outer packaging substrate region 110e located between the reinforcing ring 150 and the outer edge of the packaging substrate 110. The width of the outer packaging substrate region 110e is W110e. The width W110e may be substantially uniform over the entire periphery of the reinforcing ring 150. In at least one embodiment, the width W110e of the outer packaging substrate region 110e may be smaller than the width W110c of the separating region 110c.

[0170] like Figure 3B As further shown, the packaging substrate 110 may have a substantially rectangular shape. Other shapes are also included within the scope of this invention. The outer edges of the upper fiber-reinforced dielectric layer 140 and the lower fiber-reinforced dielectric layer 240 may be substantially the same as the outer edge of the packaging substrate 110. Specifically, both the upper fiber-reinforced dielectric layer 140 and the lower fiber-reinforced dielectric layer 240 may be formed over the entire area of ​​the packaging substrate 110.

[0171] like Figure 3C As shown, the dielectric material 141 in the upper fiber-reinforced dielectric layer 140 may include a top portion 141a of dielectric material located above the fiber sheet 142. The thickness of the top portion 141a of dielectric material may be at least 5% of the total thickness of the upper fiber-reinforced dielectric layer 140. The dielectric material 141 may also include a bottom portion 141b of dielectric material located below the fiber sheet 142. The thickness of the bottom portion 141b of dielectric material may also be at least 5% of the total thickness of the upper fiber-reinforced dielectric layer 140. The dielectric material 141 may also include a connecting portion (not shown) that connects the top portion 141a of dielectric material to the bottom portion 141b of dielectric material through an opening O42 in the fiber sheet 142 (see reference). Figure 2A and Figure 2B ).

[0172] like Figure 3C As further shown, the upper metal via 145 in the upper fiber-reinforced dielectric layer 140 can extend along the z-direction through the opening O141 in the dielectric material 141 and the opening O142 in the fiber sheet 142. The diameter of the opening O142 can range from 105% to 125% of the maximum diameter of the upper metal via 145.

[0173] like Figure 3D As shown, the dielectric material 241 in the lower fiber-reinforced dielectric layer 240 may include a top portion 241a of dielectric material located above the fiber sheet 142. The thickness of the top portion 241a of dielectric material may be at least 5% of the total thickness of the lower fiber-reinforced dielectric layer 240. The dielectric material 241 may also include a bottom portion 241b of dielectric material located below the fiber sheet 142. The thickness of the bottom portion 241b of dielectric material may also be at least 5% of the total thickness of the lower fiber-reinforced dielectric layer 240. The dielectric material 241 may also include a connecting portion (not shown) that connects the top portion 241a of dielectric material to the bottom portion 241b of dielectric material through an opening O42 in the fiber sheet 142 (see reference). Figure 2A and Figure 2B ).

[0174] like Figure 3D As further shown, the lower metal via 245 in the lower fiber-reinforced dielectric layer 240 can extend along the z-direction through the opening O241 in the dielectric material 241 and the opening O242 in the fiber sheet 142. The diameter of the opening O242 can range from 105% to 125% of the maximum diameter of the lower metal via 245.

[0175] Figures 4A to 4I A vertical cross-sectional view of an intermediate structure of a method for manufacturing a package structure 100 according to one or more embodiments is shown.

[0176] Figure 4A This is a vertical cross-sectional view of an intermediate structure including a first dielectric layer 114 formed on a core 112, according to one or more embodiments. The core 112 can be formed by forming an opening O112 in a core material layer (e.g., epoxy resin, fiberglass laminate, etc.). The opening O112 can be formed, for example, by a laser etching process. Alternatively, the opening O112 can also be formed by a photolithography process. The photolithography process may include forming a patterned photoresist mask (not shown) on the core material layer and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the core material layer through the opening in the photoresist mask. The photoresist mask can then be removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during the etching process.

[0177] A through-hole 112a can then be formed in the opening O112 (e.g., a via in the core 112). The through-hole 112a can be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive material) in the opening O112 and on the upper surface of the core material layer, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques. The metal layer can be deposited using CVD, PVD, or other suitable processes. The metal layer can then be etched using processes such as wet etching or dry etching to form the through-hole 112a and complete the fabrication of the core 112.

[0178] A first dielectric layer 114 may then be formed on the core 112. The first dielectric layer 114 may include multiple dielectric layers, for example, formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination or other suitable deposition techniques.

[0179] During the formation of the multilayer dielectric layer 114, the metal layers (e.g., circuits) and metal vias of the first metal interconnect structure 114b can be formed layer by layer. The first metal interconnect structure 114b can be formed to contact the through-hole 112a in the core 112. The formation of the first dielectric layer 114 is completed as the uppermost metal line 114b-U is formed on the upper surface of the first dielectric layer 114.

[0180] The metal layer (e.g., circuitry) and metal vias of the first metal interconnect structure 114b can be formed using a semi-additive process (SAP). The semi-additive process may include depositing a seed layer (e.g., a copper seed layer) on a dielectric layer (e.g., using electroless copper plating techniques such as CVD, PVD, or other suitable processes), depositing a photoresist layer on the seed layer (e.g., using CVD, PVD, or other suitable processes), exposing and developing the photoresist layer to form a patterned photoresist layer, electroplating the exposed areas of the seed layer through openings in the patterned photoresist layer, stripping the photoresist layer, and etching away the unplated portions of the seed layer.

[0181] Figure 4BThis is a vertical cross-sectional view of an intermediate structure including an upper fiber-reinforced dielectric layer 140 according to one or more embodiments. The upper fiber-reinforced dielectric layer 140 can be formed on a first dielectric layer 114 through a series of steps. First, a bottom portion 141b of dielectric material can be deposited on the first dielectric layer 114 (e.g., by CVD, PVD, or other suitable processes). Then, a fiber sheet 142 can be placed on the bottom portion 141b of dielectric material. In at least one embodiment, the fiber sheet 142 can be placed on the bottom portion 141b of dielectric material using an electromechanical pick-and-place (PNP) machine. Subsequently, a top portion 141a of dielectric material can be deposited on the fiber sheet 142 (e.g., by CVD, PVD, or other suitable processes). The top portion 141a of dielectric material can be deposited on the surface of the bottom portion 141b of dielectric material through an opening O142 in the fiber sheet 142 (see reference). Figures 2A to 2B ).

[0182] The openings O142 in the fiber sheet 142 and the openings O141 in the dielectric material 141 can be formed in the same step. For example, the openings O141 and O142 can be formed by a laser etching process. The openings O141 and O142 can also be formed by a photolithography process. The photolithography process may include forming a patterned photoresist mask (not shown) on the dielectric material 141 and etching the exposed upper surface of the dielectric material 141 through the openings in the photoresist mask (e.g., wet etching, dry etching, etc.). The photoresist mask can then be removed by ashing, dissolving, or consuming the photoresist mask during the etching process.

[0183] Upper metal vias 145 can then be formed in openings O141 and O142. Upper metal vias 145 can be formed to contact the uppermost metal line 114b-U of the first metal interconnect structure 114b. Upper metal vias 145 can be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive material) on the dielectric material 141 and in openings O141 and O142. The metal layer on the upper surface of the dielectric material 141 can then be removed by etching (e.g., wet etching, dry etching, etc.) to form the upper metal vias 145. An upper solder mask layer 113 can then be formed on the upper fiber-reinforced dielectric layer 140 using CVD, PVD, or other suitable deposition processes.

[0184] Figure 4C This is a vertical cross-sectional view of an intermediate structure including a second dielectric layer 116 according to one or more embodiments. Figure 4C As shown, it can be flipped. Figure 4B The intermediate structure in the core 112 forms a second dielectric layer 116.

[0185] The formation process of the second dielectric layer 116 can be substantially similar to that of the first dielectric layer 114. The second dielectric layer 116 may comprise multiple dielectric layers, for example, formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination, or other suitable deposition techniques. The metal layers (e.g., circuitry) and metal vias of the second metal interconnect structure 116b can be formed layer by layer during the formation of the multilayer dielectric layers of the second dielectric layer 116. The second metal interconnect structure 116b can be formed to contact the through-hole 112a in the core 112. The formation of the second dielectric layer 116 is completed as the bottommost metal line 116b-L is formed on the lower surface of the second dielectric layer 116. The metal layers (e.g., circuitry) and metal vias of the second metal interconnect structure 116b can also be formed by a semi-additive process (SAP) associated with the first metal interconnect structure 114b.

[0186] Figure 4D This is a vertical cross-sectional view of an intermediate structure including a lower fiber-reinforced dielectric layer 240 according to one or more embodiments. The lower fiber-reinforced dielectric layer 240 can be formed on a second dielectric layer 116 through a series of steps. First, a top portion 241a of dielectric material can be deposited on the second dielectric layer 116 (e.g., by CVD, PVD, or other suitable processes). Then, a fiber sheet 142 can be placed on the top portion 241a of dielectric material. In at least one embodiment, the fiber sheet 142 can be placed on a bottom portion 241b of dielectric material using a motor mechanical pick-and-place (PNP) machine. Subsequently, the bottom portion 241b of dielectric material can be deposited on the fiber sheet 142 (e.g., by CVD, PVD, or other suitable processes). The bottom portion 241b of dielectric material can be deposited on the surface of the top portion 241a of dielectric material through an opening O42 in the fiber sheet 142 (see reference). Figures 2A to 2B ).

[0187] The openings O242 in the fiber sheet 142 and the dielectric material 241 can be formed in the same step. The openings O241 and O242 can be formed, for example, by a laser etching process. Alternatively, they can be formed by a photolithography process. The photolithography process may include forming a patterned photoresist mask (not shown) on the dielectric material 241 and etching the exposed upper surface of the dielectric material 241 through the openings in the photoresist mask (e.g., wet etching, dry etching, etc.). The photoresist mask can then be removed by ashing, dissolving, or consuming it during the etching process.

[0188] A lower metal via 245 can then be formed in openings O241 and O242. The lower metal via 245 can be formed to contact the lowest metal line 116b-L of the second metal interconnect structure 116b. The lower metal via 245 can be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive material) on the dielectric material 241 and in openings O241 and O242. The metal layer on the upper surface of the dielectric material 241 can then be removed by etching (e.g., wet etching, dry etching, etc.) to form the lower metal via 245. A lower solder mask layer 115 can then be formed on the lower fiber-reinforced dielectric layer 240 using CVD, PVD, or other suitable deposition processes.

[0189] Figure 4E A vertical cross-sectional view of an intermediate structure according to one or more embodiments is shown, wherein the semiconductor module 120 may be mounted on the package substrate 110 (e.g., via a flip chip bonding (FCB) process).

[0190] Solder resist openings (SROs) O113 may be formed on the upper metal via 145 to expose the upper surface of the upper metal via 145. The solder resist openings O113 may be formed by a photolithography process. The photolithography process may include forming a patterned photoresist mask (not shown) on the upper solder resist layer 113 and etching the exposed upper surface of the upper solder resist layer 113 through openings in the photoresist mask (e.g., wet etching, dry etching, etc.). The photoresist mask may subsequently be removed by ashing, dissolving, or consuming it during the etching process. The solder resist openings O113 may have tapered sidewalls, thus reducing the diameter (in the XY plane) of the solder resist openings O113 in the direction toward the upper metal via 145.

[0191] The semiconductor module 120 can be placed above the package substrate 110 (e.g., via a PNP machine) such that the C4 bump 121 of the semiconductor module 120 is positioned above the upper metal via 145 on the package substrate 110. The semiconductor module 120 can then be lowered so that the C4 bump 121 contacts the upper surface of the upper metal via 145. An intermediate structure can then be heated to bond the solder portion of the C4 bump 121 to the portion of the upper metal via 145 exposed through the upper solder mask layer 113.

[0192] Figure 4F A vertical cross-sectional view of an intermediate structure according to one or more embodiments is shown, wherein an encapsulation underfill layer 129 may be formed on an encapsulation substrate 110. The encapsulation underfill layer 129 may be made of an epoxy resin-based polymer material. Figure 4FAs shown, an underfill layer 129 can be formed below and around the semiconductor module 120 and the C4 bump 121 to secure the semiconductor module 120 to the package substrate 110. The underfill layer 129 can then be cured, for example, by heating in a box oven at about 150°C for about 90 minutes, to give it sufficient rigidity and mechanical strength.

[0193] Figure 4G A vertical cross-sectional view of an intermediate structure according to one or more embodiments is shown, wherein an adhesive 160 may be applied to a packaging substrate 110. The adhesive 160 may include, for example, a silicone adhesive or an epoxy adhesive. The adhesive 160 may be applied, for example, to the ring mounting region 100b of the packaging substrate 110 (see reference). Figure 1 The width and shape of the adhesive 160 may correspond to the width and shape of the reinforcing ring 150. The adhesive 160 may be formed as a continuous bead surrounding the semiconductor module 120. The adhesive 160 may be dispensed in sufficient quantity onto the surface of the package substrate 110 to ensure that the reinforcing ring 150 is firmly bonded to the package substrate 110.

[0194] Figure 4H The figure shows a vertical cross-sectional view of an intermediate structure according to one or more embodiments, wherein a reinforcing ring 150 may be attached to (e.g., mounted on) a package substrate 110. The reinforcing ring 150 may be made of a metallic material (e.g., aluminum) and may be formed by milling using a computer numerical control (CNC) milling machine.

[0195] A packaging substrate 110 with a semiconductor module 120 can be placed on a surface, and then a reinforcing ring 150 is lowered onto the packaging substrate 110 to surround the semiconductor module 120. The reinforcing ring 150 can then be aligned with an adhesive 160 formed on the packaging substrate 110. Pressure can then be applied downward to secure the reinforcing ring 150 to the packaging substrate 110 using the adhesive 160.

[0196] Alternatively, the reinforcing ring 150 can be placed on a surface (e.g., a flat surface), and then the package substrate 110 can be inverted and lowered onto the reinforcing ring 150. That is, the semiconductor module 120 is inserted into the reinforcing ring 150. The package substrate 110 and the semiconductor module 120 can then be pressed into the reinforcing ring 150 by applying pressure, thereby securing the reinforcing ring 150 to the package substrate 110 by the adhesive 160.

[0197] The reinforcing ring 150 can be clamped onto the packaging substrate 110 for a certain period of time to allow the adhesive 160 to cure and form a strong bond between the packaging substrate 110 and the reinforcing ring 150. The reinforcing ring 150 can be clamped, for example, by using a thermal clamping module. The thermal clamping module can apply uniform pressure to the upper surface of the reinforcing ring 150.

[0198] Figure 4I A vertical cross-sectional view of an intermediate structure according to one or more embodiments is shown, wherein a plurality of solder balls 191 may be formed on a package substrate 110.

[0199] Solder mask openings (SROs) O115 can be formed above each bonding pad 246 to expose the surface of the bonding pad 246. The solder mask openings O115 can be formed by a photolithography process. The photolithography process may include forming a patterned photoresist mask (not shown) on the lower solder mask layer 115 and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the lower solder mask layer 115 through openings in the photoresist mask. The photoresist mask can then be removed by ashing, dissolving, or consuming it during the etching process. The solder mask openings O115 may have tapered sidewalls, so that the diameter of the solder mask openings O115 (in the XY plane) can decrease in the direction toward the bonding pad 246.

[0200] Solder balls 191 can be formed on bonding pads 246 using an electroplating process. Solder balls 191 can contact bonding pads 246 through openings in solder mask openings O115. Solder balls 191 can form a ball grid array (BGA) 190, enabling the semiconductor package 100 to be securely mounted on and electrically coupled to a substrate (e.g., a printed circuit board). Solder balls 191 can be located, for example, below reinforcing ring 150 and semiconductor module 120.

[0201] Figure 5 This is a flowchart of a method for manufacturing a semiconductor package according to one or more embodiments. Step 510 includes forming a first dielectric layer on a first side of the core. Step 520 includes forming a second dielectric layer on a second side of the core (i.e., the side opposite to the first side of the core). Step 530 includes forming a fiber-reinforced dielectric layer on at least one of the first or second side of the core.

[0202] Figure 6This is a flowchart of a method for manufacturing a semiconductor package according to one or more embodiments. Step 610 includes forming a package substrate, the package substrate including a core and a fiber-reinforced dielectric layer on a first side or a second side of the core, wherein the first side is opposite to the second side. Step 620 includes mounting a semiconductor module on the package substrate and on the first side of the core. Step 630 includes mounting a reinforcing ring around the semiconductor module on the package substrate and on the first side of the core. Step 640 includes forming a ball grid array on the second side of the package substrate and the core.

[0203] Figure 7 This is a vertical cross-sectional view of a package structure having a first alternative configuration according to one or more embodiments. For example... Figure 7 As shown, the packaging structure with the first alternative configuration and Figures 3A to 3D The encapsulation structures are substantially similar. However, the encapsulation structure 100 with a first alternative configuration may include an embedded upper fiber-reinforced dielectric layer 340 embedded in a first dielectric layer 114. At least a portion of the first dielectric layer 114 may be formed above the embedded upper fiber-reinforced dielectric layer 340, and at least a portion of the first dielectric layer 114 may be formed below the embedded upper fiber-reinforced dielectric layer 340. The embedded upper fiber-reinforced dielectric layer 340 may be substantially similar to the upper fiber-reinforced dielectric layer 140. Specifically, the embedded upper fiber-reinforced dielectric layer 340 may include a dielectric material 341 (substantially the same as dielectric material 141) and fiber sheets 342 (substantially the same as fiber sheets 142) within the dielectric material 341. However, unlike the upper fiber-reinforced dielectric layer 140, the embedded upper fiber-reinforced dielectric layer 340 may not include an upper metal via 145. Furthermore, the embedded upper fiber-reinforced dielectric layer 340 may include a portion of the first metal interconnect structure 114b. Specifically, the first metal interconnect structure 114b may be continuously formed in the embedded upper fiber-reinforced dielectric layer 340.

[0204] The package structure 100 with the first alternative configuration may further include an embedded under-fiber reinforced dielectric layer 440 embedded in the second dielectric layer 116. At least a portion of the second dielectric layer 116 may be formed above the embedded under-fiber reinforced dielectric layer 440, and at least a portion of the second dielectric layer 116 may be formed below the embedded under-fiber reinforced dielectric layer 440. The embedded under-fiber reinforced dielectric layer 440 may be substantially similar to the under-fiber reinforced dielectric layer 240. Specifically, the embedded under-fiber reinforced dielectric layer 440 may include a dielectric material 441 (substantially the same as dielectric material 241) and fiber sheets 442 (substantially the same as fiber sheets 142) within the dielectric material 441. However, unlike the under-fiber reinforced dielectric layer 240, the embedded under-fiber reinforced dielectric layer 440 may not include an under-metal via 245. Furthermore, the embedded under-fiber reinforced dielectric layer 440 may include a portion of the second metal interconnect structure 116b. Specifically, the second metal interconnect structure 116b may be continuously formed in the embedded under-fiber reinforced dielectric layer 440.

[0205] Figures 8A to 8B Various views of a package structure 100 having a second alternative configuration according to one or more embodiments are shown. Figure 8A It is a vertical cross-sectional view of a package structure 100 having a second alternative configuration according to one or more embodiments. Figure 8B It is a top view (plan view) of a package structure 100 having a second alternative configuration according to one or more embodiments. Figure 8A The perspective along Figure 8B Line segment B-B' in the diagram.

[0206] like Figure 8A As shown, the packaging structure 100 with the second alternative configuration can be used with... Figures 3A to 3D The packaging structure 100 is substantially the same. Specifically, in the second alternative configuration, the positions of dielectric material 141 and dielectric material 241 are the same as... Figures 3A to 3D The same as in. However, with Figures 3A to 3D Unlike the encapsulation structure 100 in the second alternative configuration, the fiber sheet 142 of the encapsulation structure 100 is located only in a portion of the upper fiber-reinforced dielectric layer 140, and the fiber sheet 142 is located only in a portion of the lower fiber-reinforced dielectric layer 240.

[0207] Reference Figure 8B The position of fiber sheet 142 is indicated by shading. Figure 8B The dashed line in the figure represents the outline of the position of fiber sheet 142.

[0208] like Figure 8BAs shown, the outer edges of dielectric material 141 and dielectric material 241 can be substantially aligned with the outer edge of the packaging substrate 110. However, the fiber sheet 142 is not necessarily located in the entire area of ​​dielectric material 141 and dielectric material 241. Instead, the fiber sheet 142 can be in a frame shape and located below the inner region of reinforcing ring 150 and the outer region of semiconductor module 120. Specifically, the fiber sheet 142 can be located in the partition region 110c, which is particularly prone to cracking.

[0209] Reference Figures 1 to 8B The packaging substrate 110 may include a core 112, a first dielectric layer 114 located on a first side of the core 112, a second dielectric layer 116 located on a second side of the core 112 (opposite to the first side), and at least one fiber-reinforced dielectric layer 20 located on the first or second side of the core 112.

[0210] In some embodiments, the fiber-reinforced dielectric layer 20 may include dielectric materials 141, 241 and fiber sheets 142, 242 embedded in the dielectric materials 141, 241. In some embodiments, the fiber sheets 142, 242 may include inorganic materials, including at least one of glass, silicon dioxide (SiO2), aluminum oxide (Al2O3), calcium (Ca), boron (B), or magnesium (Mg). In some embodiments, the fiber sheets 142, 242 may include woven fiber sheets or fiber mesh sheets. In some embodiments, the packaging substrate 110 may further include a die mounting region 110a, a ring mounting region 110b located adjacent to the die mounting region 110a, and a separation region 110c located between the die mounting region 110a and the ring mounting region 110b, wherein the fiber-reinforced dielectric layer 20 may be located in the separation region 110c. In some embodiments, the fiber-reinforced dielectric layer 20 may include an upper fiber-reinforced dielectric layer 140 located on a first side of the core 112 and a lower fiber-reinforced dielectric layer 240 located on a second side of the core 112. In some embodiments, the upper fiber-reinforced dielectric layer 140 may be located on the upper surface of the first dielectric layer 114 and may also include a plurality of upper metal vias 145 extending through the fiber sheet 142. In some embodiments, the first dielectric layer 114 may include a plurality of first metal interconnect structures 114b, and the plurality of upper metal vias 145 may be electrically coupled to the plurality of first metal interconnect structures 114b. In some embodiments, the fiber-reinforced dielectric layer 20 may also include an embedded upper fiber-reinforced dielectric layer 340 embedded in the first dielectric layer 114. In some embodiments, the lower fiber-reinforced dielectric layer 240 may be located on the lower surface of the second dielectric layer 116 and may also include a plurality of lower metal vias 245 extending through the fiber sheet 242. In some embodiments, the second dielectric layer 116 may include a plurality of second metal interconnect structures 116b, and a plurality of underlying metal vias 245 may be electrically coupled to the plurality of second metal interconnect structures 116b. In some embodiments, the fiber-reinforced dielectric layer 20 may further include an embedded underlying fiber-reinforced dielectric layer 440 embedded in the second dielectric layer 116.

[0211] Refer again Figures 1 to 8B The packaging structure 100 may include a packaging substrate 110, the packaging substrate 110 includes a core 112, the core 112 includes a plurality of through holes 112a, and an upper fiber-reinforced dielectric layer 140 located on a first side of the core 112, which includes a plurality of upper metal vias 145 electrically coupled to the plurality of through holes 112a, and a semiconductor module 120 is attached to the packaging substrate 110 on the first side of the core 112 and includes a plurality of C4 bumps 121 that respectively contact the plurality of upper metal vias 145.

[0212] In some embodiments, the package structure 100 may further include a reinforcing ring 150 surrounding the semiconductor module 120 on the package substrate 110, wherein the package substrate 110 may include a separation region 110c separating the reinforcing ring 150 from the semiconductor module 120, and an upper fiber-reinforced dielectric layer 140 is located in the separation region 110c. The package structure 100 may further include a lower fiber-reinforced dielectric layer 240 located on the second side of the core 112, which includes a plurality of lower metal vias 245 and a ball grid array (BGA) 190 attached to the package substrate 110 on the second side of the core 112, the ball grid array 190 being electrically coupled to the plurality of lower metal vias 245 through a plurality of through-holes 112a in the core 112. The package structure 100 may further include a first dielectric layer 114 located between the core 112 and the upper fiber-reinforced dielectric layer 140, and a second dielectric layer 116 located between the core 112 and the lower fiber-reinforced dielectric layer 240. The encapsulation structure 100 may further include an embedded upper fiber-reinforced dielectric layer 340 embedded in a first dielectric layer 114, and an embedded lower fiber-reinforced dielectric layer 440 embedded in a second dielectric layer 116. The upper fiber-reinforced dielectric layer 140 is located on the upper surface of the first dielectric layer 114 and includes a dielectric material 141 and fiber sheets 142 within the dielectric material 141, wherein a plurality of upper metal vias 145 in the dielectric material 141 can extend through the fiber sheets 142. The lower fiber-reinforced dielectric layer 240 is located on the lower surface of the second dielectric layer 116 and includes a dielectric material 241 and fiber sheets 242 within the dielectric material 241, wherein a plurality of lower metal vias 245 in the dielectric material 241 can extend through the fiber sheets 242.

[0213] Refer again Figures 1 to 8B The method of forming the encapsulation substrate 110 includes forming a first dielectric layer 114 on a first side of the core 112, forming a second dielectric layer 116 on a second side of the core 112 (i.e., the side opposite to the first side of the core 112), and forming a fiber-reinforced dielectric layer 20 on at least one side of the first side and the second side of the core 112.

[0214] The foregoing outlines the features of many embodiments, thus enabling those skilled in the art to better understand various aspects of this invention. Those skilled in the art may readily design or modify other processes and structures based on this invention to achieve the same objectives and / or obtain the same advantages as the embodiments of this invention. It should also be understood by those skilled in the art that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this invention, and such equivalent creations do not exceed the spirit and scope of this invention.

Claims

1. A package substrate, characterized by, include: One core; A first dielectric layer is located on a first side of the core; A second dielectric layer is located on a second side of the core, the second side being opposite to the first side of the core; and A fiber-reinforced dielectric layer is located on at least one of the first side and the second side of the core.

2. The package substrate of claim 1, wherein, The fiber-reinforced dielectric layer includes a dielectric material and a fiber sheet, wherein the fiber sheet is embedded in the dielectric material, and the fiber sheet includes either a woven fiber sheet or a fiber mesh sheet.

3. The package substrate of claim 1, wherein, Also includes: One-chip mounting area; A ring mounting area, adjacent to the die mounting area; and A separation region is located between the grain mounting region and the ring mounting region, wherein the fiber-reinforced dielectric layer is located in the separation region.

4. The package substrate of claim 1, wherein, The fiber-reinforced dielectric layer includes: A fiber-reinforced dielectric layer is located on the first side of the core; and A lower fiber-reinforced dielectric layer is located on the second side of the core.

5. The package substrate of claim 4, wherein, The upper fiber-reinforced dielectric layer is located on an upper surface of the first dielectric layer, and the upper fiber-reinforced dielectric layer includes a fiber sheet and a plurality of upper metal vias, the plurality of upper metal vias extending through the fiber sheet, wherein the first dielectric layer includes a plurality of first metal interconnect structures, and the plurality of upper metal vias are electrically coupled to the plurality of first metal interconnect structures.

6. The package substrate of claim 4, wherein, The lower fiber-reinforced dielectric layer is located on a lower surface of the second dielectric layer, and the lower fiber-reinforced dielectric layer includes a fiber sheet and a plurality of lower metal vias, the plurality of lower metal vias extending through the fiber sheet, wherein the second dielectric layer includes a plurality of second metal interconnect structures, and the plurality of lower metal vias are electrically coupled to the plurality of second metal interconnect structures.

7. A package structure, characterized by, include: A packaging substrate, comprising: One core, including multiple through holes; and A superstructure fiber-reinforced dielectric layer, located on a first side of the core, includes a plurality of superstructure metal vias electrically coupled to the plurality of through-holes; and A semiconductor module is attached to the packaging substrate on the first side of the core and includes a plurality of solder bumps that respectively contact a plurality of the upper metal vias.

8. The package structure of claim 7, wherein, Also includes: A reinforcing ring surrounds the semiconductor module on the packaging substrate, wherein the packaging substrate includes a separation region separating the reinforcing ring from the semiconductor module, and the upper fiber-reinforced dielectric layer is located in the separation region.

9. The package structure of claim 7, wherein, Also includes: A lower fiber-reinforced dielectric layer is located on a second side of the core and includes multiple lower metal vias; as well as A ball grid array is attached to the packaging substrate on the second side of the core and electrically coupled to a plurality of through-holes in the core through a plurality of lower metal vias.

10. The package structure of claim 9, wherein, Also includes: A first dielectric layer is located between the core and the upper fiber-reinforced dielectric layer; A second dielectric layer is located between the core and the underlying fiber-reinforced dielectric layer; An embedded upper fiber-reinforced dielectric layer is embedded within the first dielectric layer; as well as An embedded lower fiber-reinforced dielectric layer is embedded within the second dielectric layer.

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