Semiconductor packaging device

Abstract

This application discloses a semiconductor packaging device comprising: a ceramic substrate; an upper metal layer having an upper trench extending through the upper metal layer; and a lower metal layer having a lower trench not extending through the lower metal layer; wherein the projection patterns of the lower trench and the upper trench along the normal direction of the ceramic substrate are substantially identical and substantially symmetrical. This application improves the structural symmetry of the lower and upper metal layers, making their thermal expansion behavior more compatible. This reduces warpage of the ceramic substrate, thereby reducing the stress on the silicon carbide element and lowering the risk of silicon carbide element breakage due to stress concentration. This application also improves the bonding strength between the lower metal layer and other structures, reducing delamination.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and more specifically to a semiconductor packaging device. Background Technology

[0002] In the automotive and power component industries, ceramic substrates are widely used due to their high thermal conductivity and mechanical strength. Furthermore, with the increasing demand for high-efficiency and high-frequency applications, advanced semiconductor devices based on silicon carbide (SiC) materials are widely used due to their high-temperature, high-frequency, and high-power handling capabilities. However, these devices generate significant thermal stress during operation, which can easily cause warping of the ceramic substrate. Since automotive electronics have extremely high requirements for safety and stability, any stress concentration caused by warping can affect component performance and even lead to damage to critical components. For example, excessive warping of the ceramic substrate can generate excessively high internal stress, which is particularly detrimental to silicon carbide materials. Because silicon carbide is hard and brittle, it is highly susceptible to cracking under high stress, leading to component breakage and failure.

[0003] In existing structural designs, the volume of the copper layers on the upper and lower surfaces of the ceramic substrate differs, leading to a mismatch in the coefficient of thermal expansion (CTE). This CTE mismatch causes uneven thermal stress distribution between the upper and lower layers during temperature changes, further exacerbating substrate warping.

[0004] For example, refer to Figure 1 , Figure 1 This is a schematic diagram of the longitudinal cross-sectional structure of an existing power module packaging structure. (Example:) Figure 1 As shown, the packaging structure includes a ceramic substrate 91 with a lower metal layer 92 on its lower surface and an upper metal layer 93 on its upper surface. The upper metal layer 93 is patterned, and electronic components 94, such as silicon carbide components, are disposed on the patterned upper metal layer 93. (Continue to refer to...) Figure 2 , Figure 2 This is a schematic diagram of a warped structure in an existing power module packaging. (Example:) Figure 2 As shown, the ceramic substrate 91 warps under temperature changes. This warping phenomenon will lead to internal stress concentration, which can easily cause the silicon carbide element to crack.

[0005] In summary, effectively reducing structural warpage, achieving CTE matching, controlling internal stress, and mitigating the risk of silicon carbide (SiC) component breakage due to excessive stress have become key technological challenges in improving the reliability of SiC components and other power components. This issue urgently needs to be addressed in current technological developments. Utility Model Content

[0006] The purpose of this application is to provide a semiconductor packaging device that helps reduce the risk of silicon carbide element breakage and improve the reliability of the device.

[0007] This application provides a semiconductor packaging device, comprising: a ceramic substrate; an upper metal layer having an upper trench formed therethrough; a lower metal layer having a lower trench formed therethrough; wherein the projection patterns of the lower trench and the upper trench along the normal direction of the ceramic substrate are substantially consistent and substantially symmetrical in position.

[0008] In some alternative implementations, the width of the lower groove is substantially equal to the width of the upper groove.

[0009] In some alternative embodiments, the semiconductor packaging device further includes an adhesive material disposed below the lower metal layer and filling the lower trench.

[0010] In some alternative embodiments, the semiconductor packaging device further includes a heat sink disposed below the adhesive material, which connects the lower metal layer to the adhesive material.

[0011] In some alternative embodiments, the binder is a sintered material.

[0012] In some alternative embodiments, the semiconductor packaging device further includes electronic components disposed on the upper metal layer.

[0013] In some alternative implementations, the electronic component is a silicon carbide component.

[0014] In some alternative embodiments, the semiconductor packaging device further includes: a molding material covering the ceramic substrate, the upper metal layer, the lower metal layer, and the electronic components.

[0015] In some alternative embodiments, the semiconductor packaging device further includes a lead frame connected to the upper metal layer and partially exposed to the molding material.

[0016] In some alternative embodiments, the lower surface of the lower metal layer and the lower surface of the molding material are substantially flush.

[0017] In some alternative implementations, the thickness of the lower metal layer is different from the thickness of the upper metal layer.

[0018] In some alternative implementations, the depth of the lower trench is between 50 μm and 200 μm.

[0019] To address the risk of breakage in silicon carbide (SiC) devices, this application proposes a semiconductor packaging device. By etching a pattern in the lower metal layer beneath the ceramic substrate, the material amount of the lower metal layer is reduced, forming a lower trench that does not penetrate the lower metal layer. Furthermore, the lower trench and the upper trench in the upper metal layer share the characteristic of having "substantially identical and substantially symmetrical projection patterns along the normal direction of the ceramic substrate." This improves the structural symmetry of the lower and upper metal layers, making their thermal expansion behavior more compatible. Consequently, it reduces the warping of the ceramic substrate caused by temperature changes due to mismatched coefficients of thermal expansion. Reduced warping of the ceramic substrate lowers the stress on the SiC device, thereby reducing the risk of breakage due to stress concentration. In addition, the lower trench increases the area on the lower surface of the lower metal layer available for sintering bonding, effectively improving the bonding strength between the lower metal layer and other structures and reducing delamination. In summary, this application can not only reduce the warpage of ceramic substrates and stress concentration, thereby improving the reliability of silicon carbide components and other devices under high stress environments, but also improve the reliability of bonding, reduce delamination, and provide higher stability and safety for automotive and power components, thereby improving process yield. Attached Figure Description

[0020] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0021] Figure 1 This is a schematic diagram of the longitudinal cross-section of an existing power module packaging structure;

[0022] Figure 2 This is a schematic diagram of a warped structure in an existing power module packaging.

[0023] Figure 3 This is a longitudinal cross-sectional structural schematic diagram of a semiconductor packaging device according to an embodiment of this application;

[0024] Figure 4 This is a bottom view of a semiconductor packaging device according to an embodiment of this application;

[0025] Figure 5 This is a longitudinal cross-sectional structural schematic diagram of a semiconductor packaging device according to another embodiment of this application;

[0026] Figure 6 This is a simulation diagram of room temperature warp and high temperature warp of the present application and prior art;

[0027] Figure 7 This is a schematic diagram of the manufacturing steps of a semiconductor packaging apparatus according to an embodiment of this application;

[0028] Figure 8 This is a schematic diagram of the manufacturing steps of a semiconductor packaging apparatus according to another embodiment of this application.

[0029] Explanation of reference numerals / symbols in the attached diagram:

[0030] 11: Ceramic substrate; 12: Lower metal layer; 121: Lower trench; 13: Upper metal layer; 131: Upper trench; 14: Electronic component; 15: Adhesive material; 16: Molding material; 17: Lead frame; 18: Heat sink; 19: Oxide layer; 20: Photoresist; 21: Active metal paste;

[0031] 91: Ceramic substrate; 92: Lower metal layer; 93: Upper metal layer; 94: Electronic component. Detailed Implementation

[0032] The specific embodiments of this application will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this application and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0033] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0034] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0035] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0036] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0037] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the scope of this application and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed in this application. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0038] It should also be noted that the longitudinal section corresponding to the embodiment of this application can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0039] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] refer to Figure 3 , Figure 3This is a longitudinal cross-sectional structural diagram of a semiconductor packaging device 3a according to an embodiment of this application. Figure 3 As shown, the semiconductor packaging device 3a of this application includes:

[0041] Ceramic substrate 11;

[0042] An upper metal layer 13 is disposed on the upper surface of the ceramic substrate 11, and an upper trench 131 is formed thereon, the upper trench 131 penetrating the upper metal layer 13.

[0043] The lower metal layer 12 is disposed on the lower surface of the ceramic substrate 11, and a lower trench 121 is formed thereon. The lower trench 121 does not penetrate the lower metal layer 12.

[0044] Among them, the projection patterns of the lower trench 121 and the upper trench 131 along the normal direction of the ceramic substrate 11 are substantially the same and substantially symmetrical in position.

[0045] Here, the ceramic substrate 11 is a substrate made of ceramic material, including but not limited to alumina or aluminum nitride. The upper metal layer 13 and the lower metal layer 12 are made of materials including but not limited to copper. The ceramic substrate 11, the upper metal layer 13, and the lower metal layer 12 can together form a copper-clad ceramic substrate.

[0046] Typically, in automotive and power component applications, the upper metal layer 13 above the ceramic substrate 11 is patterned, forming a circuit pattern by setting upper trenches 131 that penetrate the upper metal layer 13, thereby connecting electronic components or other components. However, the lower metal layer 12 below the ceramic substrate 11 is usually not patterned, but remains as a single unit, mainly serving a heat dissipation function. In this application, the lower metal layer 12 is also patterned, but unlike the upper metal layer 13, the lower trenches 121 used to pattern the lower metal layer 12 are designed to be non-penetrating, in order to maintain the integrity of the lower metal layer 12 and continue to maintain good thermal conductivity.

[0047] Here, by etching a pattern in the lower metal layer 12, the amount of material in the lower metal layer 12 is reduced, forming a lower trench 121 that does not penetrate the lower metal layer 12. The lower trench 121 and the upper trench 131 in the upper metal layer 13 are substantially consistent with each other in terms of their projection patterns along the normal direction of the ceramic substrate 11 and are substantially symmetrical in position. This improves the structural symmetry of the lower metal layer 12 and the upper metal layer 13, making the thermal expansion behavior of the lower metal layer 12 and the upper metal layer 13 more matched. As a result, the warping of the ceramic substrate 11 under temperature changes caused by the mismatch of thermal expansion coefficients can be reduced.

[0048] In some alternative embodiments, the width of the lower groove 121 is substantially equal to the width of the upper groove 131. This further improves structural symmetry and further reduces warping.

[0049] In some alternative implementations, the thickness of the lower metal layer 12 may be different from or the same as the thickness of the upper metal layer 13.

[0050] In some alternative embodiments, the thickness of both the lower metal layer 12 and the upper metal layer 13 can be between 0.1 mm and 1 mm, for example, 0.3 mm.

[0051] In some alternative implementations, the depth of the lower trench 121 may be between 50 μm and 200 μm.

[0052] In some optional embodiments, the semiconductor packaging device 3a further includes an electronic component 14 disposed on the upper metal layer 13. Here, the electronic component 14 includes, but is not limited to, a silicon carbide (Si) element. As a new generation of power semiconductor devices, SiC elements significantly outperform traditional silicon (Si) devices in several key performance indicators due to their superior material properties, especially in high-temperature, high-frequency, and high-power applications.

[0053] In some alternative embodiments, the semiconductor packaging device 3a further includes an adhesive material 15 disposed between the electronic component 14 and the upper metal layer 13. The electronic component 14 is connected to the upper metal layer 13 via the adhesive material 15. Here, the adhesive material 15 may be, for example, a sintered material. Sintered materials are generally formed by forming a dense body from material powder through processes such as high temperature. Here, powders of copper, silver, aluminum, or their alloys with good thermal conductivity can be used to form the adhesive material 15 through a sintering process.

[0054] Next, refer to Figure 4 , Figure 4 This is a bottom view schematic diagram of a semiconductor packaging device 3a according to an embodiment of this application. Figure 4 As shown, the layout of the pattern of the lower trench 121 on the lower metal layer 12 can be varied. It can be regular or irregular, as long as it is consistent with the pattern of the upper trench 131 on the upper metal layer 13 and is symmetrical in position.

[0055] refer to Figure 5 , Figure 5 This is a longitudinal cross-sectional structural diagram of a semiconductor packaging device 5a according to another embodiment of this application. Figure 5 The semiconductor packaging device 5a shown is similar to, for example Figure 3 The semiconductor packaging device 3a shown differs in that:

[0056] In the semiconductor packaging device 5a, a heat sink is further included, disposed below the lower metal layer 12, and thermally connected to the lower metal layer 12. Here, the heat sink 18 can be of various types and materials, and this application is not limited thereto.

[0057] In some alternative embodiments, the semiconductor packaging device 5a further includes an adhesive material 15 disposed below the lower metal layer 12 and filling the lower trench 121. Here, the adhesive material 15 is disposed between the lower metal layer 12 and the heat sink 18, serving to bond and conduct heat. The heat sink 18 is connected to the lower metal layer 12 through the adhesive material 15.

[0058] As described above, the binder material 15 may be, for example, a sintered material, such as a binder material formed by sintering powders of copper, silver, aluminum or their alloys with good thermal conductivity.

[0059] In some alternative embodiments, the semiconductor packaging device 5a further includes: a molding material 16 covering a ceramic substrate 11, an upper metal layer 13 and a lower metal layer 12, and an electronic component 14.

[0060] Here, the molding compound 16 can be formed from various molding compounds. For example, molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc. For example, molding compound 16 may specifically be EMC (epoxy molding compound).

[0061] In some alternative embodiments, the lower surface of the lower metal layer 12 and the lower surface of the molding material 16 are substantially flush. This forms a flat surface as a mounting surface for better connection of the heat sink 18.

[0062] In some alternative embodiments, the semiconductor packaging device 5a further includes a lead frame 17 connected to the upper metal layer 13 and partially exposed to the molding material 16.

[0063] Next, refer to Figure 6 , Figure 6 This is a schematic diagram simulating room temperature warpage and high temperature warpage compared to existing technologies. For example... Figure 6 As shown, existing technologies (such as...) Figure 1 In the example shown), no trenches are formed on the lower metal layer, and its warpage can reach +73 μm at room temperature (e.g., around 25°C) and -76 μm at high temperatures (e.g., above 100°C or 150°C). This application (as shown) Figure 3 As shown, a lower trench 121 is formed on the lower metal layer 12 to suppress warping. The room temperature warping can be reduced to +48 μm, and the high temperature warping can be reduced to -51 μm. It can be seen that this application can reduce both room temperature warping and high temperature warping by 25 μm.

[0064] In summary, this application proposes a semiconductor packaging device.

[0065] This application reduces the amount of material in the lower metal layer 12 by etching a pattern, forming a lower trench 121 that does not penetrate the lower metal layer 12. The lower trench 121 and the upper trench 131 in the upper metal layer 13 are substantially consistent with each other in terms of their projection patterns along the normal direction of the ceramic substrate 11 and are substantially symmetrical in position. This improves the structural symmetry of the lower metal layer 12 and the upper metal layer 13, making the thermal expansion behavior of the lower metal layer 12 and the upper metal layer 13 more matched. As a result, the warping of the ceramic substrate 11 under temperature changes caused by the mismatch of thermal expansion coefficients can be reduced.

[0066] As the warpage of the ceramic substrate 11 is reduced, the stress on the electronic component 14 (specifically, a silicon carbide component) is reduced, thereby reducing the risk of silicon carbide component breakage due to stress concentration.

[0067] Furthermore, due to the provision of the lower trench 121, this application can also increase the area of ​​the lower surface of the lower metal layer 12 for sintering bonding, effectively improving the bonding strength between the lower metal layer 12 and other structures, and reducing delamination.

[0068] In addition, the lower groove 121 can increase the contact area with the sintered material, thereby increasing the heat conduction area and enhancing heat dissipation performance.

[0069] In addition, the non-through design of the lower trench 121 can prevent the bonding between the ceramic substrate 11 and the lower metal layer 12 from being affected by the penetration of sintering material through the ceramic substrate.

[0070] In addition, the lower trench 121 can reduce stress concentration on the lower metal layer 12, thereby avoiding delamination between the lower metal layer 12 and the molding material 16 and the sintering material 15. Even if delamination causes cracks, the lower trench 121 can help prevent crack propagation.

[0071] In summary, this application can not only reduce the warpage of ceramic substrates and stress concentration, thereby improving the reliability of silicon carbide components and other devices under high stress environments, but also improve the reliability of bonding, enhance heat dissipation performance, and reduce delamination, providing higher stability and safety for automotive and power components, thereby improving process yield.

[0072] Next, refer to Figure 7 , Figure 7 This is a schematic diagram of the manufacturing steps of a semiconductor packaging apparatus according to an embodiment of this application.

[0073] like Figure 7 As shown, the manufacturing process of the semiconductor packaging device of this application uses Direct Bonding Copper (DBC) technology to fabricate a copper-clad ceramic substrate, which may specifically include the following steps:

[0074] Step A01: Provide copper foil to be used as the lower metal layer 12 and the upper metal layer 13. The copper foil may be oxygen-free copper foil, and its thickness may be between 0.1 mm and 1 mm, for example, 0.3 mm.

[0075] Step A02: The upper surface of the lower metal layer 12 and the lower surface of the upper metal layer 13 are subjected to copper oxidation treatment to form a copper oxide layer 19, which facilitates subsequent bonding with the ceramic material. This is because pure copper has poor chemical compatibility with ceramic materials, and the difference in their coefficients of thermal expansion is also significant. Compared to pure copper, the copper oxide layer has better chemical compatibility with ceramic materials, and the difference in their coefficients of thermal expansion is smaller.

[0076] Step A03: A ceramic substrate 11 is provided, and a lower metal layer 12 and an upper metal layer 13 are respectively disposed on the lower and upper surfaces of the ceramic substrate 11. A high-temperature process (e.g., 1065°C to 1085°C) is used to form a covalent bond between the copper oxide layer and the ceramic substrate 11. Compared to pure copper, the copper oxide layer can form a denser and stronger bond with the ceramic substrate 11.

[0077] Step A04: Photoresist 20 is disposed on the surfaces of the lower metal layer 12 and the upper metal layer 13, and the photoresist 20 is patterned through photolithography, development and other steps.

[0078] Step A05: Next, the upper metal layer 13 and the lower metal layer 12 are patterned through an etching step to form the desired circuit pattern. In this step, an upper trench 131 is etched through the upper metal layer 13, while the lower metal layer 12 is partially etched, and the resulting lower trench 121 does not penetrate the lower metal layer 12, thus keeping the lower metal layer 12 as a single unit. At this point, a copper-clad ceramic substrate composed of the ceramic substrate 11, the lower metal layer 12, and the upper metal layer 13 is formed.

[0079] Step A06: Place the electronic component 14 (e.g., a silicon carbide component) above the upper metal layer 13. Optionally, the electronic component 14 and the upper metal layer 13 can be connected by sintering material.

[0080] Next, a lead frame 17 can be further disposed on the upper metal layer 13 of the copper-clad ceramic substrate, and a molding material 16 covering the aforementioned components can be formed through a molding process to produce a product as follows. Figure 5 The semiconductor packaging device 5a shown is illustrated.

[0081] refer to Figure 8 , Figure 8 This is a schematic diagram of the manufacturing steps of a semiconductor packaging apparatus according to another embodiment of this application.

[0082] like Figure 8 As shown, the manufacturing process of the semiconductor packaging device of this application uses Active Metal Brazing (AMB) technology to fabricate a copper-clad ceramic substrate, which may specifically include the following steps:

[0083] Step B01: Provide copper foil to be used as the lower metal layer 12 and the upper metal layer 13. The copper foil may be oxygen-free copper foil, and its thickness may be between 0.1 mm and 1 mm, for example, 0.3 mm.

[0084] Step B02: Provide a ceramic substrate 11, and respectively apply a ceramic-active metal paste coating 21 to the upper and lower surfaces of the ceramic substrate 11 to facilitate subsequent bonding with copper foil. Here, the material of the metal paste coating 21 includes, but is not limited to, titanium (Ti), zirconium (Zr), copper (Cu), and silver (Ag). This is because pure copper has poor chemical compatibility with ceramic materials, and the difference in their coefficients of thermal expansion is also significant. Using the ceramic-active metal paste coating 21 as an intermediate layer can improve the bonding between copper and ceramic materials.

[0085] Step B03: The lower metal layer 12 and the upper metal layer 13 are respectively disposed on the lower surface and the upper surface of the ceramic substrate 11, and the copper can be covalently bonded to the ceramic substrate 11 through the ceramic active metal paste coating 21 by a high temperature process (e.g., 800°C).

[0086] Step B04: Photoresist 20 is disposed on the surfaces of the lower metal layer 12 and the upper metal layer 13, and the photoresist 20 is patterned through photolithography, development and other steps.

[0087] Step B05: Next, the upper metal layer 13 and the lower metal layer 12 are patterned through an etching step to form the desired circuit pattern. In this step, an upper trench 131 is etched through the upper metal layer 13, while the lower metal layer 12 is partially etched, and the resulting lower trench 121 does not penetrate the lower metal layer 12, thus keeping the lower metal layer 12 as a single unit. At this point, a copper-clad ceramic substrate composed of the ceramic substrate 11, the lower metal layer 12, and the upper metal layer 13 is formed.

[0088] Step B06: Place the electronic component 14 (e.g., a silicon carbide component) above the upper metal layer 13. Optionally, the electronic component 14 and the upper metal layer 13 can be connected by sintering material.

[0089] Next, a lead frame 17 can be further disposed on the upper metal layer 13 of the copper-clad ceramic substrate, and a molding material 16 covering the aforementioned components can be formed through a molding process to produce a product as follows. Figure 5 The semiconductor packaging device 5a shown is illustrated.

[0090] here, Figure 8 The process shown is compared to Figure 7 The process shown can reduce the process temperature, and the ceramic-active metal paste coating can improve thermal conductivity and electrical conductivity compared to the copper oxide layer.

[0091] Although this application has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of this application. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this application as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this application and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this application may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this application. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this application.

Claims

1. A semiconductor packaging device, characterized in that, include: Ceramic substrate; An upper metal layer is formed with an upper trench that penetrates the upper metal layer; A lower metal layer is formed with a lower trench, the lower trench not penetrating the lower metal layer; Furthermore, the projection patterns of the lower trench and the upper trench along the normal direction of the ceramic substrate are substantially the same and substantially symmetrical in position.

2. The semiconductor package device of claim 1, wherein, The width of the lower groove is substantially equal to the width of the upper groove.

3. The semiconductor package device of claim 1, wherein, The semiconductor packaging apparatus further includes: An adhesive material is disposed below the lower metal layer and fills the lower trench.

4. The semiconductor package device of claim 3, wherein, The semiconductor packaging apparatus further includes: A heat sink is disposed below the adhesive material and is connected to the lower metal layer through the adhesive material.

5. The semiconductor packaging apparatus according to claim 1, characterized in that, Further includes: Electronic components are disposed on the upper metal layer, and the electronic components include silicon carbide components.

6. The semiconductor package device of claim 5, wherein, The semiconductor packaging apparatus further includes: A molding material is used to encapsulate the ceramic substrate, the upper metal layer, the lower metal layer, and the electronic components.

7. The semiconductor package device of claim 6, wherein, The semiconductor packaging apparatus further includes: The lead frame is connected to the upper metal layer and is partially exposed in the molding material.

8. The semiconductor package device of claim 6, wherein, The lower surface of the lower metal layer and the lower surface of the molding material are substantially flush.

9. The semiconductor package device of claim 1, wherein, The thickness of the lower metal layer is different from the thickness of the upper metal layer.

10. The semiconductor packaging apparatus according to claim 1, characterized in that, The depth of the lower trench is between 50 μm and 200 μm.

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