A low dropout linear regulator structure in SOT23-3 package form

Abstract

This utility model discloses a low-dropout linear regulator structure in an SOT23-3 package, including input pins, output pins, and ground pins extending outside the package body, as well as a base island region and a wafer disposed within the package body. The base island region and the ground pins are an integral structure, and the base island region is spaced apart from the input pins and output pins. The wafer substrate is fixed to the base island region with conductive adhesive, and both the wafer substrate and the ground pins are at ground potential. The input pads and output pads of the wafer are soldered to the input pins and output pins respectively via wire bonding. Since the wafer substrate and the ground pins are at ground potential, and conductive adhesive can be used for encapsulation, there is no need to worry about the insulating adhesive getting damp, the adhesive being too thin, uneven thickness, or a series of risks such as reduced load capacity, etc., thus structurally improving the reliability risks associated with insulating adhesive.

Description

Technical Field

[0001] This utility model relates to a low dropout linear regulator structure in an SOT23 package, and more particularly to a low dropout linear regulator structure in an SOT23-3 package. Background Technology

[0002] Low dropout linear regulators (LDOs) are widely used in various electronic products, serving as DC-DC voltage converters in circuits. LDOs are low-cost, high-performance, and have simple application circuits, making them a common component in almost every electronic product. As a critical power supply component in electronic product systems, their reliability directly affects the quality and safety of the electronic products. With the widespread application of LDOs in automotive electronics, medical devices, industrial control, and military fields, many performance requirements have been placed on these products, such as overheat protection, short-circuit protection, current limiting protection, ultra-low static power consumption, and high PSRR. Among these, chip reliability is the most important, directly affecting the product's lifespan. Currently, the most common LDO package on the market is the SOT23-3, which has a relatively stable pin definition, such as... Figure 1 As shown, one side has a grounding pin PIN1 and an output pin PIN2, and the other side has an input pin PIN3. Input pin PIN3 is the input potential, grounding pin PIN1 is the grounding position, and output pin PIN2 is the output potential. To meet the following requirements... Figure 1 The SOT23-3 package shown is a traditional packaging solution that selects, for example... Figure 2The frame shown includes a base island region 4a for placing the chip (wafer 5a), and wire bonding 10a electrically connecting the chip's ground pad 6a and output pad 7a to ground pin PIN1 and output pin PIN2. In traditional bipolar wafer substrates, the input pin PIN3 is the input potential. During packaging, when the wafer is placed in base island region 4a, conductive adhesive is typically used for fixation, ensuring the wafer substrate and the base island region (PIN3) have the same input potential. However, with advancements in wafer manufacturing processes, the mainstream analog power chip production process has shifted from bipolar to BCD (Bipolar Discrete Coding). With the widespread adoption of BCD, the wafer substrate's input potential has changed to ground potential. If the traditional SOT23-3 frame is used, the wafer substrate's ground potential conflicts with the input potential of the base island region (PIN3). Therefore, the packaging process necessitates the use of insulating adhesive for fixation and potential isolation. Replacing conductive adhesive with insulating adhesive meets basic packaging requirements, but introduces new reliability risks. Firstly, the thermal conductivity of insulating adhesive is significantly lower than that of conductive adhesive, as shown in Table 1. Due to the reduced thermal conductivity, using insulating adhesive for the same package shape leads to decreased load capacity and higher chip temperature rise, impacting chip reliability. Secondly, current insulating adhesive application often uses a dispensing process, resulting in variations in adhesive thickness between individual units. If the insulating adhesive is too thin, it can cause insufficient chip withstand voltage. Furthermore, if the insulating adhesive contains numerous air bubbles before application and is not fully sprayed, voids may form after encapsulation, potentially leading to short circuits when the chip absorbs moisture. In summary, the reliability of LDOs manufactured using insulating adhesive is significantly lower than that using conductive adhesive. With advancements in wafer fabrication processes, SOT23-3 packaged LDOs need to switch from conductive adhesive to insulating adhesive to maintain consistent pin definitions. While this meets basic requirements, it also introduces new reliability risks. Replacing conductive adhesive with insulating adhesive satisfies basic packaging requirements, but introduces new reliability concerns. Firstly, the thermal conductivity of insulating adhesive is significantly lower than that of conductive adhesive, as shown in Table 1. Due to the reduced thermal conductivity, using insulating adhesive for the same package shape will result in decreased load capacity and higher chip temperature rise, impacting chip reliability. Secondly, current adhesive application often uses a dispensing process, and the thickness of the adhesive varies between individual units. If the insulating adhesive is too thin, it may cause insufficient chip withstand voltage. Furthermore, if the insulating adhesive contains numerous air bubbles before use, insufficient dispensing may lead to voids after encapsulation, which can easily cause short circuits when the chip absorbs moisture. In summary, the reliability of LDOs produced using insulating adhesive is significantly lower than that produced using conductive adhesive. Additionally, as mentioned in the improved SOT223 frame disclosed in Chinese Patent No. 201910252355.2, the base island and pins are encapsulated with an insulating molding compound.Alternatively, as mentioned in the Chinese patent publication No. 202510093376.X, a SOT23 package lead frame with high heat dissipation capability is preferred. To ensure the mesh fits snugly, the mesh priority is preferably in the following order: molding compound, lead frame, adhesive, and chip. With the improvement of wafer fabrication technology, the SOT23-3 packaged LDO needs to change from conductive adhesive to insulating adhesive to maintain the pin definitions. Although this meets the basic requirements, it also introduces certain reliability risks.

[0003] Table 1 Utility Model Content

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low dropout linear regulator structure in SOT23-3 package. Since the substrate of the wafer and the ground terminal pin are both at ground potential, conductive adhesive can be used for encapsulation. There is no need to worry about the insulating adhesive getting damp, the adhesive being too thin, the thickness being uneven, and the load-carrying capacity being reduced. The reliability risks caused by the insulating adhesive are improved from the structure.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: This low-dropout linear regulator structure in an SOT23-3 package includes input pins, output pins, and ground pins extending outside the package body, as well as a base island region and a wafer disposed within the package body. The base island region and the ground pins are an integrated structure, and the base island region is spaced apart from the input pins and output pins. The wafer substrate is fixed to the base island region with conductive adhesive, and both the wafer substrate and the ground pins are at ground potential. The input pads and output pads of the wafer are soldered to the input pins and output pins respectively via wire bonding.

[0006] The output pin and ground pin are located on the same side of the base island region, while the input pin is located on the other side of the base island region.

[0007] The input pin is located on the upper right side of the base island area, and a first gap area is provided between the input pin and the base island area.

[0008] The output pin is located on the lower left side of the base island area, and a second gap area is provided between the output pin and the base island area.

[0009] Through the above technical solution, this utility model has the following beneficial effects: Since the substrate and grounding pin of the wafer are both at ground potential, and conductive adhesive can be used for encapsulation, there is no need to worry about a series of risks such as the insulating adhesive getting damp, the adhesive being too thin, uneven thickness, and reduced load-carrying capacity. The reliability risks brought by the insulating adhesive are improved structurally. Attached Figure Description

[0010] Figure 1 The background diagram shows the SOT23-3 package structure.

[0011] Figure 2 The background technology is a schematic diagram of the SOT23-3 package framework structure.

[0012] Figure 3 This is a schematic diagram of the low dropout linear regulator in SOT23-3 package of this utility model. Specific Implementation

[0013] The utility model will be further described below with reference to the accompanying drawings.

[0014] like Figure 3 As shown, this low-dropout linear regulator structure in an SOT23-3 package includes an input pin 3, an output pin 2, and a ground pin 1 extending outside the package body, as well as a base island region 4 and a wafer 5 disposed within the package body. The base island region 4 and the ground pin 1 are integrated into a single structure. The base island region 4 is spaced apart from both the input pin 3 and the output pin 2. Specifically, the input pin 3 is located on the upper right side of the base island region 4, with a first spacing region 8 between the input pin and the base island region. The output pin 2 is located on the lower left side of the base island region 4, with a second spacing region 9 between the output pin and the base island region. The wafer substrate is fixed to the base island region using conductive adhesive, and both the wafer substrate and the ground pin are at ground potential. The wafer's input pad 6 and output pad 7 are respectively soldered to the input pin and output pin via a wire bonding pad 10.

[0015] Compared with existing technologies, since the substrate and grounding pins of the wafer are both at ground potential, and conductive adhesive can be used for encapsulation, there is no need to worry about a series of risks such as moisture in the insulating adhesive, excessively thin adhesive, uneven thickness, and reduced load-carrying capacity. This structurally improves the reliability risks brought by the insulating adhesive.

Claims

1. A low dropout linear regulator structure in SOT23-3 package form, comprising an input terminal pin (3), an output terminal pin (2) and a ground terminal pin (1) extending out of the package body, and a base island region (4) and a wafer (5) provided in the package body, characterized in that: The base island area (4) and the ground terminal pin (1) are integrated into one structure. The base island area, the input terminal pin (3) and the output terminal pin (2) are spaced apart. The wafer substrate is fixed to the base island area with conductive adhesive. The wafer substrate and the ground terminal pin are both at ground potential. The wafer input pad (6) and the output pad (7) are soldered to the input terminal pin and the output terminal pin respectively by wire bonding.

2. The low dropout linear regulator structure in the SOT23-3 package form according to claim 1, characterized in that: The output pin (2) and the ground pin (1) are located on the same side of the base island area (4), and the input pin (3) is located on the other side of the base island area.

3. The low dropout linear regulator structure in SOT23-3 package as described in claim 1 or 2, characterized in that: The input pin (3) is located on the upper right side of the base island area (4), and a first gap area (8) is provided between the input pin and the base island area.

4. The low dropout linear regulator structure in SOT23-3 package as described in claim 1 or 2, characterized in that: The output pin (2) is located on the lower left side of the base island area (4), and a second gap area (9) is provided between the output pin and the base island area.

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