Packaging structure

Abstract

This application provides a packaging structure including a bridging chip assembly, which includes a first electrical connector and connecting lines. The connecting lines are located near the active side of the bridging chip assembly, and the first electrical connector is located below the passive side of the bridging chip assembly. A first molding layer covers the first electrical connector. A second molding layer covers the bridging chip assembly and the first molding layer. At least two functional chips are included, and the multiple functional chips are communicatively connected through the connecting lines of the bridging chip assembly. The advantages of this application are: using a molding material to cover the electrical connector on the passive side of the bridging chip assembly improves the adhesion between the electrical connector and the chip adhesive film, which is insufficient due to single-point connection, and avoids the problem of the electrical connector tipping over during the manufacturing process.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more specifically, to a packaging structure. Background Technology

[0002] Through-Silicon Vias (TSVs) are a high-density interconnect technology used in 2.5D / 3D advanced packaging. They enable ultra-high-speed signal transmission and power distribution between multiple chips by fabricating micron-sized TSVs in silicon interposers or dedicated silicon bridges. In existing technologies, TSVs are typically connected to redistribution layers via solder. However, heat treatment during manufacturing can lead to the formation of intermetallic compounds (IMCs). IMCs are usually brittle, and excessively thick or uneven IMC layers can degrade solder joint reliability (e.g., cracking, brittle failure).

[0003] Figure 1 A schematic diagram of a prior art packaging structure is shown. For example... Figure 1 As shown, the packaging structure includes a bridging chip assembly 90, a molding layer 91, a first rewiring layer 92, a second rewiring layer 93, a functional chip assembly 94, and a connection layer 95. The molding layer 91 covers the bridging chip assembly 90. The first rewiring layer 92 is disposed above the bridging chip assembly 90, and the functional chip assembly 94 is disposed above the first rewiring layer 92. The bridging chip assembly 90 is connected to the functional chip assembly 94 through the first rewiring layer 92. The second rewiring layer 93 is disposed below the bridging chip assembly 90, with the passive surface of the bridging chip assembly 90 facing the second rewiring layer 93. The bridging chip assembly 90 is connected to the second rewiring layer 93 through solder 907. The connection layer 95 is disposed below the second rewiring layer 93. The heat-treated solder 907 forms an intermetallic compound at the connection point with the circuit 908. Substances such as water contained in the solder can cause gaps and cracks in the intermetallic compound, leading to a decrease in reliability and potentially a 100% yield loss in severe cases.

[0004] To address the aforementioned issues, two existing technologies offer improvements. The first approach employs a low-temperature process, reducing the standard heat treatment temperature from approximately 230°C to around 200°C. The drawback of this approach is that it prevents the solder from fully melting, reducing the strength of the solder joint. The second approach utilizes copper studs as electrical connectors to link the bridging chip and the redistribution layer. Figure 2 A schematic diagram of a bridge chip with another prior art packaging structure is shown. (See diagram for example.) Figure 2As shown, the bridging chip includes a silicon layer 901, a functional layer 902, copper pillars 903, a first conductive via 904, a dielectric layer 905, an electrical connector 906, and solder 907. The functional layer 902 includes a circuit layer 902a, and the electrical connector 906 includes a first copper element 906a, a second copper element 906b, and a dielectric material 906c. In a side view, the dielectric layer 905, the silicon layer 901, and the functional layer 902 are arranged sequentially from top to bottom. The electrical connector 906 is disposed above the dielectric layer 905, the solder 907 is disposed on top of the electrical connector 906, and the copper pillar 903 is disposed below the functional layer. The copper pillar 903 is electrically connected to the circuit layer 902a. The first conductive via 904 passes through the silicon layer 901, and the circuit layer 902a is electrically connected to the electrical connector 906 through the first conductive via 904. This type of bridging chip requires connection to the redistribution layer or substrate via a die-attach film (DAF) 908. Its disadvantages include a small contact area between each copper pillar 903 and the die-attach film 908, resulting in insufficient adhesion; furthermore, the thin copper pillars 903 are prone to tipping over during manufacturing. These problems significantly impact product yield.

[0005] In summary, there is a need in the art to provide a packaging structure that can overcome the shortcomings of the prior art. Utility Model Content

[0006] This application provides a packaging structure that can solve the problems of the prior art. The objective of this application is achieved through the following technical solution.

[0007] One embodiment of this application provides a packaging structure including a bridging chip assembly, the bridging chip assembly including a first electrical connector and a connection line, the connection line being close to the active side of the bridging chip assembly, the first electrical connector being located below the connection line on the back side of the bridging chip assembly, wherein the back side is the other side of the bridging chip assembly relative to the active side; a first molding layer covering the first electrical connector; and at least two functional chips, the multiple functional chips being communicatively connected through the connection line of the bridging chip assembly.

[0008] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a second molded layer, and the bridging chip assembly further includes a second electrical connector. Each second electrical connector is located between the active surface of the bridging chip assembly and a functional chip. The second molded layer covers the bridging chip assembly, the first molded layer, and the second electrical connector. The connection line is electrically connected to the functional chip through the second electrical connector.

[0009] In some alternative embodiments, the packaging structure provided according to one embodiment of this application above, wherein the bottom surface of the first electrical connector is flush with the bottom surface of the first molding layer.

[0010] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application further includes a second wiring layer disposed below the second molding layer and electrically connected to the first electrical connector.

[0011] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application includes a second conductive via extending through the second redistribution layer. In a side view, the width of the second conductive via gradually decreases from the side away from the second molding layer to the side closer to the second molding layer.

[0012] In some alternative embodiments, the packaging structure provided according to one embodiment of this application further includes a first conductive via in the bridging chip assembly, wherein the connection line is electrically connected to the first conductive via.

[0013] In some alternative embodiments, the encapsulation structure provided according to one embodiment of the present application includes a first molded layer comprising filler particles that protrude from the lower surface and side surface of the first molded layer.

[0014] In some alternative embodiments, the encapsulation structure provided according to one embodiment of this application above, wherein the portion of the filler particles exposed from the side of the first molded layer is flush with the side of the first molded layer.

[0015] In some alternative embodiments, the encapsulation structure provided according to one embodiment of this application above, wherein the portion of the filler particles exposed from the side of the first molded layer contacts the second molded layer.

[0016] In some alternative embodiments, the packaging structure provided according to one embodiment of this application above, wherein the first electrical connector is a copper / polyimide / copper pillar.

[0017] In some alternative embodiments, the packaging structure provided according to one of the above embodiments of this application includes a functional chip that is an application-specific integrated circuit chip and / or a high-bandwidth memory chip.

[0018] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application further includes a first wiring layer disposed above the second molding layer, wherein the functional chip is electrically connected to the bridging chip assembly through the first wiring layer.

[0019] The advantages of the packaging structure according to the embodiments of this application are: the use of molding material to cover the electrical connectors on the passive side of the bridging chip assembly improves the adhesion between the electrical connectors and the chip adhesive film that is insufficient due to single-point connection, and avoids the problem of the electrical connectors tipping over during the manufacturing process; it improves product yield and reduces production costs. Attached Figure Description

[0020] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0021] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0022] Figure 1 A schematic diagram of a prior art packaging structure is shown;

[0023] Figure 2 A schematic diagram of a bridged chip assembly with another prior art packaging structure is shown;

[0024] Figure 3 A schematic diagram of a packaging structure according to an embodiment of this application is shown;

[0025] Figure 4 As shown Figure 3 A schematic diagram of a bridge chip assembly with a packaging structure according to an embodiment of this application is shown;

[0026] Figure 5-1 , Figure 5-2 and Figure 5-3 As shown Figure 4 The diagram shows a manufacturing process of a bridge chip assembly with a packaging structure according to an embodiment of this application.

[0027] Figure 6-1 , Figure 6-2 and Figure 6-3 As shown Figure 3 The diagram shown is a manufacturing process diagram of a packaging structure according to an embodiment of this application;

[0028] Figure 7-1 , Figure 7-2 , Figure 7-3 and Figure 7-4 A schematic diagram of the manufacturing process of a bridge chip assembly with a packaging structure according to a second embodiment of this application is shown;

[0029] Figure 8-1 , Figure 8-2 , Figure 8-3 and Figure 8-4A schematic diagram of the manufacturing process of a bridge chip assembly with a packaging structure according to a third embodiment of this application is shown;

[0030] Figure 9-1 , Figure 9-2 , Figure 9-3 and Figure 9-4 A schematic diagram of the manufacturing process of a bridge chip assembly with a packaging structure according to a fourth embodiment of this application is shown.

[0031] Labels and component names: 1-Bridging chip assembly, 11-Silicon layer, 12-Functional layer, 12a-Connection line, 13-Second electrical connector, 14-First conductive via, 15-First dielectric layer, 16-First electrical connector, 16a-First copper layer, 16b-Second copper layer, 16c-Second dielectric layer, 2-First molding layer, 3-Second molding layer, 31-Conductive pillar, 4-Functional chip, 5-First redistribution layer, 6-Second redistribution layer, 61-Conductive via 7-Hole, 8-Adhesive film, 9-Substrate, 10-Adhesive layer, 11-Third molding layer, 90-Bridge chip assembly, 91-Molding layer, 92-First redistribution layer, 93-Second redistribution layer, 94-Functional chip assembly, 95-Connection layer, 100-Bridge chip, 101-Silicon layer, 102-Functional layer, 102a-Connection line, 103-Second electrical connector, 104-First conductive via, 105-First protective layer, 106-First carrier, 107 108-First dielectric layer, 109-First electrical connector, 110-First molding layer, 111-Adhesive film, 112-Protective backplane, 113-Second protective layer, 114-Second carrier board, 115-Third protective layer, 201-First carrier board, 202-Release film, 203-First metal layer, 204-Conductive pillar, 205-Chip assembly, 206-Second molding layer, 207-First redistribution layer, 208-Second redistribution layer, 2 09-Bump, 210-Third carrier, 211-Functional chip, 212-Third sealing layer, 213-Substrate, 214-Third electrical connector, 215-First pad, 216-Second carrier, 217-Solder ball, 218-Dielectric layer, 219-Adhesive layer, 901-Silicon layer, 902-Functional layer, 903-Copper pillar, 904-First conductive via, 905-Dielectric layer, 906-Electrical connector, 907-Solder, 908-Chip bonding film. Detailed Implementation

[0032] The specific embodiments of this application are described below with reference to the accompanying drawings and examples. Through the content described in this specification, those skilled in the art can clearly and completely understand the technical solution, the technical problem solved, and the resulting technical effects of this application. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, for ease of description, only the parts related to this application are shown in the accompanying drawings.

[0033] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0034] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0035] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the scope of this application and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed in this application. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0036] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0037] The terms “dielectric layer,” “dielectric material,” or “dielectric material” as used herein may include organic and / or inorganic materials. Organic materials may include, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc. Inorganic materials may include, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0038] The molding compound described in this article can be formed from various molding compounds. For example, molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0039] The redistribution layer described herein can be a redistribution layer composed of conductive and dielectric materials. It should be noted that the fabrication process can employ currently known or future-developed redistribution layer formation technologies, and this disclosure does not specifically limit this. For example, redistribution layers can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. Here, the dielectric material can include organic and / or inorganic materials. Organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0040] The carrier plate in this article can be circular or square; its material can be organic: polyamide fiber (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), and / or, inorganic: silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0041] The electrical connectors mentioned in this article can be pads or bumps. Among them, bumps can be, for example, gold bumps (usually rectangular, made of gold), solder bumps (usually round, made of copper and tin), or pillar bumps (usually octagonal or polygonal, made of copper and tin or lead and tin).

[0042] The protective layer described herein may include liquid and / or thin-film organic materials, such as: non-conductive plastic (NCP), non-conductive film (NCF), anisotropic conductive adhesive film (ACF), anisotropic conductive adhesive plastic (ACP), polyimide (PI), epoxy, resin, PP (Prepreg, also known as prepreg or semi-cured resin / prepreg), ABF (Ajinomoto Build-up Film), adhesive, etc. This is merely an example of protective layer materials and not a specific limitation.

[0043] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0044] Figure 3 A schematic diagram of a packaging structure according to an embodiment of this application is shown. Figure 4 As shown Figure 3 The diagram shows a bridge chip assembly with a packaging structure according to an embodiment of this application. Figure 3 and Figure 4 As shown, the packaging structure includes a bridging chip assembly 1, which includes a first electrical connector 16 and a connection line 12a. The connection line 12a is located on the side of the bridging chip assembly 1 with the connection line 12a, which is the active side. The first electrical connector 16 is located below the back side of the bridging chip assembly 1, which is the other side of the bridging chip assembly 1 opposite to the active side. A first molded encapsulation layer 2 covers the first electrical connector 16. There are at least two functional chips 4, and multiple functional chips 4 are communicatively connected through the connection line 12a of the bridging chip assembly 1.

[0045] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a second molded layer 3, and the bridging chip assembly 1 further includes a second electrical connector 13. Each second electrical connector 13 is located between the active surface of the bridging chip assembly 1 and a functional chip 4. The second molded layer 3 covers the bridging chip assembly 1, the first molded layer 2, and the second electrical connector 13. The second electrical connector 13 is connected to the connection line 12a, and the connection line 12a is electrically connected to the functional chip 4 through the second electrical connector 13.

[0046] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application, wherein the bottom surface of the first electrical connector 16 is flush with the bottom surface of the first molding layer 2.

[0047] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a second wiring layer 6, which is disposed below the second molding layer 3. The second wiring layer 6 is electrically connected to the first electrical connector 16, and the bridging chip assembly 1 is connected to the second wiring layer 6 through an adhesive film 7.

[0048] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the second redistribution layer 6 includes a second conductive via 61, the second conductive via 61 penetrating the second redistribution layer 6, and in the side view direction, the width of the second conductive via 61 gradually decreases from the side away from the second molding layer 3 to the side closer to the second molding layer 3.

[0049] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the bridging chip assembly 1 further includes a first conductive via 14, and the connection line 12a is electrically connected to the first conductive via 14.

[0050] In some optional embodiments, according to the packaging structure provided by one embodiment of the present application, the bridging chip assembly 1 further includes a silicon layer 11 and a first dielectric layer 15, the first dielectric layer 15 being located on the passive surface of the bridging chip assembly 1. In a side view, the functional layer 12, the silicon layer 11 and the first dielectric layer 15 are arranged sequentially from top to bottom, and the first conductive via 14 passes through the silicon layer 11.

[0051] In some alternative embodiments, the encapsulation structure provided according to one embodiment of the present application includes a first mold sealing layer 2 comprising filler particles (not shown in the figure) that are exposed from the lower surface and side surface of the first mold sealing layer 2.

[0052] In some alternative embodiments, according to the encapsulation structure provided by one embodiment of the present application, the portion of the filling particles exposed from the side of the first molded layer 2 is flush with the side of the first molded layer 2.

[0053] In some alternative embodiments, the encapsulation structure provided according to one embodiment of the present application, wherein the portion of the filler particles exposed from the side of the first molded layer 2 contacts the second molded layer 3.

[0054] In some optional embodiments, according to the packaging structure provided by one embodiment of this application, the first electrical connector 16 is a copper / polyimide / copper stud (Cu / PI / Cu Stud). The first electrical connector 16 includes a first copper layer 16a, a second copper layer 16b, and a second dielectric layer 16c. The first copper layer 16a and the second copper layer 16b are electrically connected, and the first copper layer 16a is electrically connected to the second redistribution layer 6. The second dielectric layer 16c wraps around the first copper layer 16a and the second copper layer 16b, and the second copper layer 16b is electrically connected to the first conductive via 14. The second dielectric layer 16c is made of polyimide material, which, as an insulating dielectric layer, can reduce parasitic capacitance, absorb mechanical stress, and improve high temperature resistance (above ~350°C). Copper / polyimide / copper pillar is an interconnect structure used in high-density advanced packaging (such as Fan-Out and 3D ICs). It combines the characteristics of copper pillars (Cu Stud) and polyimide (PI) dielectric layers to achieve highly reliable fine-pitch interconnects.

[0055] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the functional chip 4 is an application-specific integrated circuit (ASIC) chip and / or a high-bandwidth memory (HBM) chip.

[0056] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a first rewiring layer 5, which is disposed above the second molding layer 3, and the functional chip 4 is electrically connected to the bridging chip assembly 1 through the first rewiring layer 5.

[0057] In some optional embodiments, according to the packaging structure provided by one embodiment of this application, the adhesive film 7 is a die-attach film (DAF). A die-attach film is a thin adhesive film used to fix a die, which is bonded to a substrate, lead frame, or other carrier by hot pressing or heat curing. It is a solid alternative to traditional liquid or paste adhesives (such as epoxy resin), and is particularly suitable for thin-film, high-precision packaging requirements.

[0058] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, a conductive post 31 is provided in the second molding layer 3, and the conductive post 31 is electrically connected to the first rewiring layer 5 and the second rewiring layer 6.

[0059] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a substrate 8, an adhesive material 9, and a third mold sealing layer 10. The substrate 8 is disposed below the second redistribution layer 6. The substrate 8 is fixedly connected to the second redistribution layer 6 and the second mold sealing layer 3 by the adhesive material 9. The functional chip 4 is fixedly connected to the first redistribution layer 5 by the adhesive material 9. The third mold sealing layer 10 covers the functional chip 4 and the adhesive material 9 that fixes the functional chip 4 and the first redistribution layer 5.

[0060] Figure 5-1 , Figure 5-2 and Figure 5-3 As shown Figure 4 The diagram shows a manufacturing process of a bridge chip assembly with a packaging structure according to an embodiment of this application. Figure 5-1 , Figure 5-2 and Figure 5-3 As shown, the manufacturing process of the bridging chip assembly includes several steps:

[0061] Step 1001: Provide a bridging chip 100, and provide a second electrical connector 103 on the functional layer 102 of the bridging chip 100; wherein the bridging chip 100 includes a silicon layer 101, a functional layer 102 and a first conductive via 104, the functional layer 102 is located on one side of the silicon layer 101, the second electrical connector 103 is disposed above the functional layer 102 and is electrically connected to the connection line 102a in the functional layer 102, one end of the first conductive via 104 is electrically connected to the connection line 102a, and the other end of the first conductive via 104 penetrates into the silicon layer 101;

[0062] Step 1002: Set a first protective layer 105 on the functional layer 102, and set a first carrier plate 106 on the first protective layer 105;

[0063] Step 1003: Flip the product obtained in step 1002 and thin the top of the silicon layer 101 so that the first conductive via 103 is exposed from the top of the silicon layer 101; wherein, preferably, the thickness of the silicon layer 101 is thinned to 50±10um.

[0064] Step 1004: Etch the top of the silicon layer 101 so that the top of the first conductive via 103 protrudes from the top of the silicon layer 101.

[0065] Step 1005: A first dielectric layer 107 is formed on the top of the silicon layer 101; wherein the first dielectric layer 107 covers the top of the protruding first conductive via 10.

[0066] Step 1006: Planarize the first dielectric layer 107 so that the top of the first conductive via 10 is exposed from the top of the first dielectric layer 107.

[0067] Step 1007: A first electrical connector 108 is disposed on the top of the first dielectric layer 107; wherein, the first electrical connector 108 is electrically connected to the first conductive via 10, and the first electrical connector 108 includes a first copper layer 108a, a second copper layer 108b, and a second dielectric layer 108c.

[0068] Step 1008: A first mold sealing layer 109 is formed on the first dielectric layer 107, and then the top of the first mold sealing layer 109 is thinned; wherein, the first mold sealing layer 109 covers the first electrical connector 108;

[0069] Step 1009: Place the flipped product obtained in step 1008 onto the adhesive film 110;

[0070] Step 1010: Remove the first carrier plate 106 and the first protective layer 105; and

[0071] Step 1011: Cut the product obtained in step 1010.

[0072] Figure 6-1 , Figure 6-2 and Figure 6-3 As shown Figure 3 The diagram shown illustrates the manufacturing process of a packaging structure according to an embodiment of this application. Figure 6-1 , Figure 6-2 and Figure 6-3 As shown, the manufacturing process of the packaging structure includes multiple steps:

[0073] Step 5001: Provide a first carrier plate 201, and provide a release film 202 on the first carrier plate 201, and provide a first metal layer 203 on the release film;

[0074] Step 5002: Conductive pillars 204 are disposed on the first metal layer 203;

[0075] Step 5003: Place the bridging chip assembly 205 on the first metal layer 203; wherein, the bridging chip assembly 205 can be as described above. Figure 5-1 , Figure 5-2 and Figure 5-3 In the product made by the steps shown, the adhesive film 110 of the bridging chip assembly 205 is removed before placement;

[0076] Step 5004: Use the second molding layer 206 to cover the bridging chip assembly 205 and the conductive post 204, and grind the top of the second molding layer 206 so that the second electrical connector 103 and the conductive post 204 of the bridging chip assembly 205 are exposed from the top of the second molding layer 206.

[0077] Step 5005: Form a first rewiring layer 207 on top of the second mold sealing layer 206, and form a first pad 215 on top of the first rewiring layer 207;

[0078] Step 5006: Remove the first carrier plate 201 and release film 202, place the second carrier plate 216 above the first gasket 215, grind the first metal layer 203, place the second redistribution layer 208 below the second sealing layer 206, and then place bumps 209 and solder balls 217 below the second redistribution layer 208, and cover the bumps 209 with a dielectric layer 218; wherein, the bumps 209 are electrically connected to the second redistribution layer 208;

[0079] Step 5007: Remove the second carrier board 216, and place the adhesive layer 219 and the third carrier board 210 below the solder ball 217;

[0080] Step 5008: A functional chip 211 is placed above the first rewiring layer 207, and the functional chip 211 is covered by a third encapsulation layer 212. The top of the third encapsulation layer 212 is ground to expose the functional chip 211 from the top of the third encapsulation layer 212. The functional chip 211 is electrically connected to the first rewiring layer 207 through a first pad 215.

[0081] Step 5009: Remove the adhesive layer 219, the third carrier 210, and the dielectric layer 218; perform backside metallization (BSM) on the functional chip 211; and

[0082] Step 5010: The product obtained in step 5009 is placed on the substrate 213; wherein, the bottom of the substrate 213 is provided with a third electrical connector 214, and the third electrical connector 214 is electrically connected to the bump 209 through the substrate 213.

[0083] Figure 7-1 , Figure 7-2 , Figure 7-3 and Figure 7-4 A schematic diagram illustrating the manufacturing process of a bridge chip assembly with a packaging structure according to a second embodiment of this application is shown. Figure 7-1 , Figure 7-2 , Figure 7-3 and Figure 7-4 As shown, the manufacturing process of the bridge chip assembly of the packaging structure in the second embodiment includes several steps:

[0084] Step 2001: Provide a bridging chip 100; wherein the bridging chip 100 includes a silicon layer 101, a functional layer 102 and a first conductive via 104, the functional layer 102 is located on one side of the silicon layer 101, one end of the first conductive via 104 is electrically connected to the connection line 102a, and the other end of the first conductive via 104 penetrates into the silicon layer 101.

[0085] Step 2002: A groove 102b is provided on the functional layer 102 so that the connecting line 102a is exposed from the bottom of the groove 102b. A first protective layer 105 is provided on the functional layer 102, and a first carrier board 106 is provided on the first protective layer 105.

[0086] Step 2003: Flip the product obtained in step 2002 and thin the top of the silicon layer 101 so that the first conductive via 103 is exposed from the top of the silicon layer 101; wherein, preferably, the thickness of the silicon layer 101 is thinned to 50±10um.

[0087] Step 2004: Etch the top of the silicon layer 101 so that the top of the first conductive via 103 protrudes from the top of the silicon layer 101.

[0088] Step 2005: A first dielectric layer 107 is formed on the top of the silicon layer 101; wherein the first dielectric layer 107 covers the top of the protruding first conductive via 10.

[0089] Step 2006: Planarize the first dielectric layer 107 so that the top of the first conductive via 10 is exposed from the top of the first dielectric layer 107.

[0090] Step 2007: A first electrical connector 108 is disposed on the top of the first dielectric layer 107; wherein, the first electrical connector 108 is electrically connected to the first conductive via 10, and the first electrical connector 108 includes a first copper layer 108a, a second copper layer 108b, and a second dielectric layer 108c.

[0091] Step 2008: A first mold sealing layer 109 is formed on the first dielectric layer 107; wherein, the first mold sealing layer 109 covers the first electrical connector 108;

[0092] Step 2009: Flip the product obtained in step 2008, and then remove the first carrier plate 106 and the first protective layer 105;

[0093] Step 2010: A second electrical connector 103 is provided on the functional layer 102 of the bridging chip 100. The second electrical connector 103 passes through the groove 102b and is electrically connected to the connection line 102a.

[0094] Step 2011: Provide a protective backplate 111 on the functional layer 102, so that the protective backplate 111 covers the second electrical connector 103, and thin the first mold sealing layer 109.

[0095] Step 2012: Remove the protective backing plate 111, and then place the product obtained in step 2011 onto the adhesive film 110; and

[0096] Step 2013: Cut the product obtained in step 2012.

[0097] Figure 8-1 , Figure 8-2 , Figure 8-3 and Figure 8-4 A schematic diagram illustrating the manufacturing process of a bridge chip assembly with a packaging structure according to a third embodiment of this application is shown. Figure 8-1 , Figure 8-2 , Figure 8-3 and Figure 8-4 As shown, the manufacturing process of the bridge chip assembly of the packaging structure in the third embodiment includes several steps:

[0098] Step 3001: Provide a bridging chip 100; wherein the bridging chip 100 includes a silicon layer 101, a functional layer 102 and a first conductive via 104, the functional layer 102 is located on one side of the silicon layer 101, one end of the first conductive via 104 is electrically connected to the connection line 102a, and the other end of the first conductive via 104 penetrates into the silicon layer 101.

[0099] Step 3002: A groove 102b is provided on the functional layer 102 so that the connecting line 102a is exposed from the bottom of the groove 102b. A first protective layer 105 is provided on the functional layer 102, and a first carrier board 106 is provided on the first protective layer 105.

[0100] Step 3003: Flip the product obtained in step 3002 and thin the top of the silicon layer 101 so that the first conductive via 103 is exposed from the top of the silicon layer 101; wherein, preferably, the thickness of the silicon layer 101 is thinned to 50±10um.

[0101] Step 3004: Etch the top of the silicon layer 101 so that the top of the first conductive via 103 protrudes from the top of the silicon layer 101.

[0102] Step 3005: A first dielectric layer 107 is formed on the top of the silicon layer 101; wherein the first dielectric layer 107 covers the top of the protruding first conductive via 10.

[0103] Step 3006: Planarize the first dielectric layer 107 so that the top of the first conductive via 10 is exposed from the top of the first dielectric layer 107.

[0104] Step 3007: A first electrical connector 108 is disposed on the top of the first dielectric layer 107; wherein, the first electrical connector 108 is electrically connected to the first conductive via 10, and the first electrical connector 108 includes a first copper layer 108a, a second copper layer 108b, and a second dielectric layer 108c.

[0105] Step 3008: A first mold sealing layer 109 is formed on the first dielectric layer 107; wherein, the first mold sealing layer 109 covers the first electrical connector 108;

[0106] Step 3009: Thin the first mold sealing layer 109;

[0107] Step 3010: Flip the product obtained in step 3009, remove the first carrier plate 106 and the first protective layer 105, and then set the second protective layer 112 and the second carrier plate 113 at the bottom of the first mold sealing layer 109;

[0108] Step 3011: A second electrical connector 103 is provided on the functional layer 102 of the bridging chip 100. The second electrical connector 103 passes through the groove 102b and is electrically connected to the connection line 102a.

[0109] Step 3012: Place the product obtained in step 3011 on the adhesive film 110, and then remove the second protective layer 112 and the second carrier plate 113;

[0110] Step 3013: Flip the product on the adhesive film 110 and calibrate its position; and

[0111] Step 3014: Cut the product obtained in step 3013.

[0112] Figure 9-1 , Figure 9-2 , Figure 9-3 and Figure 9-4 A schematic diagram illustrating the manufacturing process of a bridge chip assembly with a packaging structure according to a fourth embodiment of this application is shown. Figure 9-1 , Figure 9-2 , Figure 9-3 and Figure 9-4 As shown, the manufacturing process of the bridge chip assembly of the packaging structure in the fourth embodiment includes several steps:

[0113] Step 4001: Provide a bridging chip 100; wherein the bridging chip 100 includes a silicon layer 101, a functional layer 102 and a first conductive via 104, the functional layer 102 is located on one side of the silicon layer 101, one end of the first conductive via 104 is electrically connected to the connection line 102a, and the other end of the first conductive via 104 penetrates into the silicon layer 101.

[0114] Step 4002: A groove 102b is provided on the functional layer 102 so that the connecting line 102a is exposed from the bottom of the groove 102b. A first protective layer 105 is provided on the functional layer 102, and a first carrier board 106 is provided on the first protective layer 105.

[0115] Step 4003: Flip the product obtained in step 4002 and thin the top of the silicon layer 101 so that the first conductive via 103 is exposed from the top of the silicon layer 101; wherein, preferably, the thickness of the silicon layer 101 is thinned to 50±10um.

[0116] Step 4004: Etch the top of the silicon layer 101 so that the top of the first conductive via 103 protrudes from the top of the silicon layer 101.

[0117] Step 4005: A first dielectric layer 107 is formed on the top of the silicon layer 101; wherein the first dielectric layer 107 covers the top of the protruding first conductive via 10.

[0118] Step 4006: Planarize the first dielectric layer 107 so that the top of the first conductive via 10 is exposed from the top of the first dielectric layer 107.

[0119] Step 4007: A first electrical connector 108 is disposed on the top of the first dielectric layer 107; wherein, the first electrical connector 108 is electrically connected to the first conductive via 10, and the first electrical connector 108 includes a first copper layer 108a, a second copper layer 108b, and a second dielectric layer 108c.

[0120] Step 4008: Flip the product obtained in step 4007, remove the first carrier plate 106 and the first protective layer 105, and then set the second protective layer 112 and the second carrier plate 113 at the bottom of the first dielectric layer 107.

[0121] Step 4009: A second electrical connector 103 is provided on the functional layer 102 of the bridging chip 100. The second electrical connector 103 passes through the groove 102b and is electrically connected to the connection line 102a.

[0122] Step 4010: Flip the product obtained in step 4009, remove the second carrier plate 113 and the second protective layer 112, and then set the third protective layer 114 and the third carrier plate 115 at the bottom of the functional layer 102.

[0123] Step 4011: A first mold sealing layer 109 is formed on the first dielectric layer 107; wherein, the first mold sealing layer 109 covers the first electrical connector 108;

[0124] Step 4012: Thin the first mold sealing layer 109;

[0125] Step 4013: Place the product obtained in step 4012, after removing the third carrier plate 115 and the third protective layer 114, onto the adhesive film 110; and

[0126] Step 4014: Cut the product obtained in step 4013.

[0127] The advantages of the packaging structure according to the embodiments of this application are: the use of molding material to cover the electrical connectors on the passive side of the bridging chip improves the adhesion between the electrical connectors and the chip adhesive film that is insufficient due to single-point connection, and avoids the problem of the electrical connectors tipping over during the manufacturing process; it improves product yield and reduces production costs.

[0128] Although this application has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not intended to limit the application. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the scope of protection of this application as defined by the claims. Differences may exist between the technical representation in this application and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this application may exist that are not specifically described. The specification and illustrations should be considered illustrative rather than restrictive, and modifications can be made to suit the purpose and spirit of this application, all of which are within the scope of the claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be rearranged, subdivided, or arranged to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the application.

Claims

1. A package structure, characterized by, include: A bridging chip assembly includes a first electrical connector and a connection line, the connection line being close to the active surface of the bridging chip assembly, and the first electrical connector being located below the back surface of the bridging chip assembly, wherein the back surface is the other side of the bridging chip assembly opposite to the active surface. A first mold sealing layer covers the first electrical connector; The functional chips are provided, with at least two of them, and multiple functional chips are communicatively connected through the connection lines of the bridge chip assembly.

2. The package structure of claim 1, wherein, The packaging structure further includes a second molding layer, and the bridging chip assembly further includes a second electrical connector. Each second electrical connector is located between the active surface of the bridging chip assembly and a functional chip. The second molding layer covers the bridging chip assembly, the first molding layer, and the second electrical connector. The connection line is electrically connected to the functional chip through the second electrical connector.

3. The package structure of claim 2, wherein, The bottom surface of the first electrical connector is flush with the bottom surface of the first molded layer.

4. The package structure of claim 3, wherein, The packaging structure further includes a second wiring layer, which is disposed below the second molding layer and is electrically connected to the first electrical connector.

5. The package structure of claim 4, wherein, The second redistribution layer includes a second conductive via that penetrates the second redistribution layer. In a side view, the width of the second conductive via gradually decreases from the side away from the second molding layer to the side closer to the second molding layer.

6. The package structure of claim 1, wherein, The bridging chip assembly further includes a first conductive via, and the connection line is electrically connected to the first conductive via.

7. The package structure of claim 2, wherein, The first molding layer includes filler particles that protrude from the lower surface and side surface of the first molding layer, with the portion of the filler particles protruding from the side surface of the first molding layer flush with the side surface of the first molding layer.

8. The package structure of claim 7, wherein, The portion of the filler particles exposed from the side of the first molding layer comes into contact with the second molding layer.

9. The package structure of claim 1, wherein, The first electrical connector is a copper / polyimide / copper pillar.

10. The package structure of claim 4, wherein, The packaging structure further includes a first wiring layer, which is disposed above the second molding layer, and the functional chip is electrically connected to the bridging chip assembly through the first wiring layer.

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