Packaging structure

Abstract

The package structure includes a substrate, a first semiconductor wafer, a second semiconductor wafer, a packaging material, a thermal interface material layer, and a cap structure. The first semiconductor wafer is located on the substrate. The second semiconductor wafer is located on the substrate. The packaging material laterally surrounds the first and second semiconductor wafers. The thermal interface material layer is located on the first and second semiconductor wafers. The cap structure is located on the thermal interface material. The cap structure has a trench. From a top view, the trench does not overlap the first and second semiconductor wafers and is aligned with a region between the first and second semiconductor wafers.

Description

Technical Field

[0001] This disclosure relates to a packaging structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have led to the production of generation after generation of ICs, each generation being smaller and more complex than the last. However, these advancements have also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are necessary to realize these advancements.

[0003] In the evolution of integrated circuits, functional density (i.e., the number of interconnect components per wafer region) has typically increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also results in relatively high power dissipation values, which can be addressed by using low-power dissipation components such as complementary metal-oxide-semiconductor (CMOS) devices. Utility Model Content

[0004] In some embodiments, the encapsulation structure includes a substrate, an encapsulation element, an encapsulation material, a thermal interface material layer, a first adhesive structure, a second adhesive structure, and a cover structure. The encapsulation element is located on the substrate. The encapsulation material laterally surrounds the encapsulation element. The thermal interface material layer is located on the encapsulation element. The first adhesive structure is located on the encapsulation material and laterally surrounds the thermal interface material. The second adhesive structure is located on the encapsulation material and laterally surrounds the first adhesive structure. The height of the first adhesive structure relative to the encapsulation material is greater than the height of the second adhesive structure relative to the encapsulation material. The cover structure is located on the thermal interface material and the second adhesive structure.

[0005] In some embodiments, the package structure includes a substrate, a first semiconductor wafer, a second semiconductor wafer, a packaging material, a thermal interface material layer, and a cap structure. The first semiconductor wafer is located on the substrate. The second semiconductor wafer is located on the substrate. The packaging material laterally surrounds the first and second semiconductor wafers. The thermal interface material layer is located on the first and second semiconductor wafers. The cap structure is located on the thermal interface material. The cap structure has a trench. From a top view, the trench does not overlap the first and second semiconductor wafers and is aligned with a region between the first and second semiconductor wafers.

[0006] In some embodiments, the encapsulation structure includes a substrate, an encapsulation element, an encapsulation material, a thermal interface material layer, a first adhesive layer, and a cover structure. The encapsulation element is located on the substrate. The encapsulation material laterally surrounds the encapsulation element. The thermal interface material layer is located on the encapsulation element. The first adhesive layer is located on the encapsulation material, wherein the first adhesive layer laterally surrounds the thermal interface material. The cover structure is located on the thermal interface material layer, wherein the cover structure has a first groove recessed from the bottom surface of the cover structure, the planar area of ​​the first groove on the substrate surrounding the planar area of ​​the encapsulation element on the substrate, and the planar area of ​​the first adhesive layer on the substrate surrounding the planar area of ​​the first groove on the substrate. Attached Figure Description

[0007] When viewed in conjunction with the accompanying drawings, the best understanding of the nature of this disclosure is found in the following detailed illustrations. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figures 1 to 18G and Figures 19 to 21B A schematic diagram illustrating an intermediate stage in forming an encapsulation structure according to some embodiments of this disclosure is provided.

[0009] Figure 18H and Figure 18I Schematic illustrations of some embodiments according to this disclosure Figure 18G A top view of the packaging structure.

[0010] [Symbol Explanation]

[0011] 10: Packaging

[0012] 12a: Logic chip

[0013] 12b: Memory chip

[0014] 14: Package

[0015] 60, 62: Adhesive structure

[0016] 60s, 62s: line segments

[0017] 62a: First layer

[0018] 62b: Second layer

[0019] 62t2, 116t, 60t, T 100b T 300 T UF1 Top surface

[0020] 70: Cover structure

[0021] 70c: Covered area

[0022] 70g: Feet

[0023] 70p: Highlighted Parts

[0024] 70t1, 70t2: Trench

[0025] 75: Heatsink

[0026] 100a, 100b: Semiconductor wafers

[0027] 110: Semiconductor substrate

[0028] 110': Semiconductor wafer

[0029] 112, 113: Release membrane

[0030] 114: Substrate

[0031] 115, 117: Flux

[0032] 116: Thermal interface materials

[0033] 120: Interconnection Structure

[0034] 122, 130, 202: Dielectric layer

[0035] 124: Patterned conductive layer

[0036] 140: Conductive pad structure

[0037] 150: Passivation layer

[0038] 160: Post-passivation layer

[0039] 170: Conductive column

[0040] 180: Conductive terminal

[0041] 200: Intermediary layer

[0042] 200a: First surface

[0043] 200b: Second surface

[0044] 204: Conductive Patterned Layer

[0045] 206: Conductive via

[0046] 300: Package

[0047] A1-A1', B1-B1', B2-B2', B3-B3', C1-C1',

[0048] C2-C2', C3-C3': Package

[0049] BSM1, BSM2: Conductive layers

[0050] C1: First conductive layer

[0051] C2: Second conductive layer

[0052] C3: Third conductive layer

[0053] D2, D10: Distance

[0054] FS: Front Surface

[0055] H1, H2: Vertical dimensions

[0056] L1: Length

[0057] L2: Region

[0058] M1, M2, D3, D4, D5, D6, D7, D8, D9: Sizes

[0059] O1, O2, OP1, OP2, OP3: Openings

[0060] P2: Curing process

[0061] P3, P4: Cooling process

[0062] PR: Patterned photoresist layer

[0063] PKG: Packaging Structure

[0064] R1, R2, R3: Carriers

[0065] RS: Rear Surface

[0066] SL: Seed layer

[0067] UF1: Bottom packing layer

[0068] W1, W2, W3, W4, W5, W6, W7: Width Detailed Implementation

[0069] The following disclosure provides numerous different implementations or examples for implementing various features of the provided object. Specific examples of components and configurations are illustrated below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following illustrations, the formation of a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated in this disclosure. This repetition is for simplicity and clarity and does not, in itself, define the relationships between the various implementations and / or configurations discussed.

[0070] Additionally, for ease of illustration, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, are used herein to illustrate the relationship between one element or feature as illustrated in the figures and another. These spatial relative terms are intended to cover different orientations of elements in use or operation, in addition to those depicted in the figures. Elements may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative illustration terms used herein may be interpreted accordingly. As used herein, “approximately,” “probably,” “around,” or “substantially” can mean within 20%, 10%, or 5% of a given value or range. However, those skilled in the art will understand that the values ​​or ranges listed throughout the illustrations are merely examples and may decrease as integrated circuits shrink. The numerical values ​​disclosed herein are approximate, and unless explicitly stated otherwise, terms such as “approximately,” “probably,” “around,” or “substantially” can be inferred.

[0071] Unless otherwise defined, all terms used in this disclosure (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and this disclosure, and shall not be interpreted as having an idealized or overly formal meaning, unless expressly defined herein.

[0072] The embodiments disclosed herein are applicable to memory computing, memory processing, processing using memory, near memory computing, near data processing, near memory processing, in-memory processing, GPU accelerators, TPU accelerators, memory computing, memory processing, near memory computing and / or near memory processing.

[0073] For large chip-on-wafer-on-substrate (CoWoS) packages, the surface above the substrate is completely flat. Such packages may face the risk of cap structure layer peeling when using a flat cap structure. Furthermore, irregular voids may be found within the package after a heatsink is installed. In some implementations, these voids may impair the mechanical bond between the thermal interface material (TIM) and the cap structure, reducing the package's structural integrity and making it more susceptible to peeling or failure during thermal cycling.

[0074] Therefore, various embodiments of this disclosure provide a flat cap structure with recesses (or cavities) in the package, thereby mitigating peeling and preventing irregular gaps formed due to the use of metal thermal interface materials between the cap structure and the package. Additional grooves within the cap structure provide space for constructing an adhesive (ADH) barrier structure. This adhesive barrier structure may include two or more layers of adhesive around the chip-on-wafer (CoW) die, thereby controlling package warpage and suppressing leakage / overflow of metal thermal interface materials between the cap structure and the package. Furthermore, the top layer of the adhesive barrier structure with openings prevents potential deformation of the barrier structure itself.

[0075] See Figures 1 to 20B and Figures 20E to 21B . Figures 1 to 18G and Figures 19 to 21B A schematic diagram illustrating intermediate stages in forming an encapsulation structure according to some embodiments of this disclosure is provided. Specifically, Figures 1 to 9A , Figures 10 to 17A , Figure 18A , Figure 19 , Figure 20A , Figure 21A and Figure 21B A schematic cross-sectional view of the package 10 obtained from reference sections A1-A1' of the 9B is illustrated according to some embodiments of the present disclosure. Figure 9B , Figure 17B and Figure 18G The corresponding figures are illustrated schematically. Figure 9A , Figure 17A and Figure 18A A top view of the packaging structure, according to some embodiments disclosed herein. For simplicity and clarity, Figure 9B , Figure 17B and Figure 18G Some elements are omitted in the simplified top view, and these elements may not be on the same plane. Figure 18B A top view of a cover structure 70 according to some embodiments of this disclosure is schematically illustrated. Figure 18C , Figure 18D , Figure 18E and Figure 18F The illustration shows the process from... Figure 18B The cross-sectional views of the cover structure 70 obtained from reference sections B1-B1', B2-B2', B3-B3', and B4-B4' are based on some embodiments disclosed herein. Figure 20B Some embodiments according to this disclosure are illustrated schematically. Figure 20A A magnified view of region L2 in the image. Figure 20C , Figure 20D and Figure 20E Cross-sectional views of the packaging structure obtained from reference sections C1-C1', C2-C2', and C3-C3' of section 20B are schematically illustrated according to some embodiments of this disclosure. It should be understood that... Figures 1 to 18G and Figures 19 to 21B Additional operations may be provided before, during, and after the illustrated process, and some of the operations described below may be replaced or eliminated to implement additional embodiments of the method. The order of operations / processes may be interchanged.

[0076] See Figure 1 A semiconductor wafer 110' may be provided. In some embodiments, the semiconductor wafer 110' may be made of suitable element semiconductors, such as crystalline silicon, diamond, or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. In some embodiments, the semiconductor wafer 110' may have active elements (e.g., transistors or similar elements) and passive elements (e.g., resistors, capacitors, inductors, or similar elements) formed therein.

[0077] In some embodiments, an interconnect structure 120 may be formed on a semiconductor wafer 110'. In some embodiments, the interconnect structure 120 may include a dielectric layer 122 and multiple patterned conductive layers 124. For simplicity, the dielectric layer 122 may be shown as a bulk layer, but it should be understood that the dielectric layer 122 may consist of multiple dielectric layers. The patterned conductive layers 124 and the dielectric layers of the dielectric layer 122 may be stacked alternately. In some embodiments, two vertically adjacent patterned conductive layers 124 may be electrically connected to each other through conductive vias sandwiched between them.

[0078] In some embodiments, the dielectric layer 122 may be made of polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or other suitable polymer-based dielectric materials. The dielectric layer 122 may be formed using suitable manufacturing techniques, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In some embodiments, the patterned conductive layer 124 may be made of aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof. The patterned conductive layer 124 may be formed by electroplating, deposition, and / or photolithography and etching. It should be noted that... Figure 1 The number of patterned conductive layers 124 and dielectric layers 122 shown is merely illustrative and is not limited to this disclosure. In some alternative embodiments, the number of dielectric layers in the patterned conductive layers 124 and dielectric layers 122 may be adjusted according to wiring requirements.

[0079] See Figure 2 A dielectric layer 130 may be formed on the interconnect structure 120. In some embodiments, the material of the dielectric layer 130 may include polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, PBO, or any other suitable polymer-based dielectric material. The dielectric layer 130 may be formed using suitable fabrication techniques, such as spin coating, chemical vapor deposition, plasma-enhanced chemical vapor deposition, etc. In some embodiments, multiple openings may be formed in the dielectric layer 130 to expose portions of the top patterned conductive layer 124. After forming the openings, multiple conductive pad structures 140 may be formed on the dielectric layer 130. For example, the conductive pad structures 140 may be formed on the semiconductor wafer 110' and the interconnect structure 120, such that the interconnect structure 120 may be located between the semiconductor wafer 110' and the conductive pad structures 140. In some embodiments, the positions of the conductive pad structures 140 may correspond to the opening positions of the dielectric layer 130. For example, the conductive pad structure 140 may extend into the opening of the dielectric layer 130 to achieve electrical connection between the conductive pad structure 140 and portions of the interconnect structure 120 (i.e., the patterned conductive layer 124). In some embodiments, the conductive pad structure 140 may be an aluminum pad, a copper pad, or other suitable metal pad. The number and shape of the conductive pad structures 140 can be selected as needed.

[0080] After distributing the conductive pad-like structure 140 on the dielectric layer 130, a passivation layer 150 and a post-passivation layer 160 can be formed sequentially on the dielectric layer 130 and the conductive pad-like structure 140. In some embodiments, the passivation layer 150 may have multiple contact openings OP1 that partially expose the conductive pad-like structure 140. In some embodiments, the passivation layer 150 may be a dielectric layer formed of silicon dioxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. Figure 2 As shown, the post-passivation layer 160 may cover the passivation layer 150 and have a plurality of contact openings OP2. The conductive pad-like structure 140 may be partially exposed in the contact openings OP2 of the post-passivation layer 160. In some embodiments, the post-passivation layer 160 may be a dielectric layer formed of a polyimide layer, a polybenzoxazole layer, or other suitable polymer. It should be noted that the post-passivation layer 160 may be optional in some embodiments.

[0081] See Figure 3 After the post-passivation layer 160 is formed, a seed layer SL can be formed on the post-passivation layer 160. For example, at least a portion of the seed layer SL extends into the contact opening OP2 of the post-passivation layer 160 to physically contact the conductive pad structure 140. The seed layer SL can be formed by sputtering, physical vapor deposition (PVD), or the like. In some embodiments, the seed layer SL may consist of two sublayers (not shown). In these embodiments, the first sublayer may include titanium, titanium nitride, tantalum, tantalum nitride, other suitable materials, or combinations thereof, while the second sublayer may include copper, a copper alloy, or other suitable material selection.

[0082] See Figure 4 A patterned photoresist layer PR can be formed on the seed layer SL. In some embodiments, the patterned photoresist layer PR can be made of a photosensitive material. In some embodiments, the patterned photoresist layer PR can have multiple openings OP3 that partially expose the seed layer SL, these openings being located above the conductive pad structure 140. For example, the openings OP3 can expose the seed layer SL directly above the conductive pad structure 140.

[0083] See Figure 5A first conductive layer C1, a second conductive layer C2, and a third conductive layer C3 can be sequentially deposited onto an exposed seed layer SL. For example, the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 can fill the opening OP3 of a patterned photoresist layer PR. In some embodiments, the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 can be formed using the same technique. However, this disclosure is not limited thereto. In some alternative embodiments, the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 can be formed using different techniques. In some embodiments, the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 can be formed using an electroplating process. The electroplating process can be, for example, an electroplating process, an autocatalytic electroplating process, an immersion electroplating process, etc. In some embodiments, the materials of the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 can be different. For example, the first conductive layer C1 can be made of aluminum, titanium, copper, tungsten, and / or alloys thereof; the second conductive layer C2 can be made of nickel; and the third conductive layer C3 can be made of solder. In some embodiments, solder flux (not shown) can be applied to the third conductive layer C3 to achieve better adhesion. In some embodiments, the thickness of the first conductive layer C1 can be greater than the thicknesses of the second conductive layer C2 and the third conductive layer C3. Moreover, the thickness of the third conductive layer C3 can be greater than the thickness of the second conductive layer C2.

[0084] See Figure 5 and Figure 6 The patterned photoresist layer PR can be removed. The patterned photoresist layer PR can be removed using etching, stripping, ashing, or combinations thereof. Subsequently, using the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 as a hard mask, the seed layer SL not covered by the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 can be removed. In some embodiments, a portion of the seed layer SL can be removed using an etching process. After removing a portion of the seed layer SL, the remaining seed layer SL can be located directly below the first conductive layer C1. That is, the seed layer SL can be sandwiched between the conductive pad structure 140 and the first conductive layer C1. In some embodiments, the remaining seed layer SL, the first conductive layer C1, and the second conductive layer C2 are collectively referred to as conductive pillars 170.

[0085] See Figure 6 and Figure 7The third conductive layer C3 can be reflowed to transform it into a conductive terminal 180. That is, the conductive terminal 180 can be formed on the conductive post 170. In some embodiments, the third conductive layer C3 can be reformed during the reflow process to form a hemispherical conductive terminal 180.

[0086] See Figure 7 and Figure 8 It can be Figure 7 The structure shown is divided into multiple semiconductor wafers 100a, such as Figure 8 As shown. In some embodiments, the singulation process typically includes cutting using a rotating blade and / or a laser beam. In other words, the singulation process can include laser cutting, mechanical cutting, laser grooving, other suitable processes, or combinations thereof. For example, it can be... Figure 7 Laser etch is performed on the structure shown to form trenches (not shown). Subsequently, a mechanical cutting process can be performed at the trench locations to cut through the structure, thereby dividing the semiconductor wafer 110' into semiconductor substrate 110 and obtaining semiconductor wafer 100a.

[0087] See Figure 8 The semiconductor wafer 100a may include a semiconductor substrate 110, an interconnect structure 120, a dielectric layer 130, a conductive pad structure 140, a passivation layer 150, a rear passivation layer 160, a conductive pillar 170, and a conductive terminal 180. In some embodiments, the semiconductor substrate 110 may have a front surface FS and a rear surface RS opposite to the front surface FS. The interconnect structure 120 may be disposed on the front surface FS of the semiconductor substrate 110. The dielectric layer 130, the conductive pad structure 140, the passivation layer 150, and the rear passivation layer 160 may be sequentially disposed on the interconnect structure 120. The conductive pillar 170 may be disposed on the rear passivation layer 160 and electrically connected to the conductive pad structure 140. The conductive terminal 180 may be disposed on the conductive pillar 170. Furthermore, as... Figure 8 As shown, although four conductive pillars 170 and four conductive terminals 180 are shown in the semiconductor wafer 100a for illustrative purposes, those skilled in the art will understand that the number of conductive pillars 170 and conductive terminals 180 may be more or less. Figure 8 As shown in the figure, and can be specified according to requirements and / or design layout.

[0088] In some embodiments, the semiconductor wafer 100a may have the capability to perform logical functions. For example, the semiconductor wafer 100a may include a central processing unit (CPU) wafer, a graphics processing unit (GPU) wafer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), or a similar wafer. In some embodiments, the semiconductor wafer 100a may be used in a package structure. For example, the semiconductor wafer 100a may be assembled with other components to form a package structure. The process of manufacturing a package structure using the semiconductor wafer 100a will be described below.

[0089] See Figure 9A and Figure 9B An interposer 200 may be provided. In some embodiments, the interposer 200 may be disposed on (or attached to) a carrier R1 via a release film 112. A carrier R1 may be provided to support the encapsulation structure thereon. In some embodiments, a carrier R1 and a release film 112 may not be used. The carrier R1 may be a glass carrier, an organic carrier, etc., in use. The release film 112 may be formed on the carrier R1 for securing the encapsulation element to the carrier R1. The release film 112 may be made of a polymer-based material (e.g., a light-to-heat-conversion (LTHC) material), which may be a heat-release material based on epoxy resin.

[0090] In some embodiments, the interposer 200 may include a plurality of dielectric layers 202, a plurality of conductive pattern layers 204, and a plurality of conductive vias 206. In some embodiments, the dielectric layers 202 and conductive pattern layers 204 may be stacked alternately. In some embodiments, the conductive vias 206 may be embedded in the dielectric layers 202. In some embodiments, the conductive pattern layers 204 may be interconnected through the conductive vias 206. For example, the conductive vias 206 may penetrate the dielectric layers 202 to connect the conductive pattern layers 204. In some embodiments, each conductive pattern layer 204 may include a plurality of conductive patterns as redistributed wiring. In some embodiments, Figure 9A The outermost conductive pattern layer 204 (i.e., the uppermost conductive pattern layer 204 and the lowermost conductive pattern layer 204) shown in the diagram can be referred to as an under-ball metallurgy (UBM) pattern for ball bonding. In some embodiments, the conductive pattern layer 204 can transmit signals horizontally, and the conductive via 206 can transmit signals vertically.

[0091] In some embodiments, the dielectric layer 202 may be made of polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, PBO, or any other suitable polymer-based dielectric material. In some embodiments, the dielectric layer 202 may comprise a filler-mixed resin. The dielectric layer 202 may be formed using suitable manufacturing techniques, such as film lamination, spin coating, CVD, PECVD, etc. In some embodiments, the conductive pattern layer 204 and the conductive via 206 may be made of aluminum, titanium, copper, nickel, tungsten, or alloys thereof. The conductive pattern layer 204 and the conductive via 206 may be formed by electroplating, deposition, and / or photolithography and etching. In some embodiments, the conductive pattern layer 204 and the underlying conductive via 206 may be formed simultaneously. It should be noted that... Figure 9A The number of dielectric layers 202, conductive patterned layers 204, and conductive vias 206 shown is for illustrative purposes only and is not limited thereto. In some alternative embodiments, fewer or more dielectric layers 202, conductive patterned layers 204, and conductive vias 206 may be formed depending on the circuit design.

[0092] In some embodiments, the interposer 200 may have a first surface 200a and a second surface 200b opposite to the first surface 200a. The uppermost conductive patterned layer 204 may be exposed on the first surface 200a, and the lowermost conductive patterned layer 204 may be exposed on the second surface 200b. In some embodiments, the interposer 200 may be a silicon-free substrate. In some embodiments, the interposer 200 may be referred to as an "organic interposer." Organic interposers help reduce the overall process cost of the package structure because they can be low-cost interposers. In some embodiments, the critical dimensions (e.g., linewidth or pitch width) of the organic interposer may be closer to the critical dimensions of at least one semiconductor wafer. In some embodiments, the interposer 200 may be interchangeably referred to as a substrate.

[0093] See also Figure 9A and Figure 9B , Figure 8 At least one semiconductor wafer 100a and at least one semiconductor wafer 100b are bonded to the first surface 200a of the interposer layer 200. As shown... Figure 9A and Figure 9B As shown, each semiconductor wafer 100b may be located next to or around a semiconductor wafer 100a. However, this disclosure is not limited thereto. Those skilled in the art will understand that the number of semiconductor wafers 100a may be greater than [the number of wafers 100a]. Figure 9A and Figure 9B As shown, the number of semiconductor wafers 100b may be more or less than [the specified number]. Figure 9A and Figure 9BAs shown, and can be specified according to requirements and / or design layout. In some alternative embodiments, if more than one semiconductor wafer 100a and more than two semiconductor wafers 100b can be bonded to the interposer 200, then the semiconductor wafers 100b can be located around each semiconductor wafer 100a. In some embodiments, more than one identical semiconductor wafer 100a can be bonded to the interposer 200. However, this disclosure is not limited thereto. In some alternative embodiments, different semiconductor wafers 100a can be bonded to the interposer 200.

[0094] In addition, such as Figure 9A and Figure 9B As shown, semiconductor wafers 100a and 100b can be bonded to the first surface 200a of the interposer 200 via flip chip bonding. That is, each semiconductor wafer 100a and 100b can be upside down, such that the conductive terminals 180 of each semiconductor wafer 100a and 100b can face the interposer 200. Specifically, as... Figure 9A As shown, semiconductor wafers 100a and 100b can be attached to the interposer 200 via conductive terminals 180. For example, the conductive terminals 180 of semiconductor wafers 100a and 100b can physically contact the uppermost conductive pattern layer 204 exposed on the first surface 200a of the interposer 200 to achieve electrical connections between semiconductor wafer 100a and the interposer 200 and between semiconductor wafer 100b and the interposer 200. In some embodiments, after attaching the conductive terminals 180 to the uppermost conductive pattern layer 204 of the interposer 200, a reflow process can be performed to reformat the conductive terminals 180. Furthermore, as... Figure 9A As shown, although two conductive posts 170 and two conductive terminals 180 are shown in the semiconductor wafer 100b for illustrative purposes, those skilled in the art will understand that the number of conductive posts 170 and conductive terminals 180 in the semiconductor wafer 100b may be more or less than [the number shown in the original text]. Figure 9A As shown, and can be specified according to requirements and / or design layout.

[0095] In some implementations, the semiconductor chip 100b may be a memory chip. For example, such as Figure 9A and Figure 9B As shown, semiconductor chip 100b may include either a high bandwidth memory (HBM) chip or a hybrid memory cube (HMC) chip. In these embodiments, such as Figure 9A and Figure 9BAs shown, the semiconductor chip 100b may include a logic chip 12a, a memory chip stack stacked on the logic chip 12a, and a package 14 for laterally packaging the memory chip stack, wherein the memory chip stack includes a plurality of memory chips 12b. The number of memory chips 12b may be less than or more than [number missing]. Figure 9A As shown, and can be specified according to requirements and / or design layout; this disclosure is not limited thereto. In some embodiments, memory chip stacks can be bonded to logic chip 12a, and memory chips 12b can be bonded to each other. In some embodiments, electrical connections between logic chip 12a and memory chip 12b can be established via substrate vias and microbump bonding. However, this disclosure is not limited thereto. In some alternative embodiments, electrical connections between logic chip 12a and memory chip 12b can be established via substrate vias and hybrid bonding metal-to-metal bonding. In some alternative embodiments, electrical connections between logic chip 12a and memory chip 12b can be established via a redistribution structure and via insulating layer vias. In some embodiments, the material of package 14 may include molding compounds, molding underfills, resins (such as epoxy resin, phenolic resin), etc. In some alternative embodiments, the material of package 14 may include silicon dioxide (SiO2). x (where x>0), silicon oxynitride (SiO) x N y (where x>0 and y>0), silicon nitride (SiN) x (where x>0) or other suitable dielectric materials. In some embodiments, the material of the package 14 may further include filler particles (e.g., silica, clay, etc.). In some embodiments, the package 14 can be formed by a molding process. For example, the molding process may be a compression molding process. In some alternative embodiments, the package 14 can be formed by a thin film deposition process. For example, the thin film deposition process includes CVD, high-density plasma chemical vapor deposition (HDPCVD), PECVD, atomic layer deposition (ALD), or combinations thereof. In some embodiments, such as Figure 9A As shown, the top surface T of the semiconductor wafer 100b 100b It can be substantially coplanar with the rear surface RS of the semiconductor substrate 110 in the semiconductor wafer 100a.

[0096] In addition, such as Figure 9A and Figure 9BAs shown, semiconductor chip 100b can be presented as a high-bandwidth memory chip or a hybrid memory cube chip, but this is only an illustrative example. In some alternative embodiments, semiconductor chip 100b can be other types of memory chips, such as dynamic random-access memory (DRAM) chips, static random-access memory (SRAM) chips, or resistive random-access memory (RRAM) chips. Moreover, as Figure 9A As shown, two identical semiconductor wafers 100b can be bonded to the interposer 200. However, this disclosure is not limited thereto. In some alternative embodiments, different semiconductor wafers 100b can be bonded to the interposer 200.

[0097] In some embodiments, a bottom filler layer UF1 may be formed on the interposer 200 to encapsulate semiconductor wafers 100a and 100b. For example... Figure 9A and Figure 9B As shown, the bottom filler layer UF1 encapsulates the conductive pillars 170 and conductive terminals 180 of semiconductor wafers 100a and 100b, as well as the uppermost conductive pattern layer 204 exposed on the first surface 200a of the interposer layer 200 and bonded to the conductive terminals 180 of semiconductor wafers 100a and 100b. Due to the bottom filler layer UF1, the bonding strength between semiconductor wafer 100a and the interposer layer 200, and between semiconductor wafer 100b and the interposer layer 200, is enhanced, thereby improving the reliability of the package structure. In some embodiments, such as... Figure 9A As shown, the underfill layer UF1 can be formed to fill the gap between semiconductor wafer 100a and semiconductor wafer 100b. Specifically, as... Figure 9A and Figure 9B As shown, the bottom filler layer UF1 can completely cover the inner sidewalls of semiconductor wafers 100a and 100b, and partially cover the outer sidewalls of semiconductor wafers 100a and 100b. For example, as... Figure 9A As shown, a portion of the bottom filler layer UF1 located in the gap between semiconductor wafer 100a and semiconductor wafer 100b has a top surface T. UF1 The top surface can be substantially coplanar with the rear surface RS of the semiconductor substrate 110 in the semiconductor wafer 100a. However, this disclosure is not limited thereto. In some alternative embodiments, the top surface T of the bottom filler layer UF1... UF1It can be located below or above the rear surface RS of the semiconductor substrate 110. In some embodiments, the bottom filler layer UF1 can be formed by a capillary flow process after attaching the semiconductor wafers 100a and 100b to the interposer 200. That is, the bottom filler layer UF1 can be introduced into the gaps between the semiconductor wafers 100a and 100b, between the semiconductor wafers 100a and the interposer 200, and between the semiconductor wafers 100b and the interposer 200 by capillary action. In some embodiments, the material of the bottom filler layer UF1 can be an insulating material, including resins (e.g., epoxy resin), filler materials, stress release agents (SRA), adhesion promoters, other materials, or combinations thereof. In some embodiments, the bottom filler layer UF1 can be optional.

[0098] See Figure 10 A package 300 can be formed on the interposer 200 to encapsulate semiconductor wafers 100a and 100b, and the bottom filler layer UF1. For example, the package 300 can laterally encapsulate semiconductor wafers 100a and 100b, and the bottom filler layer UF1. Figure 10 As shown, the top surface T of the package 300 300 It can be used with the rear surface RS of the semiconductor substrate 110 and the top surface T of the semiconductor wafer 100b. 100b and the top surface T of the bottom packing layer UF1 UF1 The components are essentially coplanar. That is, the package 300 exposes the semiconductor substrate 110 of the semiconductor wafer 100a and the memory wafer 12b of the semiconductor wafer 100b. In some embodiments, the package 300 may be a molding compound, a molding underfill, a resin (such as epoxy resin, phenolic resin), etc. In some alternative embodiments, the material of the package 300 may include silicon dioxide (SiO2). x (where x>0), silicon oxynitride (SiO) x N y (where x>0 and y>0), silicon nitride (SiN) x (where x>0) or other suitable dielectric materials. In some embodiments, the package 300 includes filler. The filler may be particles made of silicon dioxide, alumina, etc. In some embodiments, the package 300 may be formed by molding processes, injection molding processes, thin film deposition processes, combinations thereof, etc. Molding processes include, for example, transfer molding processes, compression molding processes, etc. Thin film deposition processes include, for example, CVD, HDPCVD, PECVD, ALD, or combinations thereof.

[0099] See Figure 11 The top surface T of package 300 300The rear surface RS of semiconductor substrate 110 and the top surface T of semiconductor wafer 100b 100b The top surface TUF1 of the bottom filler layer UF1 can be disposed on (or fixed to) the carrier R2 via the release film 113. That is, each semiconductor wafer 100a and semiconductor wafer 100b can be upside down, so that the interposer layer 200 can be located away from the carrier R2. The carrier R2 can be provided to support the package structure thereon. In some embodiments, the carrier R2 and the release film 113 may not be used. The carrier R2 can be a glass carrier, an organic carrier, etc., when used. The release film 113 can be formed on the carrier R2 for fixing the packaged elements to the carrier R2. The release film 113 can be made of a polymer-based material (e.g., a light-to-heat-conversion (LTHC) material), which may be a heat-release material based on epoxy resin.

[0100] Subsequently, according to some embodiments, the carrier R1 can be removed from the intermediate layer 200. According to some embodiments, a light beam (such as a laser beam) is projected onto the release membrane 112, which can decompose under the heat of the light beam. Therefore, the intermediate layer 200 and the structure thereon can be released from the carrier R1.

[0101] See Figure 12 A substrate 114 may be provided. The substrate 114 may be made of suitable element semiconductors, such as crystalline silicon, diamond, or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. In some embodiments, the substrate 114 may have active elements (e.g., transistors or similar elements) and / or integrated passive devices (IPDs) (e.g., resistors, capacitors, inductors, or similar elements) formed therein. In some embodiments, the substrate 114 may be bonded to the second surface 200b of the interposer 200 by flip-chip bonding. That is, each element in the substrate 114 may be upside down, such that the conductive terminals (not shown) of the substrate may face the interposer 200. Therefore, the substrate can be attached to the interposer 200 through the conductive terminals thereon. For example, the conductive terminals of the substrate 114 can physically contact the conductive pattern layer 204 exposed on the second surface 200b of the interposer 200 to achieve electrical connection between the components in the substrate 114 and the interposer 200.

[0102] See Figure 13 It can be Figure 12The carrier R2 in the structure shown is removed from the package 300, semiconductor substrate 110, semiconductor wafer 100b, and bottom filler layer UF1. According to some embodiments, a light beam (such as a laser beam) is projected onto the release film 113, which can be decomposed by the heat of the beam. Subsequently, the... Figure 12 The structure shown is placed on a carrier R3. The carrier R3 may include a frame and a thin film tightly supported by the frame. In some embodiments, the carrier R3 may help provide support for forming the conductive layer BSM1 on the semiconductor wafer 100a, semiconductor wafer 100b, and package 300. However, this disclosure is not limited thereto. In some alternative embodiments, the carrier R3 may be a glass carrier to facilitate carrier bonding processes on the substrate 114.

[0103] The conductive layer BSM1 can be formed to physically contact the top surface T of the package 300. 300 The rear surface RS of semiconductor substrate 110 and the top surface T of semiconductor wafer 100b 100b and the top surface T of the bottom filler layer UF1 UF1 This forms a reconstructed wafer. In some embodiments, the conductive layer BSM1 may include multiple metal layers, including an adhesion layer to ensure strong bonding, a diffusion barrier layer to prevent unwanted material migration, and an antioxidant layer (e.g., gold) to prevent environmental damage. However, this disclosure is not limited thereto. In some embodiments, the material of the conductive layer BSM1 may include metals such as aluminum (Al), titanium (Ti), nickel (Ni), vanadium (V), tantalum (Ta), silver (Ag), and gold (Au). In some embodiments, the thickness of the conductive layer BSM1 may range from about 0.1 μm to about 10 μm. In some embodiments, the conductive layer BSM1 may be formed by sputtering, electroplating, deposition, or deposition processes. It should be noted that the conductive layer BSM1 may be used to facilitate the subsequent formation of a thermal interface material (TIM) layer (e.g., Figure 15 The thermal interface material 116 shown is adhered to the package structure and can be referred to as back metallization or back metal layer. In some alternative embodiments, no metallization is applied to the top surface T of the package 300. 300 The rear surface RS of semiconductor substrate 110 and the top surface T of semiconductor wafer 100b 100b A conductive layer BSM1 is formed on the top surface TUF1 of the bottom filler layer UF1. In some embodiments, the conductive layer BSM1 can be formed overlapping the back surface RS of the semiconductor substrate 110 and the top surface T of the semiconductor wafer 100b. 100b and the top surface T of the bottom filler layer UF1 UF1 The top surface T of the package 300 does not overlap (or partially overlaps) 300 .

[0104] Subsequently, the reconstructed wafer can be sawed open to form a separate package structure PKG. In some embodiments, the package structure PKG can be a large-size, fully planar wafer-wafer-substrate package. The molded package 300 and the bottom filler layer UF1 can be diced to obtain... Figure 13 The package structure shown is PKG. Although for illustrative purposes... Figure 13 Only one package structure PKG is shown, but those skilled in the art will understand that multiple package structure PKGs can be obtained after a dicing process. In some embodiments, the dicing process typically includes cutting using a rotating blade and / or a laser beam. In other words, the dicing process can include laser dicing, mechanical dicing, laser dicing, other suitable processes, or combinations thereof. In some embodiments, the package structure PKG can be considered as being formed by a wafer-on-wafer process, and the package structure PKG is also referred to as a wafer-on-wafer package. In some embodiments, the package structure PKG can have a rectangular top view with first and second dimensions M1 and M2 (see [reference needed]). Figure 17B In some embodiments, dimension M1 may be substantially the same as dimension M2. In some embodiments, dimension M1 may be smaller or larger than dimension M2. By way of example only and not limitation, dimension M1 may be in the range of about 50 to 150 mm, for example, about 50, 55, 60, 65, 70, 75, 80, 85, 90, 91, 95, 100, 110, 120, 130, 140 or 150 mm. In some embodiments, dimension M2 may be in the range of about 50 to 150 mm, for example, about 50, 55, 60, 65, 70, 75, 80, 85, 90, 91, 95, 100, 110, 120, 130, 140 or 150 mm.

[0105] See Figure 14 Flux 115 can be applied to the conductive layer BSM1 to achieve better adhesion. For example, in the metal thermal interface material 116 (see... Figure 15 Before being placed on the conductive layer BSM1, flux 115 can be formed on the package structure PKG. In some embodiments, the formation of flux 115 may include a spraying process or a dispensing process. In some embodiments, the flux may be a solder flux. In some embodiments, the material of flux 115 may include rosin or acids.

[0106] See Figure 15A thermal interface material 116 can be formed on the conductive layer BSM1. In some embodiments, the thermal interface material 116 can be a sheet material. In some embodiments, the thermal interface material 116 can be formed on the conductive layer BSM1 by a pick-and-place process. In some embodiments, the material of the thermal interface material 116 can be a solder-type material. In some embodiments, the thermal interface material 116 can be formed of a pure metal material and can be interchangeably referred to as a metallic thermal interface material. In some embodiments, the thermal interface material 116 may not contain organic materials and polymer materials. In some embodiments, the material of the thermal interface material 116 includes metallic materials, such as indium, copper, tin, silver, or alloys thereof. In some embodiments, the thermal conductivity of the thermal interface material 116 ranges from about 10 W / (m·K) to about 90 W / (m·K). In some embodiments, the Young's modulus of the thermal interface material 116 ranges from about 5 GPa to about 70 GPa.

[0107] In some embodiments, the thermal interface material 116 may overlap with the semiconductor wafers 100a and 100b. For example, the vertical projection of the thermal interface material 116 onto the interposer 200 may completely overlap with the vertical projection of the semiconductor wafer 100a onto the interposer 200. However, this disclosure is not limited thereto. In some alternative embodiments, the vertical projection of the thermal interface material 116 onto the interposer 200 may partially overlap the vertical projections of the semiconductor wafers 100a and 100b onto the package element 20. From another perspective, the thermal interface material 116 may at least be formed to correspond to the positions of the semiconductor wafers 100a and 100b.

[0108] See Figure 16 Flux 117 can be applied to the thermal interface material 116 to achieve better adhesion. For example, when applying the cover structure 70 (see...) Figure 18A Before being placed on the thermal interface material 116, flux 117 may be formed on the thermal interface material 116. In some embodiments, the formation of flux 117 may include a spraying process or a dispensing process. In some embodiments, the flux may be a solder flux. In some embodiments, the material of flux 117 may include rosin or acid.

[0109] See Figure 17A and Figure 17B Adhesive structures 60 and 62 can be formed on the conductive layer BSM1. Specifically, adhesive structure 60 can be formed near the edge of the encapsulation structure PKG to surround / encircle the thermal interface material 116. In some embodiments, adhesive structure 60 partially overlaps the encapsulation body 300 and is physically isolated from the encapsulation structure PKG and the bottom filler layer UF1. In some embodiments, adhesive structure 60 has a ring-shaped shape in a plan view, as shown in the top view (see top view). Figure 17BIt has at least one opening O1 (see Figure 17B This forms separate line segments 60s. In other words, the adhesive structure 60 may have an opening O1 in the top view that exposes the package 300. The opening O1 in the adhesive structure 60 helps to accommodate the thermal expansion and contraction of the material within the package during the curing process or thermal cycling. By allowing flexibility in the adhesive structure 60, it helps to relieve stress and prevent the adhesive structure 60 from warping or deforming, which could lead to peeling or cracking. In some embodiments, the pattern of the adhesive structure 60 can be designed according to various designs. For example, the adhesive structure 60 may have linear, L-shaped, U-shaped, dotted, and other shapes. In some embodiments, the shape of the adhesive structure 60 may depend on the shape of the package structure PKG. For example, when the package structure PKG may be in panel form (i.e., having a rectangular or square top view), the adhesive structure 60 may present a rectangular or square ring shape in the top view. In some embodiments, the adhesive structure 60 may be interchangeably referred to as an adhesive layer.

[0110] Adhesive structure 62 may be formed near thermal interface material 116 to surround / encircle thermal interface material 116 and spaced apart from adhesive structure 62. Alternatively, adhesive structure 60 may surround / encircle adhesive structure 62. In some embodiments, adhesive structure 62 partially overlaps encapsulation 300 and is physically isolated from encapsulation structure PKG and bottom filler layer UF1. In some embodiments, adhesive structure 62 has a ring shape in a plan view, as shown in the top view. In some embodiments, adhesive structure 62 may be a layered structure with multiple vertically stacked layers, the number of layers being greater than 2, such as 2, 3, 4, or 5. By way of example only and not limitation, adhesive structure 62 may be a two-layer ring structure having a first layer 62a and a second layer 62b, the second layer 62b being located on and contacting the top of the first layer 62a. In some embodiments, adhesive structure 62 may have a vertical dimension H1 (e.g., height) greater than that of adhesive structure 60. By way of example only and not limitation, the vertical dimension H2 of the adhesive structure 60 can be in the range of about 0.05-0.50 mm, for example about 0.05, 0.10, 0.15, 0.20, 0.25, 0.30, 0.35, 0.40, 0.45, 0.50 mm, and the vertical dimension H1 of the adhesive structure 62 can be in the range of about 0.1-1.00 mm, for example about 0.10, 0.20, 0.30, 0.40, 0.50, 0.55, 0.60, 0.70, 0.80, 0.90, 1.00 mm.

[0111] In some embodiments, the adhesive structure 62 may have at least one opening to prevent deformation of the adhesive structure 62. In some embodiments, in the laminated structure of the adhesive structure 62, an opening (e.g., opening O2, as shown) is provided on the top layer (e.g., the second layer 62b). Figure 17BAs shown), to form separate line segments 62s, the adhesive structure 62 can therefore be interchangeably referred to as a bonding barrier structure. In other words, the second layer 62b of the adhesive structure 62 can have an opening O2. The opening O2 in the top layer of the adhesive structure 62 helps to accommodate the thermal expansion and contraction of the material within the encapsulation during the curing process or thermal cycling. By allowing flexibility in the adhesive structure 62, it helps to alleviate stress and prevent the adhesive structure 62 from warping or deforming, which could lead to peeling or cracking. Figure 17B As shown in the top view, a portion of the first layer 62a can be exposed from the opening O2 of the second layer 62b.

[0112] Conversely, the bottom layer of the adhesive structure 62 (e.g., the first layer 62a) is solid, without any openings, to act as a closed barrier for the thermal interface material 116. During subsequent curing or reflow processes, the thermal interface material 116 can become more fluid. Without a solid barrier, the thermal interface material 116 could flow out from above the semiconductor wafers 100a / 100b into unwanted components, leading to inadequate thermal management or contamination of adjacent areas within the package. By preventing the thermal interface material 116 from flowing out (or leaking / overflowing), the first layer 62a ensures a uniform and consistent thermal interface material 116 is formed in the area between the semiconductor wafers 100a / 100b and the cover structure 70, ensuring maximum contact area and minimizing thermal resistance. Therefore, the top surface 62t2 (or highest position) of the second layer 62b can have a greater height than the top surface 116t (or highest position) of the thermal interface material 116 and / or the top surface 60t (or highest position) of the adhesive structure 60. In some embodiments, the first layer 62a of the adhesive structure 62 may be interchangeably referred to as the first adhesive layer, and the second layer 62b of the adhesive structure 62 may be interchangeably referred to as the second adhesive layer.

[0113] In some embodiments, the pattern of the adhesive structure 62 can be designed according to various designs. For example, the adhesive structure 62 can have linear, L-shaped, U-shaped, dotted, or other shapes. In some embodiments, the shape of the adhesive structure 62 can depend on the shape of the encapsulation structure PKG. For example, when the encapsulation structure PKG can be in the form of a panel (i.e., having a rectangular or square top view), the adhesive structure 62 can present a rectangular or square ring shape in the top view. In some embodiments, the width W1 of the adhesive structure 60 (see...) Figure 17B The width W2 of the adhesive structure 62 (see...) Figure 17BThe width W1 can be greater than the width W2. In some embodiments, the width W1 of the adhesive structure 60 is greater than the width W2 of the adhesive structure 62 because they serve different purposes. The adhesive structure 60 is located at the outer edge of the package, providing robust mechanical support and distributing stress over a larger area, which helps maintain the structural integrity of the package. The adhesive structure 62 is located near the core of the thermal interface material, and its narrower width is sufficient to accommodate the thermal interface material and prevent its excessive diffusion, ensuring its effectiveness in heat management without taking up unnecessary space. Therefore, the width W1 can be greater than the width W2 to balance structural stability and effective thermal management. In some embodiments, the ratio of width W1 to width W2 can be in the range of about 1.1 to 10, such as 1.1, 2, 3, 4, 5, 6, 7, 8, 9, or 10. By way of example only and not limitation, the width W1 of the adhesive structure 60 may be in the range of about 2 to 15 mm, such as about 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 or 15 mm, and the width W2 of the adhesive structure 62 may be in the range of about 0.5 to 5 mm, such as about 0.5, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5 or 5 mm.

[0114] In some embodiments, the adhesive structure 60 can be applied to the conductive layer BSM1 by a dispensing process, spin coating process, or similar process. A first layer 62a of adhesive structures 60 and 62 can be formed first, followed by the formation of a second layer 62b of adhesive structure 62 on the first layer 62a. In some embodiments, the thermal conductivity of adhesive structures 60 / 62 can be greater than about 0 W / m·K to 5 W / m·K. In some embodiments, adhesive structures 60 / 62 can comprise an epoxy resin-based material. However, this disclosure is not limited thereto. In some alternative embodiments, other polymeric materials with adhesion properties can be used as adhesive structures 60 / 62. In some embodiments, adhesive structure 62 can be made of the same material as adhesive structure 60. In some embodiments, adhesive structure 62 can be made of a different material than adhesive structure 60. In some embodiments, the first layer 62a of adhesive structure 62 can be made of the same material as the second layer 62b of adhesive structure 60, thus forming a distinguishable interface between the first layer 62a and the second layer 62b. In some embodiments, the first layer 62a of the adhesive structure 62 may be made of a different material than the second layer 62b of the adhesive structure 60, so that no distinguishable interface may be formed between the first layer 62a and the second layer 62b.

[0115] See Figures 18A to 18GThe cover structure 70 can be placed on the thermal interface material 116 and the adhesive structures 60 and 62, so that the encapsulation structure PKG can be located between the cover structure 70 and the substrate 114. In some embodiments, the cover structure 70 can have a heat dissipation function. In other words, the heat generated during the operation of the encapsulation structure PKG can be dissipated through the path created by the cover structure 70. In some embodiments, the cover structure 70 can be made of metal, plastic, ceramic, etc. The metals of the cover structure 70 include, but are not limited to, aluminum, copper, stainless steel, solder, gold, nickel, molybdenum, NiFe, or NiFeCr. In some embodiments, the thermal conductivity of the cover structure 70 ranges from about 80 W / (m·K) to about 450 W / (m·K). In some embodiments, the Young's modulus of the cover structure 70 ranges from about 50 GPa to about 200 GPa.

[0116] In some embodiments, the cover structure 70 may be planar, containing at least one groove (e.g., grooves 70t1, 70t2) including a central cover portion 70c, feet 70g extending around its periphery, and a protrusion 70p projecting from the center of the cover portion. In some embodiments, the feet 70g may be interchangeably referred to as feet, protrusions, or peripheral areas, while the protrusion may be interchangeably referred to as the central portion. In some embodiments, the extension direction of the cover portion 70c may be perpendicular to the extension direction of the feet 70g. From another perspective, in some embodiments, the cover portion 70c extends along the X and Y directions, and the feet 70g extends along the Z direction. In some embodiments, the cover portion 70c and the feet 70g may be integrally formed. In some embodiments, the feet 70g may be attached to the conductive layer BSM1 during the curing process via an adhesive structure 60. In some embodiments, the shape of the feet 70g may depend on the shape of the encapsulation structure PKG. For example, when the package structure PKG can be in panel form (i.e., having a rectangular or square top view), the foot 70g can present a rectangular or square annular shape in the top view. In other words, the bottom surface area of ​​the trench 70t1 can have an annular shape, surrounding the bottom surface area of ​​the semiconductor wafers 100a and 100b on the interposer layer 200, and can be interchangeably referred to as an annular trench.

[0117] In some embodiments, the protruding portion 70p may protrude from the surface of the covering portion 70c. For example... Figure 18AAs shown, the bottom surface of the protrusion 70p is at the same height as the bottom surface of the foot 70g. In some embodiments, the protrusion 70p and the cover 70c can be integrally formed. For example, the material of the protrusion 70p can be the same as the material of the cover 70c. However, this disclosure is not limited thereto. In some alternative embodiments, the protrusion 70p can be mounted on the cover 70c. For example, the material of the protrusion 70p can be different from the material of the cover 70c. In some embodiments, the encapsulation structure PKG is located below the protrusion 70p of the cover structure 70.

[0118] In some embodiments, voids may be created within the thermal interface material 116 of the semiconductor package or around the cover structure 70, which in turn affects the thermal performance of the package. These voids can be air gaps formed during assembly, including during solder reflow, application of the thermal interface material, or thermal cycling of the package. In some embodiments, voids may be created due to the venting of solvent or flux. Voids can act as thermal insulators, reducing the overall heat dissipation efficiency from the semiconductor wafer 100a / 100b to the cover structure 70 due to the low thermal conductivity of air. Furthermore, voids may impair the mechanical bond between the thermal interface material 116 and the cover structure 70, reducing the structural integrity of the package and making it more susceptible to peeling or failure during thermal cycling.

[0119] Therefore, at least one groove (e.g., grooves 70t1, 70t2) can be formed on the back side of the cover structure 70 to mitigate the effects of voids. The grooves formed on the back side of the cover structure 70 can serve as reservoirs for storing venting material, flux, and air, which may create voids in the interface region. By providing grooves 70t1 and 70t2 to allow voids to escape, the formation of voids within the thermal interface material 116 or between the thermal interface material 116 and the cover structure 70 can be minimized. By reducing the presence of voids, grooves 70t1 and 70t2 can improve the thermal conductivity of the interface, thereby increasing heat dissipation efficiency and extending device life. In some embodiments, grooves 70t1 and 70t2 formed on the back side of the cover structure 70 can be interchangeably referred to as cavities.

[0120] Specifically, the groove 70t1 can be defined by the foot 70g and the protrusion 70p of the cover structure 70, allowing the foot 70g to surround the groove 70t1 from the outside and the protrusion 70p to surround the groove 70t1 from the inside. In other words, the foot 70g, the groove 70t1, and the protrusion 70p of the cover structure 70 create a concentric layout. The bottom surface area of ​​the groove 70t1 (see...) Figure 18B and Figure 18GThe trench 70t2 can have a ring shape, surrounding the bottom surface area of ​​the semiconductor wafers 100a and 100b on the interposer layer 200. The trench 70t2 can provide additional space for the bonding structure 62 to control package deformation and prevent leakage of thermal interface materials. (See Trench 70t2) Figure 18B and Figure 18G It can have a linear shape and be positioned in a location that does not overlap with semiconductor wafers 100a and 100b. Instead, it overlaps with semiconductor wafer 100b (see...). Figure 18G The gaps or areas between the trenches (e.g., the bottom packing layer UF1) are aligned. In some embodiments, the trenches 70t2 may be interchangeably referred to as linear trenches. In some embodiments, the bottom surface area of ​​the trenches 70t2 is located within the bottom surface area of ​​the bottom packing layer UF1. For example... Figure 18G As shown, the bottom surface area of ​​trench 70t1 can surround the bottom surface area of ​​trench 70t2. The depth of trench 70t2 is the same as the depth of trench 70t1, and trench 70t2 is connected to trench 70t1 (see [reference]). Figure 18D and Figure 18E In some embodiments, the groove 70t2 may be aligned with the opening O2 on the adhesive structure 62. In some embodiments, the groove 70t2 may be located on the opposite side of the thermal interface material 116.

[0121] like Figure 18B As shown, from a top view, the cover structure 70 may have a dimension D3 in the X direction (see...). Figure 18C and Figure 18D ) and has a dimension D4 in the Y direction (see Figure 18E and Figure 18F The protruding portion 70p can have a dimension D5 in the X direction (see...). Figure 18C and Figure 18D ) and has a dimension D6 in the Y direction (see Figure 18E and Figure 18F The first part of a pair of feet extending along the Y direction, 70g, can have a width of W3 (see...). Figure 18C and Figure 18D The second part of a pair of feet extending along the X direction, 70g, can have a width of W4 (see...). Figure 18E and Figure 18F The first portion of a pair of grooves 70t1 extending along the Y direction may have a width W5 (see...). Figure 18C The second portion of a pair of grooves 70t1 extending along the X direction may have a width W6 (see...). Figure 18E and Figure 18F(This is for illustrative purposes only and not as a limitation.) Width W5 can be in the range of approximately 1 to 30 mm, such as approximately 1, 5, 10, 15, 20, 25, or 30 mm. Width W6 can be in the range of approximately 1 to 30 mm, such as approximately 1, 5, 10, 15, 20, 25, or 30 mm. Groove 70t2 can have width W7 (see...). Figure 18F ) and length L1 (see Figure 18D (This is by way of example only and not limitation.) The length L1 of the groove 70t2 can be in the range of about 1 to 30 mm, for example, about 1, 5, 10, 15, 20, 25, or 30 mm. In some embodiments, the width W7 of the groove 70t2 can be less than the width W3 and / or the width W3 of the first and second portions of the groove 70t1 (see [link to documentation]). Figures 18C to 18F (For illustrative purposes only and not as a limitation, the width W7 can be in the range of approximately 0.3 to 20.0 mm, such as approximately 0.3, 1, 2, 4, 6, 8, 9, 12, 14, 16, 18 or 20.0 mm, and the length can be in the range of approximately 0.3 to 20.0 mm, such as approximately 0.3, 1, 2, 4, 6, 8, 9, 12, 14, 16, 18 or 20.0 mm.)

[0122] like Figures 18C to 18F As shown, the cover structure 70 may have a vertical dimension D7 (e.g., thickness). By way of example and not limitation, the vertical dimension D7 may be in the range of about 1 to 4 mm, for example, about 1, 1.5, 2, 2.5, 3, 3.5, or 4 mm. The groove 70t1 may have a vertical dimension D8 (e.g., depth), and the groove 70t2 may have a vertical dimension D9 (e.g., depth). In some embodiments, the vertical dimension D9 may be the same as the vertical dimension D8. In some embodiments, the vertical dimension D9 may be different from the vertical dimension D8. By way of example and not limitation, dimension D8 may be in the range of about 0.2 to 1.0 mm, for example, about 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, or 1.0 mm. The vertical dimension D8 may be in the range of about 0.2 to 1.0 mm, for example, about 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, or 1.0 mm.

[0123] In some embodiments, a conductive layer BSM2 may be formed on the protrusion 70p of the cover structure 70 prior to attaching the cover structure 70. In some embodiments, the conductive layer BSM2 may be formed at the bottom of the trench 70t2 (see [link to documentation]). Figure 18DIt should be noted that the conductive layer BSM2 can be used to promote the adhesion between the metal thermal interface material 116 and the cover structure 70, and can be referred to as back metallization or back metal layer. In some embodiments, the material of the conductive layer BSM2 can be the same as the material of the conductive layer BSM1. In some alternative embodiments, the material of the conductive layer BSM2 can be different from the material of the conductive layer BSM1. In some embodiments, the conductive layer BSM2 can be formed on the cover structure 70 by plating, sputtering, or dispensing processes. In some embodiments, the material of the conductive layer BSM2 can include metals such as aluminum, titanium, nickel, vanadium, gold, silver, or copper. In some embodiments, the conductive layer BSM2 can be a gold-plated heat sink. That is, the back side of the cover structure 70 can be gold-plated (Au) to improve thermal conductivity and oxidation resistance. In some embodiments, the conductive layer BSM2 can be interchangeably referred to as a gold layer.

[0124] In some embodiments, after forming the conductive layer BSM2 on the cover structure 70, the cover structure 70 and the conductive layer BSM2 can be placed on the thermal interface material 116 and the adhesive structures 60 and 62, so that the conductive layer BSM2 can be in physical contact with the top surface of the metal thermal interface material 116, and the cover structure 70 can be in physical contact with the top surfaces of the adhesive structures 60 and 62. This allows for near-complete coverage of the thermal interface material 116 on the packaging structure PKG. Figure 18A As shown, the second layer 62b of the adhesive structure 62 can be located within the first trench. In some embodiments, the first layer 62a of the adhesive structure 62 can be located outside the trench 70t1. That is, the top surface of the first layer 62a can be located at a lower height than the bottom surface 70b of the cover structure 70. In some embodiments, at least a portion of the first layer 62a of the adhesive structure 62 can be located within the trench 70t1. That is, the top surface of the first layer 62a can be located at a higher height than the bottom surface 70b of the cover structure 70. In some embodiments, the top surface of the first layer 62a can be located at the same height as the bottom surface 70b of the cover structure 70.

[0125] In some implementations, the coverage may be greater than about 95%, such as about 95%, 96%, 97%, 98%, 99%, 99.5%, or 99.9%. The adhesive structures 60 and 62, including their placement and the merging of openings (e.g., openings O1 and O2), can help manage thermal stress and accommodate material expansion, thereby minimizing the likelihood of bond failure or peeling by allowing the structure to bend or expand without compromising its integrity or overall adhesion. Furthermore, incorporating grooves (e.g., grooves 70t1 and 70t2) in the cover structure 70 can help trap venting material and reduce void formation, thereby maintaining uniform contact between the thermal interface material 116 and the encapsulation structure PKG, ensuring complete coverage.

[0126] In some alternative embodiments, the conductive layer BSM2 is not formed on the cover structure 70. For example... Figure 18A As shown, the thermal interface material 116 can be located between the protrusion 70p of the cover structure 70 and the encapsulation structure PKG. The adhesive structures 60 and 62 can be located between the foot 70g of the cover structure 70 and the encapsulation body 300.

[0127] See Figure 18H and Figure 18I . Figure 18H and Figure 18I Explained with Figure 18G A schematic top view of the corresponding package, according to some embodiments disclosed herein. Although Figure 18H and Figure 18I The illustration shows the diagram. Figures 1 to 18G The illustrations depict different adhesive structure configurations and different cover structure configurations, but reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and is not intended to determine the relationship between the various embodiments and / or configurations discussed.

[0128] like Figure 18H As shown, the adhesive structure 60 may include more openings O1 (e.g., four openings O1), thereby forming a structure that is more flexible than the adhesive structure 60. Figure 18G The adhesive structure 60 shown has more separation segments (60s). Similarly, the second layer 62b of the adhesive structure 62 may include more openings O2 (e.g., four openings O2), thereby forming a more... Figure 18G The adhesive structure 62 shown has more separation segments 62s. In some embodiments, more openings (e.g., openings O1 and / or O2) can facilitate better thermal management by allowing for a more uniform distribution of thermal stress within the package structure. Furthermore, more openings (e.g., openings O1 and / or O2) can introduce additional flexibility within the adhesive structure (e.g., adhesive structures 60 and / or 62) to more effectively accommodate thermal expansion and contraction. This flexibility helps reduce the risk of mechanical stress buildup, which could lead to peeling or cracking of the adhesive layer. Additionally, more openings (e.g., openings O1 and / or O2) can allow the adhesive structure (e.g., adhesive structures 60 and / or 62) to better adapt to package deformation, maintaining effective bonding and thermal interfaces between packaged elements.

[0129] like Figure 18IAs shown, the trench 70t2 can have a linear shape and be positioned to avoid overlapping with the semiconductor wafers 100a and 100b. The trench 70t2 can also be positioned to align with the gap (e.g., the underfill layer UF1) between the semiconductor wafers 100a and 100b. In some embodiments, the bottom surface area of ​​the trench 70t2 is located within the bottom surface area of ​​the underfill layer UF1. This alignment of the trench 70t2 serves as a preventative measure against the formation of thermal barriers by trapping exhaust material and air that could potentially create insulating gaps, ensuring a more efficient thermal interface between the semiconductor wafers 100a and 100b and the cover structure 70, and promoting better heat dissipation.

[0130] See Figure 19 Subsequently, the cover structure 70 and the conductive layer BSM2 are pressed onto the thermal interface material 116 and the adhesive structures 60 and 62. In some embodiments, pressing the cover structure 70 and the conductive layer BSM2 onto the thermal interface material 116 and the adhesive structures 60 and 62 may include a thermal clamping process P1, wherein the process temperature of the thermal clamping process is in the range of approximately 60°C to approximately 300°C.

[0131] See Figures 20A to 20E Subsequently, a curing process P2 can be performed on the adhesive structures 60 and 62, allowing the cover structure 70 to attach to the package 300 and / or the conductive layer BSM1 via the adhesive structures 60 and 62. Specifically, a curing process can be performed on the adhesive structures 60 and 62 to securely fix the cover structure 70 to the package 300 and / or the conductive layer BSM1. In some embodiments, the process temperature range of the curing process is from about 60°C to about 300°C. However, this disclosure is not limited thereto. In some embodiments, during the curing process, the cover structure 70 can be attached to the package structure PKG via the attached protrusions 70p and the thermal interface material 116. That is, in these embodiments, a good physical and metallurgical bond exists between the cover structure 70 and the package structure PKG during the curing process. In these embodiments, the process temperature range of the curing process is from about 160°C to about 260°C.

[0132] In some embodiments, during the curing process P2, the thermal interface material 116 may flow due to the heat applied during curing. Prior to curing process P2, the thermal interface material 116 may be positioned in a manner that does not contact the adhesive structure 62. During curing, the heat may cause the thermal interface material 116 to become more fluid, allowing it to flow and diffuse. After curing process P2, the thermal interface material 116 may have flowed to direct contact with the adhesive structure 62. This contact can... Figure 20C and Figure 20DThe illustration shows how the thermal interface material 116 expands to fill gaps and voids. During the curing process, the flow of the thermal interface material is controlled to ensure it does not overflow or exceed predetermined boundaries. The adhesive structure 62 acts as a barrier to control the diffusion of the thermal interface material 116 and maintain its integrity.

[0133] like Figure 20C and Figure 20D As shown, the adhesive structure 62 can be separated from the outermost semiconductor wafer 100a / 100b by a lateral distance D2, and can be separated from the protruding portion 70p of the cover structure 70 by a lateral distance D10. Figure 20C The distance D10 between the adhesive structure 62 and the protruding part 70p is... Figure 20D The difference in distance is mainly due to the presence of linear grooves 70t2, which lengthens the space between the two features. Figure 20C In this context, the lateral distance D10 can represent the lateral spacing between the adhesive structure 62 and the protrusion 70p, without any intermediate structures altering this path. However, in Figure 20D In this context, the linear groove 70t2 located between the adhesive structure 62 and the protrusion 70p can increase the lateral distance. This linear groove 70t2 can effectively extend the path, resulting in... Figure 20D The measured value of this distance is compared to Figure 20C The lateral distance D10 is larger. In some implementations, Figure 20D The lateral distance in the middle (through the linear groove 70t2) and Figure 20C The ratio of the lateral distance D10 in the groove can reflect the extent to which this interval is increased. In some implementations, Figure 20D The lateral distance in the middle (through the 70t2 trench) and Figure 20C The ratio of the lateral distance D10 in the package can range from approximately 1.1 to 100, for example, approximately 1.1, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, or 100. This ratio may depend on the specific configuration and dimensions of the linear trench 70t2, allowing design flexibility to accommodate different thermal expansion characteristics and structural requirements within the package.

[0134] In some embodiments, distance D2 may be greater than distance D10. By way of example only and not limitation, distance D2 may be less than about 3.0 mm, for example, about 0.5, 1, 1.5, 2, 2.5, or 3 mm. In some embodiments, distance D10 may be in the range of about 0.1 to 1 mm, for example, about 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, or 1.0 mm. By way of example only and not limitation, distance D2 may be less than about 3.0 mm, for example, about 0.5, 1, 1.5, 2, 2.5, or 3 mm. In some embodiments, the width W2 of the adhesive structure 62 may be less than distance D2. In some embodiments, the width W2 of the adhesive structure 62 may be greater than distance D10. Figure 20C and Figure 20D In the case of the cover structure 70, the protruding portion 70p may have a vertical dimension D11 (e.g., thickness). By way of example only and not a limitation, the vertical dimension D11 may range from about 0.2 to 1.0 mm, for example, about 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, or 1.0 mm. Figure 20D As shown, the presence of linear groove extensions provides additional space, thus facilitating the placement of the opening O2 at this location without concern for the thermal expansion of the thermal interface material 116 beyond the first layer 62a. Figure 20E In the middle, the line segment 62s of the second layer 62b of the adhesive structure 62 (see Figure 17B It can have a maximum distance D1. As an example and not a limitation, the distance D1 can be in the range of about 0.1 to 0.5 mm, for example about 0.1, 0.2, 0.3, 0.4 or 0.5 mm.

[0135] See Figure 21A and Figure 21B An external cooling process can be performed to manage the thermal performance of the packaged PKG. This external cooling process may include applying cooling techniques to the outside of the semiconductor package to enhance heat dissipation. The external cooling process may include a heat sink cooling process P3 (see...). Figure 21A ) and immersion cooling process P4. (e.g.) Figure 21A As shown, the heat sink cooling process P3 can be performed by directly attaching the heat sink 75 to the surface of the cover structure 70. The heat sink 75 can be made of a material with high thermal conductivity, such as aluminum or copper, to maximize the surface area in contact with air. As the device operates and generates heat, this heat can be transferred from the encapsulation structure PKG to the heat sink 75 via the thermal interface material 116. The heat sink 75 can then dissipate the heat into the surrounding air via natural convection or forced airflow (typically assisted by a fan or blower). Figure 21BAs shown, the immersion cooling process P4 can be carried out by immersing the package structure PKG in a liquid with high thermal conductivity but electrical insulation. This insulating coolant can absorb heat from the package surface (including the cover structure 70) and then circulate to remove the heat. The heated liquid can be cooled externally, for example, through a heat exchanger, and then recirculated.

[0136] Therefore, based on the above discussion, it can be seen that this disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, not all of which are disclosed herein, and no specific advantage is claimed in any embodiment. Various embodiments of this disclosure provide a flat cover structure on a package with internal trenches (or cavities) that mitigates delamination and the formation of irregular voids associated with the use of metal thermal interface materials between the cover structure and the package. The additional trenches within this cover structure can provide space for constructing a bonding barrier structure. The bonding barrier structure may include two or more layers of bonding agent surrounding the chip-on-wafer (CoW) to control package deformation and suppress leakage / overflow of metal thermal interface material between the cover structure and the package. Furthermore, the top layer of the bonding barrier structure with openings can prevent potential deformation of the barrier structure itself.

[0137] In some embodiments, a method of manufacturing a package structure includes: bonding a package element to a substrate; forming a package material laterally surrounding the package element; forming a thermal interface material layer on the package element; forming a first adhesive layer on the package material, wherein the first adhesive layer laterally surrounds the thermal interface material; attaching a bottom surface of a cover structure to the thermal interface material, wherein the cover structure has a first groove recessed from the bottom surface of the cover structure, a planar area of ​​the first groove on the substrate surrounding a planar area of ​​the package element on the substrate, and a planar area of ​​the first adhesive layer on the substrate surrounding a planar area of ​​the first groove on the substrate. In some embodiments, a top surface of the package element is flush with a top surface of the package material. In some embodiments, viewed from a top view, the first adhesive layer has an opening. The opening of the first adhesive layer exposes the package material. In some embodiments, the method of manufacturing a package structure further includes: forming a second adhesive layer on the package material. The second adhesive layer laterally surrounds the thermal interface material. After the step of attaching the bottom surface of the cover structure to the thermal interface material, the second adhesive layer is located below the first groove. In some embodiments, the method of manufacturing the encapsulation structure further includes forming a third adhesive layer on the second adhesive layer. From a top view, the third adhesive layer has an opening. The opening of the third adhesive layer exposes the second adhesive layer. After the step of attaching the bottom surface of the cover structure to the thermal interface material, the second adhesive layer is located in a first trench. In some embodiments, a top surface of the second adhesive layer is higher than a top surface of the thermal interface material. In some embodiments, the cover structure further includes a second trench recessed from the bottom surface of the cover structure. The planar area of ​​the first trench on the substrate surrounds a planar area of ​​the second trench on the substrate. In some embodiments, the method of manufacturing the encapsulation structure further includes plating a gold layer on the bottom surface of the cover structure before the step of attaching the bottom surface of the cover structure to the thermal interface material. In some embodiments, the cover structure includes copper, aluminum, steel, or a combination thereof. In some embodiments, the thermal interface material includes silver, copper, indium, tin, or an alloy thereof.

[0138] In some embodiments, the encapsulation structure includes a substrate, an encapsulation element, an encapsulation material, a thermal interface material layer, a first adhesive structure, a second adhesive structure, and a cover structure. The encapsulation element is located on the substrate. The encapsulation material laterally surrounds the encapsulation element. The thermal interface material layer is located on the encapsulation element. The first adhesive structure is located on the encapsulation material and laterally surrounds the thermal interface material. The second adhesive structure is located on the encapsulation material and laterally surrounds the first adhesive structure. The height of the first adhesive structure relative to the encapsulation material is greater than the height of the second adhesive structure relative to the encapsulation material. The cover structure is located on the thermal interface material and the second adhesive structure. In some embodiments, viewed from a top view, the width of the second adhesive structure is greater than the width of the first adhesive structure. In some embodiments, the ratio of the width of the second adhesive structure to the width of the first adhesive structure is in the range of about 5 to 50. In some embodiments, viewed from a top view, the first adhesive structure has a first annular profile. The second adhesive structure has a second annular profile. The second annular profile surrounds the first annular profile. In some embodiments, the encapsulation structure further includes a conductive layer. The conductive layer is located on the encapsulation element and the encapsulation material. The thermal interface material is located on the conductive layer.

[0139] In some embodiments, the package structure includes a substrate, a first semiconductor wafer, a second semiconductor wafer, a packaging material, a thermal interface material layer, and a cap structure. The first semiconductor wafer is located on the substrate. The second semiconductor wafer is located on the substrate. The packaging material laterally surrounds the first and second semiconductor wafers. The thermal interface material layer is located on the first and second semiconductor wafers. The cap structure is located on the thermal interface material. The cap structure has a trench. Viewed from a top view, the trench does not overlap the first and second semiconductor wafers and is aligned with a region between the first and second semiconductor wafers. In some embodiments, the cap structure includes an annular trench recessed from a bottom surface of the cap structure. A planar area of ​​the annular trench on the substrate surrounds a planar area of ​​the first and second semiconductor wafers on the substrate. In some embodiments, the trench and the annular trench are spatially connected. In some embodiments, the package structure further includes a first annular adhesive layer and a second annular adhesive layer. The first annular adhesive layer is located on the packaging material and surrounds the thermal interface material. The second annular adhesive layer is located on the first annular adhesive layer. In some embodiments, viewed from a top view, the second annular adhesive layer has an opening. The opening in the second annular adhesive layer exposes the first annular adhesive layer.

[0140] In some embodiments, the encapsulation element is located on a substrate. An encapsulation material laterally surrounds the encapsulation element. A thermal interface material layer is located on the encapsulation element. A first adhesive layer is located on the encapsulation material, wherein the first adhesive layer laterally surrounds the thermal interface material. A cover structure is located on the thermal interface material layer, wherein the cover structure has a first groove recessed from the bottom surface of the cover structure, the planar area of ​​the first groove on the substrate surrounding the planar area of ​​the encapsulation element on the substrate, and the planar area of ​​the first adhesive layer on the substrate surrounding the planar area of ​​the first groove on the substrate. In some embodiments, the top surface of the encapsulation element is flush with the top surface of the encapsulation material.

[0141] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A packaging structure, characterized in that, include: One substrate; A packaged component is located on the substrate; A packaging material is laterally wrapped around the package element; A thermal interface material layer is located on the packaged element; A first adhesive structure is located on the encapsulation material and laterally surrounds the thermal interface material layer; A second adhesive structure is located on the encapsulation material and laterally surrounds the first adhesive structure, wherein the height of the first adhesive structure relative to the encapsulation material is greater than the height of the second adhesive structure relative to the encapsulation material; as well as A cover structure is located on the thermal interface material layer and the second adhesive structure.

2. The packaging structure as described in claim 1, characterized in that, From a top view, the width of the second adhesive structure is greater than the width of the first adhesive structure.

3. The packaging structure as described in claim 2, characterized in that, The ratio of the width of the second adhesive structure to the width of the first adhesive structure is in the range of 5 to 50.

4. The packaging structure as described in claim 1, characterized in that, From a top view, the first adhesive structure has a first annular profile, the second adhesive structure has a second annular profile, and the second annular profile surrounds the first annular profile.

5. A packaging structure, characterized in that, include: One substrate; A first semiconductor wafer is located on the substrate; A second semiconductor wafer is located on the substrate; A packaging material is laterally surrounding the first semiconductor wafer and the second semiconductor wafer; A thermal interface material layer is located on the first semiconductor wafer and the second semiconductor wafer; as well as A cover structure is located on the thermal interface material layer, wherein the cover structure has a groove, which, from a top view, does not overlap the first semiconductor wafer and the second semiconductor wafer, and is aligned with a region between the first semiconductor wafer and the second semiconductor wafer.

6. The packaging structure as described in claim 5, characterized in that, The cover structure includes an annular groove recessed from a bottom surface of the cover structure, and a planar area of ​​the annular groove on the substrate surrounds a planar area of ​​the first semiconductor wafer and the second semiconductor wafer on the substrate.

7. The packaging structure as described in claim 6, characterized in that, The groove is connected to the annular groove.

8. The packaging structure as described in claim 5, characterized in that, Also includes: A first annular adhesive layer is located on the encapsulation material and surrounds the thermal interface material layer; as well as A second annular adhesive layer is located on the first annular adhesive layer.

9. A packaging structure, characterized in that, include: One substrate; A packaged component is located on the substrate; A packaging material is laterally wrapped around the package element; A thermal interface material layer is located on the packaged element; A first adhesive layer is located on the encapsulation material, wherein the first adhesive layer laterally surrounds the thermal interface material layer; as well as A cover structure is located on the thermal interface material layer, wherein the cover structure has a bottom surface and a first groove recessed from the bottom surface, a planar area of ​​the first groove on the substrate surrounds a planar area of ​​the encapsulation element on the substrate, and a planar area of ​​the first adhesive layer on the substrate surrounds a planar area of ​​the first groove on the substrate.

10. The packaging structure as described in claim 9, characterized in that, One top surface of the packaged element is flush with one top surface of the packaged material.

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