Vehicle power management system

Abstract

The application relates to a vehicle power management system, comprising an HSD unit for switch control and current collection in a working mode; a bypass unit for providing load power supply current and realizing current trigger wake-up, short circuit protection and overcurrent protection in a sleep mode; a control unit for switching the working state of the vehicle power management system between the working mode and the sleep mode through a control pin; microampere-level low-power supply in the sleep state and intelligent protection in the working state are realized through a dual-mode switching mechanism, and the vehicle power management system has the advantages of reducing sleep power consumption, improving power supply flexibility and system reliability.

Description

Technical Field

[0001] This application relates to the field of automotive electronics technology, and in particular to a vehicle power management system. Background Technology

[0002] Vehicle power management systems are a core component of modern automotive electrical architecture. Their primary function is to provide a stable and efficient power supply to onboard electronic devices while ensuring electrical safety and overall system reliability. With the increasing intelligence and electrification of automobiles, traditional power management solutions are gradually revealing their limitations. Although some existing solutions have been improved, they still fail to fully meet the demands. Therefore, there is an urgent need for an innovatively designed vehicle power management system to overcome the shortcomings of existing technologies and improve the overall comfort, safety, and economy of the vehicle.

[0003] For a long time, existing vehicle power management has mainly relied on a combination of relays and fuses. While this solution is simple in structure, it has revealed a series of drawbacks in practice. These include: fuses being single-use components requiring manual replacement after blowing, increasing maintenance workload and costs; slow response times for overcurrent and short-circuit protection, potentially escalating electrical faults and even causing safety accidents; lack of fault diagnosis capabilities during maintenance, making it difficult to quickly locate problems and reducing efficiency; short lifespan and large size of relays, susceptibility to poor contact, and high energy consumption, affecting system stability and energy efficiency; and the inability to support mixed use of 24V and 12V devices, limiting application flexibility. Furthermore, it fails to meet the stringent ASIL (Advanced Safety Level Indicator) requirements of modern vehicles.

[0004] To better address the aforementioned technical issues, the industry has proposed intelligent power management solutions based on high-side drivers (HSDs) and electronic fuses (EFUSEs). However, these existing solutions suffer from several drawbacks. Firstly, the operating current of the HSD in sleep mode typically exceeds 1mA, making it unable to power the load during sleep, thus increasing vehicle sleep power consumption and impacting low-power management. Secondly, replacing traditional fuses with EFUSEs significantly increases system costs. Furthermore, EFUSEs only support a current of 0.1A in sleep mode; exceeding this limit will wake the entire vehicle, restricting the feasibility of sleep mode functionality. In short, existing vehicle power management systems are inadequate in terms of sleep power consumption, cost, and functional flexibility, failing to meet the demands of modern vehicle power management. Utility Model Content

[0005] The purpose of this application is to provide a vehicle power management system that has the advantages of reducing sleep power consumption, improving power supply flexibility and system reliability.

[0006] This application provides a vehicle power management system, the technical solution of which is as follows: A vehicle power management system has a working mode and a sleep mode. The system includes: an HSD unit for performing switch control and current acquisition in the working mode; a bypass unit for providing load power supply current and realizing current-triggered wake-up, short-circuit protection and overcurrent protection in the sleep mode; and a control unit for switching the working state of the vehicle power management system between the working mode and the sleep mode through a control pin.

[0007] Furthermore, this application also proposes that the HSD unit includes an HSD chip; the bypass unit includes a trigger chip, an operational amplifier chip, a high-power PMOS, and a sampling resistor.

[0008] Furthermore, this application also proposes that the control unit controls the system's operating mode through the EN_SLEEP and EN_HSD pins: in sleep mode, the EN_SLEEP pin is set to a high level and the EN_HSD pin is configured to a high impedance state, so that the current of the HSD chip is reduced to the microamp level and the load power supply is mainly provided by a high-power PMOS; in operating mode, the EN_HSD pin is set to a high level so that the HSD chip can operate normally.

[0009] Furthermore, this application also proposes that the bypass unit detects the change in load current through a sampling resistor, converts the current change into a voltage signal using an operational amplifier chip, and then generates a wake-up signal through a trigger chip to wake up the control unit and enable the HSD unit.

[0010] Furthermore, this application also proposes that when the trigger chip detects an increase in load current, it outputs a pulse signal of a certain duration as a wake-up signal.

[0011] Furthermore, this application also proposes that the system performs overcurrent protection through the HSD unit in the working mode. When the current exceeds the preset threshold, the control unit configures the EN_HSD and EN_SLEEP pins to low level at the same time to cut off the power output.

[0012] Furthermore, this application also proposes that the system implements short-circuit protection through a bypass unit in sleep mode. When a short circuit occurs, the trigger chip outputs a signal to make the HSD unit enter the protection state and cuts off the power output through the control circuit.

[0013] Furthermore, this application also proposes that the system further includes a microcontroller for controlling the operation of the HSD unit and the bypass unit, and for realizing current monitoring, fault diagnosis and protection functions.

[0014] Furthermore, this application also proposes that the system is implemented using semiconductor devices, and features high integration, small size and low power consumption.

[0015] Furthermore, this application also proposes that the system further includes an ultra-low power timed wake-up module, which is used to further reduce power consumption in a long standby state. This module includes an ultra-low power timer chip and a low power microcontroller, and realizes wake-up control of the main system through timed wake-up and intelligent judgment.

[0016] As can be seen from the above, the vehicle power management system provided in this application includes the coordinated operation of an HSD unit, a bypass unit, and a control unit. Through a dual-mode switching mechanism, it achieves microampere-level low-power power supply in sleep mode and intelligent protection in working mode, which has the advantages of reducing sleep power consumption, improving power supply flexibility, and system reliability. Attached Figure Description

[0017] Figure 1 This is the circuit diagram of the control unit of this application.

[0018] Figure 2 This is a schematic diagram of the control unit of this application.

[0019] In the diagram: 10, HSD unit; 20, bypass unit; 30, battery; 40, load. Detailed Implementation

[0020] The following content will be combined with the contents of this application. Figure 1 and Figure 2 The technical solutions in this application are clearly and completely described herein. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following descriptions of the technical solutions in this application are as follows: Figure 1 and Figure 2 The detailed description of the embodiments provided herein is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of the application without inventive effort are within the scope of protection of the application. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] In the prior art of the technical field covered by this application, vehicle power management has long relied on a combination of relays and fuses. This approach suffers from high maintenance costs, slow response times, and inability to diagnose faults. While intelligent solutions based on high-side drivers and electronic fuses have shown some improvement with the development of automotive intelligence, they still suffer from drawbacks such as excessively high power consumption during sleep mode, high costs, and stringent current limitations. For example, when a vehicle enters sleep mode after a long period of parking, existing systems cannot maintain low power consumption while ensuring necessary load power, leading to rapid battery depletion. To address the problems of the prior art, the researchers of this application noted the contradiction between mode switching and power consumption control in traditional solutions: the operating mode requires precise current control, while the sleep mode needs to balance low power consumption and emergency wake-up. Analysis revealed that if the high-side driver is used only in the operating state, switching to an independent power supply path during sleep mode can avoid static current loss. Simultaneously, a dedicated triggering mechanism is designed to quickly restore the main system when load demands change, ensuring functional continuity while reducing energy consumption.

[0022] Based on the above analysis, this application proposes a vehicle power management system, please refer to... Figure 1 and Figure 2The vehicle power management system includes a high-side driver unit (HSD unit), a bypass unit 20, and a control unit. The high-side driver unit 10 performs switching control and current acquisition functions in operating mode; the bypass unit 20 provides power to the load 40 in sleep mode and implements current-triggered wake-up, short-circuit protection, and overcurrent protection; the control unit switches between the system's operating and sleep modes via pin control. The high-side driver unit 10 is an integrated circuit module with power switching and current detection functions, specifically implemented using a high-side driver chip integrating MOSFETs and sampling circuits, used to precisely control the on / off state of the load 40 and monitor the current status during normal vehicle operation. The bypass unit 20 is a standby circuit structure independent of the main power supply path, specifically implemented using a combination of trigger chips, operational amplifiers, high-power PMOS transistors, and sampling resistors, capable of maintaining low-power supply when the main system is in sleep mode, and triggering system wake-up via current changes. The control unit is a mode switching logic controller, specifically implemented using a microprocessor with multi-pin output capabilities, controlling the switching of the power supply path between the high-side driver and the bypass unit 20 via level signals. When the vehicle enters sleep mode, the control unit places the high-side driver in a high-impedance state to cut off its static current. At this time, the high-power PMOS transistor of the bypass unit 20 is turned on, continuously providing milliamp-level current to the load 40 through the sampling resistor. When the current of the load 40 suddenly increases due to the device wake-up demand, the operational amplifier chip converts the current change into a voltage signal, and the trigger chip then generates a wake-up pulse signal. After receiving the signal, the control unit reactivates the high-side driver unit, and the system switches back to the operating mode. In the event of a short circuit or overcurrent, the bypass unit 20 monitors the current status in real time through a comparator and triggers the protection mechanism to cut off the power supply circuit. This solution completely eliminates the static current loss of the high-side driver in the sleep state by physically isolating the power supply paths of the operating mode and sleep mode. Compared with the traditional relay solution, there is no need to use fragile mechanical contact components, avoiding the risk of poor contact; compared with the electronic fuse solution, the bypass unit 20 uses discrete component combinations, significantly reducing hardware costs while achieving the same protection function. In addition, the dual-mode independent power supply architecture supports the mixed use of devices with different voltage levels, expanding the applicable scenarios of the system. This application effectively solves the problems of frequent maintenance, excessive energy consumption, and slow response in traditional power management systems. During vehicle hibernation, the current maintaining power supply to critical equipment can be controlled at the microamp level, reducing power consumption by two orders of magnitude compared to existing solutions. The dual-path power supply design enables the system to quickly switch to a safe state in the event of a fault, shortening the protection response time to the microsecond level. The discrete protection circuit achieves the function of an electronic fuse while avoiding the use of high-cost dedicated chips, reducing the overall hardware cost by approximately 40%.

[0023] like Figure 1 and Figure 2As shown, this application further proposes a vehicle power management system, including an HSD unit 10 and a bypass unit 20. The HSD unit 10 includes an HSD chip, and the bypass unit 20 includes a trigger chip, an operational amplifier chip, a high-power PMOS, and a sampling resistor. The HSD chip is a high-side drive chip, specifically implemented using a semiconductor device with integrated switch control and current acquisition functions, used to replace traditional relays for circuit on / off control. The trigger chip is an integrated circuit with logic judgment functions, specifically implemented using a Schmitt trigger or a monostable multivibrator, used to generate a wake-up signal based on the load 40's state. The operational amplifier chip is an operational amplifier chip, specifically implemented using a differential amplifier circuit structure, used to convert the current signal into a voltage signal to trigger the protection mechanism. The high-power PMOS is a P-type metal-oxide-semiconductor field-effect transistor with high current carrying capacity, specifically implemented using a low on-resistance power device, used to directly power the load 40 in sleep mode. The sampling resistor is a low-resistance precision resistor, specifically made of manganin alloy or constantan alloy material, used to detect real-time changes in the load 40's current. In sleep mode, the high-power PMOS conducts to form a current bypass, directly supplying power to load 40. At this time, the HSD chip is in a non-operating state, avoiding the generation of milliamp-level quiescent current. When the current of load 40 fluctuates abnormally, the sampling resistor converts the current change into a voltage signal. The operational amplifier chip amplifies this signal and inputs it to the trigger chip, which outputs a pulse signal to trigger system wake-up. In operating mode, the HSD chip takes over the circuit control functions, monitoring the status of load 40 in real time through its built-in current acquisition module and simultaneously executing overcurrent protection. Existing traditional solutions using a combination of relays and fuses cannot achieve real-time current monitoring and rapid protection, and relay contacts suffer from mechanical wear. This solution replaces the relay with the HSD chip, eliminating the risk of mechanical contact failure. Furthermore, the electronic protection circuit built using the operational amplifier chip and trigger chip offers a response speed two orders of magnitude faster than the fuse blowing mechanism. Compared to intelligent power supply solutions using EFUSE, the on-resistance of the high-power PMOS can be as low as milliohms, allowing it to carry higher currents in sleep mode, such as supporting standby power supply above 0.5A, without triggering system wake-up. This application implements low-power power supply and fast wake-up function in sleep mode, solving the problem of excessive static current in traditional solutions. The introduction of electronic protection circuitry reduces the overcurrent protection response time to the microsecond level, effectively preventing fault escalation. The combination of high-power PMOS and sampling resistor ensures power supply reliability while reducing hardware costs by approximately 60% compared to the EFUSE solution.

[0024] like Figure 1 and Figure 2As shown, this application further proposes a control unit that controls the system's operating mode through the EN_SLEEP and EN_HSD pins: In sleep mode, the EN_SLEEP pin is set to a high level, and the EN_HSD pin is configured to a high-impedance state, reducing the current of the HSD chip to the microamp level, with the load power mainly provided by a high-power PMOS; in operating mode, the EN_HSD pin is set to a high level, enabling the HSD chip to operate normally. The EN_SLEEP pin is the signal interface in the control unit used to trigger the sleep mode, which can be implemented using a level-triggered I / O port. When this pin is set to a high level, the system enters a low-power state. The EN_HSD pin is the signal interface in the control unit used to enable the HSD chip, which can be implemented using a push-pull output I / O port. Changing the level of this pin controls the on / off state of the HSD chip. The high-impedance state means that the EN_HSD pin is in a state of no-drive output in sleep mode, which can be achieved by configuring the I / O port to a high-impedance mode, thereby avoiding additional current consumption of the HSD chip. The microamp level refers to the static current range of the HSD chip in sleep mode, which can be limited to the range of 1μA to 500μA through the chip's internal shutdown circuit. The high-power PMOS refers to the metal-oxide-semiconductor field-effect transistor in the bypass unit 20 used to carry the current of the load 40. It can be implemented using a device with a drain-source on-resistance of less than 10mΩ, replacing the HSD chip to power the load 40 in sleep mode. When the vehicle is in sleep mode, the EN_SLEEP pin is set to a high level signal, and the control unit sets the EN_HSD pin to a high-impedance state. This configuration causes the HSD chip's drive circuit to lose its enable signal, the internal power transistor to enter a shutdown state, and only the necessary detection circuitry is maintained, with current consumption controlled at the microamp level. Simultaneously, the high-power PMOS in the bypass unit 20 is activated and conducts, directly providing power to the load 40. When switching to the operating mode is required, the EN_HSD pin is set to a high level signal. At this time, the HSD chip's drive circuit is reactivated, restoring normal switching control and current acquisition functions, while the high-power PMOS stops supplying power. In existing solutions, the HSD chip still needs to maintain a milliamp-level operating current in sleep mode. This solution, however, reduces the quiescent current of the HSD chip by two orders of magnitude through a high-impedance setting on the EN_HSD pin. Existing technologies using EFUSE devices for sleep power supply limit the maximum supply current to 0.1A, while this solution uses a high-power PMOS that can support loads of several amperes up to 40A, while avoiding the increased cost associated with EFUSE. Furthermore, by independently controlling the voltage levels of the EN_SLEEP and EN_HSD pins, the switching process between the two operating modes eliminates the risk of false triggering.This application effectively solves the problem of excessive power consumption of HSD chips in sleep mode. While maintaining the integrity of the original HSD functions, it achieves physical isolation between the sleep power supply path and the working power supply path. The resulting technical effects include: reducing the overall system power consumption to the milliwatt level when the vehicle is parked for a long time, extending the battery life; providing continuous power to high-power loads even in sleep mode, such as supporting the operation of vehicle anti-theft systems or remote communication modules; and directly controlling mode switching through hardware pins, avoiding the delay or failure risks that may occur with software control.

[0025] As another embodiment of this application, refer to Figure 1 and Figure 2This application further proposes a vehicle power management system. The bypass unit 20 detects changes in the current of the load 40 through a sampling resistor, converts the current change into a voltage signal using an operational amplifier chip, and then generates a wake-up signal through a trigger chip to wake up the control unit and enable the HSD unit 10. The sampling resistor is a current sensing element connected in series in the power supply circuit, specifically a milliohm-level precision resistor, used to convert the current flowing through the load 40 into a measurable voltage signal. The operational amplifier chip is an operational amplifier circuit, specifically a differential amplifier circuit structure, used to amplify the small voltage difference across the sampling resistor. The trigger chip is an integrated circuit with signal comparison and logic output functions, specifically a Schmitt trigger or monostable trigger, used to generate a pulse signal based on changes in the voltage signal threshold. The wake-up signal is an electrical signal with a specific pulse width and amplitude, specifically implemented using rising edge triggering or level holding, used to trigger the control unit to switch from sleep mode to operating mode. In sleep mode, when the current of the load 40 changes abruptly, the current change flowing through the sampling resistor is converted into a voltage difference across the resistor. The voltage difference is amplified by the operational amplifier chip to form a voltage signal with sufficient amplitude. When this signal exceeds the set threshold of the trigger chip, the trigger chip outputs a square wave signal with a fixed pulse width. This square wave signal is transmitted to the wake-up pin of the control unit as a wake-up signal, triggering the control unit to exit the sleep state and reactivate the power supply function of the HSD unit 10, realizing the system switching from low-power mode to normal operation mode. Existing solutions cannot continuously monitor the current change of load 40 in sleep state, relying solely on EFUSE devices for overcurrent protection, resulting in response delay. This solution achieves real-time detection of current changes through sampling resistors, combined with signal conditioning by operational amplifier chips, enabling effective capture of microampere-level current changes. The application of trigger chips replaces the traditional MCU polling detection method, reducing system power consumption and improving response speed. This application achieves accurate monitoring of the current change of load 40 in sleep state, and can quickly trigger system wake-up when load 40 is abnormal, avoiding the risk of equipment damage caused by detection delays in traditional solutions. At the same time, the wake-up function is implemented through hardware circuitry, which reduces the computational load and power consumption of the control unit compared to the software polling solution, extending the standby time of the vehicle in sleep state.

[0026] As a further embodiment of this application, refer to Figure 1 and Figure 2This application further proposes that when a trigger chip detects an increase in the load current (40V), it outputs a pulse signal of a certain duration as a wake-up signal. A trigger chip is an integrated circuit capable of generating specific output logic based on changes in the input signal state. Specifically, it can be implemented using a chip with monostable triggering functionality, such as a 555 timer or a dedicated logic device configured in monostable mode. When a change in load current is detected, it triggers the output of a pulse signal of fixed width. The pulse signal is a level transition signal with a fixed duration. This can be achieved by setting the time constant of an external RC circuit or the parameters of an internal timer. For example, a programmable timer chip can be used to generate a pulse width of 50 milliseconds to 500 milliseconds for automatic reset after waking up the control unit to avoid continuous signal interference. When the load current (40V) increases, the voltage difference across the sampling resistor is converted into a voltage signal by the operational amplifier chip and input to the trigger terminal of the trigger chip. The trigger chip determines whether the current change meets the wake-up condition based on a preset threshold. If the condition is met, the monostable trigger is activated and outputs a pulse signal of fixed duration. This pulse signal is transmitted to the wake-up pin of the control unit through the control circuit, causing the system to switch from sleep mode to operating mode. During this process, the duration of the pulse signal is preset to ensure that the control unit has sufficient time to complete the state switch and will not cause malfunctions due to the continuous presence of the signal. Compared with existing technologies, existing solutions typically use a continuous high or low level for the wake-up signal, which is prone to false wake-ups due to signal interference or instantaneous fluctuations, and cannot automatically reset the signal path after wake-up. This solution achieves precise control of the wake-up action through a timed pulse signal, which avoids false triggering caused by signal residue and reduces the power consumption of the control unit in processing the wake-up signal. This application effectively solves the problem of false wake-ups caused by load current fluctuations in sleep mode, reduces the invalid power consumption of the system in standby mode, and ensures the reliability and response speed of the wake-up action, thereby improving the stability of the power management system under complex operating conditions.

[0027] like Figure 1 and Figure 2As shown, this application further proposes that the vehicle power management system performs overcurrent protection through the HSD unit 10 in the operating mode. When the detected current exceeds a preset threshold, the control unit simultaneously configures the EN_HSD and EN_SLEEP pins to low level to cut off the power output. The HSD unit 10 refers to the high-side drive unit, which can be implemented using a high-side drive chip with integrated switch control and current acquisition functions. It is used to perform power on / off operations and monitor the load current in real time in the operating mode. Overcurrent protection is a protection mechanism that automatically cuts off the power supply when the load current exceeds a safety threshold. It can be implemented through a current sampling circuit and a threshold comparison circuit to prevent circuit overheating or device damage. The preset threshold is a pre-set current protection trigger value, which can be implemented using programmable resistors or software parameter configuration to match the overcurrent protection requirements of different load devices. The control unit is a logic control module that performs mode switching and signal processing. It can be implemented using a microcontroller or application-specific integrated circuit to adjust the pin level state according to the current detection result. The EN_HSD and EN_SLEEP pins refer to the level signal interfaces output by the control unit. These can be implemented using general-purpose input / output ports to control the switching between the operating state of the HSD unit 10 and the system sleep mode, respectively. In operating mode, the HSD unit 10 continuously collects the current data of the load 40 and compares it with a preset threshold in real time. When the current exceeds the threshold, the control unit immediately switches the EN_HSD pin level from high to low and simultaneously sets the EN_SLEEP pin to low. This dual-pin synchronous action causes the HSD unit 10 to immediately stop working and forces the system to exit the operating mode, thus completely cutting off the power supply circuit to the load 40. During this process, the current detection and protection actions do not rely on mechanical contacts; the state switching is completed directly through electronic signals. Existing solutions rely on fuse blowing for overcurrent protection, with response speed limited by the physical characteristics of the fuse, and manual replacement is required after a failure. This solution, through electronic detection and control, can complete overcurrent judgment and power cut-off within milliseconds, and power supply can be restored through a reset operation without manual intervention. Furthermore, the dual-pin level coordinated control design avoids the risk of protection function failure due to a single signal failure. This application enables real-time monitoring and rapid protection response of a 40V load current, effectively preventing equipment damage or safety accidents caused by overcurrent. By replacing traditional fuses with electronic control, the problems of high maintenance costs and slow response speed are solved. Furthermore, dual-pin collaborative control enhances the reliability of the system's protection function.

[0028] like Figure 2As shown, this application further proposes that the system achieves short-circuit protection in sleep mode through a bypass unit 20. When a short circuit occurs, the trigger chip outputs a signal to cause the HSD unit 10 to enter a protection state, and the power output is cut off through the control circuit. The bypass unit 20 refers to a circuit module that provides a power supply path to the load 40 and performs fault detection in sleep mode. Specifically, it can use a high-power PMOS transistor as the current path, combined with a sampling resistor for current detection. Its function is to maintain low-power supply while possessing fault response capability. The trigger chip refers to an integrated circuit used to detect abnormal current and generate control signals. Specifically, it can be implemented using a logic device with threshold comparison function. Its function is to convert the overcurrent signal detected by the sampling resistor into a logic level signal. The HSD unit 10 refers to a power control module containing a high-side driver chip. Specifically, it can be implemented using an intelligent power device integrating MOSFETs and driver circuits. Its function is to switch the power supply path and perform a fast shutdown operation according to the control signal. The control circuit refers to a circuit structure that receives the trigger signal and performs power cut-off. Specifically, it can be implemented using a combination circuit of transistor switches and logic gates. Its function is to respond to fault signals and interrupt current output. In sleep mode, the high-power PMOS transistor conducts to provide a low-current supply to load 40, while the sampling resistor continuously monitors the current of load 40. When a short circuit occurs, the current of load 40 rises sharply, causing the voltage across the sampling resistor to exceed a preset threshold, and the trigger chip immediately outputs a high-level signal. This signal drives the protection circuit inside the HSD unit 10 into a locked state, and simultaneously cuts off the gate drive voltage of the PMOS transistor through the transistor switch in the control circuit, thereby completely disconnecting the power output within milliseconds. In existing technologies, protection in sleep mode relies solely on electronic fuses, whose response speed is limited by the fusing mechanism and cannot automatically recover. This solution, however, through the coordinated operation of real-time current detection and logic control circuitry, can trigger a dual protection mechanism the instant a short circuit occurs, avoiding device damage and eliminating the need for manual intervention. This application achieves rapid isolation of short-circuit faults in sleep mode, solving the risk of equipment burnout caused by protection delays in traditional solutions. Furthermore, by replacing the physical fusing mechanism with logic control, it significantly reduces maintenance costs and improves system reliability.

[0029] like Figure 1 and Figure 2As shown, this application further proposes that the vehicle power management system also includes a microcontroller for controlling the operation of the HSD unit 10 and the bypass unit 20, and realizing current monitoring, fault diagnosis, and protection functions. The microcontroller refers to a microcomputer chip integrating a central processing unit, memory, and peripheral interfaces. Specifically, it can be implemented using an STM32 series or NXP S32K series automotive-grade microcontroller, used for performing logic judgments, signal processing, and mode switching control. Current monitoring refers to the real-time acquisition of the current flowing through the HSD unit 10 and the bypass unit 20 in the load circuit 40. Specifically, it can be implemented using a built-in ADC module combined with a sampling resistor voltage divider circuit, acquiring current data through periodic scanning. Fault diagnosis refers to the identification of overcurrent, short circuit, or device failure states. Specifically, it can be implemented through preset current threshold comparison, abnormal signal duration statistics, and fault code generation algorithms. For example, protection is triggered when the detected current exceeds a preset value for 10ms. The protection function refers to the response mechanism to abnormal operating conditions. Specifically, it can be implemented by cutting off power supply, recording fault logs, or triggering redundant circuit switching. For example, in a short circuit event, the PMOS is immediately shut down and the backup power path is activated. Specifically, the microcontroller establishes bidirectional communication with the enable signal of HSD unit 10 and the trigger output of bypass unit 20 via GPIO pins to receive current sampling data in real time. In operating mode, the microcontroller reads the current value of HSD unit 10 at fixed intervals (e.g., 1ms) and compares it with a preset overcurrent threshold. When an abnormality is detected, the EN_HSD pin is immediately pulled low to cut off the power supply. In sleep mode, the microcontroller switches to a low-power state but still monitors the wake-up signal of bypass unit 20 through an interrupt mechanism. When the sampling resistor detects an increase in load current, the voltage signal output by the trigger amplifier is processed by a comparator to wake up the microcontroller, thereby reactivating HSD unit 10. For fault diagnosis, the microcontroller distinguishes between transient interference and real faults by analyzing current waveform characteristics (e.g., abrupt change slope and duration), and stores the fault type encoding in the internal EEPROM for subsequent reading of diagnostic information via the CAN bus. Traditional solutions rely on discrete components for protection, which cannot accurately distinguish fault types and have significant response delays. This solution, however, integrates current monitoring and diagnostic algorithms into a microcontroller, enabling it to identify overcurrent or short-circuit events and execute tiered protection strategies within 2ms. Existing EFUSE solutions only support a single protection threshold, while this solution allows for dynamic adjustment of the current protection threshold via software. For example, in low-temperature environments, the overcurrent threshold can be increased by 10% to adapt to load characteristic variations. This application achieves intelligent monitoring of the power supply path, enabling rapid fault type identification and targeted protection actions in the event of anomalies, avoiding the device damage risk caused by protection delays in traditional solutions.Meanwhile, the software-configurable diagnostic strategies solve the problem of incompatibility with devices of different voltage levels in existing technologies. For example, it supports automatic switching of protection parameters when 12V and 24V loads are mixed, thus improving the system's adaptability.

[0030] As another typical embodiment of this application, refer to Figure 1 and Figure 2This application further proposes that the system is implemented using semiconductor devices, featuring high integration, small size, and low power consumption. Semiconductor devices refer to electronic components manufactured based on semiconductor materials, specifically HSD chips, high-power PMOS, operational amplifier chips, and trigger chips. Multiple functional modules are integrated into a single chip or package using integrated circuit technology, thereby reducing the number of discrete components. High integration refers to integrating control circuits, protection circuits, and power devices into the same chip or module using semiconductor technology. This can be achieved using multi-chip packaging or system-in-package (SiP) technology to reduce circuit complexity. Small size refers to achieving a compact design by reducing the number of discrete components and optimizing circuit layout. This can be achieved using surface-mount devices and high-density PCB wiring technology to adapt to the limited space conditions of vehicles. Low power consumption refers to reducing static power consumption through the low on-resistance characteristics of semiconductor devices. This can be achieved using low-threshold voltage MOSFETs or optimized drive circuit design to reduce energy loss in standby mode. The system replaces traditional relays and fuses with semiconductor devices, integrating switching control, current acquisition, and short-circuit protection functions into the HSD chip, while using high-power PMOS for sleep power supply. The control unit and power devices are directly connected via integrated circuits, reducing wiring length and the number of connectors. For example, the HSD chip integrates overcurrent detection and temperature protection functions, and the gate drive circuit of the PMOS is directly integrated into the control chip. In the PCB layout, the power path uses a copper foil area optimization design to reduce line impedance. The fast switching characteristics of semiconductor devices shorten the protection action time, while their absence of mechanical contacts avoids contact problems. In some specific implementations, the HSD chip can be a smart power device with an SPI interface to achieve digital current monitoring and fault feedback. The PMOS can be an automotive-grade device with an on-resistance of less than 5mΩ, combined with a copper substrate heat dissipation design. The control unit uses an automotive-grade MCU with a built-in low-power mode management module, dynamically optimizing power consumption by adjusting the clock frequency. Existing solutions rely on bulky relays and discrete protection circuits, resulting in a large system footprint and complex wiring. This solution integrates power switches, protection circuits, and control logic into a single module through semiconductor integration technology, eliminating the space occupied by mechanical components. In traditional solutions, the coil drive power consumption of relays is typically in the hundreds of milliwatts range, while the quiescent current of semiconductor devices can be controlled in the microampere range, significantly reducing standby power consumption. Furthermore, the integrated design reduces the number of wiring harness connection points, improving system reliability. This application solves the problems of large size and high power consumption in traditional power management systems, achieving a compact installation layout that adapts to the limited electrical compartment space of vehicles. The low conduction loss characteristics of semiconductor devices reduce system operating temperature and extend component lifespan. The integrated design reduces the number of external connection devices, lowering the probability of failures due to poor contact, while supporting the power supply requirements of loads with different voltage levels within a single system.

[0031] like Figure 2 As shown, this application further proposes that the vehicle power management system also includes an ultra-low power timed wake-up module, used to further reduce power consumption in long-term standby mode. This module includes an ultra-low power timer chip and a low-power microcontroller, achieving wake-up control of the main system through timed wake-up and intelligent judgment. The ultra-low power timed wake-up module refers to a circuit unit that maintains low-power operation of the system by periodically triggering wake-up events. Specifically, it can be implemented using a timer chip with nanoamp-level standby current combined with a microcontroller, waking up the microcontroller at a fixed time interval to perform status detection tasks. The ultra-low power timer chip refers to a timer device with an operating current below microamps, specifically implemented using a CMOS timer chip with a built-in crystal oscillator, used to maintain basic timing functions in standby mode. The low-power microcontroller refers to a processor with multiple sleep modes, specifically implemented using an ARM Cortex-M0+ core chip supporting dynamic voltage regulation, used to quickly complete system status judgment and control the main system wake-up logic within the wake-up cycle. When the vehicle is in a long-term standby state with the engine off, the ultra-low power timer chip generates an interrupt signal at a fixed period, triggering the low-power microcontroller to enter the running mode from deep sleep mode. After waking up, the microcontroller collects system power supply status parameters, such as battery voltage 30 and load current 40, and uses a preset algorithm to determine whether the main system wake-up conditions are met. If it determines that the main system does not need to be woken up, the microcontroller will re-enter sleep mode and reset the timer chip to start the next timing cycle. This process avoids frequent wake-ups of the main system through an intelligent decision-making mechanism, and the main control unit will only be triggered to resume operation when an abnormal state or preset wake-up conditions are detected. In standby mode, the system status is maintained by continuously running monitoring circuits, making it difficult to reduce static power consumption. This solution, however, uses a time-sharing wake-up mechanism to concentrate standby power consumption in the short-term operating range of the timer chip and microcontroller, reducing the average standby current to the nanoamp level while retaining the ability to respond to sudden events. Compared to the solution that uses a single EFUSE device to achieve sleep power supply, this design significantly extends the standby time of the vehicle battery 30 while ensuring functional safety through hardware and software co-optimization. This application effectively solves the problem of excessive static power consumption of the power system leading to battery 30 depletion when the vehicle is parked for a long time. It reduces standby power consumption by two orders of magnitude while maintaining necessary monitoring functions, avoiding system failures caused by over-discharge of the battery 30. The module's intelligent judgment mechanism can also dynamically adjust the wake-up cycle based on parameters such as ambient temperature and battery health status, further optimizing energy management efficiency.

[0032] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A vehicle power management system, having a working mode and a sleep mode, characterized in that, The vehicle power management system includes: an HSD unit for switching control and current acquisition in the operating mode; a bypass unit for providing load power supply current and implementing current-triggered wake-up, short-circuit protection, and overcurrent protection in the sleep mode; and a control unit for switching the operating state of the vehicle power management system between the operating mode and the sleep mode via a control pin.

2. The vehicle power management system according to claim 1, characterized in that, The HSD unit includes an HSD chip; the bypass unit includes a trigger chip, an operational amplifier chip, a high-power PMOS, and a sampling resistor.

3. The vehicle power management system according to claim 2, characterized in that, The control unit controls the system's operating mode via the EN_SLEEP and EN_HSD pins: in sleep mode, the EN_SLEEP pin is set to a high level and the EN_HSD pin is configured to a high impedance state, reducing the current of the HSD chip to the microamp level, with the load power mainly provided by the high-power PMOS; in operating mode, the EN_HSD pin is set to a high level, enabling the HSD chip to operate normally.

4. The vehicle power management system according to claim 2 or 3, characterized in that, The bypass unit detects changes in load current through the sampling resistor, converts the current change into a voltage signal using the operational amplifier chip, and then generates a wake-up signal through the trigger chip to wake up the control unit and enable the HSD unit.

5. The vehicle power management system according to claim 4, characterized in that, When the trigger chip detects an increase in load current, it outputs a pulse signal of a certain duration as a wake-up signal.

6. The vehicle power management system according to any one of claims 1, 2, 3, and 5, characterized in that, In the operating mode, the system performs overcurrent protection through the HSD unit. When the current exceeds the preset threshold, the control unit configures the EN_HSD and EN_SLEEP pins to low level at the same time to cut off the power output.

7. The vehicle power management system according to claim 2, characterized in that, In sleep mode, the system achieves short-circuit protection through the bypass unit. When a short circuit occurs, the trigger chip outputs a signal to put the HSD unit into a protection state and cuts off the power output through the control circuit.

8. The vehicle power management system according to claim 7, characterized in that, The system also includes a microcontroller for controlling the operation of the HSD unit and the bypass unit, and for implementing current monitoring, fault diagnosis and protection functions.

9. The vehicle power management system according to claim 8, characterized in that, The system is implemented using semiconductor devices and features high integration, small size, and low power consumption.

10. The vehicle power management system according to claim 9, characterized in that, The system also includes an ultra-low power timed wake-up module, which is used to further reduce power consumption in long-term standby mode. This module includes an ultra-low power timer chip and a low power microcontroller, and realizes wake-up control of the main system through timed wake-up and intelligent judgment.

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