A centralized power supply test circuit

Abstract

The utility model discloses a centralized power supply test circuit, including power module, control module, timing module, discharge detection circuit and data storage circuit. Power module converts commercial power into double -way direct current voltage output, and control module drives power supply control circuit and discharge control circuit through control chip, and the on -off state of commercial power input and discharge loop is automatically switched, and timing module shows real -time and automatically switches work countdown and discharge positive timing double mode, and discharge detection circuit real -time acquisition discharge voltage state signal feedback to control chip, and data storage circuit is complete to save test data through non -volatile memory chip. The utility model solves the technical problem of the automation absence, high security risk, poor data reliability of centralized power supply test circuit in the prior art.

Description

Technical Field

[0001] This utility model relates to the field of power supply testing technology, and in particular to a centralized power supply testing circuit. Background Technology

[0002] Current centralized power supply testing equipment generally suffers from a critical deficiency of low automation. During testing, manual intervention is required for mains power on / off control and discharge circuit switching, along with manual timing and recording. This results in low testing efficiency and poses a risk of electric shock to operators who directly contact high-voltage circuits. Furthermore, existing equipment lacks automatic switching timing for operating / discharging times, real-time discharge voltage status detection, and frequent data loss due to the absence of hardware-level power-off protection. Therefore, there is an urgent need for an integrated testing circuit with fully automatic on / off control, dual-mode timing management, and power-off data preservation capabilities. Utility Model Content

[0003] The main purpose of this invention is to propose a centralized power supply test circuit, which aims to solve the technical problems of lack of automation, high safety risks, and poor data reliability in existing centralized power supply test circuits.

[0004] To achieve the above objectives, the first aspect of this utility model proposes a centralized power supply test circuit, including a power supply module, a control module, a timing module, a discharge detection circuit, and a data storage circuit. The power supply module's input terminal is connected to mains power, its first output terminal outputs a first DC voltage, and its second output terminal outputs a second DC voltage. The control module includes a control chip, a power supply control circuit, and a discharge control circuit. The output terminal of the power supply control circuit is connected to the mains input terminal of the centralized power supply under test, and its input terminal is connected to the first output terminal of the control chip, controlling the on / off state of the mains power according to the instructions of the control chip. The output terminal of the discharge control circuit is connected to the discharge circuit of the centralized power supply under test, and its input terminal is connected to the second output terminal of the control chip, controlling the on / off state of the discharge circuit according to the instructions of the control chip. The input terminal of the timing module is connected to the third output terminal of the control chip, used to display the working time and discharge time of the centralized power supply under test. The input terminal of the discharge detection circuit is connected to the discharge detection point of the centralized power supply under test, and its output terminal is connected to the first input terminal of the control chip, used to detect the discharge voltage status signal. The data storage circuit includes a storage chip, which is connected to the fourth output terminal of the control chip, used to store the working time and discharge time of the centralized power supply under test.

[0005] Preferably, the power supply control circuit includes a solid-state relay and a first transistor; the first terminal of the main circuit of the solid-state relay of the power module is connected to the mains L line, the second terminal of the main circuit is connected to the mains input L terminal of the power supply under test, the cathode of the control terminal is connected to the collector of the first transistor, and the anode of the control terminal is connected to the second output terminal of the power module; the emitter of the first transistor is grounded, and the base is connected to the first output terminal of the control chip and the second output terminal of the power module.

[0006] Preferably, the discharge control circuit includes a first optocoupler isolator and a first MOSFET; the first input terminal of the first optocoupler isolator is connected to the second output terminal of the power module, the second input terminal is connected to the second output terminal of the control chip, the first output terminal is connected to the first output terminal of the power module, and the second output terminal is connected to the gate of the first MOSFET; the source of the first MOSFET is grounded, and the drain is connected to the discharge circuit of the power supply under test.

[0007] Preferably, the power module includes an input filter rectifier circuit, a power management chip, and an isolation transformer; the input terminal of the input filter rectifier circuit is connected to the mains power, and the output terminal outputs high-voltage DC power; the first input terminal of the power management chip is connected to the output terminal of the input filter rectifier circuit; the first input terminal of the main winding of the isolation transformer is connected to the output terminal of the input filter rectifier circuit, the second input terminal is connected to the output terminal of the power management chip, and the output terminal outputs a first DC voltage.

[0008] Preferably, the power module further includes a step-down chip, a first inductor, and a first capacitor; the first input terminal of the step-down chip is connected to the output terminal of the main winding of the isolation transformer; the output terminal of the step-down chip is connected to the first terminal of the first inductor, the second terminal of the first inductor is connected to the first terminal of the first capacitor and outputs a second DC voltage, and the second terminal of the first capacitor is grounded.

[0009] Preferably, the data storage circuit further includes a power-off detection circuit and a voltage sustaining circuit; the power-off detection circuit includes a second transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first diode; the input terminal of the voltage sustaining circuit is connected to the second output terminal of the power module, and the output terminal is connected to the second input terminal of the control chip and the first terminal of the first resistor; the second terminal of the first resistor and the first terminal of the second resistor are connected to the base of the second transistor; the first terminal of the third resistor is connected to the second output terminal of the power module, and the second terminal of the third resistor and the first terminal of the fourth resistor are connected to the emitter of the second transistor; the collector of the second transistor is connected to the third input terminal of the control chip; the second terminal of the second resistor is grounded through the first diode, and the second terminal of the fourth resistor is grounded.

[0010] Preferably, the voltage sustaining circuit includes a fifth resistor, a sixth resistor, a second diode, a third diode, a fourth diode, a second capacitor, and a third capacitor; the anode of the second diode and the first terminal of the fifth resistor are connected to the second output terminal of the power module, and the cathode of the second diode is connected to the first terminal of the sixth resistor; the second terminal of the fifth resistor is connected to the anode of the third diode, and the cathode of the third diode is connected to the anode of the fourth diode and the positive terminal of the second capacitor; the second terminal of the sixth resistor is connected to the cathode of the fourth diode and the positive terminal of the third capacitor and serves as the output terminal of the voltage sustaining circuit; the negative terminals of the second capacitor and the third capacitor are grounded.

[0011] Preferably, the discharge detection circuit includes a discharge detection interface, a seventh resistor, a second optocoupler, a fourth capacitor, and a fifth capacitor; the first pin of the discharge detection interface is connected to the first terminal of the seventh resistor and the positive terminal of the fourth capacitor, the second terminal of the seventh resistor is connected to the first input terminal of the second optocoupler; the first output terminal of the second optocoupler is connected to the first terminal of the fifth capacitor and the fourth input terminal of the control chip; the second pin of the discharge detection interface, the negative terminal of the fourth capacitor, the second terminal of the fifth capacitor, the second input terminal and the second output terminal of the second optocoupler are grounded.

[0012] Preferably, the timing module includes a driver chip, a decoder chip, and four electronic digital tubes; the input bus of the driver chip is connected to the fourth output terminal of the control chip, and the output bus is connected to the segment selection terminal of the four electronic digital tubes; the input terminal of the decoder chip is connected to the fifth output terminal of the control chip, and the output terminal is connected to the digit selection terminal of the digital tubes.

[0013] Preferably, it further includes a real-time clock circuit and a temperature monitoring circuit; the real-time clock circuit includes a clock chip and a crystal oscillator, the power supply terminal of the clock chip is connected to the second output terminal of the power module, and the crystal oscillator terminal is connected to both ends of the crystal oscillator; the output terminal of the clock chip is connected to the fifth input terminal of the control chip; the temperature monitoring circuit includes a temperature sensor, the input terminal of the temperature sensor is connected to the second output terminal of the power module, and the output terminal is connected to the sixth input terminal of the control chip.

[0014] This invention proposes a centralized power supply test circuit. It achieves electrical isolation between high and low voltage circuits through the dual DC output of the power module, ensuring system stability from the source. The control module's dual-circuit hardware collaborative design for power supply and discharge replaces manual high-voltage operation, eliminating the risk of electric shock. The hardware-level dual-mode automatic timing of the timing module eliminates manual intervention, improving the accuracy of recording both working and discharging time periods. The discharge detection circuit monitors the discharge status in real time and feeds back abnormal signals, ensuring a reliable and controllable discharge process. The data storage circuit uses a non-volatile memory chip to completely save test data, overcoming the industry-wide problem of data loss due to sudden power outages. Ultimately, this invention achieves a simultaneous leap in testing efficiency, safety, and data reliability.

[0015] Furthermore, this invention achieves millisecond-level safe on / off control of the mains L line through the coordinated driving of solid-state relays and transistors, improving the safety of high-voltage operation; completely blocks high-voltage surges in the discharge circuit through the optocoupler-coupled MOSFET architecture, improving discharge switching response speed, eliminating the risk of electric shock during manual operation, and extending equipment life; constructs a physical isolation barrier between high and low voltage circuits through an isolation transformer, eliminating the risk of electrical coupling between mains power and DC output; achieves high-efficiency voltage conversion through a step-down chip combined with an inductor-capacitor switching topology, reducing energy loss in the low-voltage power supply system; and sets a voltage drop threshold through a transistor resistor voltage divider network, achieving millisecond-level power outage detection. The system measures the following: It triggers an interrupt in the control chip to preserve data; it constructs an anti-backflow isolation chain using multi-stage series diodes, and works with capacitors to store energy to provide a hardware-level sustaining voltage window for sudden power outages; it achieves electrical isolation and signal purification of the high-voltage discharge circuit through optocoupler isolation and RC filtering, blocking potential difference interference and improving the accuracy of status recognition; it uses a hardware dynamic scanning architecture with a driver chip and decoder to achieve automatic switching and display of dual-mode timing, significantly reducing the pin occupancy and power consumption of the control chip; it constructs a millisecond-level time base through an independent clock chip to ensure timing continuity after power failure, and combines a wide-range temperature sensor to capture the thermal status of the equipment in real time, forming a "time-temperature" dual-dimensional hardware monitoring system.

[0016] In summary, this utility model solves the technical problems of lack of automation, high safety risks, and poor data reliability in the existing centralized power supply test circuit. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a circuit block diagram of a centralized power supply test circuit according to the present invention. Figure 2 This is a circuit diagram of the power supply control circuit of this utility model; Figure 3 This is a circuit diagram of the discharge control circuit of this utility model; Figure 4 This is a circuit diagram of the power module of this utility model; Figure 5 This is a circuit diagram of the data storage circuit of this utility model; Figure 6 This is a circuit diagram of the power failure detection circuit and voltage maintenance circuit of this utility model; Figure 7 This is a circuit diagram of the discharge detection circuit of this utility model; Figure 8 This is a circuit diagram of the timing module of this utility model; Figure 9 The circuit diagram of the control chip and the switch of this utility model is shown. Figure 10 This is a circuit schematic diagram of the real-time clock circuit of this utility model; Figure 11 This is a circuit diagram of the temperature monitoring circuit of this utility model.

[0019] In the attached diagram: 1-Power supply module, 2-Control module, 3-Timing module, 4-Discharge detection circuit, 5-Data storage circuit.

[0020] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0022] It should be noted that if the embodiments of this utility model involve directional indicators, such as up, down, left, right, front, back, etc., the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0023] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0024] The main purpose of this invention is to propose a centralized power supply test circuit, which aims to solve the technical problems of lack of automation, high safety risks, and poor data reliability in existing centralized power supply test circuits.

[0025] like Figures 1 to 11 As shown, this utility model proposes a centralized power supply test circuit, including a power supply module 1, a control module 2, a timing module 3, a discharge detection circuit 4, and a data storage circuit 5. The power supply module 1 has its input terminal connected to mains power, a first output terminal outputting a first DC voltage, and a second output terminal outputting a second DC voltage. The control module 2 includes a control chip, a power supply control circuit, and a discharge control circuit. The output terminal of the power supply control circuit is connected to the mains input terminal of the centralized power supply under test, and its input terminal is connected to the first output terminal of the control chip, controlling the on / off state of the mains power according to the instructions of the control chip. The output terminal of the discharge control circuit is connected to the discharge circuit of the centralized power supply under test, and its input terminal is connected to the second output terminal of the control chip, controlling the on / off state of the discharge circuit according to the instructions of the control chip. The input terminal of the timing module 3 is connected to the third output terminal of the control chip, used to display the working time and discharge time of the centralized power supply under test. The input terminal of the discharge detection circuit 4 is connected to the discharge detection point of the centralized power supply under test, and its output terminal is connected to the first input terminal of the control chip, used to detect the discharge voltage status signal. The data storage circuit 5 includes a storage chip connected to the fourth output terminal of the control chip, used to store the working time and discharge time of the centralized power supply under test.

[0026] For details, see Figures 1 to 11As shown, in this embodiment, the power supply module 1 converts the mains power into dual DC outputs. The first output terminal outputs a first DC voltage of 24V, and the second output terminal outputs a second DC voltage of 5V. The first DC voltage of 24V is used to drive the high-power load circuit, and the second DC voltage of 5V supplies power to the digital circuit. The control module 2 uses an STC89C52RC microcontroller as the control chip U1. It is connected to the input terminal of the power supply control circuit through the first output terminal P36 pin to control the on / off state of the mains input L line of the power supply under test. The control chip U1 is connected to the input terminal of the discharge control circuit through the second output terminal P13 pin to control the on / off state of the discharge circuit of the power supply under test. The timing module 3 includes four electronic digital tubes to display the working countdown and discharge positive countdown data generated by the internal timer of the control chip U1 in real time. The discharge detection circuit 4 collects the voltage state of the negative terminal of the power supply under test through a high-precision optocoupler. When a discharge end signal (high level) is detected, it is fed back to the first input terminal P37 pin of the control chip U1. The data storage circuit 5 uses an AT24C02 memory chip to store the timing data of the control chip U1. The working process is as follows: After the device is powered on and initialized, the control chip U1 automatically loads the historical test data in the storage chip and displays it on the digital tube. In this embodiment, six switches (SW1-SW6, see below) are set. Figure 9 The operator can set test parameters via the control panel switches. Pressing the SW3 movement button switches the cursor position for the time setting. Using the SW1 down button and the SW2 up button adjusts the countdown value, and after confirmation, pressing the SW4 start button begins the test. The working time is the continuous operating duration of the power supply under test under mains power input, and the discharge time is the duration of the power supply battery's self-discharge. After starting the test, the control chip U1 drives the power supply control circuit to connect to the mains power input through its first output terminal, and the power supply under test starts working. Simultaneously, the timing module switches to countdown display mode. When the countdown reaches zero, the control chip U1 automatically triggers the discharge control circuit to cut off the mains power and triggers the discharge control circuit to conduct the discharge circuit through its second output terminal, and the timing module simultaneously switches to positive timing mode. If a pause is needed during the test, SW4 can be pressed again. In an emergency, pressing the SW5 clear button resets the test data. The discharge detection circuit monitors the negative discharge voltage in real time. When a high-level signal indicating completion of discharge is detected, it feeds back to the control chip U1 to stop the timing. Finally, the control chip U1 freezes the current discharge time value and stores the working time and discharge time in the memory chip. If overheating or abnormal noise occurs during the entire process, press the SW6 mute button to turn off the buzzer alarm, but the system will still perform a protective power-off operation. Throughout the test, the working time and discharge time are automatically switched and recorded by the hardware, without the need for manual intervention in timing.

[0027] Understandably, this embodiment achieves fully automated control of the centralized power supply testing process through a pure hardware structure. The dual DC voltage output provides isolated power supply for the high and low voltage circuits, the microcontroller precisely coordinates the timing switching of the power supply and discharge circuits, the digital tube hardware-level dual-mode timing eliminates manual intervention, the real-time monitoring of the discharge status avoids misjudgment, and the non-volatile memory chip ensures the persistent storage of test data, ultimately improving the testing efficiency, operational safety, and data reliability of the centralized power supply.

[0028] Based on the above technical solutions, those skilled in the art can make corresponding equivalent improvements according to the application scenario. For example, they can improve control performance by selecting microcontrollers or ARM processors with different architectures; realize multi-parameter visualization by configuring an LCD screen to replace the digital tube; enhance discharge detection accuracy by deploying a differential amplifier circuit combined with a voltage comparator; and accelerate data access speed by selecting a larger capacity FRAM memory chip.

[0029] Preferably, the power supply control circuit includes a solid-state relay and a first transistor; the first terminal of the main circuit of the solid-state relay of the power module 1 is connected to the mains L line, the second terminal of the main circuit is connected to the mains input L terminal of the power supply under test, the cathode of the control terminal is connected to the collector of the first transistor, and the anode of the control terminal is connected to the second output terminal of the power module 1; the emitter of the first transistor is grounded, and the base is connected to the first output terminal of the control chip and the second output terminal of the power module 1.

[0030] For details, see Figure 2 As shown, in this embodiment, the solid-state relay U10 of the power module 1 is model CX240D5. Its main circuit first terminal is connected to the mains L line, and the main circuit second terminal is connected to the L input terminal of the power supply under test. The anode CTRL+ of the control terminal is connected to the 5V power supply through the current limiting resistor R7, and the cathode CTRL- is connected to the collector of the NPN transistor Q1. The emitter of the transistor Q1 is grounded, and the base is connected to the P36 pin of the control chip U1 through the series resistor R6. At the same time, it is connected to 5V through the pull-up resistor R35 to form a stable drive circuit, so as to realize the high reliability of the solid-state relay U10 to be controlled by the low level signal of the control chip U1.

[0031] Understandably, this embodiment achieves high-voltage physical isolation by directly connecting the main circuit of the solid-state relay in series with the L line of the mains power. It uses a transistor to amplify the control signal of the control chip and convert it into relay drive current. Combined with the pull-up resistor to stabilize the drive circuit design, it can effectively improve the response speed and anti-interference capability of high-voltage on / off control, and achieve the technical goal of safely controlling the on / off of 220V mains power with low-voltage signals.

[0032] Based on the above technical solutions, those skilled in the art can make corresponding equivalent improvements according to the application scenario. For example, the solid-state relay can be replaced with a light-controlled relay of the same voltage rating; or the transistor model can be replaced with a general-purpose NPN device such as 2N3904; or the resistance values ​​of the current-limiting resistor and the pull-up resistor can be adjusted according to the driving requirements.

[0033] Preferably, the discharge control circuit includes a first optocoupler isolator and a first MOSFET; the first input terminal of the first optocoupler isolator is connected to the second output terminal of the power module 1, the second input terminal is connected to the second output terminal of the control chip, the first output terminal is connected to the first output terminal of the power module 1, and the second output terminal is connected to the gate of the first MOSFET; the source of the first MOSFET is grounded, and the drain is connected to the discharge circuit of the power supply under test.

[0034] For details, see Figure 3 As shown, in this embodiment, the discharge control circuit includes a first optocoupler U11 and a first MOSFET Q4, wherein the first optocoupler U11 is an EL817 and the first MOSFET Q4 is a MOS-IRF540. The first input terminal of the first optocoupler U11 is connected to the second output terminal 5V of the power module 1, the second input terminal is connected to the second output terminal P13 pin of the control chip U1, the first output terminal is connected to the first output terminal 24V of the power module 1, and the second output terminal is connected to the gate of the first MOSFET Q4 through a resistor R63; the source of the first MOSFET Q4 is grounded, and the drain is connected to the discharge circuit of the power supply under test.

[0035] Understandably, this embodiment uses an optocoupler isolator to achieve high and low voltage electrical isolation between the control chip and the discharge circuit, avoiding high voltage crosstalk from damaging the control circuit; it uses the low on-resistance characteristic of the MOSFET to reduce voltage drop loss in the discharge circuit; and it uses a gate direct drive design to eliminate the need for an additional drive circuit, thereby improving response speed and reducing system complexity.

[0036] Based on the above technical solutions, those skilled in the art can make corresponding equivalent improvements according to the application scenario. For example, the optocoupler isolator can be replaced with a device of the same type as PC817 / TLP521-4; the MOSFET can be a high-current field-effect transistor such as IRF3205; and the gate resistance of the MOSFET can be adjusted according to the switching speed requirements to suppress oscillation.

[0037] Preferably, the power module 1 includes an input filter rectifier circuit, a power management chip, and an isolation transformer; the input terminal of the input filter rectifier circuit is connected to the mains power, and the output terminal outputs high-voltage DC power; the first input terminal of the power management chip is connected to the output terminal of the input filter rectifier circuit; the first input terminal of the main winding of the isolation transformer is connected to the output terminal of the input filter rectifier circuit, the second input terminal is connected to the output terminal of the power management chip, and the output terminal outputs a first DC voltage.

[0038] For details, see Figure 4 As shown, in this embodiment, the input filtering and rectifier circuit of power module 1 includes a fuse F1, a varistor VR1, a common-mode inductor LF1, and a rectifier bridge composed of four diodes D1 / D3 / D5 / D6; the mains line L is connected to the first input terminal of the common-mode inductor LF1 via the fuse F1, and the N line is connected to the second input terminal of the common-mode inductor LF1 via the varistor VR1. The output terminal of the common-mode inductor is connected to the rectifier bridge composed of D1 / D3 / D5 / D6 to generate high-voltage DC output; in this embodiment, the power management chip U2 is model DK045G, and the first input terminal HV of the power management chip U2 is connected to the output terminal of the rectifier bridge to obtain high-voltage DC; the isolation transformer T1 includes a main winding T1A and a secondary winding T1B, wherein the main winding T1A is a main winding T1A and the secondary winding T1B ... The first input terminal of winding T1A is connected to the positive terminal of the high-voltage DC output of the rectifier bridge, and the second input terminal is connected to the SW pin of the power management chip U2. The output terminal of the main winding T1A is rectified by the fourteenth diode D14 and filtered by the parallel electrolytic capacitors EC2 and EC31 to output a stable 24V first DC voltage. At the same time, the secondary winding T1B is rectified by diode D11 and filtered by electrolytic capacitors EC1 and C1 and then connected to the VCC pin of the power management chip U2 to generate an auxiliary power supply voltage. The power management chip U2 constructs a closed-loop feedback with the programmable voltage regulator U13 (TL431) through optocoupler U12 to feed back the output 24V voltage fluctuation signal to the FB pin of the power management chip U2 to achieve precise voltage regulation.

[0039] Understandably, this embodiment effectively suppresses high-frequency interference and surge impact from the mains power supply through the input filtering and rectifier circuit, precisely controls the energy transfer efficiency of the isolation transformer winding through the power management chip, and completely blocks electrical risks between high and low voltage circuits by relying on physical isolation design. Finally, it achieves a stable DC power supply with high conversion efficiency and high-precision output voltage in a compact structure, providing a safe and reliable power foundation for the test system.

[0040] Based on the above technical solutions, those skilled in the art can make corresponding equivalent improvements according to the application scenario. For example, the input filter rectifier circuit can be replaced with a π-type filter combined with an integrated rectifier bridge; the power management chip can be a compatible control IC such as PN8370; and the isolation transformer can adjust the turns ratio according to actual needs to adapt to the output voltage requirements.

[0041] Preferably, the power module 1 further includes a step-down chip, a first inductor, and a first capacitor; the first input terminal of the step-down chip is connected to the output terminal of the main winding of the isolation transformer; the output terminal of the step-down chip is connected to the first terminal of the first inductor, the second terminal of the first inductor is connected to the first terminal of the first capacitor and outputs a second DC voltage, and the second terminal of the first capacitor is grounded.

[0042] For details, see Figure 4As shown, in this embodiment, the step-down chip is an OC5864 step-down converter. Its input terminal IN is connected to the 24V DC voltage output from the main winding T1A of the isolation transformer. The enable terminal EN is connected to the 24V power supply through resistor R73 to keep it constantly on. The switching terminal SW is connected to the cathode of SBD diode D13 and the first terminal of inductor L4. The anode of diode D13 is grounded. The second terminal of inductor L4 is connected to the first terminal of the first capacitor EC11 and outputs a second DC voltage of 5V. The second terminal of the first capacitor EC11 is grounded. The FB pin of the step-down chip adjusts the output voltage accuracy in real time through a resistor divider network (R70 / R71) to complete the efficient conversion from 24V to 5V.

[0043] Understandably, this embodiment achieves efficient voltage conversion by combining the high-frequency switching control of the buck chip with an inductor-capacitor filter network, significantly reducing energy loss; it effectively suppresses inductor current surges through freewheeling circuit design, enhancing system stability; it ensures output voltage accuracy through a closed-loop feedback mechanism; and its compact switching power supply architecture reduces heat dissipation requirements, providing clean, low-voltage power to digital circuits.

[0044] Based on the above technical solutions, those skilled in the art can make corresponding equivalent improvements according to the application scenario. For example, they can replace the original model with a compatible switching buck chip; optimize the selection of the freewheeling diode to adapt to different current requirements; adjust the inductor parameters to match a specific switching frequency; change the type of output filter capacitor to improve the filtering effect; or modify the resistance value of the voltage divider resistor to adapt to multiple output voltages.

[0045] Preferably, the data storage circuit 5 further includes a power-off detection circuit and a voltage sustaining circuit; the power-off detection circuit includes a second transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first diode; the input terminal of the voltage sustaining circuit is connected to the second output terminal of the power module 1, and the output terminal is connected to the second input terminal of the control chip and the first terminal of the first resistor; the second terminal of the first resistor and the first terminal of the second resistor are connected to the base of the second transistor; the first terminal of the third resistor is connected to the second output terminal of the power module 1, and the second terminal of the third resistor and the first terminal of the fourth resistor are connected to the emitter of the second transistor; the collector of the second transistor is connected to the third input terminal of the control chip; the second terminal of the second resistor is grounded through the first diode, and the second terminal of the fourth resistor is grounded.

[0046] For details, see Figure 6As shown, in this embodiment, the power-off detection circuit includes a second transistor Q3, a first resistor R53, a second resistor R54, a third resistor R52, a fourth resistor R55, and a first diode D10. The input terminal of the voltage sustaining circuit is connected to the second output terminal 5V of the power module 1, and the output terminal is connected to the second input terminal VCC pin of the control chip U1 and the first terminal of the first resistor R53. The second terminal of the first resistor R53 and the first terminal of the second resistor R54 are connected to the base of the second transistor Q3. The first terminal of the third resistor R52 is connected to the second output terminal 5V of the power module 1, and the second terminal of the third resistor R52 and the first terminal of the fourth resistor R55 are connected to the emitter of the second transistor Q3. The collector of the second transistor Q3 is connected to the third input terminal P32 pin of the control chip U1 for power-off detection. The second terminal of the second resistor R54 is grounded through the first diode D10, and the second terminal of the fourth resistor R55 is grounded. When the 5V power supply voltage drops, the second transistor Q3 is cut off, triggering a high-level interrupt signal on the P32 pin. At this time, the control chip U1 uses the voltage sustaining circuit to complete data saving.

[0047] Understandably, this embodiment uses a resistor divider network to precisely set the voltage drop detection threshold, utilizes the switching characteristics of a transistor to quickly trigger an interrupt signal when the power supply is abnormal, and works in conjunction with the temporary power supply guarantee of the voltage maintenance circuit to achieve a data preservation mechanism with a millisecond-level response at the moment of power failure, thus solving the core problem of data loss caused by sudden power failure during testing.

[0048] Based on the above technical solutions, those skilled in the art can make corresponding equivalent improvements according to the application scenario. For example, the resistance value of the voltage divider resistor can be adjusted according to the detection threshold requirements; or the transistor can be replaced with an NPN device of the same type as 2N3904; the clamping diode can be replaced with a Zener diode to limit the base voltage; or the voltage maintenance circuit can be replaced to adapt to different capacitor energy storage schemes.

[0049] Preferably, the voltage sustaining circuit includes a fifth resistor, a sixth resistor, a second diode, a third diode, a fourth diode, a second capacitor, and a third capacitor; the anode of the second diode and the first terminal of the fifth resistor are connected to the second output terminal of the power module 1, and the cathode of the second diode is connected to the first terminal of the sixth resistor; the second terminal of the fifth resistor is connected to the anode of the third diode, and the cathode of the third diode is connected to the anode of the fourth diode and the positive terminal of the second capacitor; the second terminal of the sixth resistor is connected to the cathode of the fourth diode and the positive terminal of the third capacitor and serves as the output terminal of the voltage sustaining circuit; the negative terminals of the second and third capacitors are grounded.

[0050] For details, see Figure 6As shown, in this embodiment, the voltage sustaining circuit includes a fifth resistor R50, a sixth resistor R51, a second diode D7, a third diode D8, a fourth diode D9, a second capacitor EC3, and a third capacitor EC4. The second capacitor EC3 and the third capacitor EC4 are both electrolytic capacitors, and the third diode D8 and the fourth diode D9 are SBD diodes. The anode of the second diode D7 and the first terminal of the fifth resistor R50 are connected to the second output terminal 5V of the power module 1. The cathode of the second diode D7 is connected to the first terminal of the sixth resistor R51. The second terminal of the fifth resistor R50 is connected to the anode of the third diode D8. The cathode of the third diode D8 is connected to the anode of the fourth diode D9 and the positive terminal of the second capacitor EC3. The second terminal of the sixth resistor R51 is connected to the cathode of the fourth diode D9 and the positive terminal of the third capacitor EC4, serving as the output terminal of the voltage sustaining circuit. The negative terminals of the second capacitor EC3 and the third capacitor EC4 are grounded.

[0051] Understandably, this embodiment constructs a unidirectional conduction barrier using multi-level diodes to effectively block the backflow of energy from the energy storage capacitor into the power supply path; it significantly reduces voltage loss in the sustaining circuit through the low forward voltage drop characteristics of the SBD diode; it greatly extends the power supply sustaining time during power outages through the parallel structure of dual electrolytic capacitors; and it optimizes capacitor charging efficiency through a resistor-diode collaborative bias design, ultimately providing a sufficiently long stable emergency power supply window for the control chip to ensure complete preservation of test data during sudden power outages.

[0052] Based on the above technical solutions, those skilled in the art can make corresponding equivalent improvements according to the application scenario. For example, the number of series diodes can be reduced to two stages or increased to four stages to adapt to different voltage drop requirements; or the diode type can be replaced with Schottky diodes to reduce the on-state voltage drop; or low ESR solid capacitors can be selected for the energy storage capacitor to improve the response speed.

[0053] Preferably, the discharge detection circuit 4 includes a discharge detection interface, a seventh resistor, a second optocoupler isolator, a fourth capacitor, and a fifth capacitor; the first pin of the discharge detection interface is connected to the first terminal of the seventh resistor and the positive terminal of the fourth capacitor, the second terminal of the seventh resistor is connected to the first input terminal of the second optocoupler isolator; the first output terminal of the second optocoupler isolator is connected to the first terminal of the fifth capacitor and the fourth input terminal of the control chip; the second pin of the discharge detection interface, the negative terminal of the fourth capacitor, the second terminal of the fifth capacitor, the second input terminal and the second output terminal of the second optocoupler isolator are grounded.

[0054] For details, see Figure 7As shown, in this embodiment, the discharge detection circuit 4 includes a discharge detection interface P3, a seventh resistor R33, a second optocoupler U9, a fourth capacitor EC5, and a fifth capacitor C7. The first pin of the discharge detection interface P3 is connected to the first terminal of the seventh resistor R33 and the positive terminal of the fourth capacitor EC5, and the second terminal of the seventh resistor R33 is connected to the first input terminal of the second optocoupler U9. The first output terminal of the second optocoupler U9 is connected to the first terminal of the fifth capacitor C7 and the fourth input terminal of the control chip U1. The second pin of the discharge detection interface P3, the negative terminal of the fourth capacitor EC5, the second terminal of the fifth capacitor C7, the second input terminal and the second output terminal of the second optocoupler U9 are grounded.

[0055] Understandably, this embodiment achieves electrical isolation between the high-voltage discharge circuit and the control chip through an optocoupler isolator, which can effectively block potential high-voltage impact risks; through capacitor filtering of the discharge detection interface, high-frequency interference in the detection signal can be effectively suppressed; and through a dual-level grounding topology, the signal reference is ensured to be stable, ultimately achieving millisecond-level accurate monitoring of the discharge voltage state and zero false alarm triggering, significantly improving the safety and data reliability of the testing process.

[0056] Based on the above technical solutions, those skilled in the art can make corresponding equivalent improvements according to the application scenario. For example, the optocoupler isolator can be replaced with a compatible model such as TLP785; the filter capacitor can be a ceramic capacitor to optimize the high-frequency response; the discharge detection interface can be adapted to different terminal types; and the resistance value of the current limiting resistor can be adjusted and optimized according to the voltage range.

[0057] Preferably, the timing module 3 includes a driver chip, a decoder chip, and four electronic digital tubes; the input bus of the driver chip is connected to the fourth output terminal of the control chip, and the output bus is connected to the segment selection terminal of the four electronic digital tubes; the input terminal of the decoder chip is connected to the fifth output terminal of the control chip, and the output terminal is connected to the digit selection terminal of the digital tubes.

[0058] For details, see Figure 8 As shown, in this embodiment, the driver chip U5 is a 74HC245, and the decoder chip U4 is a 74HC138. The VCC pin of the driver chip U5 is connected to the second output terminal 5V of the power module 1, the GND pin is grounded, the data input terminals A0-A7 are connected to the P0-P7 data bus of the control chip U1, and the output terminals B0-B7 are connected to the segment selection pins AG and DP of the digital tube, respectively. The VCC pin of the decoder chip U4 is connected to the second output terminal 5V of the power module 1, the GND pin is grounded, the address terminals A0-A2 are connected to the P15-P17 pins of the control chip U1, and the output terminals Y0-Y6 are connected to the digit selection terminals DIG1-DIG7 of the four-digit digital tube, realizing the dual-mode dynamic scanning display of working / discharging time.

[0059] Understandably, this embodiment extends the data carrying capacity of the control chip through the driver chip to avoid damage from overcurrent; it implements hardware decoding of the bit selection signal through the decoder chip to reduce software overhead; it achieves flicker-free dual-mode timing display through hardware scanning and refreshing; and finally, it completes the automatic switching display of working countdown and discharge countdown with minimal resource consumption.

[0060] Based on the above technical solutions, those skilled in the art can make corresponding equivalent improvements according to the application scenario. For example, the driver chip can be replaced with an integrated driver IC such as TM1620; the decoder can be replaced with CD4515 to achieve 1:16 bit selection expansion; the digital tube can be adjusted to a common cathode tube and adapted to the driving circuit; the number of display bits can be expanded to six bits as needed.

[0061] Preferably, it also includes a real-time clock circuit and a temperature monitoring circuit; the real-time clock circuit includes a clock chip and a crystal oscillator, the power supply terminal of the clock chip is connected to the second output terminal of the power module 1, and the crystal oscillator terminal is connected to both ends of the crystal oscillator; the output terminal of the clock chip is connected to the fifth input terminal of the control chip; the temperature monitoring circuit includes a temperature sensor, the input terminal of the temperature sensor is connected to the second output terminal of the power module 1, and the output terminal is connected to the sixth input terminal of the control chip.

[0062] For details, see Figure 10 As shown, in this embodiment, the real-time clock circuit includes a clock chip U7 and a crystal oscillator X2. The clock chip U7 is a DS1302, and the crystal oscillator X2 is a 32.768kHz crystal oscillator. The VCC pin of the clock chip is connected to the 5V power supply at the second output terminal of the power module 1, and the GND pin is grounded. The X1 and X2 pins of the crystal oscillator are respectively connected to the two ends of the crystal oscillator X2. The SCLK pin, CE pin, and I / O pin are respectively connected to the P42 pin, P44 pin, and P46 pin of the control chip. It should be noted that the control chip U1 is connected to a crystal oscillator X1 (11.0592MHz), which enables basic timing capabilities and can meet the basic timing requirements of routine program scheduling. The DS1302 real-time clock circuit added in this embodiment provides a more stable time reference through an independent high-precision 32.768kHz crystal oscillator X2, especially for continuous and accurate timing after power failure and timestamp calibration of cross-cycle test data. In essence, it is an enhancement and upgrade of the original timing function rather than a functional supplement. The two work together to form a two-layer time guarantee system of "basic timing + reference calibration" to ensure that millisecond-level time synchronization can still be maintained in scenarios such as sudden power failure and system restart.

[0063] See Figure 11As shown, in this embodiment, the temperature monitoring circuit includes a temperature sensor U8, which is a thermocouple detection chip MAX6675. The VCC pin is connected to the 5V power supply at the second output terminal of the power module, the GND pin is grounded, and the SO, CS, and SCK pins are connected to the sixth input terminals (P10, P11, and P12 pins) of the control chip U1, respectively. The thermocouple input terminal TC+ / - of the temperature sensor U8 is connected to a K-type thermocouple through terminal P4 to collect the surface temperature of the power transformer under test in real time and convert it into a digital signal to be transmitted back to the control chip U1. If the temperature exceeds the safety threshold, an audible alarm is emitted through the buzzer circuit, and the alarm information is indicated by the corresponding LED light.

[0064] Understandably, this embodiment provides a millisecond-level time reference through a high-precision real-time clock circuit, ensuring accurate and continuous timestamps of test data after power failure recovery, thus solving the timing discontinuity problem caused by traditional reliance on the controller's internal timing. The temperature monitoring circuit achieves industrial-grade wide-temperature-range hardware direct sampling through a thermocouple chip, performing real-time temperature tracking of key nodes such as the power transformer. When the temperature exceeds the limit, the hardware protection mechanism is immediately triggered, forming a "time-temperature" dual safety protection system in conjunction with the time reference, improving the data reliability and equipment safety level of long-term testing.

[0065] Based on the above technical solutions, those skilled in the art can make corresponding equivalent improvements according to the application scenario. For example, the real-time clock chip can be replaced with a higher precision RTC such as DS3231; the crystal oscillator frequency can be adapted to the range of 32kHz-100kHz; the thermocouple detection chip can be replaced with MAX31855 or AD8495; the temperature sensing scheme can be changed to a DS18B20 digital probe with a single bus protocol; and the thermocouple type can be switched between J-type and T-type to adapt to different temperature zones.

[0066] Compared with the prior art, the beneficial effects of this utility model include at least the following: This invention proposes a centralized power supply test circuit. It achieves electrical isolation between high and low voltage circuits through the dual DC output of the power module, ensuring system stability from the source. The control module's dual-circuit hardware collaborative design for power supply and discharge replaces manual high-voltage operation, eliminating the risk of electric shock. The hardware-level dual-mode automatic timing of the timing module eliminates manual intervention, improving the accuracy of recording both working and discharging time periods. The discharge detection circuit monitors the discharge status in real time and feeds back abnormal signals, ensuring a reliable and controllable discharge process. The data storage circuit uses a non-volatile memory chip to completely save test data, overcoming the industry-wide problem of data loss due to sudden power outages. Ultimately, this invention achieves a simultaneous leap in testing efficiency, safety, and data reliability.

[0067] Furthermore, this invention achieves millisecond-level safe on / off control of the mains L line through the coordinated driving of solid-state relays and transistors, improving the safety of high-voltage operation; completely blocks high-voltage surges in the discharge circuit through the optocoupler-coupled MOSFET architecture, improving discharge switching response speed, eliminating the risk of electric shock during manual operation, and extending equipment life; constructs a physical isolation barrier between high and low voltage circuits through an isolation transformer, eliminating the risk of electrical coupling between mains power and DC output; achieves high-efficiency voltage conversion through a step-down chip combined with an inductor-capacitor switching topology, reducing energy loss in the low-voltage power supply system; and sets a voltage drop threshold through a transistor resistor voltage divider network, achieving millisecond-level power outage detection. The system measures the following: It triggers an interrupt in the control chip to preserve data; it constructs an anti-backflow isolation chain using multi-stage series diodes, and works with capacitors to store energy to provide a hardware-level sustaining voltage window for sudden power outages; it achieves electrical isolation and signal purification of the high-voltage discharge circuit through optocoupler isolation and RC filtering, blocking potential difference interference and improving the accuracy of status recognition; it uses a hardware dynamic scanning architecture with a driver chip and decoder to achieve automatic switching and display of dual-mode timing, significantly reducing the pin occupancy and power consumption of the control chip; it constructs a millisecond-level time base through an independent clock chip to ensure timing continuity after power failure, and combines a wide-range temperature sensor to capture the thermal status of the equipment in real time, forming a "time-temperature" dual-dimensional hardware monitoring system.

[0068] In summary, this utility model solves the technical problems of lack of automation, high safety risks, and poor data reliability in the existing centralized power supply test circuit.

[0069] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. All equivalent structural transformations made under the inventive concept of the present utility model using the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present utility model.

Claims

1. A centralized power supply test circuit, characterized in that, include: The power module (1) has an input terminal connected to the mains power, a first output terminal outputting a first DC voltage, and a second output terminal outputting a second DC voltage. The control module (2) includes a control chip, a power supply control circuit, and a discharge control circuit; the output terminal of the power supply control circuit is connected to the mains input terminal of the centralized power supply under test, and the input terminal is connected to the first output terminal of the control chip, and controls the on / off of the mains power according to the instructions of the control chip; The output terminal of the discharge control circuit is connected to the discharge circuit of the centralized power supply under test, and the input terminal is connected to the second output terminal of the control chip. The circuit controls the opening and closing of the discharge circuit according to the instructions of the control chip. The timing module (3) has its input end connected to the third output end of the control chip and is used to display the working time and discharge time of the power supply under test. The discharge detection circuit (4) has its input end connected to the discharge detection point of the centralized power supply under test, and its output end connected to the first input end of the control chip, for detecting the discharge voltage status signal. The data storage circuit (5) includes a storage chip connected to the fourth output terminal of the control chip, which is used to store the working time and discharge time of the power supply under test.

2. The centralized power supply test circuit as described in claim 1, characterized in that, The power supply control circuit includes a solid-state relay and a first transistor; the first terminal of the main circuit of the solid-state relay of the power module (1) is connected to the mains L line, the second terminal of the main circuit is connected to the mains input L terminal of the power supply under test, the cathode of the control terminal is connected to the collector of the first transistor, and the anode of the control terminal is connected to the second output terminal of the power module (1); the emitter of the first transistor is grounded, and the base is connected to the first output terminal of the control chip and the second output terminal of the power module (1).

3. The centralized power supply test circuit as described in claim 1, characterized in that, The discharge control circuit includes a first optocoupler isolator and a first MOS transistor; the first input terminal of the first optocoupler isolator is connected to the second output terminal of the power module (1), the second input terminal is connected to the second output terminal of the control chip, the first output terminal is connected to the first output terminal of the power module (1), and the second output terminal is connected to the gate of the first MOS transistor. The source of the first MOSFET is grounded, and its drain is connected to the discharge circuit of the power supply under test.

4. The centralized power supply test circuit as described in claim 1, characterized in that, The power module (1) includes an input filter rectifier circuit, a power management chip, and an isolation transformer; the input terminal of the input filter rectifier circuit is connected to the mains power, and the output terminal outputs high-voltage DC power. The first input terminal of the power management chip is connected to the output terminal of the input filter and rectifier circuit. The first input terminal of the main winding of the isolation transformer is connected to the output terminal of the input filter rectifier circuit, the second input terminal is connected to the output terminal of the power management chip, and the output terminal outputs a first DC voltage.

5. The centralized power supply test circuit as described in claim 4, characterized in that, The power module (1) further includes a step-down chip, a first inductor, and a first capacitor; the first input terminal of the step-down chip is connected to the output terminal of the main winding of the isolation transformer; the output terminal of the step-down chip is connected to the first terminal of the first inductor, the second terminal of the first inductor is connected to the first terminal of the first capacitor and outputs a second DC voltage, and the second terminal of the first capacitor is grounded.

6. The centralized power supply test circuit as described in claim 1, characterized in that, The data storage circuit (5) further includes a power-off detection circuit and a voltage sustaining circuit; the power-off detection circuit includes a second transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first diode; the input terminal of the voltage sustaining circuit is connected to the second output terminal of the power module (1), and the output terminal is connected to the second input terminal of the control chip and the first terminal of the first resistor; the second terminal of the first resistor and the first terminal of the second resistor are connected to the base of the second transistor; the first terminal of the third resistor is connected to the second output terminal of the power module (1), and the second terminal of the third resistor and the first terminal of the fourth resistor are connected to the emitter of the second transistor; the collector of the second transistor is connected to the third input terminal of the control chip; the second terminal of the second resistor is grounded through the first diode, and the second terminal of the fourth resistor is grounded.

7. The centralized power supply test circuit as described in claim 6, characterized in that, The voltage sustaining circuit includes a fifth resistor, a sixth resistor, a second diode, a third diode, a fourth diode, a second capacitor, and a third capacitor; the anode of the second diode and the first terminal of the fifth resistor are connected to the second output terminal of the power module (1), and the cathode of the second diode is connected to the first terminal of the sixth resistor; the second terminal of the fifth resistor is connected to the anode of the third diode, and the cathode of the third diode is connected to the anode of the fourth diode and the positive terminal of the second capacitor; the second terminal of the sixth resistor is connected to the cathode of the fourth diode and the positive terminal of the third capacitor and serves as the output terminal of the voltage sustaining circuit; the negative terminals of the second capacitor and the third capacitor are grounded.

8. The centralized power supply test circuit as described in claim 1, characterized in that, The discharge detection circuit (4) includes a discharge detection interface, a seventh resistor, a second optocoupler isolator, a fourth capacitor, and a fifth capacitor; the first pin of the discharge detection interface is connected to the first end of the seventh resistor and the positive terminal of the fourth capacitor, and the second end of the seventh resistor is connected to the first input terminal of the second optocoupler isolator; the first output terminal of the second optocoupler isolator is connected to the first end of the fifth capacitor and the fourth input terminal of the control chip; the second pin of the discharge detection interface, the negative terminal of the fourth capacitor, the second end of the fifth capacitor, the second input terminal and the second output terminal of the second optocoupler isolator are grounded.

9. The centralized power supply test circuit as described in claim 1, characterized in that, The timing module (3) includes a driver chip, a decoder chip, and four electronic digital tubes; the input bus of the driver chip is connected to the fourth output terminal of the control chip, and the output bus is connected to the segment selection terminal of the four electronic digital tubes; the input terminal of the decoder chip is connected to the fifth output terminal of the control chip, and the output terminal is connected to the digit selection terminal of the digital tubes.

10. The centralized power supply test circuit as described in claim 1, characterized in that, It also includes a real-time clock circuit and a temperature monitoring circuit; the real-time clock circuit includes a clock chip and a crystal oscillator, the power supply terminal of the clock chip is connected to the second output terminal of the power module (1), and the crystal oscillator terminal is connected to both ends of the crystal oscillator; the output terminal of the clock chip is connected to the fifth input terminal of the control chip; the temperature monitoring circuit includes a temperature sensor, the input terminal of the temperature sensor is connected to the second output terminal of the power module (1), and the output terminal is connected to the sixth input terminal of the control chip.

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