A mosfet avalanche test system

Abstract

The utility model relates to a kind of mosfet avalanche test systems, including MOSFET and control chip U1, the gate of MOSFET is electrically connected with the GATE pin of control chip U1, the source of MOSFET is electrically connected with the SW pin of control chip U1, the source of MOSFET is electrically connected with power supply circuit and energy storage circuit, power supply circuit and energy storage circuit are electrically connected by a tristate buffer BUF between, resistance R6 and capacitor C5 electrically connected in series between the source and drain of MOSFET, the source and drain of MOSFET still electrically connected with a capacitor C4. The present application realizes MOSFET avalanche accurate test, with multiple protection and high energy utilization, ensure test accurate, safe, stable.

Description

Technical Field

[0001] This utility model relates to the field of circuits, and more specifically, to a MOSFET avalanche testing system. Background Technology

[0002] In modern power electronic systems, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are widely used in power conversion, motor control, and other fields due to their advantages such as fast switching speed and low drive power. Avalanche withstand capability is a core indicator for evaluating the reliability of MOSFETs, and avalanche testing aims to verify their performance under overvoltage breakdown conditions. However, traditional MOSFET avalanche testing systems have significant drawbacks: some circuits lack sufficient precision in driving and controlling the MOSFET, making it difficult to stably trigger the avalanche effect; there is a lack of effective voltage spike suppression measures, affecting test accuracy; simultaneously, the protection mechanism is imperfect, easily causing MOSFET damage during testing, and data monitoring capabilities are limited, failing to provide comprehensive support for MOSFET performance analysis. With the increasing reliability requirements of power electronic devices for MOSFETs, the development of an avalanche testing system with precise control, reliable protection, and efficient testing capabilities has become an urgent industry need. Utility Model Content

[0003] The technical problem to be solved by this invention is to provide a MOSFET avalanche testing system to address the above-mentioned deficiencies of the prior art.

[0004] The technical solution adopted by this utility model to solve its technical problem is:

[0005] Construct a MOSFET avalanche testing system, which includes:

[0006] The MOSFET and the control chip U1 are configured such that the gate of the MOSFET is electrically connected to the GATE pin of the control chip U1, the source of the MOSFET is electrically connected to the SW pin of the control chip U1, the source of the MOSFET is electrically connected to the power supply circuit and the energy storage circuit, the power supply circuit and the energy storage circuit are electrically connected through a tri-state buffer BUF, a resistor R6 and a capacitor C5 are electrically connected in series between the source and drain of the MOSFET, and a capacitor C4 is also electrically connected between the source and drain of the MOSFET.

[0007] Furthermore, the power supply circuit includes an AC power interface, which is electrically connected to the input terminal of the rectifier bridge BR. The output terminal of the rectifier bridge BR is electrically connected to a capacitor C2 and then grounded. The output terminal of the rectifier bridge BR is electrically connected to the input terminal of the tri-state buffer BUF, and the output terminal of the tri-state buffer BUF is electrically connected to the drain of the MOSFET.

[0008] Furthermore, the energy storage circuit includes an inductor L1, which includes two secondary coils. One end of one secondary coil is electrically connected to the control terminal of the tri-state buffer BUF, and the other end is electrically connected to the drain of the MOSFET. One end of the other secondary coil is grounded, and the other end is electrically connected to a diode D2 and a resistor R1. The diode D2 is electrically connected to the VDD pin of the control chip. The VDD pin of the control chip is electrically connected to a capacitor C3 and then grounded. The resistor R1 is electrically connected to a resistor R2 and then grounded. The resistor R1 is also electrically connected to the FB pin of the control chip U1. The other end of the other secondary coil is also electrically connected to the CS pin of the control chip U1 and a resistor R3, and the resistor R3 is grounded.

[0009] Furthermore, the primary coil of the inductor L1 is electrically connected to the DC power interface, one end of the primary coil of the inductor L1 is electrically connected to a diode D1, the diode D1 is electrically connected to one end of a capacitor C1, and the other end of the capacitor C1 is electrically connected to the other end of the primary coil of the inductor L1.

[0010] Furthermore, the output terminal of the rectifier bridge BR is electrically connected to a resistor R5 and then electrically connected to the OVP / BO pin of the control chip U1. The OVP / BO pin of the control chip U1 is also electrically connected to a resistor R4 and then grounded. The GND pin of the control chip U1 is grounded.

[0011] Furthermore, the control chip U1 integrates a voltage detection module, a circuit detection module, a high-voltage start-up module, and an intelligent switch module.

[0012] The beneficial effects of this utility model are as follows:

[0013] This invention accurately achieves avalanche testing with ample data support. It suppresses voltage spikes during MOSFET turn-off using an RC snubber circuit (R6, C5) and optimizes the drain-source voltage rise curve, ensuring stable voltage changes during avalanche testing and improving test accuracy. The control chip monitors the MOSFET voltage (voltage detection module) and current (CS pin in conjunction with R3) in real time, providing precise data support for analyzing the MOSFET's avalanche breakdown voltage, current withstand capability, and other electrical characteristics.

[0014] Multiple protection mechanisms ensure circuit safety, including overvoltage protection (OVP / BO pins combined with R4 and R5) and overcurrent protection (current detection module). These functions monitor circuit anomalies in real time, triggering protection mechanisms to prevent MOSFET damage due to overvoltage or overcurrent, thus ensuring the safety of the test system. Closed-loop voltage regulation control (FB pins combined with R1, R2, and R3) ensures power supply stability during testing, reducing the interference of voltage fluctuations on test results.

[0015] The system features efficient energy utilization and strong process synergy. In the energy storage circuit, after the energy is released from inductor L1, part of it powers the control chip VDD through diode D2, achieving energy recycling; the other part is used to charge the MOSFET parasitic capacitance, triggering the avalanche effect. The strong synergy among the modules ensures a smooth testing process. The power supply circuit provides a stable DC power supply through rectifier bridge BR and capacitor C2, laying the energy foundation for the entire testing system and ensuring stable operation during the testing process. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the utility model will be further described below in conjunction with the accompanying drawings and embodiments. The drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a circuit diagram of the MOSFET avalanche testing system according to a preferred embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, a clear and complete description will be provided below in conjunction with the technical solutions in the embodiments of this utility model. Obviously, the described embodiments are some, but not all, embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0019] The preferred embodiment of this utility model is the MOSFET avalanche testing system, such as... Figure 1As shown, a MOSFET avalanche testing system includes a MOSFET and a control chip U1. The gate of the MOSFET is electrically connected to the GATE pin of the control chip U1, and the source of the MOSFET is electrically connected to the SW pin of the control chip U1. The source of the MOSFET is electrically connected to a power supply circuit and an energy storage circuit. The power supply circuit and the energy storage circuit are electrically connected through a tri-state buffer BUF. A resistor R6 and a capacitor C5 are connected in series between the source and drain of the MOSFET, and a capacitor C4 is also electrically connected between the source and drain of the MOSFET. The power supply circuit includes an AC power interface, which is electrically connected to the input terminal of a rectifier bridge BR. The output terminal of the rectifier bridge BR is connected to ground via a capacitor C2. The output terminal of the rectifier bridge BR is electrically connected to the input terminal of the tri-state buffer BUF, and the output terminal of the tri-state buffer BUF is electrically connected to the drain of the MOSFET. The energy storage circuit includes an inductor L1, which comprises two secondary coils. One end of one secondary coil is electrically connected to the control terminal of a tri-state buffer BUF, and the other end is electrically connected to the drain of a MOSFET. One end of the other secondary coil is grounded, and the other end is electrically connected to a diode D2 and a resistor R1. Diode D2 is electrically connected to the VDD pin of the control chip, which is then grounded after being connected to a capacitor C3. Resistor R1 is also electrically connected to a resistor R2 and then grounded, and is also electrically connected to the FB pin of the control chip U1. The other end of the other secondary coil is also electrically connected to the CS pin of the control chip U1 and a resistor R3, which is grounded. The primary coil of inductor L1 is electrically connected to a DC power interface. One end of the primary coil of inductor L1 is electrically connected to a diode D1, which is then connected to one end of a capacitor C1. The other end of capacitor C1 is electrically connected to the other end of the primary coil of inductor L1. The output terminal of the rectifier bridge BR is electrically connected to a resistor R5, which is then electrically connected to the OVP / BO pin of the control chip U1. The OVP / BO pin of the control chip U1 is also electrically connected to a resistor R4 and grounded. The GND pin of the control chip U1 is grounded. The control chip U1 integrates a voltage detection module, a circuit detection module, a high-voltage start-up module, and a smart switch module. The control chip U1 can use the PI TOPSwitch-GX series (such as TOP264GN), which has a built-in high-voltage start-up circuit, eliminating the need for complex external start-up resistors and directly obtaining energy from the input high voltage, meeting the circuit's "high-voltage start-up module" requirements. It integrates overvoltage protection (OVP) and overcurrent protection (OCP) functions, matching the OVP / BO pin and CS current detection functions in the circuit, enabling accurate voltage / current monitoring and protection. It has PWM control functionality, controlling the on / off state of the MOSFET through the output drive signal, adapting to the MOSFET drive requirements of the "smart switch module" in the circuit.The pin layout supports functions such as GATE drive output and SW voltage detection, and is compatible with the gate (GATE) and source (SW) connection logic of the MOSFET in the circuit.

[0020] The working principle of this utility model:

[0021] The AC power supply is connected to the rectifier bridge BR, which converts the AC power into DC power. After being filtered by capacitor C2, it provides a stable DC power supply for the entire circuit. One DC output from the rectifier bridge is connected to the drain of the MOSFET via a tri-state buffer BUF, and the other is connected to the OVP / BO pin of the control chip U1 through resistors R5 and R4 for overvoltage protection monitoring.

[0022] The control chip U1 performs the following functions: high-voltage startup, signal drive and control, monitoring and protection, and energy storage and conversion. High-voltage startup involves the high-voltage startup module obtaining energy from the high voltage output of the rectifier bridge to power the internal circuitry (VDD) of the control chip U1, ensuring normal chip operation. Signal drive and control is achieved by the intelligent switch module outputting a drive signal through the GATE pin. After the drive capability is enhanced by the tri-state buffer BUF, the signal controls the gate of the MOSFET, enabling the MOSFET to turn on and off. Monitoring and protection involves the voltage detection module monitoring the MOSFET voltage in real time, and the current detection module monitoring the circuit current through the CS pin and resistor R3. Combined with the overvoltage protection function of the OVP / BO pins, this ensures safe circuit operation. Energy storage and conversion occur when the MOSFET is on; the DC power supply charges the inductor L1 through the MOSFET, storing energy in L1 as magnetic energy. When the MOSFET is off, the energy in L1 is released through the secondary coil, with one path powering the control chip's VDD via diode D2, and the other path contributing to the voltage construction for subsequent avalanche testing.

[0023] The MOSFET avalanche test is implemented by controlling the MOSFET's on-time precisely through the intelligent switching module of the control chip U1, charging inductor L1 to the target current value. Subsequently, the MOSFET is turned off, and the energy from inductor L1 is transferred to the MOSFET's parasitic capacitance C4, causing the MOSFET's drain-source voltage to rise continuously. When the voltage reaches the MOSFET's avalanche breakdown threshold, the avalanche effect is triggered. An RC snubber circuit composed of resistor R6 and capacitor C5 absorbs energy at the moment of MOSFET turn-off, suppressing voltage spikes and optimizing the drain-source voltage rise curve to ensure test accuracy. The voltage detection module of the control chip U1 records the MOSFET's drain-source voltage changes in real time, while the current detection module monitors the current, providing data support for analyzing the MOSFET's electrical characteristics (such as breakdown voltage and current withstand capability) under avalanche conditions. The voltage divider circuit composed of resistors R1, R2, and R3 feeds the output voltage back to the FB pin of the control chip U1, achieving closed-loop voltage regulation control and ensuring power supply stability during the test. If the voltage is abnormal during the test, the OVP / BO pin will trigger overvoltage protection to prevent the MOSFET from being damaged by overvoltage. At the same time, the parameters at the time of protection triggering will be recorded to improve the basis for avalanche test analysis.

[0024] This invention accurately achieves avalanche testing with ample data support. It suppresses voltage spikes during MOSFET turn-off using an RC snubber circuit (R6, C5) and optimizes the drain-source voltage rise curve, ensuring stable voltage changes during avalanche testing and improving test accuracy. The control chip monitors the MOSFET voltage (voltage detection module) and current (CS pin in conjunction with R3) in real time, providing precise data support for analyzing the MOSFET's avalanche breakdown voltage, current withstand capability, and other electrical characteristics.

[0025] Multiple protection mechanisms ensure circuit safety, including overvoltage protection (OVP / BO pins combined with R4 and R5) and overcurrent protection (current detection module). These functions monitor circuit anomalies in real time, triggering protection mechanisms to prevent MOSFET damage due to overvoltage or overcurrent, thus ensuring the safety of the test system. Closed-loop voltage regulation control (FB pins combined with R1, R2, and R3) ensures power supply stability during testing, reducing the interference of voltage fluctuations on test results.

[0026] The system features efficient energy utilization and strong process synergy. In the energy storage circuit, after the energy is released from inductor L1, part of it powers the control chip VDD through diode D2, achieving energy recycling; the other part is used to charge the MOSFET parasitic capacitance, triggering the avalanche effect. The strong synergy among the modules ensures a smooth testing process. The power supply circuit provides a stable DC power supply through rectifier bridge BR and capacitor C2, laying the energy foundation for the entire testing system and ensuring stable operation during the testing process.

[0027] It should be understood that this utility model is not limited to the above-described preferred embodiments. Anyone can derive other forms of products under the guidance of this utility model. However, regardless of any changes made in their shape or structure, any technical solution that is the same as or similar to this application falls within the protection scope of this utility model.

Claims

1. A MOSFET avalanche testing system, characterized in that, The device includes a MOSFET and a control chip U1. The gate of the MOSFET is electrically connected to the GATE pin of the control chip U1, and the source of the MOSFET is electrically connected to the SW pin of the control chip U1. The source of the MOSFET is electrically connected to the power supply circuit and the energy storage circuit. The power supply circuit and the energy storage circuit are electrically connected through a tri-state buffer BUF. A resistor R6 and a capacitor C5 are connected in series between the source and drain of the MOSFET. A capacitor C4 is also electrically connected between the source and drain of the MOSFET.

2. The MOSFET avalanche testing system according to claim 1, characterized in that, The power supply circuit includes an AC power interface, which is electrically connected to the input terminal of the rectifier bridge BR. The output terminal of the rectifier bridge BR is electrically connected to a capacitor C2 and then grounded. The output terminal of the rectifier bridge BR is electrically connected to the input terminal of the tri-state buffer BUF. The output terminal of the tri-state buffer BUF is electrically connected to the drain of the MOSFET.

3. The MOSFET avalanche testing system according to claim 1, characterized in that, The energy storage circuit includes an inductor L1, which has two secondary coils. One end of one secondary coil is electrically connected to the control terminal of the tri-state buffer BUF, and the other end is electrically connected to the drain of the MOSFET. One end of the other secondary coil is grounded, and the other end is electrically connected to a diode D2 and a resistor R1. The diode D2 is electrically connected to the VDD pin of the control chip. The VDD pin of the control chip is electrically connected to a capacitor C3 and then grounded. The resistor R1 is electrically connected to a resistor R2 and then grounded. The resistor R1 is also electrically connected to the FB pin of the control chip U1. The other end of the other secondary coil is also electrically connected to the CS pin of the control chip U1 and a resistor R3. The resistor R3 is grounded.

4. The MOSFET avalanche testing system according to claim 3, characterized in that, The primary coil of the inductor L1 is electrically connected to the DC power interface. One end of the primary coil of the inductor L1 is electrically connected to a diode D1. The diode D1 is electrically connected to one end of a capacitor C1. The other end of the capacitor C1 is electrically connected to the other end of the primary coil of the inductor L1.

5. The MOSFET avalanche testing system according to claim 2, characterized in that, The output terminal of the rectifier bridge BR is electrically connected to a resistor R5 and then electrically connected to the OVP / BO pin of the control chip U1. The OVP / BO pin of the control chip U1 is also electrically connected to a resistor R4 and then grounded. The GND pin of the control chip U1 is grounded.

6. The MOSFET avalanche testing system according to claim 1, characterized in that, The control chip U1 integrates a voltage detection module, a circuit detection module, a high-voltage start-up module, and an intelligent switch module.

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