LDO linear voltage stabilizing circuit, chip and device

Abstract

The application discloses an LDO linear voltage stabilizing circuit, a chip and equipment. The LDO linear voltage stabilizing circuit comprises a comparison output module, a buffer driving module, a first compensation module and a power switch module. The comparison output module is used for comparing a received reference voltage and a feedback voltage to generate and output an error signal. The buffer driving module receives the error signal for amplification and buffer processing to generate and output a driving signal. The first compensation module generates a first compensation signal according to a load current and a sampling current to dynamically adjust the amplitude and / or phase of the driving signal. The power switch module controls the on-off of a switch according to the received driving signal to adjust the size of the output voltage to the load. The feedback module detects the voltage size of the load and outputs to the comparison output module. In this way, the first compensation module generates a first compensation signal according to the dynamic changes of the feedback load current and load capacitance to dynamically adjust the amplitude and / or phase of the driving signal output to the power switch module, ensuring the stability of the circuit loop.

Description

Technical Field

[0001] This application relates to the field of LDO linear regulator technology, and in particular to an LDO linear regulator circuit, chip, and device. Background Technology

[0002] Currently, existing LDO linear regulator chips have several shortcomings in frequency compensation technology. Conventional low-dropout linear regulators (LDOs) lack circuit designs for frequency compensation over a wide range of load capacitances. Traditional partial compensation methods often fail to achieve a stable frequency response when dealing with a wide range of load capacitance and current variations. For example, some early compensation circuits may maintain good performance when the load capacitance is small, but as the load capacitance increases to a certain extent, issues such as reduced phase margin and unstable output voltage will occur. Furthermore, the performance of LDOs varies under different process conditions, and some existing compensation techniques cannot guarantee consistently stable frequency response and output voltage accuracy across the entire process curve, which limits the reliability and stability of LDOs in different production batches and process environments. Utility Model Content

[0003] The main purpose of this application is to provide an LDO linear regulator circuit, chip, and device, which aims to solve the technical problem of insufficient stability of traditional LDOs under wide voltage and wide load conditions.

[0004] To achieve the above objectives, this application provides an LDO linear regulator circuit, the LDO linear regulator circuit comprising: Reference power supply terminal, used to output reference voltage; The comparison output module has a first input terminal connected to the reference power supply terminal, a second input terminal for receiving feedback voltage, and is used to compare the received reference voltage and the feedback voltage to generate and output an error signal. A buffer drive module, the input of which is electrically connected to the output of the comparison output module, is used to receive the error signal, amplify and buffer it to generate and output a drive signal. The first compensation module has its input terminal electrically connected to the output terminal of the buffer drive module. The first input signal terminal of the first compensation module is connected to the load current and the first input signal terminal is connected to the sampling current. The first compensation module is used to generate a first compensation signal based on the load current and the sampling current to dynamically adjust the amplitude and / or phase of the drive signal. A power switch module, wherein the input terminal of the power switch module is electrically connected to the output terminal of the buffer drive module and the output terminal of the first compensation module, and the power switch module is used to control the on and off of the switch according to the received drive signal, thereby adjusting the voltage output to the load. The feedback module has its first end electrically connected to the input end of the power switch module and the output end of the first compensation module, and its second end electrically connected to the second input end of the comparison output module. It is used to detect the voltage of the load and output the feedback voltage to the comparison output module.

[0005] In one embodiment, the LDO linear regulator circuit further includes: Load voltage sampling terminal, used to output load voltage; The second compensation module has its input terminal electrically connected to the load voltage sampling terminal and its output terminal electrically connected to the output terminal of the comparison output module. The second compensation module is used to generate a second compensation signal based on the received load voltage magnitude, so as to compensate the error signal and output it to the buffer drive module.

[0006] In one embodiment, the LDO linear regulator circuit further includes: A first slope enhancer is electrically connected to the reference terminal of the comparison output module. The first slope enhancer is used to output a first slope signal to adjust the slope of the reference voltage and the feedback voltage, so as to improve the transient response of the comparison output module and reduce the overshoot or undershoot of the error signal.

[0007] In one embodiment, the LDO linear regulator circuit further includes: The second slope enhancer is electrically connected to the reference terminal of the buffer drive module. The second slope enhancer is used to output a second slope signal to adjust the slope of the error signal, so as to improve the transient response of the buffer drive module and reduce the overshoot or undershoot of the drive signal.

[0008] In one embodiment, the LDO linear regulator circuit further includes: A current buffer is provided between the comparison output module and the buffer drive module. The current buffer is used to receive the error signal and, when the current of the error signal exceeds a preset value, limit the current of the error signal and output it to the buffer drive module.

[0009] In one embodiment, the first compensation module includes: The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP, the thirteenth PMOS transistor MO, the first NMOS transistor MN1, the first resistor R1, the second resistor RL, the third resistor RZ, the first capacitor CL, and the second capacitor Cc; The source of the third PMOS transistor MP3 is electrically connected to the drain of the thirteenth PMOS transistor MO, the source of the first PMOS transistor MP1, the source of the second PMOS transistor MP2, the first terminal of the third resistor RZ, and the first terminal of the second capacitor Cc. The gate of the thirteenth PMOS transistor MO is connected to the load current. The source of the thirteenth PMOS transistor MO is electrically connected to the source of the fourth PMOS transistor MP. The gate of the fourth PMOS transistor MP is connected to the sampling current. The gate of the third PMOS transistor MP3 is electrically connected to the gate of the first PMOS transistor MP1 and the drain of the third PMOS transistor MP3. The drain of the third PMOS transistor MP3 is also electrically connected to the drain of the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 is connected to an external bias voltage source. The drain of the first PMOS transistor MP1 is electrically connected to the first end of the first resistor R1. The second end of the first resistor R1 is electrically connected to the gate and drain of the second PMOS transistor MP2, the second end of the third resistor RZ, the second end of the second capacitor Cc, the first end of the second resistor RL, the first end of the first capacitor CL, and the feedback module. The second end of the first capacitor CL, the first end of the second resistor RL, and the source of the first NMOS transistor MN1 are grounded.

[0010] In one embodiment, the second compensation module includes: Fifth PMOS transistor MP4, sixth PMOS transistor MP5, seventh PMOS transistor MP6, eighth PMOS transistor MP7, ninth PMOS transistor MP8, tenth PMOS transistor MP9, eleventh PMOS transistor MP10, twelfth PMOS transistor MP11, fourth resistor R3, fifth resistor R4, sixth resistor R5, seventh resistor R6; The gates of the fifth PMOS transistor MP4, the sixth PMOS transistor MP5, the seventh PMOS transistor MP6, and the eighth PMOS transistor MP7 are all electrically connected to the output terminal of the comparator output module. The drain and source of the fifth PMOS transistor MP4 are electrically connected to the first terminal of the fourth resistor R3. The drain and source of the sixth PMOS transistor MP5 are electrically connected to the first terminal of the fifth resistor R4. The drain and source of the seventh PMOS transistor MP6 are electrically connected to the first terminal of the sixth resistor R5. The drain and source of the eighth PMOS transistor MP7 are electrically connected to the first terminal of the seventh resistor R6. The second terminal of the fourth resistor R3 is electrically connected to the drain of the ninth PMOS transistor MP8. The second end of the fifth resistor R4 is electrically connected to the drain of the tenth PMOS transistor MP9, the second end of the sixth resistor R5 is electrically connected to the drain of the eleventh PMOS transistor MP10, the second end of the seventh resistor R6 is electrically connected to the drain of the twelfth PMOS transistor MP11, the gates of the ninth PMOS transistor MP8, the tenth PMOS transistor MP9, the eleventh PMOS transistor MP10, and the twelfth PMOS transistor MP11 are all electrically connected to an external bias voltage source, and the sources of the ninth PMOS transistor MP8, the tenth PMOS transistor MP9, the eleventh PMOS transistor MP10, and the twelfth PMOS transistor MP11 are all grounded.

[0011] In one embodiment, the feedback module includes: Ninth resistor RF1 and tenth resistor RF2; The first end of the ninth resistor RF1 is electrically connected to the input end of the power switch module and the output end of the first compensation module. The second end of the ninth resistor RF1 is electrically connected to the first end of the tenth resistor RF2. The second end of the tenth resistor RF2 is electrically connected to the first input end of the comparison output module.

[0012] In addition, to achieve the above objectives, this application also provides an LDO linear regulator chip, which includes the LDO linear regulator circuit as described above.

[0013] In addition, to achieve the above objectives, this application also provides an LDO linear regulator device, which includes the LDO linear regulator chip as described above.

[0014] This application provides an LDO linear regulator circuit including: a reference power supply terminal for outputting a reference voltage; a comparison output module, wherein a first input terminal of the comparison output module is connected to the reference power supply terminal, a second input terminal of the comparison output module is used to receive a feedback voltage, and the comparison output module is used to compare the received reference voltage and the feedback voltage to generate and output an error signal; and a buffer drive module, wherein the input terminal of the buffer drive module is electrically connected to the output terminal of the comparison output module, and is used to receive the error signal, amplify and buffer it to generate and output a drive signal. A first compensation module, whose input terminal is electrically connected to the output terminal of the buffer drive module, whose first input signal terminal is connected to the load current, and whose first input signal terminal is connected to the sampling current, is used to generate a first compensation signal based on the load current and the sampling current to dynamically adjust the amplitude and / or phase of the drive signal; a power switch module, whose input terminal is electrically connected to the output terminal of the buffer drive module and the output terminal of the first compensation module, is used to control the switching on and off according to the received drive signal, thereby adjusting the voltage output to the load; a feedback module, whose first terminal is electrically connected to the input terminal of the power switch module and the output terminal of the first compensation module, and whose second terminal is electrically connected to the second input terminal of the comparison output module, is used to detect the voltage magnitude of the load and output the feedback voltage to the comparison output module. Thus, the first compensation module generates a first compensation signal based on the dynamic changes in load current and load capacitance fed back by the feedback module, so as to dynamically adjust the amplitude and / or phase of the drive signal output to the power switch module, so that the minimum phase margin is always greater than 45° in the entire load current range of 1uA-300mA, thereby ensuring the stability of the internal loop of the LDO linear regulator circuit. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a circuit system framework diagram provided for Embodiment 1 of the LDO linear regulator circuit of this application; Figure 2A circuit diagram of the first compensation module provided in Embodiment 1 of the LDO linear regulator circuit of this application; Figure 3 A circuit diagram of the second compensation module 6 provided in Embodiment 1 of the LDO linear regulator circuit of this application; Figure 4 The small-signal model of the LDO loop provided for Embodiment 1 of the LDO linear regulator circuit of this application; Figure 5 A simulation diagram of the phase margin over a wide load capacitance range provided for Embodiment 1 of the LDO linear regulator circuit of this application; Figure 6 This is an equivalent zero-pole compensation circuit diagram of the first compensation module provided in Embodiment 1 of the LDO linear regulator circuit of this application.

[0018] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0020] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0021] Please refer to Figures 1 to 6 The main solution of this application is: An LDO linear regulator circuit, the LDO linear regulator circuit comprising: Reference power supply terminal, used to output reference voltage; The comparison output module 1 has a first input terminal connected to the reference power supply terminal, a second input terminal for receiving feedback voltage, and is used to compare the received reference voltage and the feedback voltage to generate and output an error signal. The buffer drive module 2 is electrically connected to the output of the comparison output module 1. It is used to receive the error signal, amplify and buffer it to generate and output a drive signal. The first compensation module 3 has its input terminal electrically connected to the output terminal of the buffer drive module 2. The first input signal terminal of the first compensation module 3 is connected to the load current and the first input signal terminal is connected to the sampling current. The first compensation module 3 is used to generate a first compensation signal based on the load current and the sampling current to dynamically adjust the amplitude and / or phase of the drive signal. The input terminal of the power switch module 4 is electrically connected to the output terminal of the buffer drive module 2 and the output terminal of the first compensation module 3. The power switch module 4 is used to control the switching on and off according to the received drive signal, thereby adjusting the voltage output to the load. Feedback module 5, the first end of which is electrically connected to the input end of power switch module 4 and the output end of first compensation module 3 respectively, and the second end of feedback module 5 is electrically connected to the second input end of comparison output module 1, for detecting the voltage of the load, so as to output the feedback voltage to comparison output module 1.

[0022] In this embodiment, the reference power supply terminal can be provided with a stable reference voltage by a reference voltage source, or connected by an external voltage source to ensure the stability and accuracy of the circuit; the comparison output module 1 can be composed of an error amplifier or an operational amplifier, its first input terminal receives the reference voltage from the reference power supply terminal, and its second input terminal is electrically connected to the output terminal of the feedback module 5 to receive the feedback load voltage signal; the buffer drive module 2 can be composed of a buffer amplifier; the power switch module 4 can be implemented by semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or bipolar junction transistors (BJTs) to control the on / off state of the LDO linear regulator circuit and output a stable voltage to the load; the feedback module can be composed of multiple feedback resistor elements to control the LDO linear regulator circuit. The loop forms a negative feedback loop, forming a closed-loop control. The load current connected to the second input terminal of the first compensation module 3 can be measured through the load resistor to monitor the working status of the load in real time. The sampling current can be obtained by selecting a small resistor with a known resistance value as a shunt and connecting the shunt in series in the path of the load current. A differential amplifier with a specific gain setting is set to amplify the voltage drop across the shunt, thereby obtaining a sampling current signal proportional to the load current. Thus, through this load current detection mechanism, the change of the load current is monitored, and the component values ​​in the compensation network are adjusted accordingly. For example, the on-resistance of the MOS transistor inside the first compensation module 3 is changed to adjust the resistance value of the compensation network, so that the compensation zero point is automatically adjusted with the change of the load current. The comparison output module 1 compares the received reference voltage and the feedback voltage to generate and output an error signal. Subsequently, the buffer drive module 2 receives the error signal, amplifies and buffers it to generate and output a drive signal. While the buffer drive module 2 is outputting the drive signal to the power switch module 4, the first compensation module 3 generates a first compensation signal based on the load current and the sampling current to dynamically adjust the amplitude and / or phase of the drive signal, so that the output voltage of the LDO linear regulator circuit remains stable and voltage fluctuations are reduced. At the same time as the power switch module 4 outputs voltage, the feedback module 5 treats the voltage connected to the input terminal of the power switch module 4 as the load voltage and feeds it back to the second input terminal of the comparison output module 1, thereby forming a closed-loop control.

[0023] Please refer to Figure 2 Furthermore, the first compensation module 3 includes: The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP, the thirteenth PMOS transistor MO, the first NMOS transistor MN1, the first resistor R1, the second resistor RL, the third resistor RZ, the first capacitor CL, and the second capacitor Cc; The source of the third PMOS transistor MP3 is electrically connected to the drain of the thirteenth PMOS transistor MO, the source of the first PMOS transistor MP1, the source of the second PMOS transistor MP2, the first terminal of the third resistor RZ, and the first terminal of the second capacitor Cc. The gate of the thirteenth PMOS transistor MO is connected to the load current. The source of the thirteenth PMOS transistor MO is electrically connected to the source of the fourth PMOS transistor MP. The gate of the fourth PMOS transistor MP is connected to the sampling current. The gate of the third PMOS transistor MP3 is electrically connected to the gate of the first PMOS transistor MP1 and the drain of the third PMOS transistor MP3. The drain of the three PMOS transistors MP3 is also electrically connected to the drain of the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 is connected to an external bias voltage source. The drain of the first PMOS transistor MP1 is electrically connected to the first end of the first resistor R1. The second end of the first resistor R1 is electrically connected to the gate and drain of the second PMOS transistor MP2, the second end of the third resistor RZ, the second end of the second capacitor Cc, the first end of the second resistor RL, the first end of the first capacitor CL, and the feedback module 5. The second end of the first capacitor CL, the first end of the second resistor RL, and the source of the first NMOS transistor MN1 are grounded.

[0024] In this embodiment, the load current Io connected to the gate of the thirteenth PMOS transistor MO can be measured, for example, by a load resistor, to monitor the change of the load current Io in real time. The sampling current can be obtained by, for example, selecting a small resistor with a known resistance value as a shunt and connecting the shunt in series in the path of the load current. A differential amplifier with a specific gain setting is set to amplify the voltage drop across the shunt, thereby obtaining a sampling current αI proportional to the load current. This allows the collected sampling current αI and the load current Io to flow into the node of the feedback module 5 connected to the first compensation module 3. Specifically, the third PMOS transistor MP3, the first NMOS transistor MN1, and the external bias voltage source form a current mirror for replicating or amplifying the sampling current αI. The sampling current αI is more accurately replicated to the first PMOS transistor MP1, and then copied to the feedback node FB of the feedback module 5. A signal related to the main power transistor current is formed at the feedback node FB. The sampling current αI is sampled by the thirteenth PMOS transistor MO and coupled to the feedback node FB of the feedback module 5 through the second capacitor Cc. The current αI from the fourth PMOS transistor MP flows through the third resistor RL, which acts as the load resistor, to generate the load voltage Vout output to the load. The third resistor RZ is used to set the gate-source voltage of the second PMOS transistor MP2 and control its conduction state. The second resistor RL, as the load resistor, is used to generate and output the load voltage Vout. The first capacitor CL is the load capacitor, used to stabilize the output load voltage Vout and reduce voltage fluctuations. When the load current Io changes, the voltage drop across the second resistor RL also changes, resulting in a changing output voltage Vout. The presence of the first capacitor CL smooths this voltage change, reducing the fluctuation of the output voltage Vout through charging and discharging, and improving the circuit's voltage regulation performance.

[0025] Furthermore, the feedback module includes: Ninth resistor RF1 and tenth resistor RF2; The first end of the ninth resistor RF1 is electrically connected to the input end of the power switch module 4 and the output end of the first compensation module 3. The second end of the ninth resistor RF1 is electrically connected to the first end of the tenth resistor RF2. The second end of the tenth resistor RF2 is electrically connected to the first input end of the comparison output module 1.

[0026] In this embodiment, the voltage divider network composed of the ninth resistor RF1 and the tenth resistor RF2 can proportionally reduce the voltage at the input terminal of the power switch module 4, and send this divided voltage as a feedback signal to the comparator output module 1. In this embodiment, by adjusting the resistance values ​​of the ninth resistor RF1 and the tenth resistor RF2, the feedback ratio of the feedback voltage output to the comparator output module 1 can be flexibly set, thereby achieving precise control of the output voltage. Furthermore, this voltage divider feedback mechanism helps improve the stability and load regulation of the circuit, ensuring that the LDO linear regulator circuit can output a stable voltage under various load conditions. For the feedback node, the first compensation module 3 has two current paths, one of which is the main power transistor current (i.e., ... Figure 2 The Io in the input flows into the feedback node of the feedback module 5 (i.e., Figure 2 The second terminal of the ninth resistor RF1 is electrically connected to the first terminal of the tenth resistor RF2 at point FB. The other is the sampling current (i.e. Figure 2 The αI in the input flows into the feedback node FB of the feedback module 5. Therefore, the transfer function can be calculated using the superposition method. This allows for the derivation of the compensation part and the output pole. Ignoring the output pole of the op-amp and adjusting the pole position of the gate of the MOS transistor used as the power switch module 4, the transfer functions of the two are superimposed to obtain: Since the sampling coefficient α is very small, the first-order terms with α in the numerator and denominator can be ignored, and the resistance values ​​of the ninth resistor RF1 and the tenth resistor RF2 are relatively large. The denominator of the calculated compensation zero point Z1 includes the load capacitance CL. Since the output pole of the circuit is determined by the output impedance and the load capacitance CL, the compensation zero point can change in the same direction as the output pole. The dynamic resistor Req is composed of three parts connected in parallel: the first PMOS transistor MP1 and the first resistor R1, the impedance of the third PMOS transistor MP3, and the impedance 1 / gmp2 of the first PMOS transistor MP1. All three are inversely proportional to the load. Therefore, the compensation zero point Z1 changes in the same direction as the output pole P1.

[0027] The following table lists the key parameters for the above formula: For details, please refer to Figure 4 , Figure 4This is the small-signal loop model of the LDO linear regulator circuit. The small-signal loop model is disconnected at the feedback input of the first-stage amplifier. Where Gm1 is the transconductance of the first-stage amplifier (i.e., comparator output module 1), Gm2 represents the input-to-output transconductance gain of the second-stage operational amplifier (i.e., buffer drive module 2), Gm3 represents the transconductance gain of the PMOS transistor in the first compensation module 3 (i.e., pseudo-ESR compensation structure), GM4 represents the transconductance gain of the current buffer, Gmp represents the transconductance gain of the MOS transistor in the power switch module 4, R1 is the output impedance of the first-stage amplifier, C1 is the total capacitance at the output of the first-stage amplifier, Rp is the output impedance of the second-stage amplifier, Cp is the total capacitance at the output of the second-stage amplifier, Cm1 and Rm1 are the Miller compensation capacitor and resistor connected across the line between the first-stage amplifier and the second-stage amplifier, respectively; Cf and Req represent the compensation capacitor and resistor in the pseudo-ESR compensation structure, and Cm2 represents the capacitance connected between the LDO output and the gate of the load MOS transistor of the first-stage amplifier, which is connected back to the output of the first-stage amplifier through the load transistor of the first-stage amplifier. Figure 4 The first capacitor CL in the middle is equivalent to Figure 2 The first capacitor CL in the middle, Figure 4 RL in Figure 2 Given the second resistor RL, the zero-pole formula of the circuit can be obtained as follows: For a phase margin PM ≥ 45 degrees, only two zeros of the loop are required. and To eliminate the two poles other than the principal pole. Furthermore, to minimize the fourth pole... The impact can then be placed in relation to At a relatively high frequency, maintain a reasonable distance, and place it outside the loop bandwidth.

[0028] Light load / heavy load analysis: The negative feedback established to regulate the output voltage results in a negative loop gain. Furthermore, the numerator indicates the presence of an LHP zero, while the third-order polynomial in the denominator signifies three poles in the system, and two zeros in the entire loop. Therefore, a phase margin PM ≥ 45 degrees can be achieved simply by arranging the positions of the zeros and poles appropriately. According to equations 7 to 9 in the table above, the position of the P2 pole will vary under different load currents Io.

[0029] Therefore, the loop gain transfer function should be studied for different load current conditions. When the load current is lightly loaded or lightly polarized, The dominant pole moves towards the origin, and the equivalent impedance... Increase, zero point Also followed Movement. When the load is heavy, the equivalent impedance decreases, and the zero point also follows and moves away from the origin. This is the main pole. Among them, the circuit design ensures that: 10 <P4. Thus, PM≥45 degrees is achieved.

[0030] In one embodiment, the LDO linear voltage regulator circuit further includes: A load voltage sampling terminal for outputting the load voltage; A second compensation module 6. The input end of the second compensation module 6 is electrically connected to the load voltage sampling terminal, and the output end of the second compensation module 6 is electrically connected to the output end of the comparison output module 1. The second compensation module 6 is used to generate a second compensation signal according to the received load voltage magnitude to compensate the error signal and then output it to the buffer driving module 2.

[0031] In this embodiment, the load voltage sampling terminal can be composed of a high-precision and low-noise operational amplifier. The non-inverting input terminal of this operational amplifier is connected to the load output end, and the inverting input terminal is grounded through a feedback resistor to form a negative feedback module, thereby stabilizing the output load voltage. The second compensation module 6 is specifically a zero-pole compensation circuit, which includes an RC compensation network composed of multiple resistors and capacitors corresponding to the number of resistors, and is used to adjust the phase response of the circuit, reduce the oscillation tendency of the circuit, and dynamically adjust the positions of its zero and poles by adjusting the values of different numbers of resistors and capacitors to generate a second compensation signal, ensuring that a good phase margin can be maintained even under changing load conditions, so as to keep the output voltage stable under different load conditions. In addition, the design of the second compensation module 6 allows the circuit to quickly adjust during the transient response period and reduce the fluctuation of the output voltage. The load voltage sampling terminal accurately samples the voltage at the load end, ensuring that the second compensation module 6 can dynamically adjust the compensation signal according to the actual load voltage, further improving the adaptability and stability of the circuit.

[0032] Please refer to Figure 3 and Figure 6 For further details, the second compensation module 6 includes: The fifth PMOS transistor MP4, the sixth PMOS transistor MP5, the seventh PMOS transistor MP6, the eighth PMOS transistor MP7, the ninth PMOS transistor MP8, the tenth PMOS transistor MP9, the eleventh PMOS transistor MP10, the twelfth PMOS transistor MP11, the fourth resistor R3, the fifth resistor R4, the sixth resistor R5, the seventh resistor R6; The gates of the fifth PMOS transistor MP4, the sixth PMOS transistor MP5, the seventh PMOS transistor MP6, and the eighth PMOS transistor MP7 are all electrically connected to the output terminal of the comparator output module 1. The drain and source of the fifth PMOS transistor MP4 are electrically connected to the first terminal of the fourth resistor R3. The drain and source of the sixth PMOS transistor MP5 are electrically connected to the first terminal of the fifth resistor R4. The drain and source of the seventh PMOS transistor MP6 are electrically connected to the first terminal of the sixth resistor R5. The drain and source of the eighth PMOS transistor MP7 are electrically connected to the first terminal of the seventh resistor R6. The second terminal of the fourth resistor R3 is electrically connected to the drain of the ninth PMOS transistor MP8. The second end of the fifth resistor R4 is electrically connected to the drain of the tenth PMOS transistor MP9, the second end of the sixth resistor R5 is electrically connected to the drain of the eleventh PMOS transistor MP10, the second end of the seventh resistor R6 is electrically connected to the drain of the twelfth PMOS transistor MP11, the gates of the ninth PMOS transistor MP8, the tenth PMOS transistor MP9, the eleventh PMOS transistor MP10, and the twelfth PMOS transistor MP11 are all electrically connected to an external bias voltage source, and the sources of the ninth PMOS transistor MP8, the tenth PMOS transistor MP9, the eleventh PMOS transistor MP10, and the twelfth PMOS transistor MP11 are all grounded.

[0033] In this embodiment, the fifth PMOS transistor MP4, the sixth PMOS transistor MP5, the seventh PMOS transistor MP6, and the eighth PMOS transistor MP7 are all connected in parallel using diodes on the line between the comparator output module 1 and the buffer drive module 2. The drain and source of the fifth PMOS transistor MP4 are electrically connected to the first end of the fourth resistor R3. The drain and source of the sixth PMOS transistor MP5 are electrically connected to the first end of the fifth resistor R4. The drain and source of the seventh PMOS transistor MP6 are electrically connected to the first end of the sixth resistor R5. The drain and source of the eighth PMOS transistor MP7 are electrically connected to the first end of the seventh resistor R6. The second end of the fourth resistor R3 is electrically connected to the drain of the ninth PMOS transistor MP8. The second end of the fifth resistor R4 is electrically connected to the drain of the tenth PMOS transistor MP9. The second end of the sixth resistor R5 is electrically connected to the drain of the eleventh PMOS transistor MP10. The second end of the seventh resistor R6 is electrically connected to the drain of the twelfth PMOS transistor MP11. in, Figure 6 for Figure 3 The circuit diagram for equivalent four zero-pole pairs is shown. This circuit diagram has four zero-pole pairs, and the fifth PMOS transistor MP4 is equivalent to... Figure 6The capacitor C1 and the sixth PMOS transistor MP5 are equivalent to Figure 6 The capacitor C2 and the seventh PMOS transistor MP6 are equivalent to Figure 6 The capacitor C3 and the eighth PMOS transistor MP7 are equivalent to Figure 6 The capacitor C4, the ninth PMOS transistor MP8, and the fourth resistor R3 are both equivalent to the resistance R7 within the four zero-pole pair. The ninth PMOS transistor MP8 and the fourth resistor R3 are both equivalent to... Figure 6 The resistor R7 inside the zero-pole pair of the fourth PMOS transistor, the tenth PMOS transistor MP9, and the fifth resistor R4 are equivalent to Figure 6 The resistor R8 inside the zero pole pair of the middle four, the eleventh PMOS transistor MP10 and the sixth resistor R5 are equivalent to Figure 6 The resistor R9 inside the zero-pole pair of the fourth stage, the twelfth PMOS transistor MP11, and the seventh resistor R6 are equivalent to Figure 6 The resistor R10 inside the zero-pole pair in the middle is Ro. Figure 6 The zero-pole-zero compensation circuit has zero output impedance. When the gates of the ninth PMOS transistor MP8, the tenth PMOS transistor MP9, the eleventh PMOS transistor MP10, and the twelfth PMOS transistor MP11 are all electrically connected to the external bias voltage source, the voltage output from the external bias voltage source causes the gates of these four MOS transistors to operate in the subthreshold region, and the output resistance is much greater than that in the saturation region. Therefore, it is impossible to push the poles of the comparator output module 1 to a higher frequency. If the external bias voltage source is set as a reference point for the change of load current, the load current in the LDO linear regulator circuit can be indirectly adjusted by adjusting the external bias voltage. Therefore, the second compensation module 6 uses four pairs of zero-pole pairs with relatively fixed distances to minimize the phase margin attenuation at the output of the comparator output module 1, so it can track the change of load current and achieve dynamic compensation.

[0034] Furthermore, the LDO linear regulator circuit also includes: The first slope enhancer 7 is electrically connected to the reference terminal of the comparison output module 1. The first slope enhancer 7 is used to output a first slope signal to adjust the slope of the reference voltage and the feedback voltage, so as to improve the transient response of the comparison output module 1 and reduce the overshoot or undershoot of the error signal.

[0035] In this embodiment, the first slope enhancer 7 can be composed of operational amplifiers, resistors, capacitors, and other components. By reasonably designing the circuit parameters, the rise and fall rates of the output slope signal can be precisely controlled. When the input voltage or load current changes, the first slope enhancer 7 can quickly adjust the slope of the reference voltage and the feedback voltage, so that the comparison output module 1 can respond to these changes more quickly. This improves the transient performance of the LDO linear regulator circuit. At the same time, by reducing the overshoot or undershoot of the error signal, the stability of the output voltage can be further improved.

[0036] In one embodiment, the LDO linear regulator circuit further includes: The second slope enhancer 8 is electrically connected to the reference terminal of the buffer drive module 2. The second slope enhancer 8 is used to output a second slope signal to adjust the slope of the error signal, so as to improve the transient response of the buffer drive module 2 and reduce the overshoot or undershoot of the drive signal.

[0037] In this embodiment, the second slope enhancer 8 can also be composed of operational amplifiers, resistors, and capacitors. By precisely designing the circuit parameters, the second slope enhancer 8 can output a second slope signal with an appropriate slope, which is used to adjust the slope of the error signal. When the input voltage or load current changes, the second slope enhancer 8 quickly adjusts the slope of the error signal, enabling the buffer drive module 2 to respond to these changes more quickly, thereby improving the transient performance of the LDO linear regulator circuit. Simultaneously, by reducing the overshoot or undershoot of the drive signal, the ripple and stability of the output voltage can be further improved. This design allows the LDO linear regulator circuit to maintain excellent performance under various load conditions.

[0038] In one embodiment, the LDO linear regulator circuit further includes: A current buffer 9 is disposed between the lines of the comparison output module 1 and the buffer drive module 2. The current buffer 9 is used to receive the error signal and, when the current of the error signal exceeds a preset value, limit the current of the error signal and output it to the buffer drive module 2.

[0039] In this example, by setting a current buffer 9 between the comparison output module 1 and the buffer drive module 2, excessive error signal current can be effectively prevented from damaging the buffer drive module 2. When the error signal current increases abnormally, the current buffer 9 can respond quickly, limiting the current to a safe range, and then transmit the adjusted error signal to the buffer drive module 2. In this way, not only can the buffer drive module 2 be protected from the impact of large current, but the accurate transmission of the error signal can also be ensured, thereby maintaining the stable operation of the LDO linear regulator circuit. In addition, the introduction of the current buffer 9 also helps to improve the circuit's anti-interference capability, enabling the LDO linear regulator circuit to maintain excellent performance in complex and variable electromagnetic environments.

[0040] This utility model also proposes an LDO linear regulator chip, which includes the above-mentioned LDO linear regulator circuit. The specific structure of the LDO linear regulator circuit is as described in the above embodiments. Since this LDO linear regulator chip adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0041] This utility model also proposes an LDO linear voltage regulator device, especially an automotive power supply device. The device includes an LDO linear voltage regulator chip, and the specific structure of the LDO linear voltage regulator chip is as described in the above embodiments. Since this automotive power supply device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0042] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent scope of this application.

Claims

1. An LDO linear regulator circuit, characterized in that, The LDO linear regulator circuit includes: Reference power supply terminal, used to output reference voltage; The comparison output module has a first input terminal connected to the reference power supply terminal, a second input terminal for receiving feedback voltage, and is used to compare the received reference voltage and the feedback voltage to generate and output an error signal. A buffer drive module, the input of which is electrically connected to the output of the comparison output module, is used to receive the error signal, amplify and buffer it to generate and output a drive signal. A first compensation module is electrically connected to the output of the buffer drive module. The first input signal terminal of the first compensation module is connected to the load current and the first input signal terminal of the first compensation module is connected to the sampling current. The first compensation module is used to generate a first compensation signal based on the load current and the sampling current to dynamically adjust the amplitude and / or phase of the drive signal. A power switch module, wherein the input terminal of the power switch module is electrically connected to the output terminal of the buffer drive module and the output terminal of the first compensation module, and the power switch module is used to control the on and off of the switch according to the received drive signal, thereby adjusting the voltage output to the load. The feedback module has its first end electrically connected to the input end of the power switch module and the output end of the first compensation module, and its second end electrically connected to the second input end of the comparison output module. It is used to detect the voltage of the load and output the feedback voltage to the comparison output module.

2. The LDO linear regulator circuit as described in claim 1, characterized in that, The LDO linear regulator circuit also includes: Load voltage sampling terminal, used to output load voltage; The second compensation module has its input terminal electrically connected to the load voltage sampling terminal and its output terminal electrically connected to the output terminal of the comparison output module. The second compensation module is used to generate a second compensation signal based on the received load voltage magnitude, so as to compensate the error signal and output it to the buffer drive module.

3. The LDO linear regulator circuit as described in claim 1, characterized in that, The LDO linear regulator circuit also includes: A first slope enhancer is electrically connected to the reference terminal of the comparison output module. The first slope enhancer is used to output a first slope signal to adjust the slope of the reference voltage and the feedback voltage, so as to improve the transient response of the comparison output module and reduce the overshoot or undershoot of the error signal.

4. The LDO linear regulator circuit as described in claim 1, characterized in that, The LDO linear regulator circuit also includes: The second slope enhancer is electrically connected to the reference terminal of the buffer drive module. The second slope enhancer is used to output a second slope signal to adjust the slope of the error signal, so as to improve the transient response of the buffer drive module and reduce the overshoot or undershoot of the drive signal.

5. The LDO linear regulator circuit as described in claim 1, characterized in that, The LDO linear regulator circuit also includes: A current buffer is provided between the comparison output module and the buffer drive module. The current buffer is used to receive the error signal and, when the current of the error signal exceeds a preset value, limit the current of the error signal and output it to the buffer drive module.

6. The LDO linear regulator circuit as described in claim 1, characterized in that, The first compensation module includes: The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP, the thirteenth PMOS transistor MO, the first NMOS transistor MN1, the first resistor R1, the second resistor RL, the third resistor RZ, the first capacitor CL, and the second capacitor Cc; The source of the third PMOS transistor MP3 is electrically connected to the drain of the thirteenth PMOS transistor MO, the source of the first PMOS transistor MP1, the source of the second PMOS transistor MP2, the first terminal of the third resistor RZ, and the first terminal of the second capacitor Cc. The gate of the thirteenth PMOS transistor MO is connected to the load current. The source of the thirteenth PMOS transistor MO is electrically connected to the source of the fourth PMOS transistor MP. The gate of the fourth PMOS transistor MP is connected to the sampling current. The gate of the third PMOS transistor MP3 is electrically connected to the gate of the first PMOS transistor MP1 and the drain of the third PMOS transistor MP3. The drain of the third PMOS transistor MP3 is also electrically connected to the drain of the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 is connected to an external bias voltage source. The drain of the first PMOS transistor MP1 is electrically connected to the first end of the first resistor R1. The second end of the first resistor R1 is electrically connected to the gate and drain of the second PMOS transistor MP2, the second end of the third resistor RZ, the second end of the second capacitor Cc, the first end of the second resistor RL, the first end of the first capacitor CL, and the feedback module. The second end of the first capacitor CL, the first end of the second resistor RL, and the source of the first NMOS transistor MN1 are grounded.

7. The LDO linear regulator circuit as described in claim 2, characterized in that, The second compensation module includes: Fifth PMOS transistor MP4, sixth PMOS transistor MP5, seventh PMOS transistor MP6, eighth PMOS transistor MP7, ninth PMOS transistor MP8, tenth PMOS transistor MP9, eleventh PMOS transistor MP10, twelfth PMOS transistor MP11, fourth resistor R3, fifth resistor R4, sixth resistor R5, seventh resistor R6; The gates of the fifth PMOS transistor MP4, the sixth PMOS transistor MP5, the seventh PMOS transistor MP6, and the eighth PMOS transistor MP7 are all electrically connected to the output terminal of the comparator output module. The drain and source of the fifth PMOS transistor MP4 are electrically connected to the first terminal of the fourth resistor R3. The drain and source of the sixth PMOS transistor MP5 are electrically connected to the first terminal of the fifth resistor R4. The drain and source of the seventh PMOS transistor MP6 are electrically connected to the first terminal of the sixth resistor R5. The drain and source of the eighth PMOS transistor MP7 are electrically connected to the first terminal of the seventh resistor R6. The second terminal of the fourth resistor R3 is electrically connected to the drain of the ninth PMOS transistor MP8. The second end of the fifth resistor R4 is electrically connected to the drain of the tenth PMOS transistor MP9, the second end of the sixth resistor R5 is electrically connected to the drain of the eleventh PMOS transistor MP10, the second end of the seventh resistor R6 is electrically connected to the drain of the twelfth PMOS transistor MP11, the gates of the ninth PMOS transistor MP8, the tenth PMOS transistor MP9, the eleventh PMOS transistor MP10, and the twelfth PMOS transistor MP11 are all electrically connected to an external bias voltage source, and the sources of the ninth PMOS transistor MP8, the tenth PMOS transistor MP9, the eleventh PMOS transistor MP10, and the twelfth PMOS transistor MP11 are all grounded.

8. The LDO linear regulator circuit as described in claim 1, characterized in that, The feedback module includes: Ninth resistor RF1 and tenth resistor RF2; The first end of the ninth resistor RF1 is electrically connected to the input end of the power switch module and the output end of the first compensation module. The second end of the ninth resistor RF1 is electrically connected to the first end of the tenth resistor RF2. The second end of the tenth resistor RF2 is electrically connected to the first input end of the comparison output module.

9. An LDO linear regulator chip, characterized in that, The LDO linear regulator chip includes an LDO linear regulator circuit as described in any one of claims 1 to 8.

10. An LDO linear voltage regulator, characterized in that, The LDO linear regulator device includes the LDO linear regulator chip as described in claim 9.

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