Capacitive touch chip capacitor voltage regulating circuit

Abstract

The utility model provides a kind of capacitive touch chip capacitor voltage regulating circuit, comprising: touch chip, including 24 pins, each pin corresponds 1 scanning channel, wherein X axis 16 channels, Y axis 8 channels;Wherein, each channel of the X axis is connected with one capacitor in parallel, one end of each capacitor is connected with scanning channel, the other end is connected to the drain of first MOS tube, the source of first MOS tube is grounded, and the gate of first MOS tube is connected with first external control voltage.The utility model has the advantages that when self-capacitance function needs to reduce voltage, the parallel capacitor on channel can play the role of signal conditioning anti-interference well;Increase a series resistance between each channel and sensor, which can play the role of protection well, avoid the phenomenon of signal overshoot caused by excessive instantaneous current, limit the circuit during electrostatic discharge or voltage transient, and protect the sensitive input pin of touch chip.

Description

Technical Field

[0001] This utility model relates to the field of voltage control circuit technology, specifically to a capacitor voltage regulation circuit for a capacitive touch chip. Background Technology

[0002] Touchscreen scanning methods are divided into two types: self-capacitance and mutual capacitance. Self-capacitance refers to the capacitance formed between a single touch electrode and ground (or a reference plane). When a finger approaches an electrode, the finger, as a conductor, forms an additional capacitance with the electrode (increased capacitance to ground). Touch control is achieved by detecting this change.

[0003] Mutual capacitance refers to the coupling capacitance formed between two cross electrodes (driving electrode Tx and receiving electrode Rx).

[0004] In existing touchscreen control circuits, the touch chip is directly connected to the touch sensor. In high-voltage chip solutions, the output voltage of the touch pin is constant, and the high voltage has no effect on the performance under mutual capacitance conditions. Therefore, signal interference is easily generated, and excessive current can lead to signal overshoot. Utility Model Content

[0005] The objective of this utility model is achieved through the following technical solution.

[0006] Specifically, this utility model provides a capacitor voltage regulation circuit for a capacitive touch chip, comprising:

[0007] The touch chip includes 24 pins, each corresponding to one scanning channel, with 16 channels on the X-axis and 8 channels on the Y-axis; among which,

[0008] Each channel of the X-axis is connected in parallel with a capacitor. One end of each capacitor is connected to the scanning channel, and the other end is connected to the drain of the first MOS transistor. The source of the first MOS transistor is grounded, and the gate of the first MOS transistor is connected to the first external control voltage.

[0009] Furthermore, the first MOSFET is an N-channel enhancement-mode MOSFET.

[0010] Furthermore, when the gate voltage of the first MOSFET is greater than the MOSFET's turn-on voltage, the MOSFET is turned on, the parallel capacitors on the 16 channels of the X-axis are activated, and the voltages of the 16 channels of the X-axis are uniformly pulled low; when the gate voltage of the first MOSFET is less than or equal to the MOSFET's turn-on voltage, the MOSFET is turned off, the parallel capacitors on the 16 channels of the X-axis are left floating, and the voltages of the 16 channels of the X-axis are uniformly at a high voltage.

[0011] Furthermore, the capacitive touch chip capacitor voltage regulation circuit further includes three test points TP1, TP3, and TP5, wherein TP1 tests the voltage of the common terminal of the parallel capacitors on the 16 channels of the X-axis, and TP3 and TP5 are the voltage test points of the first channel X1 at the near end and the sixteenth channel X16 at the far end of the X-axis, respectively.

[0012] Furthermore, each channel of the Y-axis is connected in parallel with a capacitor. One end of each capacitor is connected to the scanning channel, and the other end is connected to the drain of the second MOS transistor. The source of the second MOS transistor is grounded, and the gate of the second MOS transistor is connected to the second external control voltage.

[0013] Furthermore, the second MOSFET is an N-channel enhancement-mode MOSFET.

[0014] Furthermore, when the gate voltage of the second MOSFET is greater than the MOSFET's turn-on voltage, the MOSFET is turned on, the parallel capacitors on the eight Y-axis channels are activated, and the voltages of the eight Y-axis channels are uniformly pulled low; when the gate voltage of the second MOSFET is less than or equal to the MOSFET's turn-on voltage, the MOSFET is turned off, the parallel capacitors on the eight Y-axis channels are left floating, and the voltages of the eight Y-axis channels are uniformly at a high voltage.

[0015] Furthermore, the capacitive touch chip capacitor voltage regulation circuit further includes three test points TP2, TP4, and TP6. TP2 tests the voltage of the common terminal of the parallel capacitors on the eight channels of the Y-axis, while TP4 and TP6 are the voltage test points for the first channel Y8 at the near end and the sixteenth channel Y1 at the far end of the Y-axis, respectively.

[0016] The advantages of this invention are as follows: when the self-capacitance function needs to reduce the voltage, the parallel capacitor on the channel can effectively condition the signal and resist interference; adding a series resistor between each channel and the sensor can effectively protect the circuit from excessive instantaneous current that could cause signal overshoot, limit the circuit during electrostatic discharge or voltage transients, and protect the sensitive input pins of the touch chip. Attached Figure Description

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0018] Appendix Figure 1 A capacitor voltage regulation circuit diagram of a capacitive touch chip according to an embodiment of the present invention is shown. Detailed Implementation

[0019] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0020] like Figure 1 As shown, according to an embodiment of this utility model, a capacitor voltage regulation circuit for a capacitive touch chip is proposed. Figure 1 The lower part is the touch chip, and the upper part includes 24 pins, each pin corresponding to one channel, including 16 channels on the X-axis (X1-X16) and 8 channels on the Y-axis (Y1-Y8).

[0021] This invention connects a capacitor (C1-C16) in parallel to each channel of the X-axis (X1-X16). One end of the capacitor is connected to the scanning channel, and the other end is connected to the drain of an N-channel enhancement-mode MOSFET Q1. The source of Q1 is grounded. When the gate voltage of Q1 (external control voltage PB1) is greater than the MOSFET's turn-on voltage, the MOSFET is turned on, and the parallel capacitors C1-C16 operate, uniformly pulling down the voltage of scanning channels X1-X16. When the gate voltage of Q1 is less than the MOSFET's turn-on voltage, the MOSFET is turned off, the parallel capacitors C1-C16 are left floating, and the voltage of scanning channels X1-X16 is uniformly high.

[0022] TP1, TP3, and TP5 are test points. TP1 tests the voltage at the common terminal of C1-C16. TP3 and TP5 are the voltage test points at the near end (X1) and far end (X16) of the sensor, respectively.

[0023] The same applies to C17-C24 and Q2 on the Y-axis. Each channel (Y1-Y8) on the Y-axis has a capacitor (C17-C24) connected in parallel. One end of the capacitor is connected to the scan channel, and the other end is connected to the drain of the N-channel enhancement-mode MOSFET Q2. The source of Q2 is grounded. When the gate voltage of Q2 (external control voltage PB2) is greater than the MOSFET's turn-on voltage, the MOSFET turns on, and the parallel capacitors C17-C24 operate, pulling the voltages of scan channels Y1-Y8 uniformly low. When the gate voltage of Q2 does not reach the MOSFET's turn-on voltage, the MOSFET turns off, the parallel capacitors C17-C24 are left floating, and the voltages of scan channels Y1-Y8 are uniformly high.

[0024] TP2, TP4, and TP6 are test points. TP2 tests the voltage at the common terminal of C17-C24. TP4 and TP6 are the voltage test points at the near end (Y8) and far end (Y1) of the sensor, respectively.

[0025] The above technical solutions enable free switching between high and low voltage in the scanning channel, simultaneously meeting the requirements of self-capacitance and mutual capacity.

[0026] The X and Y axes of a touchscreen need to send and receive pulses during operation. In high-voltage solutions, the pulse voltage is relatively high, which can easily damage the pins of the touch chip. Adding a series resistor between each channel and the sensor can effectively protect the touchscreen, prevent excessive instantaneous current from causing signal overshoot, limit the circuit during electrostatic discharge or voltage transients, and protect the sensitive input pins of the touchscreen chip.

[0027] The resistance value should be selected from tens to hundreds of ohms. Too high a value will excessively increase the channel impedance, reduce the signal strength, and affect the scanning frequency. Too low a value will result in the loss of protection.

[0028] The resistors should be placed as close as possible to the touch chip pins to reduce parasitic effects introduced by the traces.

[0029] The above description is merely a preferred embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A capacitive touch chip capacitor voltage regulating circuit, characterized in that, include: The touch chip includes 24 pins, each corresponding to one scanning channel, with 16 channels on the X-axis and 8 channels on the Y-axis; among which, Each channel of the X-axis is connected in parallel with a capacitor. One end of each capacitor is connected to the scanning channel, and the other end is connected to the drain of the first MOS transistor. The source of the first MOS transistor is grounded, and the gate of the first MOS transistor is connected to the first external control voltage.

2. The capacitive voltage regulation circuit for a capacitive touch chip according to claim 1, characterized in that, The first MOSFET is an N-channel enhancement-mode MOSFET.

3. The capacitive voltage regulation circuit for a capacitive touch chip according to claim 1, characterized in that, When the gate voltage of the first MOSFET is greater than the MOSFET's turn-on voltage, the MOSFET is turned on, and the parallel capacitors on the 16 channels of the X-axis are activated, pulling the voltage of all 16 channels of the X-axis down. When the gate voltage of the first MOSFET is less than or equal to the MOSFET's turn-on voltage, the MOSFET is turned off, the parallel capacitors on the 16 channels of the X-axis are left floating, and the voltage of all 16 channels of the X-axis is at a high voltage.

4. A capacitive touch chip capacitor voltage regulation circuit according to any one of claims 1-3, characterized in that, The capacitive touch chip capacitor voltage regulation circuit further includes three test points TP1, TP3, and TP5. TP1 tests the voltage of the common terminal of the parallel capacitors on the 16 channels of the X-axis. TP3 and TP5 are the voltage test points of the first channel X1 at the near end and the sixteenth channel X16 at the far end of the X-axis, respectively.

5. The capacitive voltage regulation circuit for a capacitive touch chip according to claim 1, characterized in that, Each channel of the Y-axis is connected in parallel with a capacitor. One end of each capacitor is connected to the scanning channel, and the other end is connected to the drain of the second MOS transistor. The source of the second MOS transistor is grounded, and the gate of the second MOS transistor is connected to the second external control voltage.

6. The capacitive voltage regulation circuit for a capacitive touch chip according to claim 5, characterized in that, The second MOSFET is an N-channel enhancement-mode MOSFET.

7. The capacitive voltage regulation circuit for a capacitive touch chip according to claim 5, characterized in that, When the gate voltage of the second MOSFET is greater than the MOSFET's turn-on voltage, the MOSFET is turned on, the parallel capacitors on the eight Y-axis channels are activated, and the voltages of the eight Y-axis channels are uniformly pulled low; when the gate voltage of the second MOSFET is less than or equal to the MOSFET's turn-on voltage, the MOSFET is turned off, the parallel capacitors on the eight Y-axis channels are left floating, and the voltages of the eight Y-axis channels are uniformly at a high voltage.

8. A capacitive touch chip capacitor voltage regulation circuit according to any one of claims 5-7, characterized in that, The capacitive touch chip capacitor voltage regulation circuit further includes three test points TP2, TP4, and TP6. TP2 tests the voltage of the common terminal of the parallel capacitors on the eight channels of the Y-axis. TP4 and TP6 are the voltage test points of the first channel Y8 at the near end and the sixteenth channel Y1 at the far end of the Y-axis, respectively.

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