A fast bypass switching circuit based on PCIE expansion card

Abstract

The utility model relates to the technical field of board card design, concretely relates to a kind of fast BYPASS switching circuit based on PCIE extension network card, comprising: power detection module, PCIE extension network card and MCU control module;The input end of power detection module is connected system power supply, for sampling and comparing to system power voltage;The output end of power detection module is connected to PCIE extension network card, and MCU control module signal input pin is connected to the signal pin of PCIE slot;First output pin and second output pin are provided on MCU control module, and first output pin and second output pin are used to connect and control the coil of relay, to switch network BYPASS state.Detect system power voltage directly by power detection module, once system voltage drops to below threshold, the output level of this module will immediately jump, and output detection signal to the specified pin of PCIE slot, and the signal input of MCU module also directly comes from the standard signal of PCIE slot, and relay is directly driven by the GPIO pin of MCU.

Description

Technical Field

[0001] This utility model relates to the field of circuit board design technology, specifically to a fast BYPASS switching circuit based on a PCIe expansion network card. Background Technology

[0002] In fields such as network communication, industrial control, and data transmission, the BYPASS function is one of the key technologies to ensure the continuous and stable operation of a system. Its core function is to automatically or manually switch the signal path to a bypass path when the main device (such as a network interface card, gateway, or data processing module) malfunctions, experiences a power outage, or requires maintenance, thus avoiding signal transmission interruption and ensuring normal data interaction with downstream devices. Currently, the mainstream technical solution for implementing the BYPASS function in the industry involves programming an onboard MCU (microcontroller unit) combined with complex logic circuits to construct a control system, and relying on the power EN (enable) signal of the extended network interface card's power integrated chip to switch the signal path from the main path to the BYPASS path.

[0003] Specifically, the implementation logic of this existing technology is as follows: First, a specific control program is written through the onboard MCU to define the triggering conditions (such as master device fault detection signals, external control commands, etc.) and execution flow of the BYPASS function; second, a complex logic circuit composed of logic gate circuits, timing control circuits, etc., is used to convert the control signal output by the MCU into a drive signal that meets the requirements of the power integrated chip; finally, when the BYPASS switching triggering condition is met, the control signal acts on the power EN pin of the extended network card power integrated chip, and the power supply to the master device is cut off by turning off the EN signal, thereby triggering the path switching and allowing the signal to be transmitted through the BYPASS path.

[0004] However, after long-term practical application verification, the above-mentioned BYPASS function implementation scheme based on onboard MCU programming, complex logic circuits, and power EN signal shutdown has the following significant technical defects, making it difficult to meet the application requirements of high reliability and low latency scenarios:

[0005] Significant switching delays and poor consistency: This solution relies on the power EN signal to turn off for switching. However, the main equipment's power supply circuit typically contains capacitive components such as filter capacitors and energy storage capacitors. When the power EN signal is turned off, these capacitive components need to discharge through the circuit to a specific threshold before the main equipment can be completely powered off and release the signal path, completing the BYPASS switch. However, in practical applications, the discharge time of capacitive components is affected by various factors such as capacitor capacitance deviation, circuit equivalent resistance fluctuations, and ambient temperature changes. This leads to significant differences in capacitor discharge times between different devices or even the same device under different operating conditions, resulting in inconsistent BYPASS switching delays. The longest delay can reach hundreds of milliseconds, failing to meet the needs of scenarios such as industrial control and real-time data transmission that are sensitive to switching delays.

[0006] The BYPASS mode response suffers from low reliability and is at risk of failure. Under certain extreme conditions, such as abnormally large capacitive component capacitance, abnormally high equivalent circuit resistance, or increased discharge circuit impedance due to parasitic inductance in the main equipment power supply circuit, the discharge time of capacitive components can be significantly prolonged, even exceeding the system-set BYPASS switching timeout threshold. In this case, the main equipment cannot power off and release the path in time, the BYPASS path cannot be properly connected, resulting in BYPASS mode response failure, signal transmission interruption, and severely impacting the normal operation of downstream equipment. Furthermore, the MCU programming logic and complex logic circuits in this solution require extremely high precision in their coordination. If there are logic flaws in the programming (such as incorrect trigger condition judgment) or problems such as soldering defects or component aging in the logic circuit, the reliability of the BYPASS mode response will be further reduced, increasing the probability of failure.

[0007] The system suffers from low overall reliability and high maintenance complexity. On the one hand, the solution involves multiple core components such as onboard MCU, complex logic circuits, and power supply integrated chips. The signal interaction links between these components are relatively long. Failure of any component (such as MCU crash, damage to logic circuit components, or failure of the EN pin of the power supply integrated chip) will cause abnormal BYPASS function, thereby reducing the overall reliability of the system. On the other hand, since the solution includes both software programming (MCU program) and hardware circuits (logic circuits and power supply loops), when the BYPASS function fails, maintenance personnel need to simultaneously check for loopholes in the software logic and damage to the hardware circuits. The troubleshooting process requires the use of professional programming tools and circuit testing equipment, and fault location is difficult (such as difficulty in distinguishing between abnormal capacitor discharge and switching failure caused by MCU logic error). This results in long maintenance cycles, high costs, and significantly higher maintenance complexity than single hardware or software implementation solutions.

[0008] In summary, existing BYPASS functionality implementation schemes based on onboard MCU programming, complex logic circuits, and power EN signal shutdown have significant shortcomings in terms of switching delay consistency, response reliability, and system maintenance convenience. A new technical solution is urgently needed to solve these problems and improve the performance and system applicability of the BYPASS function. Utility Model Content

[0009] In order to overcome the shortcomings of the existing technology, this utility model provides a fast BYPASS switching circuit based on a PCIe expansion network card, characterized in that it includes: a power detection module, a PCIe expansion network card and an MCU control module;

[0010] The input terminal of the power detection module is connected to the system power supply and is used to sample and compare the system power supply voltage.

[0011] The output of the power detection module is connected to the PCIe expansion network card, and the signal input pin of the MCU control module is connected to the signal pin of the PCIe slot.

[0012] The MCU control module is provided with a first output pin and a second output pin. The first output pin and the second output pin are used to connect to and control the coil of the relay to switch the network BYPASS state.

[0013] The power detection module described in the above technical solution includes an operational amplifier U1A, a voltage divider resistor network, and a level conversion circuit;

[0014] The voltage divider resistor network is composed of a first resistor R1 and a second resistor R3 connected in series. Its high end is connected to the system power supply, its low end is grounded, and its voltage divider midpoint is connected to the positive input terminal of the operational amplifier U1A and grounded through capacitor C1.

[0015] The DC power supply is converted into a reference voltage and connected to the inverting input of the operational amplifier U1A via the third resistor R7 and transistor Q2.

[0016] The output terminal of the operational amplifier U1A is connected to the input terminal of the level conversion circuit, and the output terminal of the level conversion circuit constitutes the output terminal of the power detection module.

[0017] The level conversion circuit described in the above technical solution includes transistor Q1, resistor R2, and a PCIe expansion network card, wherein,

[0018] The gate of transistor Q1 is connected to the output terminal of operational amplifier U1A, the source of transistor Q1 is grounded, and the drain of transistor Q1 is connected to pin B30 of the PCIe expansion network card and connected to the MCU power supply through resistor R2.

[0019] In the above technical solution, the first signal input pin of the MCU control module is connected to the PCIE_RST# signal pin of the PCIE slot; the second signal input pin of the MCU control module is connected to the 3.3V_PWRGD signal pin of the motherboard.

[0020] The MCU control module described in the above technical solution is also equipped with an I2C or SMBus communication interface. The SCL clock line and SDA data line of the communication interface are respectively connected to the MCU power supply through pull-up resistors.

[0021] The beneficial effects of this utility model are:

[0022] ① Extremely fast response speed and high reliability:

[0023] A dedicated hardware power supply detection module (composed of operational amplifiers, voltage divider resistors, and a reference voltage source) directly monitors the system power supply voltage. Once the system voltage drops below a threshold, the module's output level immediately changes. This hardware comparator-based response speed is in the microsecond range, far faster than solutions relying on software polling or capacitor discharge. This completely avoids switching failures caused by capacitor discharge delays, greatly improving system reliability in emergency situations such as abnormal power outages.

[0024] ② Seamless integration with the standard PCIe interface, offering strong versatility:

[0025] The circuit's output is directly connected to the PCIe expansion network card itself, and its detection output signal can be sent to a designated pin of the PCIe slot. The MCU module's signal input also comes directly from the standard signals of the PCIe slot. This design allows the entire BYPASS switching function to be highly integrated onto a standard PCIe network card without modifying the motherboard design, offering excellent compatibility and versatility, and facilitating widespread adoption and use. Attached Figure Description

[0026] Figure 1 This is a block diagram of a fast BYPASS switching circuit based on a PCIE expansion network card, as shown in an embodiment of the present invention.

[0027] Figure 2 This is a schematic diagram illustrating the structure of a power detection module and a PCIe expansion network card according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the structure of an MCU control module shown in an embodiment of the present invention. Detailed Implementation

[0029] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0030] The following will clearly and completely describe the concept, specific structure, and technical effects of this utility model in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of this utility model. Obviously, the described embodiments are only a part of the embodiments of this utility model, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are all within the scope of protection of this utility model. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this utility model can be combined interactively without contradicting each other.

[0031] like Figure 1 As shown, this application provides a fast BYPASS switching circuit based on a PC IE expansion network card, including a power detection module 10, a PC IE expansion network card 20, and an MCU control module 30;

[0032] The input terminal of the power detection module 10 is connected to the system power supply and is used to sample and compare the system power supply voltage.

[0033] The output terminal of the power detection module 10 is connected to the PC IE expansion network card 20, and the signal input pin of the MCU control module is connected to the signal pin of the PC IE slot.

[0034] The MCU control module 30 is provided with a first output pin and a second output pin. The first output pin and the second output pin are used to connect to and control the coil of the relay to switch the network BYPASS state.

[0035] In one possible implementation, such as Figure 2 As shown, the power detection module 10 includes an operational amplifier U1A, a voltage divider resistor network 101, and a level conversion circuit 102;

[0036] The voltage divider resistor network 101 is composed of a first resistor R1 and a second resistor R3 connected in series. Its high end is connected to the system power supply, its low end is grounded, and its voltage divider midpoint is connected to the positive input terminal of the operational amplifier U1A and grounded through capacitor C1.

[0037] The DC power supply is converted into a reference voltage and connected to the inverting input of the operational amplifier U1 A via the third resistor R7 and transistor Q2.

[0038] The output terminal of the operational amplifier U1A is connected to the input terminal of the level conversion circuit 102, and the output terminal of the level conversion circuit 102 constitutes the output terminal of the power detection module 10.

[0039] The 12V system power supply is divided by resistors R1 (32.4KΩ) and R3 (10KΩ) and then input to the positive terminal of operational amplifier U1A. The voltage V after voltage division is... R1 = (R2 + R2R1) * V in .

[0040] The standby power supply (+VDC) provides a 2.5V reference voltage to the reverse terminal through transistor Q2, which is optionally a TL431.

[0041] Optionally, the operational amplifier U1A is an LM358. The output level of U1A is isolated and inverted by the level conversion circuit 102 before being sent to the PC IE expansion network card 20.

[0042] For one possible implementation, please refer to [link / reference]. Figure 2 As shown, the level conversion circuit 102 includes transistor Q1, resistor R2, and a PCIe expansion network card, wherein,

[0043] The gate of transistor Q1 is connected to the output terminal of operational amplifier U1 A, the source of transistor Q1 is grounded, and the drain of transistor Q1 is connected to pin B30 of the PCIe expansion network card and connected to the MCU power supply through resistor R2.

[0044] Optionally, the transistor Q1 is of model number 2N7002.

[0045] In one possible implementation, such as Figure 3 As shown, the first signal input pin of the MCU control module U2 is connected to the PCIE_RST# signal pin of the PCIE slot; the second signal input pin of the MCU control module U2 is connected to the 3.3V_PWRGD signal pin of the motherboard.

[0046] The MCU control module U2 monitors the output level of transistor Q1 through the second input signal pin PC13. A low level indicates normal mode, and a high level switches to BYPASS mode.

[0047] Specifically, when the system output voltage is the normal 12V voltage, the voltage at the positive terminal of the operational amplifier U1 A is >2.5V, and the output is high, causing the transistor Q1 to reverse and output a low level. The MCU control module U2 determines that it is in normal working mode.

[0048] When the system output voltage drops, causing the voltage at the positive terminal of operational amplifier U1 A to be less than 2.5V, the output is low, causing transistor Q1 to invert and output a high level. The MCU control module U2 immediately switches to BYPASS mode.

[0049] Specifically, the switching is achieved by controlling the GPIO pins of the MCU control module U2 to high or low levels. The following is an example using the truth table of the high and low levels of the first output pin GPIO1 A and the second output pin GPIO1 B:

[0050] When the output values ​​of GPIO1 A and GPIO1 B are 00 or 11, that is, both GPIO signals controlling Bypass are low or low, the network state does not change.

[0051] The network bypass state will only change when the output values ​​of GPIO1 A and GPIO1 B are 01 or 10, that is, when the two GPIO signals controlling the bypass are one high and one low.

[0052] The relay coil is connected and controlled via the first and second output pins to switch the network BYPASS state.

[0053] For one possible implementation, please refer to [link / reference]. Figure 2 The MCU control module is also equipped with an I2C or SMBus communication interface. The SCL clock line and SDA data line of the communication interface are respectively connected to the MCU power supply through pull-up resistors.

[0054] Specifically, when the network bypass state changes, it is sent to the MCU control module via the standard I 2C (or SMBus) bus. The MCU control module stores the received data in Memory (for quick MCU reading) and Flash (for data backup after power failure). The data in Memory will be lost after the AC power is disconnected, but the data in Flash will not be lost.

[0055] This invention directly monitors the system power supply voltage using a dedicated hardware power detection module (composed of operational amplifiers, voltage divider resistors, and a reference voltage source). Once the system voltage drops below a threshold, the module's output level immediately changes, and a detection signal is output to a designated pin of the PCIe slot. The MCU module's signal input also comes directly from the standard signals of the PCIe slot, driving the relay directly through the MCU's GPIO pins. This is a physical-level switching, completely independent of the host's operating system and software state. Therefore, even in the most extreme fault scenarios such as system crashes, kernel crashes, or sudden power outages, this circuit can still operate reliably, ensuring that the network link is quickly switched to a BYPASS state physically, thus achieving true hardware-level disaster recovery.

[0056] The above is a detailed description of the preferred embodiments of the present utility model. However, the present utility model is not limited to the described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present utility model. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A PCIE extension card based fast BYPASS switching circuit, characterized in that, include: Power detection module, PCIe expansion network card and MCU control module; The input terminal of the power detection module is connected to the system power supply and is used to sample and compare the system power supply voltage. The output of the power detection module is connected to the PCIe expansion network card, and the signal input pin of the MCU control module is connected to the signal pin of the PCIe slot. The MCU control module is provided with a first output pin and a second output pin. The first output pin and the second output pin are used to connect to and control the coil of the relay to switch the network BYPASS state.

2. The fast BYPASS switching circuit according to claim 1, characterized in that, The power detection module includes an operational amplifier U1A, a voltage divider resistor network, and a level conversion circuit. The voltage divider resistor network is composed of a first resistor R1 and a second resistor R3 connected in series. Its high end is connected to the system power supply, its low end is grounded, and its voltage divider midpoint is connected to the positive input terminal of the operational amplifier U1A and grounded through capacitor C1. The DC power supply is converted into a reference voltage and connected to the inverting input of the operational amplifier U1A via the third resistor R7 and transistor Q2. The output terminal of the operational amplifier U1A is connected to the input terminal of the level conversion circuit, and the output terminal of the level conversion circuit constitutes the output terminal of the power detection module.

3. The fast BYPASS switching circuit according to claim 2, characterized in that, The level conversion circuit includes transistor Q1, resistor R2, and a PCIe expansion network card, wherein... The gate of transistor Q1 is connected to the output terminal of operational amplifier U1A, the source of transistor Q1 is grounded, and the drain of transistor Q1 is connected to pin B30 of the PCIe expansion network card and connected to the MCU power supply through resistor R2.

4. The fast BYPASS switching circuit according to claim 1, characterized in that, The first signal input pin of the MCU control module is connected to the PCIE_RST# signal pin of the PCIE slot; the second signal input pin of the MCU control module is connected to the 3.3V_PWRGD signal pin of the motherboard.

5. The fast BYPASS switching circuit according to claim 1, characterized in that, The MCU control module is also equipped with an I2C or SMBus communication interface. The SCL clock line and SDA data line of the communication interface are respectively connected to the MCU power supply through pull-up resistors.

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