An AI digital human mainboard and an AI digital human device

Abstract

This utility model discloses an AI digital human motherboard and an AI digital human device. By setting up a processor, control components, and connection ports on the motherboard, the display interfaces include an LVDS interface, an eDP interface, an HDMI OUT interface, and a V-BY-ONE interface. The V-BY-ONE interface and the HDMI to V-BY-ONE chip can meet the rendering requirements of highly realistic digital humans. The DP display signal output from the Type-C interface is combined with the Type-C protocol chip to identify the type of externally connected device to determine whether to output a DP signal, which can meet the display applications in multiple scenarios. The motherboard integrates a MIPI CAM interface to realize low-latency image acquisition. The M.2 Key-B and M.2 Key-M interfaces connect to the SSD and 5G module respectively, giving the AI ​​digital human motherboard rich expansion interface resources, improving product integration and interface compatibility.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit motherboard design technology, and in particular relates to an AI digital human motherboard and an AI digital human device. Background Technology

[0002] With the widespread application of AI digital humans in services, entertainment, education, and other fields, existing digital human devices mostly use general-purpose computing motherboards (such as industrial control motherboards or server motherboards) to implement basic functions. These motherboards typically only integrate basic interfaces (such as USB, HDMI, and Ethernet ports) and lack dedicated interface designs for digital human scenarios, which leads to the following problems: 1. Poor interface compatibility: unable to simultaneously support high-resolution displays (such as V-BY-ONE), multi-camera input (MIPI CAM), and professional audio codecs; 2. Insufficient expandability: difficult to connect to 5G modules, large-capacity SSDs, or local AI acceleration cards, restricting real-time interaction and model deployment; 3. Low integration: external expansion boards result in bulky devices, violating the lightweight requirements of digital human devices.

[0003] However, existing technical solutions, such as multi-functional interactive device motherboards based on the ARM architecture, which use an RK3588 processor, integrate basic interfaces (USB 3.0×2, HDMI×1, RJ45 Gigabit Ethernet×1, GPIO×8), and support external M.2 SSDs and 4G modules, lack...

[0004] The V-BY-ONE display interface struggles to drive 8K ultra-high-definition digital human screens. Furthermore, the lack of a dedicated audio codec chip results in an audio sampling rate of ≤48kHz, leading to distorted voice interaction. Additionally, the M.2 interface only supports a single mode (Key-B or Key-M only), preventing simultaneous expansion of 5G modules and NVMe SSDs. Therefore, there is an urgent need for an AI digital human motherboard to address these technical issues. Utility Model Content

[0005] To address the aforementioned issues, this utility model provides an AI digital human motherboard and an AI digital human device, which can solve the problems of poor interface compatibility, insufficient expandability, and bulky device size in the prior art. It features full-scene interface coverage, dual-channel high-speed expansion, and a compact design.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides an AI digital human motherboard, characterized in that the AI ​​digital human motherboard includes a motherboard body and a processor, control components and connection ports all disposed on the motherboard body;

[0008] The control components include an HDMI to V-BY-ONE chip, an audio codec chip, a PICE clock chip, a MIPI to LVDS chip, and a Type-C protocol chip, wherein the audio codec chip is connected to the processor;

[0009] The connection ports include a display interface, a Type-C interface, an M.2 Key-B interface, an M.2 Key-M interface, a MIPI LCD interface, and a MIPI CAM interface. The M.2 Key-B interface, MIPI LCD interface, and MIPI CAM interface are all connected to the processor. The M.2 Key-M interface is connected to the processor via a PCIe clock chip. The display interface includes an LVDS interface, an eDP interface, an HDMI OUT interface, and a V-BY-ONE interface. The LVDS interface, eDP interface, and HDMI OUT interface are all connected to the processor. The V-BY-ONE interface is connected to the processor via an HDMI to V-BY-ONE chip. The Type-C interface for the eDP interface display output is connected to the processor via a Type-C protocol chip. The LVDS interface is connected to the processor via a MIPI to LVDS chip.

[0010] The processor receives the device type identified by the Type-C protocol chip and accesses the connection port. Based on the device type, the processor controls the control component to drive the display interface to output AI digital human information.

[0011] As a preferred embodiment of the above technical solution, the control component further includes an Ethernet gigabit PHY chip and a USB conversion chip, and the connection port further includes an RJ45 interface and a USB interface. The RJ45 interface is connected to the processor through the Ethernet gigabit PHY chip, and the USB interface is connected to the processor through the USB conversion chip.

[0012] As a preferred embodiment of the above technical solution, the USB interface includes a USB 3.0 Type-C interface, a USB 2.0 Type-A interface, a USB 3.0 Type-A interface, and a USB 2.0 pH interface. The USB conversion chip includes a multiplexer, a UART / USB conversion chip, and a USB Hub chip, all of which are connected to the processor. The USB 2.0 Type-A, USB 3.0 Type-A, and USB 3.0 Type-C interfaces are all connected to the USB processor, and the USB 2.0 pH interface is connected to the processor through the USB Hub chip.

[0013] As a preferred embodiment of the above technical solution, the control component further includes memory chips, eMMC chips, MCU chips, and a Wi-Fi module. The connection ports further include a power amplifier interface, a microphone interface, a SATA3.0 interface, and a debug interface. The audio interface and the power amplifier interface are both connected to the processor through an audio codec chip. The memory chips, eMMC chips, MCU chips, Wi-Fi module, debug interface, SATA3.0 interface, and microphone interface are all connected to the processor.

[0014] As a preferred embodiment of the above technical solution, the control component further includes an RS232 conversion chip and an RS485 conversion chip. The connection port further includes a COM interface, an I2C interface, and a microphone interface. The COM interface includes a TTLPH interface, an RS232PH interface, and an RS485PH interface. The RS232PH interface is connected to the processor through the RS232 conversion chip, and the RS485PH interface is connected to the processor through the RS485 conversion chip. The TTLPH interface, the I2C interface, and the microphone interface are all connected to the processor. The I2C interface is used to connect to the touch screen.

[0015] As a preferred embodiment of the above technical solution, the Debug interface includes a chip programming interface, an MCU programming interface, and a debugging interface, all of which are connected to the processor.

[0016] As a preferred embodiment of the above technical solution, the control component further includes a PMIC power management chip, an RTC chip, an I2C to GPIO chip, and a level conversion chip. The connection ports further include a MINIPCI-e interface, a SIM card interface, an IR / ADC / indicator light interface, a GPIO interface, and a TF card interface. The GPIO interface is connected to the processor via the I2C to GPIO chip, the SIM card interface is connected to the MINIPCI-e interface, and the PMIC power management chip, RTC chip, level conversion chip, IR / ADC / indicator light interface, and TF card interface are all connected to the processor.

[0017] As a preferred embodiment of the above technical solution, the AI ​​digital human motherboard further includes a power supply battery, which is used to connect to the RTC chip and supply power to the RTC chip.

[0018] Secondly, this utility model also provides an AI digital human device, which includes a housing and the aforementioned AI digital human motherboard housed within the housing.

[0019] Compared with the prior art, the beneficial effects of this utility model are as follows:

[0020] By incorporating a processor, control components, and connection ports on the motherboard, the display interfaces include LVDS, eDP, HDMIOUT, and V-BY-ONE. The V-BY-ONE interface and HDMI to V-BY-ONE chip can meet the rendering requirements of highly realistic digital humans. The combination of the Type-C interface outputting DP display signals and the Type-C protocol chip identifying the type of externally connected devices determines whether to output DP signals, satisfying display applications in various scenarios. The motherboard integrates a MIPICAM interface for low-latency image acquisition, and the M.2 Key-B and M.2 Key-M interfaces can connect to SSDs and 5G modules respectively. This gives the AI ​​digital human motherboard abundant expansion interface resources, allowing for the design of numerous internal accessories and the connection of a large number of external devices, thus improving product integration and interface compatibility. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the front structure of the AI ​​digital human motherboard proposed in this utility model;

[0022] Figure 2 This is a schematic diagram of the back structure of the AI ​​digital human motherboard proposed in this utility model;

[0023] Figure 3 This is a circuit diagram of the V-BY-ONE interface proposed in this utility model;

[0024] Figure 4 This is a circuit diagram of the MIPI CAM interface proposed in this utility model;

[0025] Figure 5 This is a circuit diagram of the MIPI LCD interface proposed in this utility model;

[0026] Figure 6 This is a circuit diagram of the Type-C interface proposed in this utility model;

[0027] Figure 7 This is a circuit diagram of the M.2 Key-B interface proposed in this utility model;

[0028] Figure 8 This is a circuit diagram of the M.2 Key-M interface proposed in this utility model;

[0029] Figure 9 The circuit diagram is for the high-fidelity audio path proposed in this utility model.

[0030] Figure 10 The circuit diagram for the I2C-CPIO conversion control proposed in this utility model is shown below.

[0031] Figure 11 This is a schematic diagram of the structure of the AI ​​digital human device proposed in this utility model.

[0032] The symbols for the main components are explained below:

[0033] 1-LVDS interface; 2-M.2 Key-M interface; 3-V-BY-ONE interface; 4-HDMI OUT interface; 5-EDP interface; 6-RS485 PH interface; 7 / 8-TTLPH interface; 9 / 10-RS232 PH interface; 11-IR / ADC / indicator light interface; 12-SATA3.0 interface; 13-Amplifier interface; 14-GPIO interface; 15-Microphone interface; 16-USB2.0 PH interface; 17-Audio interface; 18-USB2.0 Type-A interface; 19-USB3.0 Type-A interface; 20-HDMI IN interface; 21-USB3.0 Type-C interface; 22-TF card interface; 23-RJ45 network port; 24-MIPI to LVDS chip; 25-Gigabit Ethernet PHY chip; 26-PMIC power management chip; 27-USB 28-Hub chip; 29-Memory chip; 30-Processor; 31-EMMC chip; 32-PCIe clock chip; 33-Power amplifier chip; 34-Wi-Fi module; 35-Touch screen interface; 36-RS485 converter chip; 37-Debug interface; 38-Audio codec chip; 39-HDMI to V-BY-ONE chip; 40-MCU chip; 41-MIPI C1-e interface; 42-M.2 Key-B interface; 43-MIPI LCD interface; 44-MIPI CAM interface; 45-SIM card interface; 46-RS232 converter chip; 47-I2C to GPIO chip; 48-Level converter chip; 49-RTC chip. Detailed Implementation

[0034] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments.

[0035] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0036] This utility model provides an AI digital human motherboard and an AI digital human device, aiming to solve the problem that existing AI digital human devices cannot meet the interface requirements of internal components due to interface mismatch.

[0037] See Figure 1 and Figure 2 This utility model provides an AI digital human motherboard, characterized in that the AI ​​digital human motherboard includes a motherboard body and a processor, control components and connection ports all disposed on the motherboard body;

[0038] The control components include an HDMI to V-BY-ONE chip, an audio codec chip, a PICE clock chip, a MIPI to LVDS chip, and a Type-C protocol chip, wherein the audio codec chip is connected to the processor;

[0039] The connection ports include a display interface, a Type-C interface, an M.2 Key-B interface, an M.2 Key-M interface, a MIPI LCD interface, and a MIPI CAM interface. The M.2 Key-B interface, MIPI LCD interface, and MIPI CAM interface are all connected to the processor. The M.2 Key-M interface is connected to the processor via a PCIe clock chip. The display interface includes an LVDS interface, an eDP interface, an HDMI OUT interface, and a V-BY-ONE interface. The LVDS interface, eDP interface, and HDMI OUT interface are all connected to the processor. The V-BY-ONE interface is connected to the processor via an HDMI to V-BY-ONE chip. The Type-C interface for the eDP interface display output is connected to the processor via a Type-C protocol chip. The LVDS interface is connected to the processor via a MIPI to LVDS chip.

[0040] The processor receives the device type identified by the Type-C protocol chip and accesses the connection port. Based on the device type, the processor controls the control component to drive the display interface to output AI digital human information.

[0041] In this embodiment, the control component further includes an Ethernet gigabit PHY chip and a USB conversion chip. The connection ports also include an RJ45 interface and a USB interface. The RJ45 interface is connected to the processor via the Ethernet gigabit PHY chip, and the USB interface is connected to the processor via the USB conversion chip. The USB interface includes a USB 3.0 Type-C interface, a USB 2.0 Type-A interface, a USB 3.0 Type-A interface, and a USB 2.0 PH interface. The USB conversion chip includes a multiplexer, a UART / USB conversion chip, and a USB hub chip, all connected to the processor. The USB 2.0 Type-A, USB 3.0 Type-A, and USB 3.0 Type-C interfaces are all connected to the USB processor, and the USB 2.0 PH interface is connected to the processor via the USB hub chip. The control components also include memory chips, eMMC chips, MCU chips, and Wi-Fi modules. The connection ports also include a power amplifier interface, a microphone interface, a SATA3.0 interface, and a debug interface. The audio interface and the power amplifier interface are both connected to the processor through an audio codec chip. The memory chips, eMMC chips, MCU chips, Wi-Fi modules, debug interfaces, SATA3.0 interfaces, and microphone interfaces are all connected to the processor.

[0042] It should be noted that the control component also includes an RS232 conversion chip and an RS485 conversion chip. The connection ports also include a COM interface, an I2C interface, and a microphone interface. The COM interface includes a TTL PH interface, an RS232 PH interface, and an RS485 PH interface. The RS232 PH interface is connected to the processor via the RS232 conversion chip, and the RS485 PH interface is connected to the processor via the RS485 conversion chip. The TTL PH interface, I2C interface, and microphone interface are all connected to the processor. The I2C interface is used to connect to the touchscreen. The debug interface includes a chip programming interface, an MCU programming interface, and a debugging interface. The chip programming interface, MCU programming interface, and debugging interface are all connected to the processor.

[0043] The control components include a PMIC power management chip, an RTC chip, an I2C-to-GPIO chip, and a level conversion chip. The connection ports include a MINIPCI-e interface, a SIM card interface, an IR / ADC / indicator light interface, a GPIO interface, and a TF card interface. The GPIO interface is connected to the processor via the I2C-to-GPIO chip, the SIM card interface is connected to the MINIPCI-e interface, and the PMIC power management chip, RTC chip, level conversion chip, IR / ADC / indicator light interface, and TF card interface are all connected to the processor. The AI ​​digital human motherboard also includes a power supply battery, which is connected to and powers the RTC chip. The AI ​​digital human motherboard includes a motherboard body, a processor with chips and electronic components all located on the motherboard body, control components, and connection ports. It has one RJ45 network port, with an Ethernet gigabit PHY chip electrically connected to the RJ45 port. The RJ45 port is electrically connected to the processor via the Ethernet gigabit PHY chip. The touchscreen interface is an I2C interface, electrically connected to the processor.

[0044] As described above, this utility model proposes an AI digital human motherboard and an AI digital human, aiming to solve the problems of existing AI digital human interfaces being too few and incompatible, inconvenient to use, and supporting too few peripherals. Please refer to... Figure 1 and Figure 2 The AI ​​digital human's motherboard includes a motherboard body and a processor 29, control components, and connection ports all mounted on the motherboard body. The control components include memory chips 28, eMMC chips 30, an Ethernet gigabit PHY chip 25, a USB hub chip 27, a MIPI-to-LVDS chip 24, a PMIC power management chip 26, and an RTC chip 48. The connection ports include a display interface, a touchscreen interface 34, an RJ45 network port 26, USB interfaces 16 / 18 / 19, an audio interface 17, an amplifier interface 13, a hard drive interface 12, and a debug interface 36. The debug interface 36 is electrically connected to the processor 29. The RJ45 network port 23 is electrically connected to the processor 29 via the Ethernet gigabit PHY chip 25. The USB interfaces are electrically connected to the processor 29 via the USB hub chip 27.

[0045] In this embodiment, the AI ​​digital human motherboard can employ a high-performance processor 29, on which a rich array of input / output interfaces, network communication interfaces, and storage interfaces are designed, such as a display interface, a touchscreen interface 34, an RJ45 network port 23, USB interfaces 16 / 18 / 19, an audio interface 17, a power amplifier interface 13, a hard disk interface 12, and a debug interface 36. This provides the AI ​​digital human with abundant interface resources, enabling it to connect to a large number of external devices and meet the needs of real-time interaction and local large-scale model deployment. Moreover, the AI ​​digital human motherboard measures only 155mm*115mm, with a maximum thickness of only 16mm, resulting in a small size and ultra-thin profile for the entire motherboard.

[0046] It should be noted that memory chip 28 is LPDDR5 / LPDDR5X, with a capacity of 8GB or 16GB; eMMC chip 30 has a capacity of 64GB or 128GB. Different levels of memory can be selected according to the device's usage scenarios and needs, fully meeting the requirements of the AI ​​digital human motherboard for various applications in multiple scenarios. Display interfaces include LVDS interface 1, HDMI OUT interface 4, V-BY-ONE interface, and eDP interface 5. eDP interface 5 and HDMI OUT interface 4 are electrically connected to processor 29. V-BY-ONE interface is electrically connected to processor 29 via HDMI to V-BY-ONE chip 38, and LVDS interface 1 is electrically connected to processor 29 via MIPI to LVDS chip 24. The AI ​​digital human motherboard outputs the information required by the device to the monitor connected to eDP interface 5, V-BY-ONE interface 3, and LVDS interface 1.

[0047] Furthermore, the USB interfaces include a USB 3.0 Type-C interface 21, a USB 2.0 Type-A interface 18, a USB 2.0 PH interface 16, and a USB 3.0 Type-A interface 19. The USB 2.0 PH interface 16 is electrically connected to the processor 29 via the USB Hub chip 27, and the USB 3.0 Type-C interface 21, USB 2.0 Type-A interface 18, and USB 3.0 Type-A interface 19 are electrically connected to the processor 29. The USB 3.0 Type-C interface 21, USB 2.0 Type-A port, and USB 3.0 Type-A port enable high-speed read and write operations, easily compatible with and smoothly using common devices such as printers, USB cameras, and fingerprint scanners. The USB 3.0 Type-C interface 21 can also be electrically connected to an external PC interface for data transfer and software upgrades.

[0048] The COM interface includes TTL PH interfaces 7 / 8, RS232 PH interfaces 9 / 10, and RS485 PH interface 6. RS232 PH interfaces 9 / 10 are electrically connected to the processor 29 via RS232 conversion chip 45; RS485 PH interface 6 is electrically connected to the processor 29 via RS485 conversion chip 35; and TTL PH interfaces 7 / 8 are electrically connected to the processor 29. In one embodiment, the two TTL PH interfaces 7 / 8, two RS232 PH interfaces 9 / 10, and one RS485 PH interface 6 enable the forwarding of communication messages and command recognition between the industrial control board and the maintenance terminal. The Debug interface 36 is a debugging interface connected to the processor, and the MCU programming interface is electrically connected to the MCU chip 39; the debugging interface is also electrically connected to the processor 29. Firmware can be programmed into the MCU chip 39 through the MCU programming interface, and the motherboard of the AI ​​digital human can be debugged through the Debug interface 36. The audio interface 17, power amplifier interface 13, and microphone interface 15 are all electrically connected to the processor 29 via the audio codec chip 37. This enables high-resolution, high-quality encoding and decoding, improving audio performance.

[0049] There is one RJ45 network port 23, which is electrically connected to the processor 29 via the corresponding gigabit Ethernet PHY chip 25. The network interface is a gigabit port, supporting 10 / 100 / 1000Mbps networks, and can be used to connect to the network for communication between the maintenance terminal and the maintained object, depending on actual usage needs. The touchscreen interface 34 is an I2C interface. The AI ​​digital human's motherboard connects to an external touchscreen via the I2C interface. The touch signals transmitted by the touchscreen through the I2C interface are received by the processor 29, thereby controlling the AI ​​digital human and enabling real-time interaction between humans and the digital human, improving the interaction level and user experience. Both the SATA 3.0 interface 13 and the M.2 Key-B interface 41 are electrically connected to the processor 29. The M.2 Key-M interface 2 is electrically connected to the processor 29 via a PCIe clock chip. The M.2 Key-B interface 41 supports 5G modules with B-Key PCIE M.2 NGFF interfaces, enabling high-speed 5G internet access; the SATA 3.0 interface 12 supports various SATA hard drives with a maximum transfer rate of 6Gbps / s (750MB / s). The M.2 Key-M interface 2 supports high-speed hard drive expansion with M-Key PCIE M.2 SSDs.

[0050] It's important to note that the M.2 interface is a new interface specification that replaces mSATA. M.2 far surpasses mSATA in both its smaller size and higher transfer performance. The motherboard for the AI ​​digital human also includes a power supply battery, which is electrically connected to and powers the RTC chip 48. The RTC chip 48 uses a high-precision crystal oscillator as its clock source. The additional power supply battery allows the RTC chip 48 to continue operating even when the main power supply is interrupted, thus providing the AI ​​digital human with a precise time reference.

[0051] Specifically, such as Figure 3 As shown, the V-BY-ONE interface uses Advanced Serialization, and its characteristics are as follows:

[0052] Highly serializable: Unlike earlier parallel interfaces (such as RGB / LVDS) that required dozens of wire pairs, V-BY-ONE uses highly optimized serialization technology to integrate and package a large amount of parallel pixel data and related control signals (such as clock, data enable, line synchronization, field synchronization, etc.) and transmit them through a very small number of differential signal pairs.

[0053] No dedicated clock lines: This is a significant feature of V-BY-ONE. It doesn't require a separate clock channel (i.e., no dedicated Clock+ and Clock- signal lines). Instead, it cleverly embeds clock information into the data stream itself. The serializer uses specific encoding rules to ensure sufficient level transitions in the signal during data serialization. These transitions can be extracted by the deserializer using dedicated clock data recovery circuitry and used as a reference clock for receiving data, similar to other high-speed serial buses (such as PCIe and USB).

[0054] Differential signal transmission: Each data channel is actually a pair of twisted pairs, transmitting signals with opposite phases (Data+ and Data-). This differential transmission method has a natural resistance to external noise; common V-BY-ONE HS (high-speed) channel rates can reach 3.0Gbps or even higher (such as 4.0Gbps) per pair, and higher versions support even higher single-channel rates.

[0055] Core Functions and Roles: The main purpose of V-BY-ONE is to efficiently and reliably transmit high-resolution video data and related control signals between video sources (such as motherboards and graphics cards) and displays (such as panels and timing controllers TCON). Its core value lies in solving the bottleneck problems of traditional interfaces (such as parallel LVDS).

[0056] Support for ultra-high resolution and high refresh rate: This is the most important function. V-BY-ONE has a very high data transmission rate per channel (such as 3.0Gbps or even 4.0Gbps per pair according to the V-BY-ONE HS specification), and through multiple channels connected in parallel, it can easily carry 4K (3840x2160), 5K and even 8K (7680x4320) ultra-high-definition resolution signals, while supporting high refresh rates such as 60Hz, 120Hz, and 144Hz.

[0057] Significantly reduces the number of interface wire pairs: Compared to the old LVDS interface, which requires a dozen or even dozens of data pairs to transmit high-definition (such as 1920x1080) signals, V-BY-ONE uses efficient serialization technology and embedded clock encoding to transmit the same bandwidth with very few differential signal pairs.

[0058] For example, implementing a 4K@60Hz (8-bit) signal requires only eight pairs of high-speed data cables (the mainstream configuration), while older LVDS systems might require more than 30 pairs. The V-BY-ONE interface used in this application is an 8-lane 4K@60 signal interface, with a connector type of JAE FI-RE51-HF surface mount socket, 51-pin surface mount; the HDMI to V-BY-ONE chip used is the RK628F chip.

[0059] Specifically, such as Figure 4 As shown, the MIPI CAM interface consists of 4 lanes of data lines (Data+ and Data-) plus a pair of clock lines (Clock+ and Clock-), totaling 10 physical lines. Operating mode: In high-speed mode (HSMode), differential signal transmission is used, with a rate of 80Mbps-1.5Gbps / lane (theoretically up to 9Gbps / lane), for transmitting image data. Transmission mechanism (using DDR transmission mechanism): Data is sampled simultaneously on both the rising and falling edges of the clock, effectively doubling the bandwidth. This application also includes a control interface: an independent I2C channel for configuring camera parameters (such as resolution and frame rate) and reading / writing control registers, separated from the data channel to ensure low latency of control signals.

[0060] The MIPI CAM interface offers the following functionalities: Increased parallel transmission speed: Four independent data channels operate synchronously, achieving a total bandwidth four times that of a single lane (e.g., 1.5Gbps per channel → 6Gbps total bandwidth); Supported resolution: Easily supports high-resolution video streams such as 4K@60fps / 8K@30fps (requires pixel depth calculation); Dynamic power management: Automatically switches to low-power mode (μW level) when there is no data transmission, and enables high-speed mode during transmission (power consumption 30%+ lower than traditional interfaces); Low-voltage differential signal: A 200mV swing design significantly reduces transmission power consumption; Differential signal noise reduction: Suppresses common-mode interference, adapting to complex electromagnetic environments such as automotive and industrial applications; Clock data recovery (CDR): Extracts the clock from the data stream, avoiding clock jitter issues; Universal pixel format: Natively supports sensor data formats such as RAW / YUV / RGB, eliminating the need for transcoding; Physical simplification: Requires only ten lines (4 pairs of data + 1 pair of clock), reducing pins by 50%+ compared to traditional parallel interfaces (such as DVP). This application uses a 4-lane data connection plus a clock channel, with an interface of a 30-pin FPC connector with a 0.5mm pitch.

[0061] Specifically, such as Figure 5 As shown, the MIPI LCD interface uses a D-PHY physical layer protocol, similar to the MIPI CSI interface. The signal composition consists of four pairs of differential data lines (Data0±~Data3±) + one pair of differential clock lines (CLK±), totaling ten lines. It supports two operating modes (high-speed mode and low-power mode). High-speed mode (HSMode): Transmits video pixel streams at a rate of 80Mbps-1.5Gbps per channel (up to 2.5Gbps in newer versions); low-voltage differential signals (swing 100-300mV, center level 200mV), resulting in higher power consumption. Low-power mode (LP Mode): Transmits control commands (such as screen parameter configuration) at a rate ≤10Mbps, using only Lane 0 for bidirectional transmission; single-ended signals (swing 0-1.2V), with extremely low power consumption (μW level).

[0062] The data transmission mechanism of the MIPI LCD interface is as follows: Parallel distribution: The transmitting end distributes the data stream byte by byte to the four channels (e.g., Byte0→Lane0, Byte1→Lane1…) to achieve parallel acceleration. The receiving end merges the data in reverse to restore the original sequence; Dynamic bandwidth management: When the data volume is not a multiple of 4, the channel that has finished transmitting early enters the EoT (End of Transmission) state to wait; Dual-edge sampling (DDR): In HS mode, data is sampled on both the rising and falling edges of the clock, effectively doubling the bandwidth.

[0063] The MIPI LCD interface operates in the following modes: Video mode: Real-time transmission of pixel streams, without dedicated synchronization signals (VSYNC / HSYNC), instead encapsulated as data packets for transmission; supports three timing modes: BurstMode (switches to LP for power saving after data compression); Non-BurstwithSyncPulses / Events (precise / simplified reconstruction timing). Command mode: Pixel data is sent only when the screen updates (relying on the screen's built-in frame buffer), and the screen refreshes automatically at other times; requires bidirectional communication (only supported by Lane 0) to read the screen state.

[0064] The MIPI LCD interface offers the following functionalities: Parallel channel speed enhancement: Four-channel concurrent transmission, with a total bandwidth four times that of a single channel (theoretically up to 6Gbps), supporting 4K@60fps / 8K@30fps video streams; Differential signal noise reduction: Suppressing common-mode interference, suitable for complex electromagnetic environments such as automotive and industrial applications; Embedded clock recovery: The receiver extracts the clock from the data stream via CDR (Clock Data Recovery), avoiding jitter issues; Physical simplification: Requires only ten wires (compared to 20+ pins for the RGB interface), saving PCB space and connector costs. Application scenarios for the MIPI LCD interface include: Mobile devices: High refresh rate screens for smartphones / tablets (e.g., 2K@120Hz); Automotive systems: Central control screens, dashboards (requiring interference resistance and low power consumption); Industrial displays: Industrial control HMIs, medical equipment screens. This application uses a 4-lane data connector plus one clock channel, with a 40-pin, 0.5mm pitch FPC connector.

[0065] Specifically, such as Figure 6 As shown, the Type-C interface operates under the DPALT Mode. Pin multiplexing and signal allocation: The USB Type-C interface includes four pairs of high-speed differential signal lines (TX / RX). In DPALT Mode: Four-channel mode: All four TX / RX pairs are used to transmit DP signals, maximizing bandwidth (up to 32.4Gbps), supporting 8K@60Hz video; Two-channel mode: Only two TX / RX pairs are used to transmit DP signals, while the remaining two pairs can simultaneously transmit USB 3.x data (such as USB 3.2 Gen2), suitable for 4K@60Hz output. Auxiliary pins: 1. CC pin: Used for protocol negotiation (USB PD) and device orientation identification; 2. SBU pin: Converted to AUX differential pair in DP mode, transmitting control signals such as EDID and HPD (hot-plug detection).

[0066] Protocol Negotiation Process: 1. USB PD Handshake: VDM (vendor-defined message) is sent via the CC pin to confirm that both parties support DPAlt Mode; 2. Hardware Switching: After successful negotiation, the MUX (multiplexer) chip switches TX / RX from the USB protocol to the DP protocol; 3. DP Link Training: The source device (e.g., a laptop) and the receiver (e.g., a monitor) establish optimal signal parameters (e.g., code rate, voltage swing). Physical Layer Support: 1. VBUS pin supports the USB PD protocol, providing up to 100W of power (e.g., a laptop reversing charge for a monitor); 2. Differential signaling suppresses common-mode noise to ensure stable transmission of high-resolution video.

[0067] The Type-C interface offers the following multi-dimensional integrated advantages: High-bandwidth video output: Supports 8K@60Hz (4:2:0 compression) or 4K@120Hz video, surpassing the bandwidth limitations of traditional HDMI 2.0, and is compatible with advanced display technologies such as HDR and DSC (Display Stream Compression) to enhance the visual experience; Multi-functional single-cable integration: A single cable simultaneously achieves video output (DP), data exchange (USB 3.x), and power supply (USB PD), simplifying device connections. It can connect multiple monitors (daisy-chain technology), peripherals (keyboard, mouse, storage), and network devices via a USB-C docking station; Cross-device compatibility: Suitable for laptops, mobile phones (such as Samsung DeX mode), tablets, graphics card docks, etc. It coexists with Thunderbolt 3 / 4, and the Thunderbolt interface is backward compatible with DPAlt Mode; Optimized system design: Replacing traditional DP / HDMI interfaces, it facilitates ultra-thin device designs (such as MacBooks retaining only USB-C), dynamically switching between high-speed mode (video transmission) and low-power mode (standby) to reduce energy consumption. This application uses a standard full-function Type-C interface, which can support USB 3.0 data exchange and DP display output. It uses the CC pin of the Type-C protocol chip for detection and identification, and the processor controls the switching of the output protocol.

[0068] Specifically, such as Figure 7As shown, the physical structure of the M.2 Key-B interface is as follows: Notch location: The notch of the Key-B interface is located on the left side (near the edge of the motherboard), corresponding to pins 12-19 of the M.2 module, forming a physical foolproof design to prevent incorrect insertion; Pin definitions: Internally, it can support low-speed buses such as SATA protocol, PCIe×2 channel, USB3.0, and I2C, but does not support PCIe×4 high-speed channel. Electrical characteristics are as follows: Bandwidth limitations: 1. SATA protocol: theoretical bandwidth 6Gbps (actual speed approximately 550MB / s); 2. PCIe×2 protocol: theoretical bandwidth 16Gbps (PCIe3.0×2, actual speed approximately 1.97GB / s), significantly lower than the PCIe×4 bandwidth of the Key-M interface; Compatibility design: Some Key-B devices adopt a B+M Key dual-notch design, which can be compatible with both Key-B and Key-M slots (but limited by PCIe×2 bandwidth). The connection mechanism is as follows: after the device is inserted, protocol communication is achieved through pin contact in the motherboard slot, without the need for an additional adapter; hot-swapping is supported (requires motherboard and operating system support), and it is suitable for modular expansion of industrial equipment.

[0069] The functions of the M.2 Key-B interface are as follows: Core function: Connecting low-to-medium speed devices to entry-level SSDs, supporting SATA protocol M.2 solid-state drives, suitable for budget-conscious or older motherboard upgrade scenarios (such as the Western Digital Blue SN570); Wireless communication modules: 1. 4G / 5G WWAN module, transmitting mobile network data via PCIe x2 lanes (such as ME906s); 2. Wi-Fi / Bluetooth module: Some early network cards use the Key-B interface (requires USB protocol); Bandwidth and performance positioning: Performance limit: Limited by PCIe x2 or SATA protocol, cannot support high-performance NVMe SSDs (requires PCIe x4); Applicable scenarios: Devices with low bandwidth requirements, such as industrial sensors, vehicle navigation modules, etc. System compatibility and expandability: Motherboard compatibility: Commonly found on entry-level motherboards or laptops, providing low-cost expansion slots; Multi-functional integration: A single interface can connect multiple devices simultaneously (such as SSD + WWAN), reducing motherboard space usage. The M.2 Key-B in this application uses the SATA protocol and can support 5G communication module expansion, improving network communication speed.

[0070] Specifically, such as Figure 8As shown, the physical structure of the M.2 Key-M interface is as follows: Notch location: The notch of the Key-M is located on the right side (pins 59–66), forming a physical foolproof design to ensure that it can only be inserted into the M Key slot; Pin definition: Supports PCIe×4 lanes (4 pairs of differential signal lines), providing high-speed data transmission capabilities; Size specifications: The common size is 2280 (22×80mm), and there are also 2230, 2242, 2260 and other specifications to adapt to different device spaces. The electrical characteristics of the M.2 Key-M interface are as follows: Bandwidth performance: PCIe 3.0×4: theoretical bandwidth 32Gbps (actual speed approximately 3.5-4GB / s); PCIe 4.0×4: theoretical bandwidth 64Gbps (actual speed approximately 7GB / s); PCIe 5.0×4: theoretical bandwidth 128Gbps (actual speed approximately 14–15GB / s). Protocol Support: NVMe Protocol: Communicates directly with the CPU via the PCIe channel, reducing latency (<10μs) and supporting high-concurrency command queues (64K depth); SATA Protocol Compatibility: Some Key-M interfaces are backward compatible with SATA mode, but bandwidth is limited (maximum 600MB / s). Connection Mechanism: Hot-swappable Support: Requires motherboard and operating system support; this feature is common in enterprise-level devices; Signal Integrity Requirements: Differential signal impedance must be strictly controlled within 85Ω±10%, and length matching error ≤5mil (PCIe 4.0+).

[0071] The core function of the M.2 Key-M interface (high-speed storage performance) is as follows: 1. Breaking bandwidth bottlenecks: Compared to SATA SSDs (550MB / s), NVMe SSDs offer speed improvements of 6-12 times (e.g., the Samsung 980 Pro PCIe 4.0 can reach 7GB / s), supporting high-throughput scenarios such as 4K / 8K video editing and loading large games; 2. Low latency optimization: The NVMe protocol reduces data path layers, increasing IOPS (random read / write) performance to the million level. System design optimization: 1. Space efficiency: Only 1 / 5 the size of a 2.5-inch hard drive, suitable for ultra-thin laptops (such as MacBook Air) and mini PCs; 2. Improved energy efficiency: Power consumption per unit speed (GB / s / W) is 3 times that of SATA SSDs, extending the battery life of mobile devices. Scalability and compatibility: 1. Enterprise applications: High-speed cache disks for data centers (such as Intel Optane P5800X), supporting hot-swapping and redundant arrays. Consumer scenarios: The preferred storage solution for game consoles (PS5) and high-performance PCs. The technological evolution is supported by: 1. Future compatibility: Supporting PCIe 5.0 / 6.0 upgrade paths, adapting to AI computing and real-time data analysis needs; 2. Heterogeneous computing integration: Connecting GPU / FPGA accelerator cards via PCIe channels (customized motherboard required). This application uses the PCIe 3.0x4 protocol, and the interface uses the standard M.2 Key-MNVME interface.

[0072] Table 1.2 Comparison of Key-B and Key-M interfaces

[0073] Gap position Left side (12-19 stitches) Right side (stitches 59–66) Maximum bandwidth 1.97GB / s (PCIe×2) 7.88GB / s (PCIe 4.0 x 4) Typical equipment SATA SSD, 4G module NVMe SSDs (such as the Samsung 990 Pro) Protocol support SATA, PCIe x2, USB PCIe x4, NVMe

[0074] It should be understood that, such as Figure 9 and Figure 10 As shown, the AI ​​digital human motherboard in this utility model has the following features: 1. Four-display protocol integrated architecture: The processor (29) simultaneously drives four types of display interfaces: LVDS (1), eDP (5), HDMIOUT (4), and V-BY-ONE (3), among which V-BY-ONE achieves protocol conversion through a dedicated conversion chip (38); 2. Dual-mode M.2 expansion system: The Key-B interface (41) is directly connected to the processor and supports SATA protocol storage devices; The Key-M interface (2) is connected to the processor through a PCIE clock chip (31) and supports PCIE protocol devices (5G module / NVMe SSD); 3. High-fidelity audio path: An independent audio codec chip (37) processes the microphone (15), power amplifier interface (13), and audio interface (17) signals and supports 192kHz / 32bit sampling; 4. I2C-GPIO conversion control: 32 programmable GPIOs (14) are expanded through an I2C to GPIO chip (46) to be compatible with sensor and actuator access.

[0075] See Figure 11 This utility model also provides an AI digital human device, which includes a housing and the aforementioned AI digital human motherboard housed within the housing. A power board, communication ports (WIFI / 4G / ETH), other peripherals, and speakers are all connected to the motherboard. The motherboard is connected to a display screen (equipped with a touchscreen), a microphone array module, a camera, and the display screen via an I2C / USB interface. The power board provides power to the motherboard and backlight power to the display screen. The motherboard sends display data and backlight control to the display screen. The speaker receives audio signals sent by the motherboard and outputs them through the microphone array module after noise reduction and echo cancellation processing. The motherboard can be connected to serial port peripherals or a hard drive.

[0076] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. An AI digital human motherboard, characterized in that, The AI ​​digital human motherboard includes a motherboard body and a processor, control components, and connection ports, all of which are mounted on the motherboard body. The control components include an HDMI to V-BY-ONE chip, an audio codec chip, a PICE clock chip, a MIPI to LVDS chip, and a Type-C protocol chip, wherein the audio codec chip is connected to the processor; The connection ports include a display interface, a Type-C interface, an M.2 Key-B interface, an M.2 Key-M interface, a MIPI LCD interface, and a MIPI CAM interface. The M.2 Key-B interface, MIPI LCD interface, and MIPI CAM interface are all connected to the processor. The M.2 Key-M interface is connected to the processor via a PCIe clock chip. The display interface includes an LVDS interface, an eDP interface, an HDMI OUT interface, and a V-BY-ONE interface. The LVDS interface, eDP interface, and HDMI OUT interface are all connected to the processor. The V-BY-ONE interface is connected to the processor via an HDMI to V-BY-ONE chip. The Type-C interface for the eDP interface display output is connected to the processor via a Type-C protocol chip. The LVDS interface is connected to the processor via a MIPI to LVDS chip. The processor receives the device type identified by the Type-C protocol chip and accesses the connection port. Based on the device type, the processor controls the control component to drive the display interface to output AI digital human information.

2. The AI ​​digital human motherboard according to claim 1, characterized in that, The control component also includes an Ethernet gigabit PHY chip and a USB conversion chip. The connection port also includes an RJ45 interface and a USB interface. The RJ45 interface is connected to the processor through the Ethernet gigabit PHY chip, and the USB interface is connected to the processor through the USB conversion chip.

3. The AI ​​digital human motherboard according to claim 2, characterized in that, The USB interface includes a USB 3.0 Type-C interface, a USB 2.0 Type-A interface, a USB 3.0 Type-A interface, and a USB 2.0 pH interface. The USB conversion chip includes a multiplexer, a UART / USB conversion chip, and a USB Hub chip, all of which are connected to the processor. The USB 2.0 Type-A, USB 3.0 Type-A, and USB 3.0 Type-C interfaces are all connected to the USB processor, and the USB 2.0 pH interface is connected to the processor through the USB Hub chip.

4. The AI ​​digital human motherboard according to claim 2, characterized in that, The control components also include memory chips, eMMC chips, MCU chips, and Wi-Fi modules. The connection ports also include an audio interface, a power amplifier interface, a microphone interface, a SATA3.0 interface, and a debug interface. The audio interface and the power amplifier interface are both connected to the processor through an audio codec chip. The memory chips, eMMC chips, MCU chips, Wi-Fi modules, debug interfaces, SATA3.0 interfaces, and microphone interfaces are all connected to the processor.

5. The AI ​​digital human motherboard according to claim 4, characterized in that, The control component further includes an RS232 conversion chip and an RS485 conversion chip. The connection ports also include a COM interface, an I2C interface, and a microphone interface. The COM interface includes a TTL PH interface, an RS232 PH interface, and an RS485 PH interface. The RS232 PH interface is connected to the processor through the RS232 conversion chip, and the RS485 PH interface is connected to the processor through the RS485 conversion chip. The TTL PH interface, the I2C interface, and the microphone interface are all connected to the processor. The I2C interface is used to connect to the touch screen.

6. The AI ​​digital human motherboard according to claim 4, characterized in that, The debug interface includes a chip programming interface, an MCU programming interface, and a debug interface, all of which are connected to the processor.

7. The AI ​​digital human motherboard according to claim 5, characterized in that, The control components also include a PMIC power management chip, an RTC chip, an I2C to GPIO chip, and a level conversion chip. The connection ports also include a MINI PCI-e interface, a SIM card interface, an IR / ADC / indicator light interface, a GPIO interface, and a TF card interface. The GPIO interface is connected to the processor via the I2C to GPIO chip, the SIM card interface is connected to the MINI PCI-e interface, and the PMIC power management chip, RTC chip, level conversion chip, IR / ADC / indicator light interface, and TF card interface are all connected to the processor.

8. The AI ​​digital human motherboard according to claim 7, characterized in that, The AI ​​digital human motherboard also includes a power supply battery, which is used to connect to the RTC chip and supply power to the RTC chip.

9. An AI digital human device, characterized in that, The AI ​​digital human device includes a housing and an AI digital human motherboard as described in any one of claims 1-8 housed within the housing.

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