Signal generating circuit and memory circuit

Abstract

A signal generation circuit includes a loopback path and a signal generator, the signal generator including: an inverter having an output coupled to a first end of the loopback path; a transistor coupled between a second end of the loopback path and a power distribution node; a buffer having an input configured to receive a clock signal; a first logic gate having a first input coupled to the input of the buffer, a second input coupled to an output of the buffer, and an output coupled to an input of the inverter and a gate of the transistor; and a second logic gate having a first input coupled to the input of the buffer, a second input coupled to the second end of the loopback path, and an output configured to output an output signal.

Description

Technical Field

[0001] This invention relates to signal generation circuits, and particularly to signal generation circuits and memory circuits. Background Technology

[0002] The ongoing trend of miniaturization in integrated circuits (ICs) has led to devices becoming increasingly smaller, offering more functionality and faster speeds than earlier technologies while consuming less power. This miniaturization is achieved through design and manufacturing innovations, as well as increasingly stringent specifications. In some cases, these specifications relate to the timing of read and write operations in memory circuits, such as multi-bank static random access memory (SRAM) circuits. Utility Model Content

[0003] This novel embodiment provides a signal generation circuit, including: a feedback path and a signal generator, the signal generator including: an inverter, the output of which is coupled to a first end of the feedback path; a transistor coupled between a second end of the feedback path and a power distribution node; a buffer, the input of which is configured to receive a clock signal; a first logic gate, the first logic gate including: a first input coupled to the input of the buffer; a second input coupled to the output of the buffer; and an output coupled to the input of the inverter and the gate of the transistor; and a second logic gate, the second logic gate including: a first input coupled to the input of the buffer; a second input coupled to the second end of the feedback path; and an output configured to output an output signal.

[0004] According to one embodiment of the signal generation circuit, the feedback path is located in a partial input / output circuit of a memory circuit; and the signal generator is located in a partial control circuit of the memory circuit.

[0005] According to one embodiment of the signal generation circuit, the transistor includes a P-type transistor; the power distribution node includes a power supply voltage node; the first logic gate includes a NOR gate; and the second logic gate includes an OR gate.

[0006] According to one embodiment of the signal generation circuit, the transistor includes an N-type transistor; the power distribution node includes a power reference node; and the first logic gate and the second logic gate both include NAND gates; wherein the signal generator further includes a clock signal inverter, the clock signal inverter including an output terminal coupled to the input terminal of the buffer.

[0007] According to one embodiment of the signal generation circuit, the output terminal of the second logic gate is coupled to a tracking circuit.

[0008] This novel embodiment also provides a memory circuit, including a global control circuit, which includes a clock generator; a local input / output circuit, which includes a feedback path located between a first memory array and a second memory array; and a local control circuit coupled to the global control circuit and the local input / output circuit, wherein the local control circuit includes a signal generator, which includes: an inverter, including an output terminal coupled to a first end of the feedback path; a transistor, coupled between a second end of the feedback path and a power distribution node of the memory circuit; a buffer, including an input terminal coupled to the clock generator; a first logic gate, which includes: a first input terminal coupled to an input terminal of the buffer; a second input terminal coupled to an output terminal of the buffer; and an output terminal coupled to an input terminal of the inverter and a gate of the transistor; and a second logic gate, which includes: a first input terminal coupled to an input terminal of the buffer; a second input terminal coupled to a second end of the feedback path; and an output terminal coupled to the global control circuit.

[0009] According to one embodiment of the memory circuit, the feedback path has a length corresponding to the number of rows of a plurality of memory cells in the first memory array and the second memory array.

[0010] According to one embodiment of the memory circuit, the plurality of memory cells of the first memory array and the second memory array include a plurality of six-crystal static random access memory devices.

[0011] According to one embodiment of the memory circuit, the transistor of the signal generator includes a P-type transistor; the power distribution node of the memory circuit includes a power supply voltage node of the memory circuit; the first logic gate of the signal generator includes a NOR gate; and the second logic gate of the signal generator includes an OR gate.

[0012] According to one embodiment of the memory circuit, the transistor of the signal generator includes an N-type transistor; the power distribution node of the memory circuit includes a power reference node of the memory circuit; and the first logic gate and the second logic gate of the signal generator both include a NAND gate; wherein the input terminal of the buffer is coupled to the clock generator of the global control circuit through a clock signal inverter. Attached Figure Description

[0013] The various aspects of this invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features in the drawings are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0014] Figure 1This is a schematic diagram of a memory circuit according to some embodiments.

[0015] Figure 2 These are based on the operating parameters of the memory circuit in some embodiments.

[0016] Figure 3 This is a block diagram of a loop end signal generation circuit according to some embodiments.

[0017] Figure 4A and Figure 4B These are schematic diagrams and descriptions of operating parameters of the loop end signal generation circuit according to certain embodiments.

[0018] Figure 4C and Figure 4D These are schematic diagrams and descriptions of operating parameters of the loop end signal generation circuit according to certain embodiments.

[0019] Figure 5 This is a flowchart of a method for operating a memory circuit according to certain embodiments.

[0020] Explanation of reference numerals in the attached figures:

[0021] 100: Memory circuit

[0022] 100WT: Top character line driver circuit

[0023] 100LC: Local control circuit

[0024] 100WB: Bottom character line driver circuit

[0025] 100GC: Global Control Circuit

[0026] 100AT: Top-of-the-line storage array

[0027] 100LIO: Partial Input / Output Circuit

[0028] 100AB: Bottom Storage Array

[0029] 100GIO: Global Input / Output Circuit

[0030] 100SG: Signal Generator

[0031] 400P, 400N: Signal generation circuit

[0032] WLD: Character Line Driver

[0033] BLPRCH,WR,RD: Signals

[0034] EOCYC: Signal

[0035] Ctrl: Control signal

[0036] LWE: Latch write enable signal

[0037] ICLK, ICLKB: Clock signals

[0038] TBL: Tracking Signal

[0039] Addr: Address signal

[0040] WE: Write enable signal

[0041] CLK: Clock signal

[0042] CE: Chip enable signal

[0043] RSTCKB: Reset Signal

[0044] WL0~WLTOP: Character Lines

[0045] MC: Storage Unit

[0046] BL: Bitline

[0047] BLB: Complementary Bit Line

[0048] SA: Sensing Amplifier

[0049] BLPCHB, SAE, READB, YDEC, WRITE: Signals

[0050] INTCLKD: Internal clock signal

[0051] INTCLKB: Internal clock signal

[0052] ICLKDB: Delayed clock signal

[0053] 100LP: Return Path

[0054] DL, D: Data cable

[0055] QLI, Q: Output lines

[0056] TWL_WR, TWL_RD: Tracking signals

[0057] MP,MN: Transistor

[0058] BF: Buffer

[0059] NR: NOR gate

[0060] OR: OR Gate

[0061] IN1, IN2: Inverters

[0062] VDD: Power supply voltage node

[0063] VSS: Power Reference Node

[0064] ND1, ND2: NAND gates

[0065] 500: Methods

[0066] 510, 520, 530, 540, 550, 560, 570: Operation Detailed Implementation

[0067] This invention provides numerous different embodiments or examples to implement various features of the provided subject matter. Examples of specific elements, values, operations, materials, configurations, or similar matters are described below to simplify the description herein. These are, of course, merely examples and are not intended to be limiting. Other elements, values, operations, materials, configurations, or similar matters are also considered. For example, in the following description, a first feature formed on or below a second feature may include embodiments where the first and second features are in direct contact, or embodiments where other features are formed between the first and second features, thus the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in different examples herein. Such repetition is for the sake of brevity and clarity and does not imply a necessary relationship between the various embodiments and / or configurations.

[0068] In addition, spatial relative terms such as “below,” “below,” “lower,” “above,” “higher,” etc., may be used herein for ease of description to describe the relationship of one element or feature relative to another element or feature, as shown in the figures. These spatial relative terms are intended to encompass different orientations of the device in use or operation, other than those shown in the figures. The device may be oriented in other ways (e.g., rotated 90 degrees or other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0069] In various embodiments, the signal generation circuit includes a loopback path and a signal generator. The signal generator includes an inverter coupled to a first end of the loopback path, a transistor coupled between a second end of the loopback path and a power distribution node, a buffer configured to receive a clock signal, a first logic gate coupled to the gates of the buffer, the inverter, and the transistor, and a second logic gate coupled to the buffer and the second end of the loopback path. Therefore, the signal generator includes a transistor and a first logic gate configured as a loopback bypass circuit, which causes the second logic gate to output a signal, such as a cycle end signal for a memory circuit, comprising a leading-edge pulse based on a clock signal and a trailing-edge pulse based on an internal clock signal propagating on the loopback path.

[0070] Compared to other methods, such as signal generators that do not include feedback bypass circuitry, this signal generation circuit is thus able to maintain the integrity of the output signal and avoid accidental circuit operations, such as dual-clocking phenomena caused by read and write operations in memory circuits, which could lead to circuit failure and increase power consumption by setting the input latches to transparent states.

[0071] As discussed below, according to certain embodiments, Figure 1 This is a schematic diagram of a memory circuit 100 including a signal generator 100SG. Figure 2 The operating parameters of the memory circuit 100 are described. Figure 3 This is a block diagram of the 100SG signal generator. Figures 4A to 4D This is a diagram related to signal generation circuits 400P and 400N, which can be used at least partially as signal generator 100SG. Figure 5 This is a flowchart of a method 500 for operating a memory circuit containing a signal generator (e.g., a memory circuit 100 containing a signal generator 100SG).

[0072] Figure 1 This is a schematic diagram of memory circuit 100 according to some embodiments. In some embodiments, memory circuit 100, sometimes also referred to as circuit, is an integrated circuit (IC) including global control circuit 100GC, global input / output (I / O) circuit 100GIO, local control circuit 100LC, local input / output circuit 100LIO, top word line driver circuit 100WT and bottom word line driver circuit 100WB, as well as top memory array 100AT and bottom memory array 100AB.

[0073] Figure 1 The configurations and quantities of local control circuits and local I / O circuits, write line drive circuits, and memory arrays shown are illustrative and not limiting examples. The scope of this document includes... Figure 1 Other configurations and quantities not shown.

[0074] The global control circuit 100GC is adjacent to and electrically coupled to the global I / O circuit 100GIO, and is also electrically coupled to the local control circuit 100LC. The local control circuit 100LC is adjacent to and electrically coupled to the local I / O circuit 100LIO, and is located between and electrically coupled to the top word line driver circuit 100WT and the bottom word line driver circuit 100WB. Both the local I / O circuit 100LIO and the top word line driver circuit 100WT are adjacent to and electrically coupled to the memory array 100AT, and both the local I / O circuit 100LIO and the bottom word line driver circuit 100WB are adjacent to and electrically coupled to the memory array 100AB. In various embodiments, the memory circuit 100 includes address lines, bit lines, data lines, word lines, and / or signal lines (in... Figure 1 (shown in the middle section) One or more combinations of the global control circuit 100GC, the global I / O circuit 100GIO, the local control circuit 100LC, the local I / O circuit 100LIO, the top word line driver circuit 100WT and the bottom word line driver circuit 100WB, as well as the memory array 100AT and the memory array 100AB are electrically coupled to each other, as discussed.

[0075] Two or more circuit elements are considered to be coupled to each other, for example, based on one or more direct signal connections and / or including one or more indirect signal connections (e.g., electrical connections), including indirect signal connections of one or more logic devices (e.g., inverters or logic gates) between the two or more circuit elements. In some embodiments, signal communication between two or more coupled circuit elements can be modified by one or more logic devices, for example, by inversion or conditionalization.

[0076] Storage arrays 100AT and 100AB are arrays of storage cells MC configured to store data. In some embodiments, the storage cells MC include static random-access memory (SRAM) cells. In various embodiments, the SRAM cells include five-transistor (5T) SRAM cells, six-transistor (6T) SRAM cells, eight-transistor (8T) SRAM cells, nine-transistor (9T) SRAM cells, or SRAM cells having other numbers of transistors. In various embodiments, the storage cells MC include dynamic random-access memory (DRAM) cells, non-volatile memory (NVM) cells, or other types of storage cells capable of storing data.

[0077] The global control circuit 100GC, the global I / O circuit 100GIO, the local control circuit 100LC, the local I / O circuit 100LIO, the top word line driver circuit 100WT, and the bottom word line driver circuit 100WB are each integrated circuits configured to perform a subset of operations, including data input, output, and storage in corresponding memory cells MC in memory arrays 100AT and 100AB. These operations respond to various combinations of address, clock, control, and / or data signals, such as in... Figure 1 The address signal Addr, write enable signal WE, clock signal CLK, and chip enable signal CE are displayed.

[0078] The global control circuit 100GC is configured to generate and receive one or more address, clock, control, and / or data signals used to control the top-level operation of the memory circuit 100; the global I / O circuit 100GIO is configured to respond to the one or more address, clock, control, and / or data signals to perform top-level I / O operations; and the local control circuit 100LC is configured to respond to the one or more address, clock, control, and / or data signals to control the one or more related I / O operations. The operation of adjacent local I / O circuits 100LIO, top word line driver circuits 100WT, and bottom word line driver circuits 100WB controls the memory arrays 100AT and 100AB diagonally adjacent to them; each local I / O circuit 100LIO, top word line driver circuit 100WT, and bottom word line driver circuit 100WB is configured to respond to one or more address, clock, control, and / or data signals, partially controlling the operation of the memory arrays 100AT and 100AB adjacent to it.

[0079] exist Figure 1 In the illustrated embodiment, a row of memory cells MC in memory array 100AT or 100AB is coupled to the write driver and sense amplifier (SA) of local I / O circuit 100LIO via bit line BL and complementary bit line BLB. The write driver and SA are coupled to the data latch / output latch of global I / O circuit 100GIO via data line DL and output line QLI.

[0080] The columns of memory cells MC in memory arrays 100AT and 100AB are coupled to their respective top word line driver WLDs 100WT and bottom word line driver 100WB via word lines WL0 to WLTOP. Each word line driver WLD is coupled to the address latch and decoder of the global control circuit 100GC and the clock generator, and thus each word line driver WLD is configured to receive one or more control signals Ctrl from the address latch and decoder, and a clock signal ICLK from the clock generator.

[0081] The local control circuit 100LC includes an enable signal generator (e.g., BL PRCH / WR clock / RD clock / SA enable) coupled to the address latch and decoder, clock generator, and write enable latch of the global control circuit 100GC, and coupled to the write driver and SA of the local I / O circuit 100LIO. Therefore, the enable signal generator is configured to respond to one or more control signals Ctrl, a latched write enable signal LWE, and a clock signal ICLK, outputting signals BLPCHB, SAE, READB, YDEC, and WRITE to the write driver and SA.

[0082] The local control circuit 100LC also includes a signal generator 100SG, which is coupled to the address latch and decoder, write enable latch, clock generator, and trace word line (WL) circuit of the global control circuit 100GC, as well as the loopback path 100LP located in the local I / O circuit 100LIO. (Further details will follow.) Figures 2 to 4D In the discussion, the signal generator 100SG is configured to respond to the clock signal ICLK received from the clock generator by outputting a signal EOCYC to each of the address latch and decoder, write enable latch and trace WL circuit of the global control circuit 100GC, sometimes also referred to as the loop end signal in some embodiments.

[0083] The signal EOCYC comprises a pulse with a leading edge based on the clock signal ICLK and a pulse with a trailing edge based on the internal clock signal INTCLKD propagated through the loopback path 100LP, as discussed further below. In operation, the internal clock signal INTCLKD propagated through the loopback path 100LP experiences a delay that increases with the length of the loopback path 100LP. In some embodiments, the length of the loopback path 100LP corresponds to the number of rows of memory cells MC in memory arrays 100AT and 100AB; therefore, as the number of rows of memory cells MC increases, the delay of the trailing edges corresponding to the pulses of the internal clock signal INTCLKD and the signal EOCYC also increases.

[0084] The following is about Figure 2 As discussed, memory circuit 100 is configured to respond to the trailing edge of the EOCYC pulse by resetting the clock signal ICLK to a logic level corresponding to the start of a read and / or write cycle during operation. Therefore, memory circuit 100 is configured to perform timing-efficient read and / or write operations based on the number of rows in memory arrays 100AT and 100AB.

[0085] The global control circuit 100GC includes an address latch and a decoder, configured to output a control signal Ctrl in response to the address signal Addr and the signal EOCYC during operation; a write enable latch is configured to output a latched write enable signal LWE in response to the write enable signal WE and the signal EOCYC; a clock generator is configured to output a clock signal ICLK in response to the clock signal CLK, the chip enable signal CE, and the reset signal RSTCKB; and a tracking WL circuit is configured to output a reset signal RSTCKB in response to the latched write enable signal LWE, the clock signal ICLK, the signal EOCYC, the reset signal RSTCKB, and the tracking signal TBL received from the tracking bit line (BL) circuit. This tracking bit line circuit is coupled to the tracking WL circuit and is located in... Figure 1 The character line driving circuit 100WB shown is used in this circuit.

[0086] The trace WL circuitry is coupled to two loopback paths located in the global I / O circuitry 100GIO and having lengths corresponding to word line lengths (e.g., corresponding to multiple rows of memory arrays 100AT and 100AB). The trace WL circuitry is configured to propagate the trace signal TWL_WR along one loopback path during a write operation and the trace signal TWL_RD along the other loopback path during a read operation.

[0087] Each feedback path is further coupled to a memory cell MC contained in the tracking BL circuit. These memory cells MC are configured to output a tracking signal TBL in operation in response to each of the tracking signals TWL_WR and TWL_RD.

[0088] Therefore, the tracking signal WBL has one or more timing features based on the feedback path length and / or the operating speed of the memory cell MC. In operation, the tracking WL circuit is thus configured to output a reset signal RSTCKB based on these one or more timing features and the timing of the signal EOCYC discussed above.

[0089] Figure 2 Operating parameters of memory circuit 100 according to some embodiments are shown. Figure 2Non-limiting examples of clock signals CLK, ICLK, EOCYC, TWL_RD (or TWL_WR for write operations) and TBL and reset signal RSTCKB are shown. Figure 2 The signals shown are a subset of the operating parameters of the memory circuit 100; additional signals are not included for clarity.

[0090] according to Figure 2 In the illustrated embodiment, the leading edge of the pulse of the clock signal ICLK is output from the clock generator of the global control circuit 100GC in response to the leading edge of the pulse of the received clock signal CLK. The leading edge of the pulse of the signal EOCYC is output from the signal generator 100SG, and the tracking signal TWL_RD (or signal TWL_WR) is output from the tracking WL circuit of the global control circuit 100GC in response to the leading edge of the pulse of the clock signal ICLK.

[0091] The tracking BL circuit responds to the leading edge of the tracking signal TWL_RD (or tracking signal TWL_WR) pulse by outputting the leading edge of the tracking signal TBL pulse, and responds to the trailing edge of the signal EOCYC by outputting the trailing edge of the tracking signal TBL pulse. The tracking WL circuit responds to each leading and trailing edge of the tracking signal TBL pulse by outputting the leading and trailing edges of the reset signal RSTCKB pulse, and the clock generator responds to the leading edge by outputting the trailing edge of the clock signal ICLK pulse.

[0092] The tracking BL circuit is configured to maintain the logic level between the leading and trailing edges of the pulse of the tracking signal TBL based on the signal generation circuit 100SG. Figure 2 In the illustrated embodiment, this is a low level, which is based on the signal generation circuit 100SG maintaining a logic level between the leading and trailing edges of the pulse of the signal EOCYC (in...). Figure 2 The result in the illustrated embodiment is a high level.

[0093] Therefore, as described below, by including a signal generator 100SG that is configured to output the leading edge of the pulse of the cycle end signal EOCYC in response to the leading edge of the pulse of the clock signal ICLK, the memory circuit 100 is configured to maintain the integrity of the pulses of the tracking signal TBL and the reset signal RSTCKB compared to other methods (e.g., methods in which the leading edge of the pulse of the cycle end signal EOCYC responds to events other than the leading edge of the clock signal pulse).

[0094] Therefore, compared to other methods, this avoids unintended circuit operations, such as dual clocking of the clock signal ICLK, which can lead to circuit failure and increase latch power consumption.

[0095] Figure 3 A block diagram of a signal generator 100SG according to some embodiments is shown. The signal generator 100SG includes an internal clock delay, a feedback path 100LP, a loop termination circuit, and bypass circuitry for the feedback path 100LP. In some embodiments, for example... Figure 1 As shown, the feedback path 100LP is separate from the signal generator 100SG, and the signal generator 100SG does not include the feedback path 100LP.

[0096] Each of the internal clock delay and the loop termination circuit is configured to receive the clock signal ICLK. The internal clock delay is coupled to the first end of the feedback path 100LP, and each of the bypass circuit of the feedback path 100LP and the loop termination circuit is coupled to the second end of the feedback path 100LP.

[0097] During operation, the internal clock delay unit will delay the pulses of the internal clock signal (in...) Figure 3 (Not shown) The output is sent to the first end of the feedback path 100LP in response to the pulse of the clock signal ICLK, and the bypass circuit of the feedback path 100LP, after propagating along the feedback path 100LP, receives the pulse of the internal clock signal from the second end of the feedback path 100LP.

[0098] The bypass circuit of the loopback path 100LP is configured to couple the second end of the loopback path 100LP to the power distribution node in response to the leading edge of the pulse of the clock signal ICLK, and decouple the second end of the loopback path 100LP from the power distribution node before receiving the trailing edge of the pulse of the internal clock signal.

[0099] As shown below Figures 4A to 4D In the non-limiting example further discussed herein, the signal generator 100SG is configured to output the leading edge of the pulse of the signal EOCYC in response to the leading edge of the pulse of the clock signal ICLK, so as to achieve the benefits discussed above.

[0100] Figure 4A and Figure 4B The schematic diagrams and descriptions of the operating parameters of the signal generation circuit 400P, according to certain embodiments, are shown. The signal generation circuit 400P, also referred to as a signal generator in some embodiments, can at least partially serve as described above. Figures 1 to 3 The signal generator 100SG discussed herein is used.

[0101] like Figure 4AAs shown, the signal generation circuit 400P includes an internal clock delay unit, which includes a buffer BF, a loop termination circuit (including an OR gate OR), and a bypass circuit for the feedback 100LP. The feedback 100LP bypass circuit includes a NOR gate NR, an inverter IN1 (including an output coupled to the first end of the feedback path 100LP), and a PMOS transistor MP. The transistor MP is coupled between the second end of the feedback path 100LP and a power distribution node including the power supply voltage node VDD.

[0102] exist Figure 4A In the illustrated embodiment, the buffer BF includes two strings of delay elements for applying a predetermined delay to the clock signal ICLK. In some embodiments, the buffer BF may be configured in other ways, for example, by including an inverter and / or other number of delay elements to apply a predetermined delay to the clock signal ICLK.

[0103] The input of NOR gate NR is coupled to each input and each output of buffer BF, and the output of NOR gate NR is coupled to the input of inverter IN1 and the gate of transistor MP.

[0104] The transistor MP includes a source / drain (S / D) terminal coupled to the second end of the feedback path 100LP, and an S / D terminal coupled to the power supply voltage node VDD.

[0105] The OR gate OR includes one input coupled to the input of the buffer BF, another input coupled to the second end of the feedback path 100LP, and the output of the OR gate OR corresponds to the output of the signal generator 100SG.

[0106] like Figure 4B As shown, during operation, buffer BF outputs a delayed clock signal ICLKD in response to clock signal ICLK. NOR gate NR outputs an internal clock signal INTCLKB in response to clock signal ICLK and the delayed clock signal ICLKD. Inverter IN1 outputs the internal clock signal INTCLKB (inverted and unlabeled) to the first terminal of feedback path 100LP. The internal clock signal INTCLKD appears at the second terminal of feedback path 100LP.

[0107] In response to the rising edge of the pulse of the clock signal ICLK, the NOR gate NR outputs the falling edge of the pulse of the internal clock signal INTCLK, thereby turning on the transistor MP and coupling the second terminal of the feedback path 100LP to the power supply voltage node VDD. Therefore, the internal clock signal INTCLKD comprises a pulse whose rising edge precedes the rising edge of the pulse propagating along the feedback path 100LP, at a point in time that would otherwise give the internal clock signal INTCLKD a rising edge.

[0108] In response to a high logic level clock signal ICLK or internal clock signal INTCLKD, the OR gate OR outputs a high logic level signal EOCYC, thereby generating a pulse of signal EOCYC. The leading edge of the pulse of signal EOCYC corresponds to the leading edge of the pulse of clock signal ICLK, and the trailing edge of the pulse of signal EOCYC corresponds to the trailing edge of the internal clock signal INTCLKD propagating along the feedback path 100LP.

[0109] Figure 4C and Figure 4D The schematic diagrams and descriptions of the operating parameters of the signal generation circuit 400N, as shown in some embodiments, are presented. The signal generation circuit 400N, also referred to as a signal generator in some embodiments, can at least partially serve as described above. Figures 1 to 3 The signal generator 100SG discussed in the article is used.

[0110] like Figure 4C As shown, the signal generation circuit 400N includes the internal clock delay unit (including buffer BF) discussed above, the loop termination circuit (including NAND gate ND2), and the bypass circuit for the feedback 100LP (including NAND gate ND1, inverter IN1 as discussed above, and an NMOS transistor MN, which is coupled between the second end of the feedback path 100LP and the power distribution node including the power reference node VSS).

[0111] The buffer BF is configured to receive a clock signal ICLKB that is complementary to the clock signal ICLK discussed above. In some embodiments, the signal generation circuit 400N includes an inverter IN2 configured to receive the clock signal ICLK and invert it to output the clock signal ICLKB.

[0112] The input of NAND gate ND1 is coupled to each input and each output of buffer BF, and the output of NAND gate ND1 is coupled to the input of inverter IN1 and the gate of transistor MN.

[0113] Transistor MN includes an S / D terminal coupled to the second end of feedback path 100LP, and an S / D terminal coupled to power reference node VSS.

[0114] NAND gate ND2 includes one input coupled to the input of buffer BF, another input coupled to the second end of feedback path 100LP, and the output of NAND gate ND2 corresponds to the output of signal generator 100SG.

[0115] like Figure 4D As shown, during operation, buffer BF responds to clock signal ICLKB and outputs a delayed clock signal ICLKDB. NAND gate ND1 responds to clock signal ICLKB and the delayed clock signal ICLKDB and outputs an internal clock signal INTCLKB. Inverter IN1 outputs the internal clock signal INTCLKB (inverted and not shown) to the first end of feedback path 100LP. An internal clock signal INTCLKD exists at the second end of feedback path 100LP.

[0116] In response to the leading edge (falling edge) of the pulse of the clock signal ICLKB, NAND gate ND1 outputs the rising edge of the pulse of the internal clock signal INTCLKB, thereby turning on transistor MN and coupling the second terminal of the feedback path 100LP to the power supply reference node VSS. Therefore, the internal clock signal INTCLKBD comprises a pulse whose leading edge (falling edge) precedes the leading edge of the pulse propagating along the feedback path 100LP, at a point in time that would otherwise give the internal clock signal INTCLKBD a leading edge.

[0117] In response to a clock signal ICLKB with a low logic level or an internal clock signal INTCLKD, NAND gate ND2 outputs a signal EOCYC with a high logic level, thereby generating a pulse of signal EOCYC. The leading edge of this pulse is used to respond to the leading edge of the pulse of clock signal ICLKB (generated from the pulse of clock signal ICLK), and the trailing edge of this pulse is used to respond to the trailing edge of the internal clock signal INTCLKD propagating along the feed path 100LP.

[0118] As mentioned above Figures 4A to 4D As discussed above, both signal generator 400P and signal generator 400N are configured to output a loop end signal EOCYC, consistent with the above description of signal generator 100SG and... Figures 1 to 3 Therefore, a memory circuit including a signal generator 400P or a signal generator 400N, such as a memory circuit 100, can achieve the advantages discussed above.

[0119] Figure 5This is a flowchart of a method 500 for operating a memory circuit according to certain embodiments. Method 500 can be used in memory circuits, such as those described above. Figures 1 to 4D The memory circuit 100 discussed herein includes a signal generator 100SG. In some embodiments, the operation of method 500 is part of a method for operating memory macros.

[0120] Figure 5 The operation sequence of method 500 shown is for reference only; the operation of method 500 can be performed in conjunction with... Figure 5 The different execution orders shown in the figure. In some embodiments, besides Figure 5 In addition to the operations shown in the image, you can also... Figure 5 Other operations can be performed before, between, during, and / or after the operations shown in the text.

[0121] In operation 510, in some embodiments, a global clock signal is generated by a clock generator. In some embodiments, generating the global clock signal includes outputting a clock signal ICLK from the clock generator of the global control circuit 100GC, as described above. Figure 1 The discussion is ongoing.

[0122] In operation 520, the clock signal and the delayed clock signal are received in the first logic gate of the signal generator. In some embodiments, the operation of receiving the clock signal and the delayed clock signal in the first logic gate includes receiving the clock signal ICLK and the delayed clock signal ICLKD in the NOR gate NR of the signal generator 400P, as described above. Figure 4A and Figure 4B As discussed above. In some embodiments, the operation of receiving a clock signal and a delayed clock signal in the first logic gate includes receiving a clock signal ICLKB and a delayed clock signal ICLKDB in the NAND gate ND1 of the signal generator 400N, as described above. Figure 4C and Figure 4D The discussion is ongoing.

[0123] In operation 530, a first internal signal is output from the first logic gate based on the clock signal and the delayed clock signal. In some embodiments, the operation of outputting the first internal signal from the first logic gate includes outputting the internal clock signal INTCLKB from the NOR gate NR, as described above. Figure 4A and Figure 4B As discussed above, the internal clock signal INTCLKB is output from NAND gate ND1. Figure 4C and Figure 4D The discussion is ongoing.

[0124] In operation 540, in response to the first internal clock signal, the second internal clock signal is output to the first end of the feedback path, and the second end of the feedback path is coupled or disconnected from the power distribution node using a transistor.

[0125] In some embodiments, the operation of outputting the second internal clock signal includes using an inverter IN1 to invert the internal clock signal INTCLKB and outputting it to the first terminal of the feedback path 100LP, as described above. Figures 4A to 4D The discussion is ongoing.

[0126] In some embodiments, the operation of using a transistor to couple or disconnect the second end of the feedback path from the power distribution node includes using a transistor MP to couple or disconnect the second end of the feedback path 100LP from the power supply voltage node VDD, as described above. Figure 4A and Figure 4B The discussion is ongoing.

[0127] In some embodiments, the operation of coupling or disconnecting the second end of the feedback path from the power distribution node using a transistor includes coupling or disconnecting the second end of the feedback path 100LP from the power reference node VSS using a transistor MN, as described above. Figure 4C and Figure 4D The discussion is ongoing.

[0128] In operation 550, a second internal clock signal is received from the second end of the feedback path at the second logic gate. In some embodiments, the operation of receiving the second internal clock signal from the second end of the feedback path at the second logic gate includes the above-described... Figure 4A and Figure 4B As discussed above, at the OR gate OR, the internal clock signal INTCLKD is received from the second terminal of the feedback circuit 100LP, or as mentioned above. Figure 4C and Figure 4D As discussed earlier, the internal clock signal INTCLKD is received from the second terminal of the feedback circuit 100LP at the NAND gate ND2.

[0129] In operation 560, a loop end signal is output from the second logic gate in response to the second internal clock signal and the clock signal. In some embodiments, the operation of outputting the loop end signal includes based on the internal clock signal INTCLKD and the OR gate OR (as described above). Figure 4A and Figure 4B (as described above) or from NAND gate ND2 (as mentioned above) Figure 4C and Figure 4D The clock signal ICLK (as described in the text) is used to output the signal EOCYC.

[0130] In operation 570, the clock generator signal is reset according to the loop end signal. In some embodiments, resetting the clock signal includes using the clock generator of the global control circuit 100GC to reset the clock signal ICLK according to the reset signal RSTCKB in response to the signal EOCYC, as described above. Figure 1 and Figure 2 The discussion.

[0131] By performing all or part of the operations in method 500, the signal generation circuit of the memory circuit can output the leading edge of the pulse of the cycle end signal in response to the leading edge of the pulse of the received clock signal, thereby achieving the aforementioned advantages associated with the signal generation circuit 100SG.

[0132] In some embodiments, a signal generation circuit includes a loopback path and a signal generator, the signal generator comprising: an inverter whose output is coupled to a first end of the loopback path; a transistor coupled between a second end of the loopback path and a power distribution node; a buffer whose input is configured to receive a clock signal; a first logic gate whose first input is coupled to an input of the buffer, a second input is coupled to an output of the buffer, and an output is connected to an input of the inverter and a gate of the transistor; and a second logic gate whose first input is coupled to an input of the buffer, a second input is coupled to the second end of the loopback path, and an output is configured to output an output signal. In some embodiments, the loopback path is located in a local I / O circuit of a memory circuit, while the signal generator is located in a local control circuit of the memory circuit. In some embodiments, the length of the loopback path corresponds to the number of rows in the memory cell array of the memory circuit. In some embodiments, the transistor includes a p-type transistor, the power distribution node includes a power supply voltage node, the first logic gate includes a NOR gate, and the second logic gate includes an OR gate. In some embodiments, the transistors include n-type transistors, the power distribution node includes a power reference node, and both the first and second logic gates include NAND gates. In some embodiments, the signal generator includes a clock signal inverter whose output is coupled to the input of a buffer. In some embodiments, the output of the second logic gate is coupled to a tracking circuit.

[0133] In some embodiments, a memory circuit includes a global control circuit comprising a clock generator, a local I / O circuit including a loopback path located between a first memory array and a second memory array, and a local control circuit coupled to the global control circuit and the local I / O circuit. The local control circuit includes a signal generator comprising an inverter whose output is coupled to a first end of the loopback path, a transistor coupled between a second end of the loopback path and a power distribution node of the memory circuit, a buffer whose input is coupled to the clock generator, a first logic gate whose first input is coupled to the input of the buffer, a second input is coupled to the output of the buffer, and the output is coupled to the input of the inverter and the gate of the transistor, and a second logic gate whose first input is coupled to the input of the buffer, the second input is coupled to the second end of the loopback path, and the output is coupled to the global control circuit. In some embodiments, the length of the loopback path corresponds to the number of rows of memory cells in the first and second memory arrays. In some embodiments, the memory cells of both the first and second memory arrays comprise 6TSRAM memory devices. In some embodiments, the transistors of the signal generator include P-type transistors, the power distribution node of the memory circuit includes a power supply voltage node of the memory circuit, the first logic gate of the signal generator includes a NOR gate, and the second logic gate of the signal generator includes an OR gate. In some embodiments, the transistors of the signal generator include N-type transistors, the power distribution node of the memory circuit includes a power supply reference node of the memory circuit, and both the first and second logic gates of the signal generator include NAND gates. In some embodiments, the input of the buffer is coupled to the clock generator of the global control circuit via a clock signal inverter. In some embodiments, the output of the second logic gate of the signal generator is coupled to the tracking circuit, the write enable latch, and the address decoder of the global control circuit.

[0134] In some embodiments, a method of generating memory circuit signals includes: receiving a clock signal and a delayed clock signal at a first logic gate of a signal generator; outputting a first internal clock signal from the first logic gate in response to the clock signal and the delayed clock signal; outputting a second internal clock signal from an inverter of the signal generator to a first end of a loopback path coupled to the signal generator; coupling and disconnecting a second end of the loopback path to a power distribution node using a transistor; receiving a second internal clock signal and a clock signal from the second end of the loopback path; and outputting memory circuit signals from a second logic gate in response to the second internal clock signal and the clock signal. In some embodiments, receiving the clock signal and the delayed clock signal at the first logic gate of the signal generator includes operating a signal generator located in local control circuitry within the memory circuitry; and outputting and receiving the second internal clock signal at the first end of the loopback path includes propagating the second internal clock signal through a loopback path located in local I / O circuitry coupled to the local control circuitry. In some embodiments, receiving a clock signal and a delayed clock signal from a first logic gate and outputting a first internal clock signal from the first logic gate includes receiving a clock signal and a delayed clock signal from a NOR gate and outputting the first internal clock signal from the NOR gate; using a transistor to couple and disconnect the second end of the feedback path to a power distribution node includes using a P-type transistor to couple and disconnect the second end of the feedback path to a power supply voltage node; receiving a second internal clock signal and a clock signal from a second logic gate and outputting a memory circuit signal from the second logic gate includes receiving a second internal clock signal and a clock signal from an OR gate and outputting the memory circuit signal from the OR gate. In some embodiments, receiving a clock signal and a delayed clock signal at a first logic gate and outputting a first internal clock signal from the first logic gate includes receiving a clock signal and a delayed clock signal from a first NAND gate and outputting the first internal clock signal from the first NAND gate; coupling and disconnecting the second end of the loopback path to a power distribution node using a transistor includes coupling and disconnecting the second end of the loopback path to a power reference node using an N-type transistor; receiving a second internal clock signal and a clock signal at a second logic gate and outputting a memory circuit signal from the second logic gate includes receiving a second internal clock signal and a clock signal from a second NAND gate and outputting the memory circuit signal from the second NAND gate. In some embodiments, receiving a clock signal and a delayed clock signal at the first logic gate includes generating a clock signal from the global clock signal of the memory circuit using an inverter. In some embodiments, outputting the memory circuit signal from the second logic gate includes outputting the memory circuit signal to the trace circuit, write enable latch, and address decoder of the memory circuit.

[0135] The foregoing has described the features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A signal generating circuit, characterized by comprising: include: One return path; as well as A signal generator, comprising: An inverter, one of whose outputs is coupled to a first end of the feedback path; A transistor is coupled between a second end of the feedback path and a power distribution node; A buffer, one input of which is configured to receive a clock signal; A first logic gate, including: A first input terminal is coupled to the input terminal of the buffer; A second input terminal is coupled to an output terminal of the buffer; and An output terminal is coupled to an input terminal of the inverter and a gate of the transistor; and A second logic gate, including: A first input terminal is coupled to the input terminal of the buffer; A second input terminal, coupled to the second end of the feedback path; and One output terminal is configured to output an output signal.

2. The signal generation circuit as described in claim 1, characterized in that, The feedback path is located in a partial input / output circuit of a memory circuit; and The signal generator is located in a local control circuit of the memory circuit.

3. The signal generation circuit as described in claim 1, characterized in that, The transistor includes a P-type transistor; The power distribution node includes a power voltage node; The first logic gate includes a NOR gate; and The second logic gate includes an OR gate.

4. The signal generation circuit as described in claim 1, characterized in that, The transistor includes an N-type transistor; The power distribution node includes a power reference node; and Both the first logic gate and the second logic gate include a NAND gate; The signal generator also includes a clock signal inverter, which has an output terminal coupled to the input terminal of the buffer.

5. The signal generation circuit as described in claim 1, characterized in that, The output of the second logic gate is coupled to a tracking circuit.

6. A memory circuit, characterized by include: A global control circuit, including a clock generator; A partial input / output circuit, including a loopback path located between a first memory array and a second memory array; and A local control circuit is coupled to the global control circuit and the local input / output circuit, wherein the local control circuit includes a signal generator, the signal generator comprising: An inverter, including an output terminal coupled to a first terminal of the feed path; A transistor is coupled between a second end of the feedback path and a power distribution node of the memory circuit; A buffer, including an input coupled to the clock generator; A first logic gate, including: A first input terminal is coupled to the input terminal of the buffer; A second input terminal is coupled to an output terminal of the buffer; and An output terminal is coupled to an input terminal of the inverter and a gate of the transistor; and A second logic gate, including; A first input terminal, coupled to the input terminal of the buffer; and A second input terminal is coupled to the second terminal of the feedback path; One output terminal is coupled to the global control circuit.

7. The memory circuit as described in claim 6, characterized in that, The return path has a length corresponding to the number of rows of multiple storage cells in the first storage array and the second storage array.

8. The memory circuit as described in claim 7, characterized in that, The plurality of memory cells in the first memory array and the second memory array include a plurality of six-crystal static random access memory devices.

9. The memory circuit as described in claim 6, characterized in that, The transistor in the signal generator includes a P-type transistor; The power distribution node of the memory circuit includes a power supply voltage node of the memory circuit; The first logic gate of the signal generator includes a NOR gate; and The second logic gate of the signal generator includes an OR gate.

10. The memory circuit as described in claim 6, characterized in that, The transistor in the signal generator includes an N-type transistor; The power distribution node of the memory circuit includes a power reference node of the memory circuit; and The first logic gate and the second logic gate of the signal generator both include a NAND gate; The input terminal of the buffer is coupled to the clock generator of the global control circuit through a clock signal inverter.

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