Energy storage device and energy storage system

Abstract

This application provides an energy storage device and an energy storage system. The energy storage device includes a battery electrochemical impedance spectroscopy (EIS) acquisition device and a battery pack. The battery pack includes multiple batteries. The acquisition device provided in this application can achieve multi-channel acquisition and supports independent acquisition of EIS data from multiple batteries. Specifically, the acquisition device includes a main control board and multiple slave control boards. The multiple slave control boards are cascaded, with the first-level slave control board connected to the main control board to receive acquisition commands from the main control board. These acquisition commands are transmitted step-by-step from the first-level slave control board to subsequent slave control boards. The last-level slave control board is also connected to the main control board to transmit the EIS data acquired by the multiple slave control boards to the main control board. Here, subsequent slave control boards include all slave control boards except the first-level slave control board. The acquisition device provided in this application also solves the problem of poor scalability caused by single-channel EIS acquisition devices.

Description

Technical Field

[0001] This application relates to the field of battery technology, and more particularly to energy storage devices and energy storage systems. Background Technology

[0002] Electrochemical impedance spectroscopy (EIS) of a battery can be used to analyze the battery's state. EIS includes the battery's internal impedance when stimulated by excitation signals of different frequencies. The excitation signal can include the current applied to the battery, also known as the excitation current. The battery's EIS reflects its internal electrochemical state and can be used to analyze the battery's condition, for example, to determine if the battery is faulty.

[0003] However, traditional EIS acquisition mostly relies on expensive electrochemical workstations, which are bulky and cannot be deployed in the limited space around the battery to complete EIS acquisition. Although some EIS acquisition devices exist that can be deployed around the battery, they are limited by single-channel acquisition, only able to acquire the EIS of one battery at a time. For battery packs with multiple cells, it is difficult to achieve good EIS acquisition results.

[0004] Therefore, how to collect the battery's EIS is a question worth discussing. Utility Model Content

[0005] This application provides an energy storage device and an energy storage system. The energy storage device includes a battery electrochemical impedance spectroscopy (EIS) acquisition device and a battery pack. The acquisition device is used to reasonably acquire the EIS of each battery in the battery pack.

[0006] In a first aspect, embodiments of this application provide an energy storage device, which includes a battery electrochemical impedance spectroscopy (EIS) acquisition device and a battery pack. The battery pack includes multiple batteries. The acquisition device includes a main control board and multiple slave control boards, which are cascaded. The first-level slave control board is connected to the main control board and is used to receive acquisition commands from the main control board. The acquisition commands are transmitted step by step from the first-level control board to the subsequent-level slave control boards. The last-level slave control board is connected to the main control board and is used to transmit the EIS acquired by the multiple slave control boards to the main control board. Each of the multiple slave control boards is coupled to one of the multiple batteries. The slave control board is connected to the negative electrode of the coupled battery and is used to output an excitation current of a preset frequency to the negative electrode of the coupled battery. The preset frequency is derived from the acquisition command. The slave control board is connected to the positive electrode of the coupled battery and is used to acquire the response voltage of the coupled battery under the excitation current. The slave control board is used to determine the EIS of the coupled battery based on the response voltage and the excitation current.

[0007] In the above embodiments, each battery in the battery pack is equipped with a slave control board, which can independently collect the EIS of different batteries, resulting in high acquisition efficiency. Furthermore, multiple slave control boards and the master control board form a communication link through a master-slave chain structure. Among the multiple slave control boards, only the wiring between the first-level slave control board and the last-level slave control board and the master control board is required. It is evident that the master-slave chain structure makes the acquisition device highly scalable. For example, when adding a slave control board coupled to a new battery, simply inserting it into the communication link completes the expansion of the master-slave chain structure. This avoids increased wiring difficulty due to a large number of batteries, allowing for flexible adaptation to large-scale battery packs.

[0008] In conjunction with the first aspect, in some embodiments, adjacent slave control boards among the plurality of slave control boards acquire EIS at different times, while non-adjacent slave control boards among the plurality of slave control boards acquire EIS at the same time.

[0009] In the above embodiments, electromagnetic interference caused by synchronous excitation is eliminated by staggering the acquisition timing of adjacent slave control boards. This allows non-adjacent slave control boards to work synchronously, shortening the overall acquisition cycle while ensuring accuracy.

[0010] In conjunction with the first aspect, in some embodiments, the control board is located on the aluminum busbar of the battery to which it is coupled.

[0011] In the above embodiments, the control board is directly integrated into the battery aluminum busbar, which shortens the excitation current transmission path and reduces the impact of line impedance on the attenuation of the excitation current.

[0012] In conjunction with the first aspect, in some embodiments, a slave control board is disposed on the aluminum busbar of the coupled battery, comprising: one end of the slave control board is welded to the aluminum busbar coupled to the negative electrode tab of the coupled battery via a first metal sheet, the first metal sheet having the same material as the negative electrode tab; the other end of the slave control board is welded to the aluminum busbar coupled to the positive electrode tab of the coupled battery via a second metal sheet, the second metal sheet having the same material as the positive electrode tab.

[0013] In the above embodiments, the control board is welded to the aluminum busbar using a metal sheet of the same material as the tab (e.g., a nickel sheet connecting to a nickel tab). In practice, it has been found that dissimilar metals are prone to contact resistance, while using the same metal can avoid introducing additional resistance and interfering with EIS data acquisition.

[0014] In conjunction with the first aspect, in some embodiments, the slave control board is equipped with an EIS acquisition chip and an excitation resistor. The EIS acquisition chip includes a positive voltage sampling terminal, a negative voltage sampling terminal, an acquisition signal input terminal, and an acquisition signal output terminal. The EIS acquisition chip is connected to the negative terminal of the battery coupled to the slave control board via the excitation resistor, providing an excitation voltage of a preset frequency to the excitation resistor. This excitation voltage forms the excitation current through the excitation resistor. The positive voltage sampling terminal of the EIS acquisition chip is connected to the positive terminal of the battery, and the negative voltage sampling terminal is connected to the negative terminal of the battery. Used to acquire the battery's response voltage under the excitation current; the cascade includes: the acquisition signal output terminal of the EIS acquisition chip on a slave control board is connected to the acquisition signal input terminal of the EIS acquisition chip on the next slave control board; the first-level slave control board among the multiple slave control boards is connected to the master control board, specifically including: the acquisition signal input terminal of the EIS acquisition chip on the first-level slave control board is connected to the master control board; the last-level slave control board among the multiple slave control boards is connected to the master control board, specifically including: the acquisition signal output terminal of the EIS acquisition chip on the last-level slave control board is connected to the master control board.

[0015] In the above embodiment, the EIS acquisition chip and the excitation resistor are separated. This layout reduces thermal coupling interference between the EIS acquisition chip and the excitation resistor through physical isolation, and avoids temperature drift of the EIS acquisition chip caused by the excitation resistor overheating.

[0016] In conjunction with the first aspect, in some embodiments, the slave control board further includes a switching circuit connected between the EIS acquisition chip and the excitation resistor, the switching frequency of which is used to control the frequency of the excitation current.

[0017] In the above embodiments, the switching circuit is used to dynamically switch the excitation current frequency to generate multi-frequency current in order to realize EIS acquisition.

[0018] In conjunction with the first aspect, in some embodiments, the EIS acquisition chip further includes a voltage output terminal and a control signal output terminal. The switching circuit is a field-effect transistor (FET). The control signal output terminal is connected to the control terminal of the FET, the voltage output terminal is connected to the source terminal of the FET, and the drain terminal of the FET is connected to the excitation resistor. The EIS acquisition chip outputs a control signal to the FET through the control signal output terminal, the frequency of which is used to control the switching frequency of the FET. The EIS acquisition chip outputs a first voltage to the FET through the voltage output terminal, and this first voltage is converted by the FET into an excitation voltage of a preset frequency through the control signal, and provided to the excitation resistor.

[0019] In the above embodiments, the field-effect transistor is used as a switching circuit, and the voltage output terminal directly drives the field-effect transistor, thereby improving the system integration.

[0020] In conjunction with the first aspect, in some embodiments, the EIS acquisition chip further includes an excitation voltage output terminal for providing an excitation voltage of the preset frequency to the excitation resistor.

[0021] In conjunction with the first aspect, in some embodiments, the EIS acquisition chip further includes a power supply terminal connected to the battery coupled to the slave control board, for receiving power from the battery, which is used to generate the excitation voltage.

[0022] In the above embodiments, the EIS acquisition chip draws power directly from the battery under test (the battery coupled to the control board), without relying on an external power source, thus reducing system complexity. Compared to methods that rely on an external power source, the excitation voltage in the above embodiments is generated by converting the battery voltage. The battery and the EIS acquisition chip are close together, which ensures that the excitation current is accurately injected into the negative terminal of the battery, avoiding external interference and thus improving the acquisition quality of EIS.

[0023] In conjunction with the first aspect, in some embodiments, there are multiple excitation resistors connected in parallel.

[0024] In the above embodiments, the parallel design of multiple excitation resistors can expand the current output capability and adapt to the excitation requirements of different batteries. Furthermore, by shunting the current, the heat loss of a single resistor is reduced, avoiding EIS measurement errors caused by resistor temperature drift.

[0025] In conjunction with the first aspect, in some embodiments, when a slave control board is not a primary slave control board, the slave control board inputs the EIS acquired by the slave control board and the EIS acquired by all the preceding slave control boards through the acquisition signal output terminal of its EIS acquisition chip to the acquisition signal input terminal of the EIS acquisition chip on the next lower slave control board; when a slave control board is a primary slave control board, the slave control board inputs the EIS acquired by the slave control board through the acquisition signal output terminal of its EIS acquisition chip to the acquisition signal input terminal of the EIS acquisition chip on the next lower slave control board.

[0026] In the above embodiments, the front-end slave control board aggregates EIS and transmits it to the rear-end slave control board. The main control board only needs to obtain the EIS of each battery from the last-end slave control board, which simplifies the process of the main control board obtaining EIS.

[0027] In conjunction with the first aspect, in some embodiments, the slave control board transmits acquisition commands to the acquisition signal input terminal of the EIS acquisition chip on the next lower slave control board through the acquisition signal output terminal of its EIS acquisition chip.

[0028] In the above embodiments, after the acquisition command is transmitted from the main control board to the first-level slave control board, it is transmitted level by level to the subsequent slave control boards, which simplifies the process of the main control board transmitting the acquisition command.

[0029] In conjunction with the first aspect, in some embodiments, the slave control board further includes a first interface, which is located at the acquisition signal input terminal of the EIS acquisition chip on the slave control board, for converting a first acquisition signal of a first form into a second form of a first acquisition signal. The second form is the form of the acquisition signal transmitted by the acquisition signal input terminal, and the first form is the form of the acquisition signal transmitted by the first interface. The first acquisition signal includes acquisition instructions from the master control board or the previous slave control board, and / or EIS from the previous slave control board.

[0030] In the above embodiments, the first interface can be interface 1 in the specification. The first interface can realize signal form conversion (such as level conversion), can be compatible with different communication protocols, and enhance system adaptability.

[0031] In conjunction with the first aspect, in some embodiments, the slave control board further includes a second interface, which is located at the acquisition signal output terminal of the EIS acquisition chip on the slave control board. This second interface is used to convert a second acquisition signal in a third form into a second acquisition signal in a first form. The third form is the form of the acquisition signal transmitted by the acquisition signal output terminal, and the first form is the form of the acquisition signal transmitted by the first interface on the next-level slave control board. The second acquisition signal includes an EIS acquisition command sent to the next-level slave control board, and / or an EIS signal sent to the next-level slave control board.

[0032] In the above embodiments, the second interface can be interface 2 as described in the specification. The second interface can realize signal form conversion (such as level conversion), can be compatible with different communication protocols, and enhance system adaptability.

[0033] In conjunction with the first aspect, in some embodiments, the slave control board also includes a pressure relief valve reserved hole, which is disposed opposite to the pressure relief valve of the battery, and the edge of the pressure relief valve reserved hole surrounds the edge of the pressure relief valve.

[0034] In the above embodiments, the design of the pre-drilled hole in the pressure relief valve not only saves material and reduces the weight of the slave control board, but also allows the high-temperature, high-pressure gas ejected from the pressure relief valve to escape through the pre-drilled hole when the battery opens the pressure relief valve to release pressure due to overheating and overpressure. This prevents the high-temperature, high-pressure gas from being sprayed onto the slave control board and causing damage to it.

[0035] In conjunction with the first aspect, in some embodiments, the main control board runs a battery detection model, which is used to determine the state of the battery through the battery's EIS, including whether the battery is faulty.

[0036] In the above embodiments, the main control board has a built-in battery detection model that analyzes the battery's EIS in real time, identifies battery faults, and thus achieves preventive maintenance.

[0037] Secondly, embodiments of this application provide an energy storage system, which includes a charge / discharge control module, a power conversion module, and at least one energy storage device; wherein the energy storage device is the energy storage device involved in any of the embodiments of the first aspect, and the power conversion module includes an AC-DC conversion module and / or a DC-DC conversion module.

[0038] The energy storage system of the second aspect includes the energy storage device involved in any of the embodiments of the first aspect. Other beneficial effects that it can achieve can be referred to the beneficial effects in the first aspect, and will not be repeated here. Attached Figure Description

[0039] Figure 1 Schematic diagrams of two single-channel EIS acquisition devices are shown;

[0040] Figure 2 A schematic diagram showing the data acquisition device according to an embodiment of this application arranged on a battery pack is shown;

[0041] Figure 3 A schematic diagram of the layout of the slave control board in the EIS acquisition device is shown;

[0042] Figure 4 A schematic diagram is shown showing a master-slave chain structure formed by a master control board and multiple slave control boards.

[0043] Figure 5 A schematic diagram of the transmission of acquisition commands is shown;

[0044] Figure 6 This diagram illustrates a collaborative acquisition of EIS data by the main control board and the slave control board.

[0045] Figure 7 Another schematic diagram shows the collaborative acquisition of EIS data by the main control board and the slave control board;

[0046] Figure 8 An exemplary equivalent circuit diagram of a battery is shown;

[0047] Figure 9 An exemplary flowchart is shown for determining the battery state using EIS (Electronic Information System).

[0048] Figure 10 An exemplary flowchart for determining battery parameters is shown;

[0049] Figure 11 Another exemplary flowchart for determining battery parameters is shown;

[0050] Figure 12 An exemplary flowchart for classifying batteries is shown. Detailed Implementation

[0051] Some single-channel EIS acquisition devices are limited by their single-channel acquisition capability when acquiring battery EIS data. Here, single-channel acquisition means that the EIS acquisition device can only acquire the EIS data of one battery at a time and does not support independent acquisition of the EIS data of multiple batteries. This lack of support includes the following two situations.

[0052] Scenario 1: When multiple batteries exist, it is necessary to switch the battery being collected from and collect data one by one. For example, see... Figure 1 The EIS acquisition device shown in Figure (1) allows the switching circuit 4 to switch the batteries connected to the VI conversion circuit 3 and the sampling circuit 5 under the control of the processor 1. Subsequently, the signal generator 2 and the VI conversion circuit 3 are used as excitation power sources to provide excitation current to the connected individual batteries. The sampling circuit 5 then collects the response voltage of the individual battery generated by the excitation current and transmits it back to the processor 1. The processor 1 then determines the EIS of the individual battery based on the excitation current and its corresponding response voltage. The aforementioned battery switching operation can be repeated, allowing the EIS acquisition device to collect the EIS of different batteries in the battery pack 6 one by one.

[0053] Scenario 2: Only EIS data can be collected for a single battery. For example, see... Figure 1 The EIS acquisition device shown in Figure (2) uses an AC220V switching power supply (S1), a linear excitation power supply, and a signal generator (S2) as excitation power supplies to provide excitation current to the battery. The signal acquisition and processing device (S4) acquires the response voltage generated by the battery due to the excitation current, and then determines the battery's EIS. However, this EIS acquisition device can only acquire the EIS of a single battery and is not equipped with a switching circuit, so it cannot switch the acquired battery.

[0054] It's important to note that the EIS acquisition device can acquire a response voltage once by applying an excitation current (frequency 1) to the battery. This allows the device to determine the battery's impedance when an excitation current of frequency 1 is applied. By changing the frequency of the excitation current, the EIS acquisition device can obtain the battery's impedance when different frequencies of excitation current are applied, thus completing the EIS acquisition.

[0055] As mentioned above, single-channel EIS acquisition devices have poor scalability. The more batteries there are, the more wiring is required when switching between batteries being acquired, making wiring difficult and unable to flexibly adapt to large-scale battery packs. Furthermore, batteries farther away from the acquisition module are more susceptible to interference when acquiring their EIS data due to the longer wiring, resulting in poorer EIS quality.

[0056] The above Figure 1The two EIS acquisition devices involved are limited not only by single-channel acquisition but also by the external excitation power supply, resulting in poor EIS acquisition quality. Here, the external excitation power supply refers to a power source outside the battery.

[0057] refer to Figure 1 The EIS acquisition device shown in (1) has an external signal generator 2 and a VI conversion circuit 3 as an external excitation power supply, which is used to provide excitation current at different frequencies to the battery connected to the VI conversion circuit 3.

[0058] See again Figure 1 The EIS acquisition device shown in (2) has an external AC220V switching power supply (S1), a linear excitation power supply and a signal generator (S2) as an external excitation power supply, which is used to provide excitation current at different frequencies to the battery (S3).

[0059] Typically, the external excitation power supply is far from the battery. When the excitation power supply is transmitted from the external excitation power supply to the battery, the excitation current is easily distorted during long-distance transmission. When the excitation current is distorted, the acquired EIS is also distorted, with poor quality, and cannot accurately reflect the state of the battery.

[0060] To address the poor scalability issue of the aforementioned single-channel EIS acquisition devices, this application provides an energy storage device. This energy storage device includes a battery electrochemical impedance spectroscopy (EIS) acquisition device (hereinafter referred to as the acquisition device) and a battery pack. The battery pack includes multiple batteries (also referred to as a battery array). The acquisition device provided in this application can achieve multi-channel acquisition, supporting independent acquisition of EIS data from multiple batteries. Specifically, the acquisition device includes a main control board and multiple slave control boards. The multiple slave control boards are cascaded. The first-level slave control board is connected to the main control board and is used to receive acquisition commands from the main control board. These acquisition commands are transmitted step-by-step from the first-level slave control board to subsequent slave control boards. The last-level slave control board is also connected to the main control board and is used to transmit the EIS data acquired by the multiple slave control boards to the main control board. Here, the subsequent slave control boards include all slave control boards other than the first-level slave control board.

[0061] Multiple slave control boards are each coupled to one of the multiple batteries. Each slave control board is connected to the negative terminal of its coupled battery and outputs an excitation current at a preset frequency derived from a data acquisition command to the negative terminal of the coupled battery. The slave control board is also connected to the positive terminal of the coupled battery and acquires the response voltage of the coupled battery under the excitation current. The response voltage and excitation current are used by the slave control boards to determine the EIS of the coupled battery.

[0062] In some possible cases, acquisition commands are used to control some or all of the slave control boards to acquire EIS. The acquisition commands include control information for each slave control board acquiring EIS. The control information for a slave control board acquiring EIS includes at least one of the following: whether the slave control board is acquiring EIS, and the parameters of the excitation current generated by the slave control board, including the frequency of the excitation current.

[0063] It should be noted that different slave control boards are coupled to different batteries. Multiple slave control boards and the master control board form a master-slave chain structure, also known as a daisy-chain structure. Under the control of the master control board, different slave control boards can be used to independently collect the EIS of the batteries coupled to the slave control board.

[0064] In some embodiments, the slave control board is equipped with an EIS acquisition chip and an excitation resistor. The EIS acquisition chip includes a voltage sampling positive terminal, a voltage sampling negative terminal, an acquisition signal input terminal, and an acquisition signal output terminal. The aforementioned cascading of multiple slave control boards includes: the acquisition signal output terminal of the EIS acquisition chip on one slave control board is connected to the acquisition signal input terminal of the EIS acquisition chip on the next-level slave control board. The aforementioned acquisition of the EIS of the coupled battery by the slave control board is achieved through the EIS acquisition chip and the excitation resistor, including: the EIS acquisition chip inputs an excitation current of a preset frequency to the negative terminal of the coupled battery of the slave control board through the excitation resistor; and the EIS acquisition chip is also used to acquire the response voltage generated by the excitation current of the coupled battery of the slave control board to determine the EIS of the coupled battery. Detailed information is not elaborated here, but can be found in the following description. Figure 2 , Figure 6 and Figure 7 The description.

[0065] The EIS acquisition chip, through an excitation resistor, inputs an excitation current of a preset frequency to the negative terminal of the battery coupled to the slave control board. This includes: the EIS acquisition chip connecting to the negative terminal of the battery coupled to the slave control board via the excitation resistor to provide an excitation voltage of a preset frequency to the excitation resistor; the excitation voltage forming an excitation current through the excitation resistor; and the excitation resistor then inputting the excitation current of the preset frequency to the negative terminal of the battery coupled to the slave control board. The EIS acquisition chip also acquires the response voltage of the battery coupled to the slave control board.

[0066] The EIS acquisition chip is also used to acquire the response voltage of the battery coupled to the control board due to the excitation current, and then determine the EIS of the battery coupled to the control board based on the excitation current and its corresponding excitation voltage. Acquiring the response voltage of the battery coupled to the control board due to the excitation current includes: connecting the positive voltage sampling terminal of the EIS acquisition chip to the positive terminal of the battery coupled to the control board, and connecting the negative voltage sampling terminal to the negative terminal of the battery coupled to the control board, for acquiring the response voltage of the battery coupled to the control board under the excitation current.

[0067] It should also be noted that the battery's EIS includes the battery's internal impedance when subjected to excitation currents of different preset frequencies. The number of preset excitation current frequencies corresponds to the number of impedances. The impedance corresponding to an excitation current of a preset frequency can be represented by the battery's resistance and reactance when that excitation current is applied. The battery's resistance and reactance can be determined by the excitation current and its corresponding response voltage. This is typically expressed as the complex number Z(f) = R + jX. Here, Z(f) represents the impedance corresponding to the excitation current at preset frequency f, R represents the resistance, which can be represented by dividing the battery's response voltage at excitation current (frequency f) by the excitation current (frequency f), X represents the reactance, which can be represented by the phase difference between the battery's response voltage at excitation current (frequency f) and the excitation current (frequency f). j is the imaginary unit.

[0068] like Figure 2 The diagram shown is a schematic of the data acquisition device arranged on a battery pack according to an embodiment of this application.

[0069] Figure 2 The example described uses a battery pack containing 8 batteries and 8 slave control boards. In practice, there may be more or fewer batteries and slave control boards, which should not be construed as limiting the embodiments of this application.

[0070] like Figure 2 As shown, the battery pack is encapsulated within a battery stack. A main control board (e.g., main control board 11) can be located on one side of the battery stack. Multiple slave control boards can be located on the other side of the battery stack (denoted as side 1). Optionally, side 1 may include aluminum busbars for the batteries. The slave control boards are located on the aluminum busbars of the batteries they are coupled to.

[0071] One of the battery's aluminum busbars can be arranged on both the positive and negative terminals of the battery. This is used to connect the battery in series or in parallel with other batteries.

[0072] Continue to refer to Figure 2 A slave control board is fixed to its next-level slave control board via a single-board series bridge 15. The wiring used when a slave control board is connected to its next-level slave control board can pass through the single-board series bridge 15. If there are L slave control boards, there are L-1 single-board series bridges 15. Wiring between slave control boards can be arranged on the single-board series bridge 15 to realize the cascading of multiple slave control boards.

[0073] Continue to refer to Figure 2The control board (e.g., control board 12) is disposed on the aluminum busbar (e.g., aluminum busbar 14) of the coupled battery (e.g., battery 13), including: one end of the control board is disposed on the aluminum busbar (e.g., aluminum busbar 141) coupled to the negative electrode tab of the coupled battery, and the other end of the control board is disposed on the aluminum busbar (e.g., aluminum busbar 142) coupled to the positive electrode tab of the coupled battery.

[0074] An exemplary configuration of the aforementioned EIS acquisition chip and excitation resistor on the slave control board can be referenced to the EIS acquisition chip 121 and excitation resistor 122 configured on slave control board 12. The EIS acquisition chip on the slave control board is located near the positive terminal of the battery coupled to the slave control board, and the excitation resistor is located near the negative terminal of the battery coupled to the slave control board. This arrangement reduces thermal coupling interference between the EIS acquisition chip and the excitation resistor through physical isolation, preventing the excitation resistor from heating up and causing temperature drift in the EIS acquisition chip. Furthermore, the positive terminal is the main area where the battery's electrochemical reaction occurs; placing the EIS acquisition chip near the positive terminal facilitates the acquisition of the response voltage by the EIS acquisition chip; placing the excitation resistor near the negative terminal shortens the distance between the excitation resistor and the negative terminal, ensuring that the excitation current of the preset frequency is accurately injected into the negative terminal from the excitation resistor.

[0075] It should be noted that the above description is based on the example of slave control board 12. For descriptions of slave control boards other than slave control board 12, or multiple slave control boards, please refer to the description of slave control board 12; this application embodiment will not repeat those descriptions.

[0076] It should also be noted that the aforementioned Figure 2 In this embodiment, it is optional to place the main control board and the slave control board on different sides of the battery pack. They can also be placed on the same side, depending on the design, and this should not constitute a limitation on the embodiments of this application.

[0077] The foregoing Figure 2 The slave control board 12 shown is merely an illustrative example and should not be construed as limiting the embodiments of this application. Optionally, the slave control board may have more features and implement richer functions than slave control board 12. For example, a pressure relief valve pre-drilled hole may also be provided in the slave control board. This pressure relief valve pre-drilled hole is provided opposite to the pressure relief valve of the battery coupled to the slave control board, and the edge of the pressure relief valve pre-drilled hole surrounds the edge of the pressure relief valve. This design of the pressure relief valve pre-drilled hole not only saves materials and reduces the weight of the slave control board, but also allows the high-temperature and high-pressure gas ejected from the pressure relief valve to be discharged through the pressure relief valve pre-drilled hole when the battery opens the pressure relief valve to release pressure due to overheating and overpressure, avoiding the high-temperature and high-pressure gas from being sprayed onto the slave control board and causing damage to the slave control board.

[0078] refer to Figure 3 The slave control board 21 shown in (1) is an exemplary slave control board with a pre-drilled hole for a pressure relief valve. (See reference...) Figure 3As shown in the schematic diagram of the coupling between the slave control board 21 and the battery and the exploded analysis view in (1), it can be seen that the pressure relief valve reserved hole 211 in the slave control board is opposite to the pressure relief valve 22 of the battery coupled to the slave control board 21, and the edge of the pressure relief valve reserved hole 211 surrounds the edge of the pressure relief valve 22.

[0079] It should be noted that, similar to the aforementioned slave control board 12, slave control board 21 also has an EIS acquisition chip and an excitation resistor, only... Figure 3 Not shown in the image. Please refer to the preceding text for details. Figure 2 The layout of the interior is not described in detail here.

[0080] The aforementioned configuration involves a control board with one end attached to the aluminum busbar coupled to the negative electrode tab of the coupled battery, and the other end attached to the aluminum busbar coupled to the positive electrode tab of the coupled battery. This includes: one end of the control board being welded to the aluminum busbar coupled to the negative electrode tab of the coupled battery via a metal sheet 1, which is made of the same material as the negative electrode tab; and the other end of the control board being welded to the aluminum busbar coupled to the positive electrode tab of the coupled battery via a metal sheet 2, which is made of the same material as the positive electrode tab. Typically, the positive and negative electrode tabs are made of nickel, so metal sheets 1 and 2 can be nickel sheets. In practice, it has been found that maintaining the same material between the metal sheets and the tabs (including metal sheet 1 and the negative electrode tab, and metal sheet 2 and the positive electrode tab) during welding can eliminate contact resistance between the metal sheets and the tabs, avoiding the introduction of additional resistance and interference with EIS data acquisition.

[0081] Figure 3 (2) is an exemplary side view after welding is completed. Reference Figure 3 (2) and Figure 3 In section (1), an exemplary description is given of the soldering of the control board onto the aluminum busbar. Each end of the control board 21 may include at least one soldering pin for soldering to a metal sheet, thereby soldering the control board onto the aluminum busbar. For example, the end of the control board 21 near the negative electrode may include two soldering pins 212, which are soldered to one end of a metal sheet 231, and the other end of the metal sheet 231 is soldered to an aluminum busbar (e.g., aluminum busbar 141) on the negative electrode tab, such that one end of the control board is located on the aluminum busbar coupled to the negative electrode tab of the battery to which it is coupled. The end of the control board 21 near the positive electrode may include two soldering pins 213, which are soldered to one end of a metal sheet 232, and the other end of the metal sheet 232 is soldered to an aluminum busbar (e.g., aluminum busbar 142) on the positive electrode tab, such that the other end of the control board is located on the aluminum busbar coupled to the positive electrode tab of the battery to which it is coupled.

[0082] Alternatively, laser welding can be used to avoid the interference caused by weld beads formed when using tin soldering.

[0083] Figure 4 A schematic diagram is shown showing a master-slave chain structure formed by a master control board and multiple slave control boards.

[0084] like Figure 4 As shown, in the master-slave chain structure, the master control board is connected in series with multiple cascaded slave control boards to form a communication link, from master control board → slave control board 1 → slave control board 2 → slave control board 3 → ... → slave control board Z → master control board. Figure 4 The example given is where Z is an integer greater than 3. However, in practice, the total number of slave control boards can be greater than... Figure 4 For more or less, Z can be an integer greater than or equal to 2.

[0085] Of multiple slave control boards, only the primary slave control board (equivalent to...) is needed. Figure 4 The slave control board 1) and the final slave control board (equivalent to Figure 4 The wiring between the slave control board (Z) and the main control board is described above. For example, the partial wiring between the first-level slave control board and the last-level slave control board and the main control board can be referred to the above. Figure 2 Wiring 16 is shown in the diagram. It is evident that the master-slave chain structure makes the acquisition device highly scalable. For example, when adding a slave control board coupled to a new battery, simply inserting it into the communication link completes the expansion of the master-slave chain structure. This avoids increased wiring difficulty due to a large number of batteries and allows for flexible adaptation to large-scale battery packs.

[0086] The main control board acts as the control center, controlling multiple slave control boards to independently acquire the EIS of the coupled battery via acquisition commands, making the acquisition process less susceptible to interference. The control process by which the main control board controls multiple slave control boards to acquire the EIS can include, but is not limited to, the following control process 1 or control process 2.

[0087] In control process 1, when the EIS includes the impedances corresponding to the excitation currents at Q preset frequencies, the main control board can send Q acquisition commands (denoted as acquisition command a) to the first-level slave control board according to a preset cycle. Each of the Q acquisition commands a carries one of the Q preset frequencies, and the preset frequencies carried in different acquisition commands a are different. The control information of acquisition command a indicates that the slave control board receiving the acquisition command needs to acquire the EIS. The Q acquisition commands a are transmitted sequentially to all slave control boards, controlling each slave control board to acquire the EIS of the coupled battery. This process includes: after the main control board sends an acquisition command a to the first-level slave control board, the first-level slave control board transmits the acquisition command a sequentially to the subsequent slave control boards. After receiving the acquisition command, each slave control board can acquire the impedance corresponding to the preset frequency carried in the acquisition command a. This process is repeated Q times, and each time the preset frequency of the excitation current carried in the acquisition command a needs to be changed. Here, Q is an integer greater than 1.

[0088] In control process 2, to further reduce interference when the slave control board acquires EIS data, adjacent slave control boards will not acquire EIS data simultaneously. Adjacent slave control boards acquire EIS data at different times, while non-adjacent slave control boards acquire EIS data at the same time. This can be understood as including slave control board 1 and slave control board 2. Slave control board 1 and slave control board 2 are adjacent; that is, if slave control board 1 has a next-level slave control board, its next-level slave control board is slave control board 2, and if slave control board 2 has a next-level slave control board, its next-level slave control board is slave control board 1. A single acquisition command sent by the master control board only controls slave control board 1 or slave control board 2 to acquire EIS data, including: the master control board sending acquisition command 1 to the first-level slave control board, acquisition command 1 being used to control slave control board 1 to acquire EIS data at time 1. The main control board sends acquisition command 2 to the primary slave control board. Acquisition command 2 is used to control the slave control board 2 to acquire EIS at time 2, which is different from time 1.

[0089] In control process 2, when the EIS includes the impedances corresponding to the excitation currents at Q preset frequencies, the main control board can send Q sets of acquisition commands to the primary slave control board according to a preset cycle. Each of the Q sets of acquisition commands carries one preset frequency from the Q preset frequencies. Different sets of acquisition commands carry different preset frequencies, while a single set of acquisition commands carries the same preset frequency. One set of acquisition commands includes the aforementioned acquisition command 1 and acquisition command 2. Acquisition command 1 indicates that slave control board 1 acquires the EIS, while slave control board 2 does not acquire the EIS. Acquisition command 2 indicates that slave control board 2 acquires the EIS, while slave control board 1 does not acquire the EIS.

[0090] The Q-group acquisition command is transmitted sequentially to all slave control boards, controlling each slave control board to acquire the EIS of the coupled battery. This process includes: the master control board sending acquisition command 1 to the first-level slave control board, which then transmits it to subsequent slave control boards. Although all slave control boards receive acquisition command 1, only slave control board 1's control information indicates EIS acquisition, therefore only slave control board 1 responds to acquisition command 1. The master control board then sends acquisition command 2 to the first-level slave control board. This acquisition command 2 is transmitted from the first-level slave control board to subsequent slave control boards. Although all slave control boards receive acquisition command 2, only slave control board 2's control information indicates EIS acquisition, therefore only slave control board 2 responds to acquisition command 2. This process is repeated Q times, each time requiring a change in the preset frequency of the excitation current in acquisition commands 1 and 2.

[0091] Since the transmission speed of acquisition commands on the communication link is very fast, it can be ignored. Therefore, in control process 1, it can be considered that each slave control board acquires EIS simultaneously. In control mode 2, it can be considered that slave control board 1 acquires EIS simultaneously, and slave control board 2 acquires EIS simultaneously. It can be seen that the acquisition device provided in this application embodiment has high acquisition efficiency, and compared with the aforementioned single-channel EIS acquisition device, the acquisition efficiency of the acquisition device provided in this application embodiment is not affected by the number of batteries in the battery pack.

[0092] It should be noted here that, in combination Figure 4 and Figure 5 As shown, the component that receives and responds to acquisition commands from the control board is the EIS acquisition chip on the control board. Figure 5 The acquisition chips 1-Z are located respectively in Figure 4 The system comprises slave control boards 1 through Z. Each EIS acquisition chip includes an acquisition signal input terminal and an acquisition signal output terminal. A slave control board can transmit acquisition commands to the acquisition signal input terminal of the EIS acquisition chip on the next-level slave control board via the acquisition signal output terminal of its EIS acquisition chip. It is understood that the acquisition signal input terminal of the EIS acquisition chip on the primary slave control board (e.g., EIS acquisition chip 1) is used to receive acquisition commands sent by the primary control board. The acquisition signal input terminals of non-primary slave control boards (e.g., EIS acquisition chips 2 through Z) are used to receive acquisition commands sent by the previous-level slave control board. These acquisition commands may include the aforementioned acquisition command a, acquisition command 1, and acquisition command 2.

[0093] The slave control board also needs to return the acquired EIS data to the master control board level by level through the EIS acquisition chip. Specifically, this return of EIS data can be achieved through the acquisition signal input and output terminals of the EIS acquisition chip. Optionally, if a slave control board is not the primary slave control board, it inputs the EIS data acquired by itself and all the EIS data acquired by its preceding slave control boards to the acquisition signal input terminal of the EIS acquisition chip on the next lower-level slave control board through the acquisition signal output terminal of its EIS acquisition chip. If a slave control board is the primary slave control board, it inputs the EIS data acquired by itself to the acquisition signal input terminal of the EIS acquisition chip on the next lower-level slave control board through the acquisition signal output terminal of its EIS acquisition chip.

[0094] Continue to refer to Figure 4The control board also includes interface 1, which is located at the acquisition signal input terminal of the EIS acquisition chip on the control board. Interface 1 is used to convert the first form of acquisition signal 1 into a second form of acquisition signal 1. The second form is the form of the acquisition signal transmitted by the acquisition signal input terminal, and the first form is the form of the acquisition signal transmitted by interface 1. Here, acquisition signal 1 is the acquisition signal from the upper level (including the previous level slave control board or master control board) of the control board, including acquisition commands from the master control board or the previous level slave control board, and / or, EIS from the previous level slave control board. Based on the foregoing, the EIS from the previous level slave control board includes the EIS acquired by all the preceding slave control boards.

[0095] It should be noted that configuring interface 1 on the slave control board is optional. If the acquisition signal from the upper level is compatible with the acquisition signal format transmitted by the acquisition signal input terminal of the EIS acquisition chip on the slave control board, then interface 1 does not need to be configured on the slave control board.

[0096] The slave control board also includes interface 2, which is located at the acquisition signal output terminal of the EIS acquisition chip on the slave control board. Interface 2 is used to convert the third form of acquisition signal 2 into the first form of acquisition signal 2. The third form is the form of the acquisition signal transmitted by the acquisition signal output terminal, and the first form is the form of the acquisition signal transmitted by interface 1 on the next-level slave control board. Here, acquisition signal 2 is the acquisition signal transmitted to the lower level (including the next-level slave control board or the master control board) of the slave control board, including EIS acquisition commands sent to the next-level slave control board, and / or EIS signals sent to the next-level slave control board or transmitted to the master control board. Based on the foregoing, the EIS signals sent to the next-level slave control board include the EIS signals acquired by the slave control board and all the preceding slave control boards. The EIS signals sent to the master control board include the EIS signals acquired by multiple slave control boards.

[0097] It should be noted that configuring interface 2 on the slave control board is optional. If the acquisition signal sent to the lower level is compatible with the acquisition signal format transmitted by the acquisition signal output terminal of the EIS acquisition chip on the slave control board, then interface 2 does not need to be configured on the slave control board.

[0098] Optionally, Interface 1 and Interface 2 can be the same or different interfaces. When Interface 1 and Interface 2 are the same interface, that same interface must have the functionality of both Interface 1 and Interface 2. The functionality of Interface 1 and Interface 2 can be found in the descriptions above, and will not be repeated here.

[0099] In practice, it has been found that when the main control board transmits signals (including acquisition commands), these signals are easily interfered with by high-frequency noise and transient high voltage in the main control board, becoming low-quality signals with a low signal-to-noise ratio. This causes a surge in the bit error rate when the primary slave control board receives acquisition commands. (Continue to refer to...) Figure 4In order to enable the main control board to better communicate with the primary slave control board (e.g. Figure 4 The master control board 1 transmits acquisition commands. The master control board also includes an isolation communication transformer, denoted as isolation communication transformer 1. This isolation communication transformer 1 is located at interface 1 on the master control board and can be used to isolate high-frequency noise and transient high voltage in the acquisition commands. Acquisition commands from the master control board are isolated by the isolation communication transformer 1 and then transmitted to the EIS acquisition chip 1 on the master control board 1 via interface 1, ensuring that the EIS acquisition chip 1 receives high-quality EIS acquisition commands. This, in turn, allows subsequent master control boards to also receive high-quality EIS acquisition commands, guaranteeing the quality of the EIS acquired by the EIS acquisition chip.

[0100] In practice, it was also found that when the final-level slave control board transmits signals (including EIS data acquired by multiple slave control boards) to the main control board, the signals are also susceptible to interference from high-frequency noise and transient high voltage in the main control board, resulting in low signal-to-noise ratio signals and causing a surge in the bit error rate when the main control board receives EIS data. (Continue to refer to...) Figure 4 In order to enable the final stage to be controlled by the control board (e.g. Figure 4 The slave control board (Z) transmits EIS to the master control board more effectively. The final slave control board also includes an isolation communication transformer, denoted as isolation communication transformer 2. This isolation communication transformer 2 is located at interface 2 on the final slave control board and can be used to isolate high-frequency noise and transient high voltage in the EIS. The EIS transmitted to the master control board is isolated by the isolation communication transformer 2 before being transmitted to the master control board, ensuring the quality of the EIS received by the master control board.

[0101] An example of the isolation communication transformer 1 can be found in the foregoing. Figure 2 The isolation communication transformer 17 is shown in the diagram. An example of the isolation communication transformer 2 can be found in the foregoing. Figure 2 The isolation communication transformer 18 is shown in the figure.

[0102] Continue to refer to Figure 4 The control board also includes a switching circuit connected between the EIS acquisition chip and the excitation resistor. The switching frequency of the switching circuit controls the frequency of the excitation current. For a detailed description of the EIS acquisition chip, switching circuit, and excitation resistor, please refer to the following... Figure 6 The description will not be elaborated here.

[0103] Optionally, to improve the heat dissipation of the excitation resistors, multiple excitation resistors can be used, connected in parallel. For example, excitation resistor 1 to excitation resistor N can be connected in parallel. Compared to a single resistor, to achieve the same excitation current, the heat dissipation area of ​​multiple excitation resistors is larger than that of a single resistor, resulting in better heat dissipation and benefiting EIS data acquisition.

[0104] In combination with the above Figure 4 The main control board and multiple slave control boards involved form a master-slave chain structure, based on Figure 6 Describe in detail the process of EIS acquisition collaboratively by the main control board and the slave control board.

[0105] like Figure 6 As shown, the control board includes an EIS acquisition chip, a switching circuit, and excitation resistors (including excitation resistors 1 and N connected in parallel).

[0106] Figure 6 China is Figure 5 The switching circuit described herein uses a field-effect transistor (FET) as an example. Specifically, this FET can be a metal-oxide-semiconductor FET (MOSFET). In practical applications, besides FETs, the switching circuit can also be other switching components, such as bipolar transistors and insulated-gate bipolar transistors. This application does not limit the specific type of these components.

[0107] like Figure 6 As shown, in addition to the aforementioned voltage sampling positive terminal, voltage sampling negative terminal, acquisition signal input terminal, and acquisition signal output terminal, the EIS acquisition chip also includes a power supply terminal, a voltage output terminal, and a control signal output terminal. An example of an EIS acquisition chip can be found here. Figure 6 Any one or more of the EIS acquisition chips 1-EIS acquisition chips Z shown in the figure.

[0108] The power supply terminal of the EIS acquisition chip is connected to the battery coupled to the control board, specifically to the positive terminal of the battery. This allows the EIS acquisition chip to receive power from the battery coupled to the control board, and the battery power is used to generate an excitation voltage. This excitation voltage is converted into an excitation current of a preset frequency by the EIS acquisition chip through a field-effect transistor and an excitation resistor, and then transmitted to the negative terminal of the battery coupled to the control board. This enables the EIS acquisition chip to acquire and transmit EIS data.

[0109] refer to Figure 6EIS acquisition chip 1 is located on slave control board 1 (an example of a primary slave control board). When the EIS acquisition chip is located on the primary slave control board, its acquisition signal input terminal is connected to the main control board to receive acquisition commands transmitted by the main control board. When the EIS acquisition chip is located on a non-primary slave control board, its acquisition signal input terminal is connected to the acquisition signal output terminal of the previous-level EIS acquisition chip to receive acquisition commands and EIS data transmitted by the previous-level EIS acquisition chip. Here, the previous-level EIS acquisition chip is the EIS acquisition chip on the previous-level slave control board. For example, the previous-level acquisition chip of EIS acquisition chip 2 (located on slave control board 2) is EIS acquisition chip 1 on slave control board 1.

[0110] Referring to the diagram, the EIS acquisition chip Z is located on the final slave control board Z. It can be seen that when the EIS acquisition chip is located on the final slave control board, its acquisition signal output is connected to the main control board, used to transmit EIS data acquired by multiple slave control boards to the main control board. When the EIS acquisition chip is located on a non-final slave control board, its acquisition signal output is connected to the acquisition signal input of the next-level EIS acquisition chip, used to transmit acquisition commands and EIS data to the next-level EIS acquisition chip. Here, the next-level EIS acquisition chip is the EIS acquisition chip on the next-level slave control board. For example, the next-level acquisition chip after EIS acquisition chip 1 (located on slave control board 1) is EIS acquisition chip 2 on slave control board 2.

[0111] It should be noted that the EIS received by the EIS acquisition chip from the previous-level EIS acquisition chip includes: the EIS acquired by all the preceding EIS acquisition chips. This can also be understood as the EIS acquired by all the preceding slave control boards of the slave control board where the aforementioned EIS acquisition chip is located. The EIS transmitted by the EIS acquisition chip to the next-level EIS acquisition chip includes: the EIS acquired by the current EIS acquisition chip and all the preceding EIS acquisition chips. This can also be understood as the EIS acquired by the slave control board where the aforementioned EIS acquisition chip is located and all the preceding slave control boards of that slave control board.

[0112] The control signal output terminal of the EIS acquisition chip is connected to the control terminal (G terminal) of the field-effect transistor (FET), the voltage output terminal is connected to the source terminal (S terminal) of the FET, and the drain terminal (D terminal) of the FET is connected to an excitation resistor (e.g., a parallel excitation resistor I-excitation resistor N). The excitation resistor is connected to the negative terminal of the battery coupled to the slave control board. The EIS acquisition chip applies an excitation current of a preset frequency to the negative terminal of the battery coupled to the slave control board through the voltage output terminal and the control signal output terminal. This process includes: the EIS acquisition chip outputs a control signal to the FET through the control signal output terminal, the frequency of which is used to control the switching frequency of the FET. The frequency of the excitation current is then controlled by the switching frequency of the FET. Furthermore, the EIS acquisition chip outputs a voltage (denoted as voltage I) to the FET through the voltage output terminal. Voltage I is converted into an excitation voltage of a preset frequency by the FET through the control signal and provided to the excitation resistor. The excitation resistor then converts the excitation voltage of the preset frequency into an excitation current of the preset frequency and applies it to the negative terminal of the battery coupled to the slave control board. It should be noted that voltage I is generated using the power supply received from the power supply terminal. The power supply comes from the battery coupled to the control board of the EIS acquisition chip.

[0113] Based on the foregoing, the power supply terminal of the EIS acquisition chip is connected to the battery coupled to its slave control board, specifically to the positive terminal of the battery. The battery's power supply is ultimately used to generate the excitation voltage, which, through the excitation resistor, yields the excitation current. Therefore, the acquisition device provided in this embodiment generates the excitation current in a self-excitation mode, that is, through the power supply of the battery being acquired. (As described above...) Figure 1 Unlike the single-channel acquisition device shown, this one does not require an external excitation power supply. Compared to the distance between an external excitation power supply and the battery, the battery is closer to the EIS acquisition chip, avoiding distortion of the excitation current and improving the quality of the acquired EIS data.

[0114] Among them, voltage 1 is converted into an excitation voltage of a preset frequency by the field-effect transistor through a control signal, including: the field-effect transistor controls the switching frequency of the field-effect transistor according to the frequency of the control signal, so as to convert voltage 1 into an excitation voltage of a preset frequency.

[0115] The positive terminal of the EIS acquisition chip is connected to the positive terminal of the battery coupled to the control board, and the negative terminal is connected to the negative terminal of the battery coupled to the control board. This allows the EIS acquisition chip to acquire the response voltage of the battery coupled to the control board after an excitation current is applied. This response voltage and excitation current are used by the EIS acquisition chip to determine the EIS of the battery coupled to the control board.

[0116] The following is based on Figure 6The provided connection relationships exemplify the process of each EIS acquisition chip responding to acquisition commands from the main control board, acquiring EIS data, and transmitting the acquired EIS data back to the main control board. This process can be implemented at preset time intervals during battery charging and discharging without affecting normal battery use. For example, the battery's EIS data can be acquired every 1 hour. The EIS acquisition involved in this process can also be referred to as online EIS acquisition. Here, 1 hour is just an example; other time intervals, such as 2 hours or 3 hours, can also be used, but this application embodiment does not limit this.

[0117] Continue to refer to Figure 6 After receiving a data acquisition command from the main control board via its data acquisition signal input terminal, EIS acquisition chip 1 acquires the EIS data of the battery coupled to slave control board 1. It then transmits this acquisition command via its data acquisition signal output terminal to the data acquisition chip input terminal of EIS acquisition chip 2, enabling EIS acquisition chip 2 to begin acquiring the EIS data of the battery coupled to slave control board 2. EIS acquisition chip 2 then transmits the acquisition command via its data acquisition signal output terminal to the data acquisition chip input terminal of EIS acquisition chip 3, enabling EIS acquisition chip 3 to acquire the EIS data of the battery coupled to slave control board 3. This process continues until the final-stage EIS acquisition chip (e.g., EIS acquisition chip Z) receives the acquisition command transmitted via its data acquisition signal output terminal from its previous-stage EIS acquisition chip, enabling EIS acquisition chip Z to acquire the EIS data of the battery coupled to slave control board Z. It should be noted that the EIS acquisition here is not completed based on a single acquisition command. Instead, it acquires the response voltage under the excitation current at frequency f according to the preset frequency (denoted as f) in the acquisition command. Then, based on the response voltage and the excitation current at frequency f, it obtains the impedance corresponding to the excitation current at frequency f, which is the process of EIS acquisition. When the EIS includes the impedance corresponding to the excitation current at Q frequencies, the EIS acquisition chip will receive Q acquisition commands (refer to the aforementioned control process 1) or Q groups of acquisition commands (refer to the aforementioned control process 2) from the main control board through the acquisition signal input terminal. Only when the impedance corresponding to the excitation current at Q preset frequencies is acquired according to the Q acquisition commands or Q groups of commands can the EIS acquisition be considered complete.

[0118] This can also be understood as follows: after receiving a acquisition command, an EIS acquisition chip not only needs to acquire the impedance corresponding to the excitation current at a preset frequency according to the preset frequency in the acquisition command to obtain the EIS of the battery coupled to its slave control board, but also needs to transmit the acquisition command to the next-level EIS acquisition chip, so that the next-level EIS acquisition command can acquire the impedance corresponding to the excitation current at a preset frequency according to the preset frequency in the acquisition command to obtain the EIS of the battery coupled to its slave control board.

[0119] After EIS acquisition chip 1 acquires the EIS data of the batteries coupled to control board 1, it transmits the EIS data of the batteries coupled to control board 1 to the acquisition signal input of acquisition chip 2 through the acquisition signal output terminal of EIS acquisition chip 1. After EIS acquisition chip 2 acquires the EIS data of the batteries coupled to control board 2, it transmits the EIS data of the batteries coupled to control board 1 and control board 2 to the acquisition signal input of acquisition chip 3 through the acquisition signal output terminal of EIS acquisition chip 2. This process continues until the final-stage EIS acquisition chip (e.g., EIS acquisition chip Z) acquires the EIS data of Z batteries and transmits it to the main control board.

[0120] It should be noted that the voltages sampled at the positive and negative terminals of the voltage sampling circuit include not only the response voltage but also the battery voltage. The EIS acquisition chip needs to filter out the battery voltage from the sampled voltage to obtain the response voltage.

[0121] It should also be noted that, based on the foregoing Figure 4 As can be seen from the relevant content, the signal input terminal of the EIS acquisition chip can receive acquisition signals (including EIS and acquisition commands) through interface 1 on its slave control board. The signal output terminal of the EIS acquisition chip can transmit acquisition signals (including EIS and acquisition commands) through interface 2 on its slave control board. For details regarding interfaces 1 and 2, please refer to the aforementioned... Figure 4 The description will not be repeated here.

[0122] The foregoing Figure 6 The example given uses N excitation resistors connected in parallel. In practice, however, a single excitation resistor can be used. When the excitation resistor is a single resistor, Figure 6 The component layout and connection relationships in the diagram also apply; simply connect the switching circuit to this single excitation resistor.

[0123] Optionally, when the excitation resistor is a single resistor, an EIS acquisition chip with a built-in switching circuit can be selected to replace the aforementioned one. Figure 6 The EIS acquisition chip involved. See Figure 7As shown, the EIS acquisition chip with a built-in switching circuit does not have a voltage output terminal and a control signal output terminal; instead, it uses an excitation voltage output terminal instead. This excitation voltage output terminal is connected to one end of the switching circuit that outputs the excitation voltage, or it is the end of the switching circuit that outputs the excitation voltage. This excitation voltage output terminal is used to provide an excitation voltage of a preset frequency to the excitation resistor. This excitation voltage is generated by the EIS acquisition chip using voltage 1 through its built-in switching circuit. Voltage 1 is generated using the power supply received from the power supply terminal. This power supply comes from the battery coupled to the control board, which is received by the EIS acquisition chip. The process of generating the excitation voltage can be referred to the aforementioned... Figure 6 The relevant descriptions are omitted here.

[0124] based on Figure 7 The provided connection relationships, the response of each EIS acquisition chip to acquisition commands from the main control board, the process of acquiring EIS data, and the process of transmitting the acquired EIS data back to the main control board are all described. Please refer to the preceding text. Figure 6 The description of the relevant content can be simplified by replacing the content related to the voltage output terminal and the control signal output terminal with the content related to the excitation voltage output terminal. The input and output signals of other ports on the EIS acquisition chip remain unchanged. This application embodiment will not elaborate further on this.

[0125] The EIS (Electrochemical Information System) of a battery reflects its internal electrochemical state. In some embodiments, the main control board can also analyze the battery's state based on the acquired EIS data. For example, it can analyze whether the battery is faulty.

[0126] While the Electrochemical Information System (EIS) of a battery can reflect its internal electrochemical state and be used to analyze its condition, the raw EIS data is quite large. Using it directly increases the analytical complexity and reduces accuracy. Therefore, to reduce analytical complexity and improve accuracy, the battery's EIS data can be converted into smaller battery parameter data, and then the values ​​of these parameters can be used to analyze the battery's state. See the following for details.

[0127] Battery parameters can be represented by components in the battery's equivalent circuit. The values ​​of these parameters can be understood as the magnitudes of these components. The battery's equivalent circuit is composed of components such as resistors, capacitors, and inductors connected in series and / or parallel. The components in the equivalent circuit simulate the complex electrochemical states inside the battery, such as charge transfer states and ion diffusion states.

[0128] The battery parameters include, but are not limited to, at least one of the following: battery inductance, battery ohmic resistance, battery solid electrolyte interphase (SEI) film capacitance, SEI film resistance, battery double layer capacitance, battery charge transfer resistance, and battery Warburg impedance.

[0129] like Figure 8 As shown in Figure (1), this is an exemplary equivalent circuit of a battery. The equivalent circuit is a cascaded circuit consisting of an element representing inductance (denoted as L) → an element representing ohmic resistance (denoted as R0) → an element representing SEI film capacitance (denoted as Csei) in parallel with an element representing SEI film resistance (denoted as Rsei) → an element representing double-layer capacitance (denoted as Cdl) in parallel with an element representing charge transfer resistance (denoted as Rct) → an element representing Warburg impedance (denoted as Zw).

[0130] Where L represents the inductance of the battery, which can be used to simulate the electromagnetic inertial effect of the internal wires, tabs, or current collectors of the battery.

[0131] R0 represents the ohmic resistance of the battery and can be used to simulate the overall ohmic resistance of the battery, including electrolyte ion conduction, electrode material electron migration, and contact resistance.

[0132] Csei represents the SEI film capacitance of the battery, and Rsei represents the SEI film resistance. Csei and Rsei are components reflecting the SEI film of the battery and can be used to represent the interfacial reactions of the battery. Specifically, Csei can simulate the state of the charge separation layer formed by lithium ion adsorption on the SEI film surface, reflecting the thickness of the SEI film. Rsei can simulate the SEI film's obstruction of ion transport, reflecting the integrity of the SIE film.

[0133] Cdl represents the electric double-layer capacitance of a battery, and Rct represents the charge transfer resistance of the battery. Cdl and Rct are relevant components reflecting the charge transfer in a battery. Cdl can be used to simulate the charge storage capacity of the electric double layer at the electrode / electrolyte interface, reflecting the effective surface area of ​​the active materials in the battery. Rct can be used to simulate the activation energy barrier of ion insertion / extraction reactions, reflecting whether the capacity decay of the battery is normal.

[0134] Zw represents the Warburg impedance of the battery, used to simulate the diffusion state of ions in the electrode material.

[0135] Optionally, the battery parameters can be represented as an array. Each element in the array can be used to record the value of the battery parameter. For example, the array can be represented as [L, R0, Csei, Rsei, Cdl, Rct, Zw].

[0136] Since the battery's EIS (acquired data) cannot be directly converted into battery parameters, the main control board must first obtain the predicted values ​​of the battery parameters. Then, it maps these predicted values ​​to the predicted EIS using a mapping relationship. By analyzing the difference between the predicted EIS and the battery's EIS, the predicted battery parameter values ​​are adjusted to reduce the gap, resulting in the adjusted predicted values. The difference between the predicted EIS and the battery's EIS can be understood as the goodness of fit of the predicted values. A larger difference between the predicted EIS and the battery's EIS indicates a lower goodness of fit, while a smaller difference indicates a higher goodness of fit.

[0137] The mapping relationship between the predicted value and the predicted EIS can be referred to the following mapping relationship (1).

[0138]

[0139] In mapping relationship (1), j represents the imaginary unit, and Z(f) represents the impedance corresponding to the excitation current at a preset frequency f. By changing the frequency f in mapping relationship (1), the predicted impedance of the battery at different frequencies can be obtained, which serves as the predicted EIS of the battery.

[0140] refer to Figure 8 The electrochemical impedance spectroscopy shown in Figure (2) can be expressed as the sum of the impedance differences (referred to as impedance differences) between the predicted EIS and the battery's EIS, corresponding to the excitation currents at Q preset frequencies. For example, the impedance difference corresponding to the preset frequency f1 can be expressed as: Where R1 and X1 represent the resistance and reactance of the impedance corresponding to the preset frequency f1 in the battery's EIS, respectively. R2 and X2 represent the resistance and reactance of the impedance corresponding to the preset frequency f1 in the predicted EIS, respectively.

[0141] If the predicted value is a single value, and the adjusted goodness of fit of the predicted value meets the requirements, the main control board can use the adjusted predicted value as the target value for the battery parameters. The goodness of fit requirements include, but are not limited to: a goodness of fit greater than a preset goodness of fit threshold, or, when the number of adjustments reaches a preset number, the goodness of fit is the highest among the multiple adjustments.

[0142] When multiple prediction values ​​are available, the main control board optimizes the prediction value with the highest fitting degree (called the optimal value) at least once to improve its fitting degree. The optimized optimal value is then used as the target value for the battery parameters. It should be noted that each optimization includes adjusting the prediction value, and the adjustment magnitude is determined with reference to the optimal value. The optimal value after a single optimization is the one with the highest fitting degree among the adjusted prediction values. A description of this process can be found in steps S22a and S22b below, which will not be elaborated upon here.

[0143] Optionally, when there are multiple predicted values, to improve optimization efficiency, the main control board can divide the multiple predicted values ​​into at least two groups based on their goodness of fit. For different groups of predicted values, different battery parameter optimization algorithms are used to optimize the optimal value in each group. This includes: for groups of predicted values ​​with low goodness of fit, where the corresponding optimal value is far from the target value, the battery parameter optimization algorithm used during optimization (denoted as Battery Parameter Optimization Algorithm 1) needs to be combined with global perturbation in addition to local search to increase the adjustment range and avoid failing to reach the optimal target value due to an excessively small adjustment range. This ensures that the optimal solution becomes the optimal target value after optimization. Here, Battery Parameter Optimization Algorithm 1 can include, but is not limited to, the bat algorithm (BA) and the global particle swarm optimization (Global PSO) algorithm. For the predicted value group with a high goodness of fit, its corresponding optimal value is close to the target value. The battery parameter optimization algorithm used during optimization (denoted as Battery Parameter Optimization Algorithm 2) should emphasize local search (meaning making small adjustments) and suppress global disturbances (meaning making large adjustments) to achieve smoother adjustments and avoid missing the optimal target value due to large adjustments. This ensures that the optimal solution becomes the optimal target value after optimization. Here, Battery Parameter Optimization Algorithm 2 can include, but is not limited to: Grey Wolf Optimizer (GWO) algorithm, Local Particle Swarm Optimization (Local PSO) algorithm, etc.

[0144] It should be noted that the goodness of fit for the predicted values ​​in different groups falls within different ranges, and these ranges do not overlap. For example, if the predicted values ​​are divided into two groups, the goodness of fit (greater than 50%) in one group is higher than that in the other group (less than or equal to 50%).

[0145] It should be noted that, for ease of explanation, the foregoing and the following text use the example of dividing multiple predicted values ​​into two groups based on their goodness of fit. Further descriptions of other predicted value groups can be found in the relevant descriptions; these will not be repeated in the embodiments of this application.

[0146] Subsequently, the main control board can analyze the battery status based on the target values ​​(target values ​​of battery parameters) corresponding to each battery. For example, by analyzing whether the target values ​​corresponding to each battery are within the normal range, it can determine whether the battery is faulty. Another example is that, based on the target values ​​corresponding to each battery, a clustering operation can be performed to divide each battery into at least one category. For example, the batteries can be divided into one or two categories. If the batteries are divided into one category, all batteries are determined to be normal. If the batteries are divided into two categories, the battery in the category with fewer batteries is determined to be the faulty battery. This is because the simultaneous failure of multiple batteries in a battery pack is a low-probability event.

[0147] Optionally, the main control board also includes a function to analyze battery status based on the battery's EIS (equivalent to the acquired data). This can be integrated into a battery detection model, whose related program instructions are stored on the main control board. When the main control board runs this battery detection model, it can perform battery status analysis based on the battery's EIS. In other words, the main control board runs a battery detection model used to determine the battery's status, including whether the battery is faulty, through its EIS data.

[0148] The battery detection model may include a battery parameter prediction algorithm, a battery parameter optimization algorithm 1, a battery parameter optimization algorithm 2, and a battery fault assessment algorithm. When the main control board runs the battery detection model and analyzes whether the battery is faulty based on the battery's EIS (Electronic Information System), the following points are relevant: Figure 9 Description of steps S21, S22a, S22b and S23.

[0149] S21. The main control board obtains N1 predicted values ​​of the battery parameters corresponding to the battery through the battery parameter prediction algorithm. The N1 predicted values ​​are divided into N11 predicted values ​​1 and N12 predicted values ​​2 according to the goodness of fit. The goodness of fit of predicted value 1 is lower than that of predicted value 2.

[0150] The battery parameter prediction algorithm involved in step S21 can be a genetic algorithm. Through this algorithm, the main control board can expand the random values ​​of the battery parameters corresponding to the battery to obtain N1 predicted values. Here, N1 is an integer greater than 1.

[0151] Optionally, the distribution of the N1 predicted values ​​follows a normal distribution.

[0152] The process of dividing N1 predicted values ​​into N11 predicted values ​​1 and N12 predicted values ​​2 according to the goodness of fit includes, but is not limited to, the following division process 1 and division process 2.

[0153] Partitioning process 1: Determine the mean goodness of fit of N1 predicted values. Among the N1 predicted values, the predicted value with a goodness of fit lower than the mean goodness of fit is taken as predicted value 1. And among the N1 predicted values, the predicted value with a goodness of fit higher than the mean goodness of fit is taken as predicted value 2.

[0154] In the second partitioning process, the N1 predicted values ​​are sorted from low to high according to their goodness of fit. Then, the N predicted values ​​are divided into two groups: the group with low goodness of fit is predicted value 1, and the group with high goodness of fit is predicted value 2.

[0155] The optimized value 1 can be obtained based on the predicted value 1. The process can be referred to the following description of step S22a.

[0156] S22a. The main control board optimizes the optimal value 1 at least once using the battery parameter optimization algorithm 1 to improve the fitting degree of the optimal value 1. Each optimization includes the first adjustment of N11 predicted values ​​1. The optimal value 1 participates in the first adjustment and the adjustment result is modified according to probability. The optimal value 1 after the first optimization is the value with the highest fitting degree among the N11 predicted values ​​1 after the first adjustment.

[0157] In step S22a, a single optimization includes a first adjustment to the N11 predicted values ​​1, specifically: adjusting the i-th predicted value 1 among the N11 predicted values ​​1 in a single optimization. The N11 predicted values ​​1 after the first adjustment include the adjusted i-th predicted value 1 and the other predicted values ​​1 that were not adjusted in the single optimization. After the first adjustment to the i-th predicted value 1, the optimal value 1 needs to be optimized once. The optimized optimal value 1 is the value with the highest fit among the N11 predicted values ​​1 after the first adjustment. The value of i ranges from 1 to N11. That is, each predicted value 1 in N11 will be adjusted. This optimization process can be repeated. The conditions for stopping repeated execution include, but are not limited to: the fit of the optimal value 1 is greater than a preset fit threshold, or the number of optimizations reaches a preset maximum number of optimizations.

[0158] Below, using battery parameter optimization algorithm 1 as the BA algorithm and the condition for stopping repeated execution being reaching the preset maximum number of optimizations, an example of step S22a will be provided. For details, please refer to the following... Figure 10 The description of steps S101-S106 is as follows.

[0159] S101. The main control board initializes the parameters of the BA algorithm, including the maximum number of optimization rounds M1 and the initial adjustment magnitude V0 corresponding to each of the N11 predicted values.

[0160] The maximum number of optimization rounds M1 multiplied by N11 can be understood as the maximum number of optimizations for the optimal value 1 mentioned above. In one optimization round, the N11 predicted values ​​1 will be adjusted once in a loop. After each adjustment, the optimal value 1 will be optimized once, including: determining the predicted value 1 with the highest fit from the N11 predicted values ​​1 after one adjustment as the optimal value 1 after one optimization. The relevant steps involved in optimizing the optimal value 1 can be referred to in step S105 below.

[0161] S102. Before the first round of optimization, determine the best value 1 among the N11 predicted values ​​1, denoted as X(best).

[0162] In steps S102-S106 below, let X(best) represent the optimal value 1. X(best) in step S102 is the prediction value with the highest good fit among the N11 predicted values ​​1 before the first round of optimization.

[0163] Subsequently, the optimization process for the optimal value 1 (here, X(best)) needs to be repeated. For a description of one of the optimizations, please refer to the following descriptions of steps S103, S104a, S104b, and S105.

[0164] S103. In the kth optimization, determine the offset ratio f(k) corresponding to the i-th predicted value 1, update the adjustment magnitude V(k) = V(k-1) + f(k) × ΔX corresponding to the i-th predicted value 1, adjust the i-th predicted value 1, X1(k) = X1(k-1) + V(k), and X1(0) is the i-th predicted value 1 before optimization.

[0165] Here, the offset ratio f(k) describes the proportion by which the i-th predicted value 1 moves towards the optimal value X(best) when it is adjusted in the k-th round of optimization, and ΔX indicates the difference between the i-th predicted value 1 and the optimal value X(best). The i-th predicted value 1 is X1(k-1), representing the adjusted value of the i-th predicted value 1 in the (k-1)-th round of optimization. X1(0) is the value of the i-th predicted value 1 before the first round of optimization. V(k-1) represents the adjustment magnitude of the i-th predicted value 1 in the (k-1)-th round of optimization.

[0166] The initial value of k is 1. X1(k) represents the adjusted value of the i-th prediction value 1 in the k-th round of optimization. It can also be understood as the value of the i-th prediction value 1 after the k-th adjustment.

[0167] In the k-th optimization, the formula for determining the offset ratio f(k) corresponding to the i-th predicted value 1 can be found in the following formula (1).

[0168] f(k)=f min +(fmax -f min )×rand(0,1) formula (1)

[0169] In formula (1), f max and f min These are the preset maximum offset ratio and the preset minimum offset ratio, respectively. rand(0,1) is a random number between 0 and 1.

[0170] To enhance the global perturbation and increase the probability of obtaining the optimal target value, it is also necessary to determine, according to the update probability, whether to modify the adjusted i-th predicted value 1 using the optimal value X(best). Specifically, it is determined whether to adjust the optimal value X(best) to replace X1(k) as the new value X(new) obtained after the k-th adjustment of the i-th predicted value 1. It should be noted that the k-th adjustment of the i-th predicted value 1 is denoted as the adjustment performed on the i-th predicted value 1 in the k-th round of adjustment mentioned in step S103 above.

[0171] The judgment process includes: generating a random number between [0,1], judging the magnitude of the random number and the update probability ri(k), and determining whether to modify the adjusted i-th predicted value 1 using the optimal value X(best). The determination can be made by referring to the following formula (2).

[0172] ri(k)=ri(k-1)×(1-exp[-γ(k-1)]) formula (2)

[0173] In formula (2), ri(k) is the update probability. ri(k-1) is the update probability used in the (k-1)th round of optimization. γ is a constant. ri(0) is a preset value.

[0174] If the random number is greater than the update probability ri(k), then the adjusted i-th predicted value 1 is not modified using the optimal value X(best), and step S104a.X(new)=X1(k) is executed. The adjusted i-th predicted value 1 is taken as the new value X(new) obtained after the k-th adjustment of the i-th predicted value 1.

[0175] If the random number is less than the update probability ri(k), then the optimal value X(best) is adjusted to replace X1(k) as the new value X(new) obtained after the kth adjustment of the i-th predicted value 1. The description of this process can be found in step S104b below.

[0176] S104b.X(new)=X(best)+εA(t), where εA(t) is the adjustment degree corresponding to the optimal value, ε is randomly generated for executing step S104b, A(t)=αA(t-1), and A(0) is the default value.

[0177] In step S104b, A(t-1) is the adjustment parameter used in the (t-1)th adjustment round, and A(t) is the adjustment parameter used in the tth adjustment round. α is the attenuation coefficient, which ranges from 0 to 1. ε is a random number between [-1, 1].

[0178] S105. Determine whether the goodness of fit of the new value X(new) is better than that of the best value X(best). If so, use the new value X(new) as the best value X(best). If not, do not update the best value X(best) after this adjustment.

[0179] It should be noted here that the X(best) used in the next adjustment is the X(best) determined in step S105. Execute i = i + 1.

[0180] If i < or = N11, it means that the optimization of the kth round is not completed, and the aforementioned step S103 is continued to adjust the i-th predicted value.

[0181] If i > N11, it means that the k-th round of optimization has been completed. Then, execute i = 1 and execute k = k + 1. Next, compare the size of k and M1 to determine if the optimization has ended. If k < or = M1, execute the aforementioned step S103 to continue optimization. If k > M1, the optimization ends, and execute the following step S106.

[0182] S106. After optimization, output the optimized optimal value X (best).

[0183] Here, the optimal value X (best) output by the main control board through the BA algorithm can be an example of the optimized optimal value 1 involved in step S23 below.

[0184] It's important to note that in the BA algorithm (Bat Optimization Algorithm), the i-th predicted value (1) can be considered the bat, and adjusting the i-th predicted value can be understood as changing the bat's position. The adjustment magnitude V(k) mentioned earlier can be understood as the bat's speed, the offset ratio f(k) can be understood as the frequency of the pulses emitted by the bat, and the adjustment parameter A(t) can be considered the bat's loudness. The update probability ri(k) can be considered the bat's pulse emission rate.

[0185] The foregoing described the process of obtaining the optimized optimal value 1 based on the predicted value 1. The following describes the process of obtaining the optimized optimal value 2 based on the predicted value 2. This process can be referred to in the following description of step S22b.

[0186] S22b. The main control board optimizes the optimal value 2 at least once using the battery parameter optimization algorithm 2 to improve the fitting degree of the optimal value 2. Each optimization includes a second adjustment to the N12 predicted values ​​2, and the optimal value 2 participates in the second adjustment. The optimal value 2 after a single optimization is at least one value with the highest fitting degree among the N12 predicted values ​​2 after the second adjustment.

[0187] In step S22b, a single optimization includes a second adjustment to the N12 predicted values ​​2, specifically: adjusting the i-th predicted value 2 among the N12 predicted values ​​2 in a single optimization. The N12 predicted values ​​2 after the second adjustment include: the adjusted i-th predicted value 2 and the other predicted values ​​2 that were not adjusted in the single optimization. After the first adjustment to the i-th predicted value 2, the optimal value 2 needs to be optimized once. The optimized optimal value 2 is the value with the highest fit among the N12 predicted values ​​2 after the first adjustment. The value of i ranges from 1 to N12. That is, each predicted value 2 in the N12 will be adjusted. This optimization process can be repeated. The conditions for stopping repeated execution include, but are not limited to: the fit of the optimal value 2 is greater than a preset fit threshold, or the number of optimizations for the optimal value 2 reaches a preset maximum number of optimizations.

[0188] The following example illustrates step S22b, using the GWO algorithm as the battery parameter optimization algorithm 2 and the condition for stopping repeated execution being reaching the preset maximum number of optimizations. For details, please refer to the following... Figure 11 The description of steps S201-S206 is as follows.

[0189] S201. The main control board initializes the parameters of the GWO algorithm, including the maximum number of optimization rounds M2.

[0190] The maximum number of optimization rounds M2 multiplied by N12 can be understood as the maximum number of optimizations for the optimal value 2 mentioned above. In one round of optimization, the N12 predicted values ​​2 will be adjusted once in a loop. After each adjustment, the optimal value 2 will be optimized once. The relevant steps involved in optimizing the optimal value 2 can be referred to in step S205 below.

[0191] S202. Before the first round of optimization, determine the optimal value X(α), the second-best value X(β), and the third-best value X(δ) among the N12 predicted values ​​2.

[0192] The optimal value X(α), the second-best value X(β), and the third-best value X(δ) in step S202 are the three prediction values ​​with the highest fit among the N12 prediction values ​​before the first round of optimization.

[0193] It should be noted that in the GWO algorithm, the optimal value X(α), the second-best value X(β), and the third-best value X(δ) can be understood as examples of the aforementioned optimal value 2. Specifically, the optimal value X(α) is the prediction with the highest good fit among the N12 predicted values ​​2. The second-best value X(β) is the prediction with the second-highest good fit among the N12 predicted values ​​2. The third-best value X(δ) is the prediction with the third-highest good fit among the N12 predicted values ​​2.

[0194] Subsequently, the optimization process for the optimal value 2 (here, the optimal value X(α), the second-best value X(β), and the third-best value X(δ)) needs to be repeated. For a description of one of the optimizations, please refer to the following descriptions of steps S203a, S203b, S203c, S204, and S205.

[0195] Here, the optimal value X(α), the second-best value X(β), and the third-best value X(δ) are used together to constrain the adjustment of the predicted value 2, so that the predicted value 2 is adjusted more smoothly under the constraints, thereby making the result of the adjusted predicted value 2 relatively better. The adjustment of the predicted value 2 based on the optimal value X(α), the second-best value X(β), and the third-best value X(δ) can be referred to in the following steps S203a, S203b, S203c, and S204.

[0196] S203a. In the k-th round of adjustment, based on X(α) and X2(k-1), the i-th predicted value 2 is adjusted to obtain X2(k1), X2(k1)=X(α)-A1×D1.

[0197] It should be noted that the adjustment made to the i-th predicted value 2 in the k-th round of adjustment can also be understood as the k-th adjustment made to the i-th predicted value 2.

[0198] Here, A1 can be viewed as an adjustment parameter related to the number of optimization iterations. D1 can be viewed as an adjustment parameter related to the relative difference, where the relative difference is the relative difference between the optimal value X(α) and the i-th predicted value 2 (after the (k-1)-th adjustment and before the k-th adjustment). D1 indicates that the adjustment result of the i-th predicted value 2 in X(α) can refer to values ​​near X(α).

[0199] Where, D1=|C1×X(α)-X2(k1-1)|. A1=a(2r11-1), a is related to k and M2, and decreases as k increases. C1=2×r12, r12 and r11 are random scaling factors, which can be random numbers between [0, 1]. The decrease of a as k increases can indicate that the adjustment of the i-th predicted value gradually becomes smoother as the value of k increases. The relevant formula for generating a can be found in the following formula (3).

[0200] In X2(k1)=X(α)-A1×D1, X2(k1) is the i-th predicted value 2 after the k-th adjustment under the constraint of X(α). X2(k1-1) is the i-th predicted value 2 after the (k-1)-th adjustment under the constraint of X(α).

[0201]

[0202] In formula (3), M2 represents the maximum number of optimization rounds, and k represents the current number of optimization rounds.

[0203] S203b. In the k-th round of adjustment, based on X(β) and X2(k-1), the i-th predicted value 2 is adjusted to obtain X2(k2), X2(k2)=X(β)-A2×D2.

[0204] Here, A2 can be viewed as an adjustment parameter related to the number of optimization iterations. D2 can be viewed as an adjustment parameter related to the relative difference, where the relative difference is the difference between the optimal value X(β) and the i-th predicted value 2 (after the (k-1)-th adjustment and before the k-th adjustment). D2 indicates that the adjustment result of the i-th predicted value 2 in X(β) can refer to values ​​near X(β).

[0205] Where D2=|C2×X(β)-X2(k2-1)|A2=a(2r21-1), a is related to k and M2, and decreases as k increases. C2=2×r22, r22 and r21 are random scaling factors, which can be random numbers between [0,1]. The decrease of a as k increases can indicate that the adjustment of the i-th predicted value gradually becomes smoother as the value of k increases. The relevant formula for generating a can be found in the aforementioned formula (3).

[0206] In X2(k2)=X(β)-A2×D2, X2(k2) is the i-th predicted value 2 after the k-th adjustment under the constraint of X(β). X2(k2-1) is the i-th predicted value 2 after the (k-1)-th adjustment under the constraint of X(β).

[0207] S203c. In the k-th round of adjustment, based on X(δ) and X2(k-1), the i-th predicted value 2 is adjusted to obtain X2(k3), X2(k3)=X(δ)-A3×D3.

[0208] Here, A3 can be viewed as an adjustment parameter related to the number of optimization iterations. D3 can be viewed as an adjustment parameter related to the relative difference, where the relative difference is the relative difference between the optimal value X(δ) and the i-th predicted value 2 (after the (k-1)-th adjustment and before the k-th adjustment). D3 indicates that the adjustment result of the i-th predicted value 2 in X(δ) can refer to values ​​near X(δ).

[0209] Where D3=|C3×X(δ)-X2(k3-1)|A3=a(2r31-1), a is related to k and M2, and decreases as k increases. C3=2×r32, r32 and r31 are random scaling factors, which can be random numbers between [0,1]. The decrease of a as k increases can be interpreted as the adjustment of the i-th predicted value gradually becoming smoother as the value of k increases. The relevant formula for generating a can be found in the aforementioned formula (3).

[0210] In X2(k3)=X(β)-A3×D3, X2(k3) is the i-th predicted value 2 after the k-th adjustment under the constraint of X(δ). X2(k3-1) is the i-th predicted value 2 after the (k-1)-th adjustment under the constraint of X(δ).

[0211] After adjusting the predicted value 2 based on the optimal value X(α), the second-best value X(β), and the third-best value X(δ), the following step S204 is performed, and the average of the three adjustments is taken as the i-th predicted value 2 after the k-th adjustment.

[0212] S204. In the k-th round of optimization, the i-th predicted value 2 is adjusted to X2(k) = [X2(k1) + X2(k2) + X2(k3)] / 3.

[0213] Where X2(k) represents the i-th predicted value 2 after the k-th adjustment.

[0214] Next, step S205 is executed, using the adjusted i-th predicted value 2. The optimal value X(α), the second-best value X(β), and the third-best value X(δ) are then optimized.

[0215] S205. Take X2(k) as the new value obtained after the kth adjustment of the i-th predicted value 2, and optimize the optimal value X(α), the second-best value X(β) and the third-best value X(δ) through the new value.

[0216] The optimal value X(α), suboptimal value X(β), and third-best value X(δ) before this optimization are sorted from highest to lowest with the new values, and the three values ​​with the highest goodness of fit are selected. These are then used as the optimal value X(α), suboptimal value X(β), and third-best value X(δ) after this optimization.

[0217] It should be noted here that the X2(k) used in the next adjustment is the X2(k) (new value) determined in step S204. Execute i = i + 1.

[0218] If i < or = N12, it means that the optimization in the kth round is not completed. Continue to execute the aforementioned steps S203a, S203b and S203c to adjust the i-th predicted value.

[0219] If i > N12, it means that the k-th round of optimization has been completed. Then, execute i = 1 and execute k = k + 1. Next, compare the size of k and M2 to determine if the optimization has ended. If k < or = M2, execute the aforementioned steps S203a, S203b, and S203c to continue optimization. If k > M2, the optimization ends, and execute the following step S206.

[0220] S206. After optimization, output the optimized optimal value X(α), the optimized second-best value X(β), and the optimized third-best value X(δ).

[0221] Here, the optimal value X(α), the optimized second-best value X(β), and the optimized third-best value X(δ) output by the main control board through the WEO algorithm can be an example of the optimized optimal value 2 involved in step S23 below.

[0222] It's important to note that in the GWO algorithm (Grey Wolf Optimization Algorithm), the optimal value X(α), the second-best value X(β), and the third-best value X(δ) can be referred to as α-wolf, β-wolf, and δ-wolf, respectively. A1, A2, A3, and C1, C2, C3 are vectors used to adjust the positional offsets of α-wolf, β-wolf, and δ-wolf.

[0223] It should be noted that steps S21, S22a, and S23a are described using a single battery as an example. For different batteries in a battery pack, steps S21, S22a, and S23a can be applied to each battery to determine the optimized optimal value 1 and optimized optimal value 2 for each battery. Then, the target value for each battery is determined using the optimized optimal value 1 and optimized optimal value 2 for each battery. The target value for a battery is the value with the highest good of fit between the optimized optimal value 1 and optimized optimal value 2 for that battery.

[0224] Because the target values ​​of the battery parameters corresponding to faulty batteries deviate from the normal range, there is a discrepancy between the target values ​​corresponding to faulty and normal batteries. Therefore, the target values ​​corresponding to each battery are separable, and the probability of multiple battery failures is low. Based on the spatial distribution distance of the target values ​​corresponding to each battery, the batteries can be classified. Batteries with similar target values ​​are close in space and can be classified into one category. If the batteries can be classified into two categories, it indicates that there are faulty batteries, and the category with fewer batteries is the faulty battery category. If the batteries are classified into only one category, it indicates that all batteries are normal batteries. For details on the process involved, please refer to step S23 below.

[0225] S23. The main control board uses a battery fault assessment algorithm to classify each battery into one or two categories based on the target value corresponding to each battery. In the case of being classified into one category, all batteries are normal batteries. In the case of being classified into two categories, there are first category batteries and second category batteries. The number of first category batteries is less than the number of second category batteries. The first category batteries are considered faulty batteries. The target value corresponding to the battery is the value with the highest fit between the optimized optimal value 1 and the optimized optimal value 2.

[0226] The battery fault assessment algorithm involved in step S23 can be a clustering algorithm. Here, we take the OPTICS (Ordering Points to Identify Clustering Structure) algorithm for classifying batteries as an example. A description of this process can be found below. Figure 12 In this context, steps S301-S304, S305a, and S305b are included.

[0227] S301. The main control board initializes the parameters of the OPTICS algorithm, including the preset neighborhood of each battery, the value of minPts, and the result queue, which is initially empty.

[0228] This explanation uses the example of all batteries within a preset neighborhood, denoted as Z batteries. Z is an integer greater than 1. The preset neighborhood determines which batteries can be used when calculating the core distance. Batteries not within the preset neighborhood are not included in the core distance calculation in step S302 below. For example, if battery 1 is not within the neighborhood of battery 2, then battery 1 is not considered when calculating the core distance of battery 2.

[0229] minPts is an integer greater than 1 and less than Z. minPts represents the minimum number of batteries that must be included in the neighborhood of a given battery when it is used as a core point. It can be used in step S302 to determine the core distance of a battery.

[0230] The following explanation uses Z=8 and minPts=5 as an example. The 8 batteries are denoted as Battery 1 (B1) to Battery 8 (B8).

[0231] The result queue is used to record the processing order and reachability distance of each battery in step S303 below.

[0232] S302. Calculate the core distance of each battery based on the preset neighborhood of each battery; the core distance of a battery is the Euclidean distance between the battery and the target neighboring battery, and the target neighboring battery of a battery is the battery within the preset neighborhood of the battery that is closest to the battery at the minPts-th distance. The Euclidean distance between two batteries represents the difference between the battery parameters corresponding to the two batteries.

[0233] In step S302, the core distance of a battery is the Euclidean distance from the battery to its nearest battery at the minPts (e.g., 5) th ...

[0234] For example, the distances between battery 1 and [batteries 2-8] are denoted as: [d12=2, d13=2.5, d14=2.5, d15=2.8, d16=3, d17=3.5, d18=3.2]. Arranged in ascending order: [d12=2, d13=2.5, d14=2.5, d15=2.8, d16=3, d18=3.2, d17=3.5]. When minPts=5, the core distance of battery 1 is d16=3, where d16 is the Euclidean distance from battery 1 to battery 6.

[0235] Once the core distance of each battery is determined, the following step S303 can be executed repeatedly to determine the processing order and minimum reachable distance of each battery.

[0236] S303. Select the s-th battery to be processed from the ordered queue, add the s-th battery to the result queue, update the ordered queue, and determine the minimum reachable distance corresponding to the s-th battery based on the result queue. This minimum reachable distance is the minimum value among the reachable distances corresponding to unprocessed batteries. The reachable distance corresponding to an unprocessed battery is the minimum value among the reachable distances from the unprocessed battery to each processed battery (including the s-th battery). The reachable distance between the unprocessed battery and a processed battery is the maximum value between distance 1 and distance 2. Distance 1 is the core distance of the processed battery, and distance 2 is the Euclidean distance between the unprocessed battery and the processed battery. The processing order of the s-th battery in the result queue is s, and the initial value of s is 1. s = s + 1, and determine whether there is s > Z. If s > Z, it means that all batteries have been processed. If s < or = Z, it means that there are still batteries that have not been processed, and continue to execute step S303.

[0237] In step S303, the result queue is used to record the processed batteries and their corresponding minimum reachable distances.

[0238] An ordered queue can also be called an ordered seed queue. The ordered queue records unprocessed batteries, and the batteries are sorted in ascending order of their reachability distance to ensure that batteries with the shortest reachability distance are processed first. When Z equals 8, the ordered queue records 8 batteries, and the reachability distance of each battery is marked as infinity. As more batteries are processed (i.e., s increases), the number of batteries recorded in the ordered queue gradually decreases.

[0239] After selecting the s-th battery to be processed from the ordered queue, the reachability distance of each battery in the ordered queue needs to be updated. The reachability distance of a battery needs to be updated to the minimum reachability distance from that battery to all processed batteries (including the s-th battery).

[0240] The formula for calculating the reachable distance from battery q to battery p can be found in the following formula (4).

[0241] reachDist(q,p)=max[coreDist(p),distance(q,p)] Formula (4)

[0242] In formula (4), reachDist(q,p) represents the reachable distance between battery q and battery p. coreDist(p) is the core distance of battery p. distance(q,p) represents the Euclidean distance between battery p and battery q.

[0243] It should be noted that the first battery processed is randomly selected, and its minimum reachable distance is denoted as infinity. Subsequent batteries are the first batteries in the ordered queue.

[0244] The following example illustrates step S303.

[0245] s=1, take the first battery to be processed, for example, battery 1 (denoted as B1). The minimum reachable distance of battery 1 is denoted as infinity. Update the sorted queue, and the updated sorted queue is arranged in ascending order of reachable distance: [reachDist(B2,B1)=3, reachDist(B3,B1)=3, reachDist(B5,B1)=3, reachDist(B6,B1)=3, reachDist(B4,B1)=3, reachDist(B8,B1)=3.2, reachDist(B7,B1)=3.5].

[0246] Then select battery 2 (B2) with the smallest reachable distance and add it to the result queue. The minimum reachable distance corresponding to battery 2 is 2. The result queue is currently represented as [B0 (minimum reachable distance, infinity), B2 (minimum reachable distance = 3)].

[0247] Then, based on the reachability distance from the unprocessed battery to battery 2, the ordered queue is updated. The updated ordered queue is sorted in ascending order of reachability distance: [reachDist(B5,B2)=2.8, reachDist(B3,B2)=2.9, reachDist(B6,B1)=3, reachDist(B4,B1)=3, reachDist(B8,B1)=3.2, reachDist(B7,B1)=3.5]. Since reachDist(B5,B2) is less than reachDist(B5,B1), the reachability distance of battery 5 (B5) in the ordered queue needs to be updated to the reachability distance from battery 5 (B5) to battery 2 (B2). The reachability distance update for battery 3 is similar. The reachability distance from battery 6 (B6) to battery B2 is reachDist(B6,B2)=3.5, which is greater than reachDist(B6,B1)=3. Therefore, the reachability distance of battery 6 in the ordered queue is not updated, and the same applies to other batteries whose reachability distances have not been updated.

[0248] Subsequently, s=2, the second battery to be processed is selected and added to the results queue, battery 5 (B5), the minimum reachable distance of battery 5 is 2.1. The results queue is currently represented as [B0 (minimum reachable distance, infinity), B2 (minimum reachable distance = 3), B5 (minimum reachable distance = 2.8)].

[0249] Then, based on the reachability distance from the unprocessed battery to battery 5, update the ordered queue. Repeat the above operation until all batteries have been processed, obtaining the minimum reachability distance for each battery. This will not be elaborated further here.

[0250] S304. Obtain the processing order and minimum reachable distance of each battery from the result queue, sort the minimum reachable distances of each battery according to the processing order, and determine whether there is a peak reachable distance.

[0251] After sorting the minimum reachable distances of each battery according to the processing order, the minimum reachable distance that is greater than the previous minimum reachable distance and the next minimum reachable distance is determined as the reachable distance peak. That is, the reachable distance peak must be greater than the two minimum reachable distances before and after it. An example of the existence of reachable distance peaks can be found in Table 1 below.

[0252] Table 1

[0253]

[0254] As shown in Table 1, after sorting the minimum reachable distances of batteries 1 to 8 according to the processing order, the minimum reachable distance 4 of battery 8 is greater than the minimum reachable distances of the two batteries before and after it (battery 4 and battery 7). Therefore, the minimum reachable distance 4 corresponding to battery 8 is the reachable distance peak.

[0255] If no peak reachable distance is found, the battery is classified as a Class I battery. Then proceed to step S305a to confirm that all batteries are normal.

[0256] If a peak reachability is found, the battery can be classified into two categories. Perform step S305b below.

[0257] S305b. Divide each battery into two categories. One category of batteries has a minimum reachable distance before (including) the target reachable distance peak, which are normal batteries. The other category of batteries has a minimum reachable distance after the target reachable distance peak, which are faulty batteries. When there are multiple reachable distance peaks, the reachable distance peak that meets the requirements is taken as the target reachable distance peak. When there is only one reachable distance peak, that reachable distance peak is taken as the target reachable distance peak.

[0258] Referring to Table 1 above, it can be seen that battery 7 is a faulty battery.

[0259] Here, the reachable distance peak that meets the requirements can be the reachable distance peak that is processed last among multiple reachable distance peaks.

[0260] It should also be noted that the battery parameter prediction algorithm involved in the embodiments of this application can also be referred to as the battery parameter prediction model, the battery parameter optimization algorithm 1 can also be referred to as the first battery parameter optimization model, the battery parameter optimization algorithm 2 can also be referred to as the second battery parameter optimization model, and the battery fault assessment algorithm can also be referred to as the battery fault assessment model.

[0261] This application also provides an energy storage system, which includes a charge / discharge control module, a power conversion module, and at least one energy storage device. The energy storage device is the aforementioned energy storage device. The power conversion module includes an AC-DC conversion module and / or a DC-DC conversion module.

[0262] The charge / discharge control module is used to control the charging and discharging process of the battery, prevent overcharging and over-discharging, and optimize energy use.

[0263] An AC-DC converter module is used to achieve bidirectional conversion between AC and DC power. For example, it can convert AC power from the grid into DC power and transmit it to the battery pack for charging. Alternatively, it can convert DC power from the battery pack into AC power to feed back into the grid or power AC loads.

[0264] The DC-DC converter module is used to adjust the DC voltage level, stepping down the high-voltage DC power (such as 400V) output from the battery pack to low-voltage DC power (such as 12V / 24V / 48V) for direct use by low-voltage loads.

[0265] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0266] Those skilled in the art will understand that implementing all or part of the processes in the above embodiments can be accomplished by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0267] In summary, the above description is merely an embodiment of the technical solution of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the disclosure of this application should be included within the scope of protection of this application.

Claims

1. An energy storage device, characterized by, The energy storage device includes a battery electrochemical impedance spectroscopy (EIS) acquisition device and a battery pack; the battery pack includes multiple batteries, and the acquisition device includes a main control board and multiple slave control boards. The multiple slave control boards are cascaded, and the first-level slave control board among the multiple slave control boards is connected to the main control board for receiving acquisition commands from the main control board. The acquisition commands are transmitted step by step from the first-level control board to the subsequent slave control boards. The last slave control board among the plurality of slave control boards is connected to the master control board and is used to transmit the electrochemical impedance spectroscopy (EIS) collected by the plurality of slave control boards to the master control board; Each of the plurality of slave control boards is coupled to one of the plurality of batteries. The slave control board is connected to the negative terminal of the coupled battery and is used to output an excitation current of a preset frequency to the negative terminal of the coupled battery. The preset frequency comes from the acquisition command. The slave control board is connected to the positive terminal of the coupled battery and is used to collect the response voltage of the coupled battery under the excitation current. The slave control board is used to determine the EIS of the coupled battery based on the response voltage and the excitation current.

2. The energy storage device of claim 1, wherein, The EIS acquisition times of adjacent slave control boards among the plurality of slave control boards are different, while the acquisition times of non-adjacent slave control boards among the plurality of slave control boards are the same.

3. The energy storage device of claim 1 or 2, wherein, The control board is located on the aluminum busbar of the battery it is coupled with.

4. The energy storage device of claim 3, wherein, The control board is located on the aluminum busbar of the coupled battery and includes: One end of the control board is welded to the aluminum busbar coupled to the negative electrode tab of the coupled battery via a first metal sheet, the first metal sheet being made of the same material as the negative electrode tab; The other end of the control board is welded to the aluminum busbar coupled to the positive electrode tab of the coupled battery via a second metal sheet, the second metal sheet being made of the same material as the positive electrode tab.

5. The energy storage device of any one of claims 1-4, wherein, The slave control board is equipped with an EIS acquisition chip and an excitation resistor. The EIS acquisition chip includes a voltage sampling positive terminal, a voltage sampling negative terminal, an acquisition signal input terminal, and an acquisition signal output terminal. The EIS acquisition chip is connected to the negative terminal of the battery coupled to the slave control board through an excitation resistor, and is used to provide an excitation voltage of a preset frequency to the excitation resistor. The excitation voltage forms the excitation current through the excitation resistor. The positive terminal of the EIS acquisition chip is connected to the positive terminal of the battery, and the negative terminal is connected to the negative terminal of the battery, which is used to acquire the response voltage of the battery under the excitation current. The cascading includes: the acquisition signal output terminal of an EIS acquisition chip on a slave control board is connected to the acquisition signal input terminal of an EIS acquisition chip on the next slave control board; The primary slave control board among the plurality of slave control boards is connected to the main control board, specifically including: the acquisition signal input terminal of the EIS acquisition chip on the primary slave control board is connected to the main control board; The last slave control board among the plurality of slave control boards is connected to the main control board, specifically including: the acquisition signal output terminal of the EIS acquisition chip on the last slave control board is connected to the main control board.

6. The energy storage device of claim 5, wherein, The slave control board also includes a switching circuit, which is connected between the EIS acquisition chip and the excitation resistor. The switching frequency of the switching circuit is used to control the frequency of the excitation current.

7. The energy storage device of claim 6, wherein, The EIS acquisition chip also includes a voltage output terminal and a control signal output terminal. The switching circuit is a field-effect transistor (FET). The control signal output terminal is connected to the control terminal of the FET, the voltage output terminal is connected to the source terminal of the FET, and the drain terminal of the FET is connected to the excitation resistor. The EIS acquisition chip outputs a control signal to the field-effect transistor through the control signal output terminal, and the frequency of the control signal is used to control the switching frequency of the field-effect transistor. The EIS acquisition chip outputs a first voltage to the field-effect transistor through the voltage output terminal. The first voltage is converted into an excitation voltage of a preset frequency by the field-effect transistor through the control signal and provided to the excitation resistor.

8. The energy storage device of claim 5, wherein, The EIS acquisition chip also includes an excitation voltage output terminal, used to provide the excitation voltage of the preset frequency to the excitation resistor.

9. The energy storage device of any one of claims 5-8, wherein, The EIS acquisition chip also includes a power supply terminal, which is connected to the battery coupled to the slave control board and is used to receive power from the battery. The power supply from the battery is used to generate the excitation voltage.

10. The energy storage device of any one of claims 5-9, wherein, There are multiple excitation resistors connected in parallel.

11. The energy storage device of any one of claims 5-10, wherein, When a slave control board is not the primary slave control board, the slave control board inputs the EIS acquired by the slave control board and the EIS acquired by all the preceding slave control boards to the EIS acquisition chip on the next lower slave control board through the acquisition signal output terminal of its EIS acquisition chip; when a slave control board is the primary slave control board, the slave control board inputs the EIS acquired by the slave control board to the EIS acquisition chip on the next lower slave control board through the acquisition signal output terminal of its EIS acquisition chip.

12. The energy storage device of any one of claims 5-11, wherein, The slave control board transmits acquisition commands to the acquisition signal input terminal of the EIS acquisition chip on the next slave control board through the acquisition signal output terminal of its EIS acquisition chip.

13. The energy storage device of any one of claims 5-12, wherein, The slave control board also includes a first interface, which is located at the acquisition signal input terminal of the EIS acquisition chip on the slave control board. The first interface is used to convert the first acquisition signal in a first form into a second form of the first acquisition signal. The second form is the form of the acquisition signal transmitted by the acquisition signal input terminal, and the first form is the form of the acquisition signal transmitted by the first interface. The first acquisition signal includes acquisition commands from the master control board or the previous slave control board, and / or EIS signals from the previous slave control board.

14. The energy storage device of any one of claims 5-13, wherein, The slave control board also includes a second interface, which is located after the acquisition signal output terminal of the EIS acquisition chip on the slave control board. The second interface is used to convert the second acquisition signal in a third form into a second acquisition signal in a first form. The third form is the form of the acquisition signal transmitted by the acquisition signal output terminal, and the first form is the form of the acquisition signal transmitted by the first interface on the next-level slave control board. The second acquisition signal includes an EIS acquisition command sent to the next-level slave control board, and / or an EIS signal sent to the next-level slave control board.

15. The energy storage device of any one of claims 1-14, wherein, The control panel also includes a pressure relief valve pre-drilled hole, which is positioned opposite to the battery's pressure relief valve, and the edge of the pressure relief valve pre-drilled hole surrounds the edge of the pressure relief valve.

16. The energy storage device of any one of claims 1-15, wherein, The main control board runs a battery detection model, which is used to determine the battery status through the battery's EIS (Electronic Information System). The battery status includes whether the battery is faulty.

17. An energy storage system characterized by, The energy storage system includes a charge / discharge control module, a power conversion module, and at least one energy storage device; wherein the energy storage device is the energy storage device according to any one of claims 1-16, and the power conversion module includes an AC-DC conversion module and / or a DC-DC conversion module.

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