Anti-boot output overcharge circuit applied to flyback topology

Abstract

The application discloses an anti-output overcharge circuit applied to a flyback topology, and relates to the technical field of anti-output overcharge circuits.The anti-output overcharge circuit comprises a plurality of resistors, a plurality of capacitors, an operational amplifier, a diode and a voltage reference source.Based on a PWM control loop, the anti-output overcharge circuit utilizes the characteristics that different point positions are established at different times during the power-on process of a power supply, and thus the anti-output overcharge circuit is provided, the possibility of overcharge during the power-on process of the power supply is greatly reduced, and the response speed of the PWM control loop is not affected after the power supply is normally powered on.Meanwhile, the characteristics of fast response speed and small overcharge during power-on are taken into account, and the overall applicability of the power supply is improved.

Description

Technical Field

[0001] This application relates to the field of output overcharge protection circuit technology, and in particular to an output overcharge protection circuit applied to a flyback topology. Background Technology

[0002] The flyback topology is a common switching power supply topology widely used in low-power devices such as adapters and power converters. Its core principle is to achieve voltage conversion and isolation through the storage and release of energy by a transformer. In a flyback topology, the input voltage is applied to the primary winding of the transformer via a switching device. When the switch is on, the current increases, and magnetic energy is stored in the transformer core; when the switch is off, the magnetic field releases energy, generating a directional voltage through the pole windings to supply the load.

[0003] Typical flyback topologies include a PWM control loop to achieve output voltage regulation. Simultaneously, switching power supplies need to strictly prevent overcharging during startup. Traditional flyback topologies, in pursuit of fast response, continuously improve the response speed of the PWM control loop. However, the fast response of the PWM control loop contradicts the goal of preventing overcharging during startup. Therefore, traditional flyback topologies struggle to balance the technical requirements of fast response and overcharging prevention, failing to meet the need for both. Utility Model Content

[0004] This application provides a circuit for preventing overcharging during startup in a flyback topology. This solves the technical problem that traditional flyback topologies cannot meet the requirements of fast response while preventing overcharging during startup. It achieves the technical effect of ensuring fast startup response of the flyback topology while preventing overcharging during startup, thus improving the overall performance of the device.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] An overcharge protection circuit for power-on output applied to a flyback topology includes an operational amplifier module and a voltage reference source IC2. The operational amplifier module is electrically connected to the voltage reference source IC2 and the flyback topology. The operational amplifier module includes an operational amplifier IC1, an operational amplifier power supply unit, an operational amplifier voltage divider unit, and an operational amplifier limiting unit. The operational amplifier power supply unit is electrically connected to the positive input terminal of the operational amplifier IC1. The operational amplifier voltage divider unit is electrically connected to the non-inverting input terminal of the operational amplifier IC1. The operational amplifier limiting unit is electrically connected to the inverting input terminal of the operational amplifier IC1. The inverting input terminal of the operational amplifier IC1 is electrically connected to the output terminal of the operational amplifier IC1. The output terminal of the operational amplifier IC1 is electrically connected to the flyback topology. The negative input terminal of the operational amplifier IC1 is grounded. The voltage reference source IC2 is electrically connected to the inverting input terminal of the operational amplifier IC1.

[0007] Furthermore, the operational amplifier power supply unit includes a capacitor C1; one end of the capacitor C1 is electrically connected to the positive power input terminal of the operational amplifier IC1 and a 12V DC power supply, and the other end is grounded.

[0008] Furthermore, the operational amplifier voltage divider unit includes resistors R1 and R3; one end of resistor R1 is electrically connected to the positive voltage signal Vo, and the other end is connected in parallel to the non-inverting input terminal of the operational amplifier IC1 and one end of resistor R3; the other end of resistor R3 is grounded.

[0009] Furthermore, the operational amplifier limiting unit includes diode D1, diode D2, resistor R2, and capacitor C2; the anode of diode D2 is electrically connected to the inverting input terminal of operational amplifier IC1, and the cathode is electrically connected to the anode of diode D1; the cathode of diode D1 is electrically connected to the positive voltage signal Vo; one end of resistor R2 is electrically connected to the positive voltage signal Vo, and the other end is electrically connected to one end of capacitor C2, with the other end of capacitor C2 grounded; the end of resistor R2 furthest from the positive voltage signal Vo is electrically connected to the anode of diode D2.

[0010] Furthermore, pin 1 of the voltage reference source IC2 is connected to a 12V DC power supply via a series resistor R4; pin 2 of the voltage reference source IC2 is connected to the inverting input terminal of the operational amplifier IC1 via a series resistor R6; pin 3 of the voltage reference source IC2 is grounded; and pin 2 of the voltage reference source IC2 is also connected in parallel to pin 1 of the voltage reference source IC2.

[0011] Furthermore, the end of the resistor R6 furthest from the voltage reference source IC2 is electrically connected to the reference voltage Vref; the inverting input terminal of the operational amplifier IC1 is electrically connected to the reference voltage Vref.

[0012] Furthermore, the inverting input terminal of the operational amplifier IC1 is electrically connected to the output terminal of the operational amplifier IC1, including: the inverting input terminal of the operational amplifier IC1 is connected to the output terminal of the operational amplifier IC1 after being connected in series with resistor R5 and capacitor C4; the inverting input terminal of the operational amplifier IC1 is electrically connected to one end of capacitor C3, and the other end of capacitor C3 is electrically connected to the output terminal of the operational amplifier IC1.

[0013] Furthermore, the output of the operational amplifier IC1 is electrically connected to the feedback compensation pin COMP, which is electrically connected to the flyback topology.

[0014] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0015] Based on the PWM control loop, this embodiment of the application utilizes the characteristic that the establishment time of different points during the power-on process is different, and adds an additional anti-overcharging circuit, which greatly reduces overcharging during power-on. At the same time, it does not affect the response speed of the PWM control loop after the circuit is powered on normally. It takes into account both fast response speed and small overcharging during power-on, thus improving the overall applicability of the power supply. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This application provides a circuit diagram for an overcharge protection circuit applied to a flyback topology. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0019] The common way to solve overcharging at startup in power supplies is to reduce the response speed of the PWM control loop. However, this method can easily lead to a deterioration in the dynamic performance of the load. When a large dynamic change in load occurs suddenly during startup or normal operation of the downstream stage (for example, the load is directly increased from 10% to 100%), the loop response speed does not match the speed of load change. Therefore, the output power supply will experience voltage drop or dips, and the downstream load of the power supply will experience a short-term power outage, which has a significant impact.

[0020] Therefore, the power-on overcharge protection circuit for flyback topologies provided in this application, by utilizing the different setup times at different points during the power-on process, adds a power-on overcharge protection circuit to the PWM control loop, reducing the occurrence of power-on overcharging. Simultaneously, it does not affect the response speed of the PWM control loop during normal power-on, thus balancing fast response and low power-on overcharge, improving the overall applicability of the power supply.

[0021] To achieve the above objectives, embodiments of this application provide a circuit for preventing power-on output overcharge in a flyback topology.

[0022] Figure 1 A circuit diagram for an overcharge protection circuit for power-on output in a flyback topology, as provided in this application embodiment, is shown below. Figure 1 As shown, the overcharge protection circuit for power-on output includes an operational amplifier module and a voltage reference source IC2. The overcharge protection circuit for power-on output includes multiple resistors, multiple capacitors, and multiple diodes.

[0023] For example, in this embodiment of the application, the voltage reference source is selected as a precision voltage regulator.

[0024] The operational amplifier module includes operational amplifier IC1, operational amplifier power supply unit, operational amplifier voltage divider unit, and operational amplifier limiting unit.

[0025] Among them, the power supply unit of the operational amplifier is connected to the positive input terminal of the operational amplifier IC1 (i.e., Figure 1 Pin 5 of the operational amplifier IC1 described herein is electrically connected to provide a positive power supply voltage to the operational amplifier IC1, ensuring that the operational amplifier IC1 can operate normally.

[0026] Specifically, the operational amplifier power supply unit includes capacitor C1. One end of capacitor C1 is electrically connected to the positive power input terminal of operational amplifier IC1, and the other end is grounded (i.e., SGND as shown in the figure). At the same time, the positive power input terminal of operational amplifier IC1 and the end of capacitor C1 furthest from the signal ground are connected in parallel to a 12V DC power supply.

[0027] The op-amp voltage divider unit includes resistors R1 and R3, and the non-inverting input terminal of operational amplifier IC1 (i.e., Figure 1 Pin 4 of the operational amplifier IC1 described herein is connected in parallel with one end of resistor R1 and one end of resistor R3. The other end of resistor R1 is electrically connected to the positive voltage signal Vo, and the other end of resistor R3 is grounded.

[0028] The operational amplifier limiting unit includes diodes D1 and D2, resistor R2, and capacitor C2. The anode of diode D2 is electrically connected to the inverting input terminal of operational amplifier IC1 (i.e., Figure 1 Pin 3 of the operational amplifier IC1 described above has its negative terminal electrically connected to the positive terminal of diode D1. The negative terminal of diode D1 is electrically connected to the positive voltage signal Vo.

[0029] One end of resistor R2 is electrically connected to the positive voltage signal Vo, and the other end is electrically connected to one end of capacitor C2. The other end of capacitor C2 is grounded (i.e., ...). Figure 1 (SGND as described in the document).

[0030] Meanwhile, the end of resistor R2 furthest from the positive voltage signal Vo is electrically connected to the positive terminal of diode D2.

[0031] The negative input terminal of the power supply of operational amplifier IC1 (i.e. Figure 1 Pin 2 of the operational amplifier IC1 described herein is grounded.

[0032] The output of operational amplifier IC1 (i.e. Figure 1 Pin 1 of the operational amplifier IC1 described herein is electrically connected to the flyback topology.

[0033] Meanwhile, the output of operational amplifier IC1 is also electrically connected to the inverting input of operational amplifier IC1. Specifically, the inverting input of operational amplifier IC1 is connected to the output of operational amplifier IC1 after being connected in series with resistor R5 and capacitor C4.

[0034] The connection relationship between voltage reference IC2 and operational amplifier IC1 is as follows:

[0035] Pin 1 of the voltage reference source IC2 is electrically connected to one end of resistor R4, and the other end of resistor R4 is connected to a 12V DC power supply.

[0036] Pin 2 of voltage reference source IC2 is connected to one end of resistor R6, and the other end of resistor R6 is electrically connected to the inverting input of operational amplifier IC1. Meanwhile, pin 3 of voltage reference source IC2 is electrically connected to pin 1 of voltage reference source IC2.

[0037] In this embodiment, the end of resistor R6 furthest from voltage reference source IC2 is also electrically connected to reference voltage Vref. Simultaneously, reference voltage Vref is also electrically connected to the inverting input terminal of operational amplifier IC1.

[0038] In this embodiment, the output of operational amplifier IC1 is electrically connected to the feedback compensation pin COMP, which is electrically connected to the flyback topology.

[0039] This overcharge protection circuit is primarily used in flyback topologies. Specifically, the main operating principle of the circuit is as follows:

[0040] When the power is turned on, the 12V DC voltage is first established and filtered by capacitor C1 to provide power to the operational amplifier IC1. At this time, the circuit is just powered on and the output voltage Vo starts to build up from 0V. The output voltage is divided by resistors R1 and R3 and input to the non-inverting input of operational amplifier IC1. At this time, the voltage at this non-inverting input slowly rises from 0V.

[0041] A 12V DC voltage is supplied to the voltage reference source IC2 through resistor R4. Since the 12V DC power supply is established immediately upon power-on, pins 2 and 1 of the voltage reference source IC2 are connected, providing a stable 2.5V output voltage. This output voltage is then input to the inverting input of operational amplifier IC1 through resistor R6. When the voltage at the inverting input of operational amplifier IC1 is not limited, it is a stable 2.5V.

[0042] The inverting input of operational amplifier IC1 is connected to the output of operational amplifier IC1 through capacitors C3 and C4 and resistor R5. The output of operational amplifier IC1 is connected to the output voltage feedback compensation pin COMP of the PWM controller and outputs a low level.

[0043] According to the control logic of the flyback topology, when the output voltage feedback compensation pin COMP of the PWM controller is low, the PWM controller judges that the output voltage is low and far from the required output voltage. It will increase the duty cycle to improve the output voltage establishment. At this time, the circuit of diode D1, diode D2, resistor R2 and capacitor C2 is added to limit the port voltage of the inverting input terminal of operational amplifier IC1.

[0044] When the system is first powered on, the inverting input of operational amplifier IC1 charges capacitor C2 through diode D2, slowing down the voltage build-up speed at the inverting input of operational amplifier IC1. This limits the voltage of the output voltage feedback compensation pin COMP of the PWM controller, causing it to drop significantly. The PWM controller can only operate on a partial duty cycle, limiting the output build-up speed and thus preventing voltage build-up during the power-on process. After the voltage at the inverting input of operational amplifier IC1 is established, capacitor C2 can still stabilize the port voltage. At the same time, capacitor C2 does not participate in loop regulation and does not affect the loop parameters.

[0045] When the shutdown procedure is initiated, the output voltage begins to decrease. Capacitor C2 discharges rapidly through resistor R2 and diode D2, ensuring that the voltage inside capacitor C2 has been completely released before the next power-on, thus not affecting the power-on effect.

[0046] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this invention, and no reference numerals in the claims should be construed as limiting the scope of the claims.

[0047] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of this application.

Claims

1. A boot-up prevention output overcharge circuit applied to a flyback topology, characterized in that, Includes flyback topology, operational amplifier module and voltage reference IC2; The operational amplifier module is electrically connected to the voltage reference source IC2 and the flyback topology, respectively. The operational amplifier module includes an operational amplifier IC1, an operational amplifier power supply unit, an operational amplifier voltage divider unit, and an operational amplifier limiting unit; The operational amplifier power supply unit is electrically connected to the positive input terminal of the operational amplifier IC1; the operational amplifier voltage divider unit is electrically connected to the non-inverting input terminal of the operational amplifier IC1; and the operational amplifier limiting unit is electrically connected to the inverting input terminal of the operational amplifier IC1. The inverting input terminal of the operational amplifier IC1 is electrically connected to the output terminal of the operational amplifier IC1; the output terminal of the operational amplifier IC1 is electrically connected to the flyback topology. The negative input terminal of the operational amplifier IC1 is grounded; The voltage reference source IC2 is electrically connected to the inverting input terminal of the operational amplifier IC1.

2. The anti-boot-up output overcharge circuit according to claim 1, wherein The operational amplifier power supply unit includes capacitor C1; One end of the capacitor C1 is electrically connected to the positive input terminal of the operational amplifier IC1 and the 12V DC power supply, respectively, and the other end is grounded.

3. The anti-boot-up output overcharge circuit according to claim 1, wherein The operational amplifier voltage divider unit includes resistors R1 and R3; One end of the resistor R1 is electrically connected to the positive voltage signal Vo, and the other end is connected in parallel to the non-inverting input terminal of the operational amplifier IC1 and one end of the resistor R3. The other end of resistor R3 is grounded.

4. The anti-boot-up output overcharge circuit according to claim 1, wherein The operational amplifier limiting unit includes diode D1, diode D2, resistor R2, and capacitor C2; The positive terminal of diode D2 is electrically connected to the inverting input terminal of operational amplifier IC1, and the negative terminal is electrically connected to the positive terminal of diode D1; the negative terminal of diode D1 is electrically connected to the positive voltage signal Vo. One end of the resistor R2 is electrically connected to the positive voltage signal Vo, and the other end is electrically connected to one end of the capacitor C2. The other end of the capacitor C2 is grounded. The end of resistor R2 furthest from the positive voltage signal Vo is electrically connected to the positive terminal of diode D2.

5. The anti-boot-up output overcharge circuit according to claim 1, wherein Pin 1 of the voltage reference source IC2 is connected to a 12V DC power supply via a series resistor R4. Pin 2 of the voltage reference source IC2 is connected in series with resistor R6 and then electrically connected to the inverting input terminal of the operational amplifier IC1; Pin 3 of the voltage reference source IC2 is grounded; Pin 2 of the voltage reference source IC2 is also connected in parallel to pin 1 of the voltage reference source IC2.

6. The overcharge protection circuit for power-on output according to claim 5, characterized in that, The end of resistor R6 furthest from voltage reference source IC2 is electrically connected to reference voltage Vref; The inverting input of the operational amplifier IC1 is electrically connected to the reference voltage Vref.

7. The anti-boot-up output overcharge circuit according to claim 1, wherein The inverting input terminal of the operational amplifier IC1 is electrically connected to the output terminal of the operational amplifier IC1, including: The inverting input terminal of the operational amplifier IC1 is connected to the output terminal of the operational amplifier IC1 after being connected in series with resistor R5 and capacitor C4. The inverting input terminal of the operational amplifier IC1 is electrically connected to one end of the capacitor C3, and the other end of the capacitor C3 is electrically connected to the output terminal of the operational amplifier IC1.

8. The anti-boot-up output overcharge circuit according to claim 1, wherein The output of the operational amplifier IC1 is electrically connected to the feedback compensation pin COMP, which is electrically connected to the flyback topology.

Images